842dcac4bb91c1cabd19891032ad63ea6665d7c2
[openwrt/svn-archive/archive.git] / target / linux / xburst / patches-2.6.35 / 054-mmc.patch
1 From 34e75141dfd8edae48030b61741c294fd0f952b1 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Thu, 15 Jul 2010 20:06:04 +0000
4 Subject: [PATCH] MMC: Add support for the controller on JZ4740 SoCs.
5
6 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
7 Acked-by: Matt Fleming <matt@console-pimps.org>
8 Cc: Andrew Morton <akpm@linux-foundation.org>
9 Cc: Matt Fleming <matt@console-pimps.org>
10 Cc: linux-mmc@vger.kernel.org
11 Cc: linux-mips@linux-mips.org
12 Cc: linux-kernel@vger.kernel.org
13 Patchwork: https://patchwork.linux-mips.org/patch/1463/
14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
15 ---
16 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 +
17 drivers/mmc/host/Kconfig | 9 +
18 drivers/mmc/host/Makefile | 1 +
19 drivers/mmc/host/jz4740_mmc.c | 1033 ++++++++++++++++++++++++
20 4 files changed, 1058 insertions(+), 0 deletions(-)
21 create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
22 create mode 100644 drivers/mmc/host/jz4740_mmc.c
23
24 --- /dev/null
25 +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
26 @@ -0,0 +1,15 @@
27 +#ifndef __LINUX_MMC_JZ4740_MMC
28 +#define __LINUX_MMC_JZ4740_MMC
29 +
30 +struct jz4740_mmc_platform_data {
31 + int gpio_power;
32 + int gpio_card_detect;
33 + int gpio_read_only;
34 + unsigned card_detect_active_low:1;
35 + unsigned read_only_active_low:1;
36 + unsigned power_active_low:1;
37 +
38 + unsigned data_1bit:1;
39 +};
40 +
41 +#endif
42 --- a/drivers/mmc/host/Kconfig
43 +++ b/drivers/mmc/host/Kconfig
44 @@ -457,3 +457,12 @@ config MMC_SH_MMCIF
45 This selects the MMC Host Interface controler (MMCIF).
46
47 This driver supports MMCIF in sh7724/sh7757/sh7372.
48 +
49 +config MMC_JZ4740
50 + tristate "JZ4740 SD/Multimedia Card Interface support"
51 + depends on MACH_JZ4740
52 + help
53 + This selects support for the SD/MMC controller on Ingenic JZ4740
54 + SoCs.
55 + If you have a board based on such a SoC and with a SD/MMC slot,
56 + say Y or M here.
57 --- a/drivers/mmc/host/Makefile
58 +++ b/drivers/mmc/host/Makefile
59 @@ -37,6 +37,7 @@ obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc
60 obj-$(CONFIG_GPIOMMC) += gpiommc.o
61 obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
62 obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
63 +obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
64
65 obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
66 sdhci-of-y := sdhci-of-core.o
67 --- /dev/null
68 +++ b/drivers/mmc/host/jz4740_mmc.c
69 @@ -0,0 +1,1033 @@
70 +/*
71 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
72 + * JZ4740 SD/MMC controller driver
73 + *
74 + * This program is free software; you can redistribute it and/or modify it
75 + * under the terms of the GNU General Public License as published by the
76 + * Free Software Foundation; either version 2 of the License, or (at your
77 + * option) any later version.
78 + *
79 + * You should have received a copy of the GNU General Public License along
80 + * with this program; if not, write to the Free Software Foundation, Inc.,
81 + * 675 Mass Ave, Cambridge, MA 02139, USA.
82 + *
83 + */
84 +
85 +#include <linux/mmc/host.h>
86 +#include <linux/io.h>
87 +#include <linux/irq.h>
88 +#include <linux/interrupt.h>
89 +#include <linux/module.h>
90 +#include <linux/platform_device.h>
91 +#include <linux/delay.h>
92 +#include <linux/scatterlist.h>
93 +#include <linux/clk.h>
94 +
95 +#include <linux/bitops.h>
96 +#include <linux/gpio.h>
97 +#include <asm/mach-jz4740/gpio.h>
98 +#include <asm/cacheflush.h>
99 +#include <linux/dma-mapping.h>
100 +
101 +#include <asm/mach-jz4740/jz4740_mmc.h>
102 +
103 +#define JZ_REG_MMC_STRPCL 0x00
104 +#define JZ_REG_MMC_STATUS 0x04
105 +#define JZ_REG_MMC_CLKRT 0x08
106 +#define JZ_REG_MMC_CMDAT 0x0C
107 +#define JZ_REG_MMC_RESTO 0x10
108 +#define JZ_REG_MMC_RDTO 0x14
109 +#define JZ_REG_MMC_BLKLEN 0x18
110 +#define JZ_REG_MMC_NOB 0x1C
111 +#define JZ_REG_MMC_SNOB 0x20
112 +#define JZ_REG_MMC_IMASK 0x24
113 +#define JZ_REG_MMC_IREG 0x28
114 +#define JZ_REG_MMC_CMD 0x2C
115 +#define JZ_REG_MMC_ARG 0x30
116 +#define JZ_REG_MMC_RESP_FIFO 0x34
117 +#define JZ_REG_MMC_RXFIFO 0x38
118 +#define JZ_REG_MMC_TXFIFO 0x3C
119 +
120 +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
121 +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
122 +#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
123 +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
124 +#define JZ_MMC_STRPCL_RESET BIT(3)
125 +#define JZ_MMC_STRPCL_START_OP BIT(2)
126 +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
127 +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
128 +#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
129 +
130 +
131 +#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
132 +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
133 +#define JZ_MMC_STATUS_PRG_DONE BIT(13)
134 +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
135 +#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
136 +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
137 +#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
138 +#define JZ_MMC_STATUS_CLK_EN BIT(8)
139 +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
140 +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
141 +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
142 +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
143 +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
144 +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
145 +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
146 +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
147 +
148 +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
149 +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
150 +
151 +
152 +#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
153 +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
154 +#define JZ_MMC_CMDAT_DMA_EN BIT(8)
155 +#define JZ_MMC_CMDAT_INIT BIT(7)
156 +#define JZ_MMC_CMDAT_BUSY BIT(6)
157 +#define JZ_MMC_CMDAT_STREAM BIT(5)
158 +#define JZ_MMC_CMDAT_WRITE BIT(4)
159 +#define JZ_MMC_CMDAT_DATA_EN BIT(3)
160 +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
161 +#define JZ_MMC_CMDAT_RSP_R1 1
162 +#define JZ_MMC_CMDAT_RSP_R2 2
163 +#define JZ_MMC_CMDAT_RSP_R3 3
164 +
165 +#define JZ_MMC_IRQ_SDIO BIT(7)
166 +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
167 +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
168 +#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
169 +#define JZ_MMC_IRQ_PRG_DONE BIT(1)
170 +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
171 +
172 +
173 +#define JZ_MMC_CLK_RATE 24000000
174 +
175 +enum jz4740_mmc_state {
176 + JZ4740_MMC_STATE_READ_RESPONSE,
177 + JZ4740_MMC_STATE_TRANSFER_DATA,
178 + JZ4740_MMC_STATE_SEND_STOP,
179 + JZ4740_MMC_STATE_DONE,
180 +};
181 +
182 +struct jz4740_mmc_host {
183 + struct mmc_host *mmc;
184 + struct platform_device *pdev;
185 + struct jz4740_mmc_platform_data *pdata;
186 + struct clk *clk;
187 +
188 + int irq;
189 + int card_detect_irq;
190 +
191 + struct resource *mem;
192 + void __iomem *base;
193 + struct mmc_request *req;
194 + struct mmc_command *cmd;
195 +
196 + unsigned long waiting;
197 +
198 + uint32_t cmdat;
199 +
200 + uint16_t irq_mask;
201 +
202 + spinlock_t lock;
203 +
204 + struct timer_list timeout_timer;
205 + struct sg_mapping_iter miter;
206 + enum jz4740_mmc_state state;
207 +};
208 +
209 +static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
210 + unsigned int irq, bool enabled)
211 +{
212 + unsigned long flags;
213 +
214 + spin_lock_irqsave(&host->lock, flags);
215 + if (enabled)
216 + host->irq_mask &= ~irq;
217 + else
218 + host->irq_mask |= irq;
219 + spin_unlock_irqrestore(&host->lock, flags);
220 +
221 + writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
222 +}
223 +
224 +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
225 + bool start_transfer)
226 +{
227 + uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
228 +
229 + if (start_transfer)
230 + val |= JZ_MMC_STRPCL_START_OP;
231 +
232 + writew(val, host->base + JZ_REG_MMC_STRPCL);
233 +}
234 +
235 +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
236 +{
237 + uint32_t status;
238 + unsigned int timeout = 1000;
239 +
240 + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
241 + do {
242 + status = readl(host->base + JZ_REG_MMC_STATUS);
243 + } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
244 +}
245 +
246 +static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
247 +{
248 + uint32_t status;
249 + unsigned int timeout = 1000;
250 +
251 + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
252 + udelay(10);
253 + do {
254 + status = readl(host->base + JZ_REG_MMC_STATUS);
255 + } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
256 +}
257 +
258 +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
259 +{
260 + struct mmc_request *req;
261 +
262 + req = host->req;
263 + host->req = NULL;
264 +
265 + mmc_request_done(host->mmc, req);
266 +}
267 +
268 +static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
269 + unsigned int irq)
270 +{
271 + unsigned int timeout = 0x800;
272 + uint16_t status;
273 +
274 + do {
275 + status = readw(host->base + JZ_REG_MMC_IREG);
276 + } while (!(status & irq) && --timeout);
277 +
278 + if (timeout == 0) {
279 + set_bit(0, &host->waiting);
280 + mod_timer(&host->timeout_timer, jiffies + 5*HZ);
281 + jz4740_mmc_set_irq_enabled(host, irq, true);
282 + return true;
283 + }
284 +
285 + return false;
286 +}
287 +
288 +static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
289 + struct mmc_data *data)
290 +{
291 + int status;
292 +
293 + status = readl(host->base + JZ_REG_MMC_STATUS);
294 + if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
295 + if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
296 + host->req->cmd->error = -ETIMEDOUT;
297 + data->error = -ETIMEDOUT;
298 + } else {
299 + host->req->cmd->error = -EIO;
300 + data->error = -EIO;
301 + }
302 + }
303 +}
304 +
305 +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
306 + struct mmc_data *data)
307 +{
308 + struct sg_mapping_iter *miter = &host->miter;
309 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
310 + uint32_t *buf;
311 + bool timeout;
312 + size_t i, j;
313 +
314 + while (sg_miter_next(miter)) {
315 + buf = miter->addr;
316 + i = miter->length / 4;
317 + j = i / 8;
318 + i = i & 0x7;
319 + while (j) {
320 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
321 + if (unlikely(timeout))
322 + goto poll_timeout;
323 +
324 + writel(buf[0], fifo_addr);
325 + writel(buf[1], fifo_addr);
326 + writel(buf[2], fifo_addr);
327 + writel(buf[3], fifo_addr);
328 + writel(buf[4], fifo_addr);
329 + writel(buf[5], fifo_addr);
330 + writel(buf[6], fifo_addr);
331 + writel(buf[7], fifo_addr);
332 + buf += 8;
333 + --j;
334 + }
335 + if (unlikely(i)) {
336 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
337 + if (unlikely(timeout))
338 + goto poll_timeout;
339 +
340 + while (i) {
341 + writel(*buf, fifo_addr);
342 + ++buf;
343 + --i;
344 + }
345 + }
346 + data->bytes_xfered += miter->length;
347 + }
348 + sg_miter_stop(miter);
349 +
350 + return false;
351 +
352 +poll_timeout:
353 + miter->consumed = (void *)buf - miter->addr;
354 + data->bytes_xfered += miter->consumed;
355 + sg_miter_stop(miter);
356 +
357 + return true;
358 +}
359 +
360 +static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
361 + struct mmc_data *data)
362 +{
363 + struct sg_mapping_iter *miter = &host->miter;
364 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
365 + uint32_t *buf;
366 + uint32_t d;
367 + uint16_t status;
368 + size_t i, j;
369 + unsigned int timeout;
370 +
371 + while (sg_miter_next(miter)) {
372 + buf = miter->addr;
373 + i = miter->length;
374 + j = i / 32;
375 + i = i & 0x1f;
376 + while (j) {
377 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
378 + if (unlikely(timeout))
379 + goto poll_timeout;
380 +
381 + buf[0] = readl(fifo_addr);
382 + buf[1] = readl(fifo_addr);
383 + buf[2] = readl(fifo_addr);
384 + buf[3] = readl(fifo_addr);
385 + buf[4] = readl(fifo_addr);
386 + buf[5] = readl(fifo_addr);
387 + buf[6] = readl(fifo_addr);
388 + buf[7] = readl(fifo_addr);
389 +
390 + buf += 8;
391 + --j;
392 + }
393 +
394 + if (unlikely(i)) {
395 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
396 + if (unlikely(timeout))
397 + goto poll_timeout;
398 +
399 + while (i >= 4) {
400 + *buf++ = readl(fifo_addr);
401 + i -= 4;
402 + }
403 + if (unlikely(i > 0)) {
404 + d = readl(fifo_addr);
405 + memcpy(buf, &d, i);
406 + }
407 + }
408 + data->bytes_xfered += miter->length;
409 +
410 + /* This can go away once MIPS implements
411 + * flush_kernel_dcache_page */
412 + flush_dcache_page(miter->page);
413 + }
414 + sg_miter_stop(miter);
415 +
416 + /* For whatever reason there is sometime one word more in the fifo then
417 + * requested */
418 + timeout = 1000;
419 + status = readl(host->base + JZ_REG_MMC_STATUS);
420 + while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
421 + d = readl(fifo_addr);
422 + status = readl(host->base + JZ_REG_MMC_STATUS);
423 + }
424 +
425 + return false;
426 +
427 +poll_timeout:
428 + miter->consumed = (void *)buf - miter->addr;
429 + data->bytes_xfered += miter->consumed;
430 + sg_miter_stop(miter);
431 +
432 + return true;
433 +}
434 +
435 +static void jz4740_mmc_timeout(unsigned long data)
436 +{
437 + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
438 +
439 + if (!test_and_clear_bit(0, &host->waiting))
440 + return;
441 +
442 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
443 +
444 + host->req->cmd->error = -ETIMEDOUT;
445 + jz4740_mmc_request_done(host);
446 +}
447 +
448 +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
449 + struct mmc_command *cmd)
450 +{
451 + int i;
452 + uint16_t tmp;
453 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
454 +
455 + if (cmd->flags & MMC_RSP_136) {
456 + tmp = readw(fifo_addr);
457 + for (i = 0; i < 4; ++i) {
458 + cmd->resp[i] = tmp << 24;
459 + tmp = readw(fifo_addr);
460 + cmd->resp[i] |= tmp << 8;
461 + tmp = readw(fifo_addr);
462 + cmd->resp[i] |= tmp >> 8;
463 + }
464 + } else {
465 + cmd->resp[0] = readw(fifo_addr) << 24;
466 + cmd->resp[0] |= readw(fifo_addr) << 8;
467 + cmd->resp[0] |= readw(fifo_addr) & 0xff;
468 + }
469 +}
470 +
471 +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
472 + struct mmc_command *cmd)
473 +{
474 + uint32_t cmdat = host->cmdat;
475 +
476 + host->cmdat &= ~JZ_MMC_CMDAT_INIT;
477 + jz4740_mmc_clock_disable(host);
478 +
479 + host->cmd = cmd;
480 +
481 + if (cmd->flags & MMC_RSP_BUSY)
482 + cmdat |= JZ_MMC_CMDAT_BUSY;
483 +
484 + switch (mmc_resp_type(cmd)) {
485 + case MMC_RSP_R1B:
486 + case MMC_RSP_R1:
487 + cmdat |= JZ_MMC_CMDAT_RSP_R1;
488 + break;
489 + case MMC_RSP_R2:
490 + cmdat |= JZ_MMC_CMDAT_RSP_R2;
491 + break;
492 + case MMC_RSP_R3:
493 + cmdat |= JZ_MMC_CMDAT_RSP_R3;
494 + break;
495 + default:
496 + break;
497 + }
498 +
499 + if (cmd->data) {
500 + cmdat |= JZ_MMC_CMDAT_DATA_EN;
501 + if (cmd->data->flags & MMC_DATA_WRITE)
502 + cmdat |= JZ_MMC_CMDAT_WRITE;
503 + if (cmd->data->flags & MMC_DATA_STREAM)
504 + cmdat |= JZ_MMC_CMDAT_STREAM;
505 +
506 + writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
507 + writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
508 + }
509 +
510 + writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
511 + writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
512 + writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
513 +
514 + jz4740_mmc_clock_enable(host, 1);
515 +}
516 +
517 +static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
518 +{
519 + struct mmc_command *cmd = host->req->cmd;
520 + struct mmc_data *data = cmd->data;
521 + int direction;
522 +
523 + if (data->flags & MMC_DATA_READ)
524 + direction = SG_MITER_TO_SG;
525 + else
526 + direction = SG_MITER_FROM_SG;
527 +
528 + sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
529 +}
530 +
531 +
532 +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
533 +{
534 + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
535 + struct mmc_command *cmd = host->req->cmd;
536 + struct mmc_request *req = host->req;
537 + bool timeout = false;
538 +
539 + if (cmd->error)
540 + host->state = JZ4740_MMC_STATE_DONE;
541 +
542 + switch (host->state) {
543 + case JZ4740_MMC_STATE_READ_RESPONSE:
544 + if (cmd->flags & MMC_RSP_PRESENT)
545 + jz4740_mmc_read_response(host, cmd);
546 +
547 + if (!cmd->data)
548 + break;
549 +
550 + jz_mmc_prepare_data_transfer(host);
551 +
552 + case JZ4740_MMC_STATE_TRANSFER_DATA:
553 + if (cmd->data->flags & MMC_DATA_READ)
554 + timeout = jz4740_mmc_read_data(host, cmd->data);
555 + else
556 + timeout = jz4740_mmc_write_data(host, cmd->data);
557 +
558 + if (unlikely(timeout)) {
559 + host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
560 + break;
561 + }
562 +
563 + jz4740_mmc_transfer_check_state(host, cmd->data);
564 +
565 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
566 + if (unlikely(timeout)) {
567 + host->state = JZ4740_MMC_STATE_SEND_STOP;
568 + break;
569 + }
570 + writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
571 +
572 + case JZ4740_MMC_STATE_SEND_STOP:
573 + if (!req->stop)
574 + break;
575 +
576 + jz4740_mmc_send_command(host, req->stop);
577 +
578 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
579 + if (timeout) {
580 + host->state = JZ4740_MMC_STATE_DONE;
581 + break;
582 + }
583 + case JZ4740_MMC_STATE_DONE:
584 + break;
585 + }
586 +
587 + if (!timeout)
588 + jz4740_mmc_request_done(host);
589 +
590 + return IRQ_HANDLED;
591 +}
592 +
593 +static irqreturn_t jz_mmc_irq(int irq, void *devid)
594 +{
595 + struct jz4740_mmc_host *host = devid;
596 + struct mmc_command *cmd = host->cmd;
597 + uint16_t irq_reg, status, tmp;
598 +
599 + irq_reg = readw(host->base + JZ_REG_MMC_IREG);
600 +
601 + tmp = irq_reg;
602 + irq_reg &= ~host->irq_mask;
603 +
604 + tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
605 + JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
606 +
607 + if (tmp != irq_reg)
608 + writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
609 +
610 + if (irq_reg & JZ_MMC_IRQ_SDIO) {
611 + writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
612 + mmc_signal_sdio_irq(host->mmc);
613 + irq_reg &= ~JZ_MMC_IRQ_SDIO;
614 + }
615 +
616 + if (host->req && cmd && irq_reg) {
617 + if (test_and_clear_bit(0, &host->waiting)) {
618 + del_timer(&host->timeout_timer);
619 +
620 + status = readl(host->base + JZ_REG_MMC_STATUS);
621 +
622 + if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
623 + cmd->error = -ETIMEDOUT;
624 + } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
625 + cmd->error = -EIO;
626 + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
627 + JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
628 + if (cmd->data)
629 + cmd->data->error = -EIO;
630 + cmd->error = -EIO;
631 + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
632 + JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
633 + if (cmd->data)
634 + cmd->data->error = -EIO;
635 + cmd->error = -EIO;
636 + }
637 +
638 + jz4740_mmc_set_irq_enabled(host, irq_reg, false);
639 + writew(irq_reg, host->base + JZ_REG_MMC_IREG);
640 +
641 + return IRQ_WAKE_THREAD;
642 + }
643 + }
644 +
645 + return IRQ_HANDLED;
646 +}
647 +
648 +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
649 +{
650 + int div = 0;
651 + int real_rate;
652 +
653 + jz4740_mmc_clock_disable(host);
654 + clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
655 +
656 + real_rate = clk_get_rate(host->clk);
657 +
658 + while (real_rate > rate && div < 7) {
659 + ++div;
660 + real_rate >>= 1;
661 + }
662 +
663 + writew(div, host->base + JZ_REG_MMC_CLKRT);
664 + return real_rate;
665 +}
666 +
667 +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
668 +{
669 + struct jz4740_mmc_host *host = mmc_priv(mmc);
670 +
671 + host->req = req;
672 +
673 + writew(0xffff, host->base + JZ_REG_MMC_IREG);
674 +
675 + writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
676 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
677 +
678 + host->state = JZ4740_MMC_STATE_READ_RESPONSE;
679 + set_bit(0, &host->waiting);
680 + mod_timer(&host->timeout_timer, jiffies + 5*HZ);
681 + jz4740_mmc_send_command(host, req->cmd);
682 +}
683 +
684 +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
685 +{
686 + struct jz4740_mmc_host *host = mmc_priv(mmc);
687 + if (ios->clock)
688 + jz4740_mmc_set_clock_rate(host, ios->clock);
689 +
690 + switch (ios->power_mode) {
691 + case MMC_POWER_UP:
692 + jz4740_mmc_reset(host);
693 + if (gpio_is_valid(host->pdata->gpio_power))
694 + gpio_set_value(host->pdata->gpio_power,
695 + !host->pdata->power_active_low);
696 + host->cmdat |= JZ_MMC_CMDAT_INIT;
697 + clk_enable(host->clk);
698 + break;
699 + case MMC_POWER_ON:
700 + break;
701 + default:
702 + if (gpio_is_valid(host->pdata->gpio_power))
703 + gpio_set_value(host->pdata->gpio_power,
704 + host->pdata->power_active_low);
705 + clk_disable(host->clk);
706 + break;
707 + }
708 +
709 + switch (ios->bus_width) {
710 + case MMC_BUS_WIDTH_1:
711 + host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
712 + break;
713 + case MMC_BUS_WIDTH_4:
714 + host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
715 + break;
716 + default:
717 + break;
718 + }
719 +}
720 +
721 +static int jz4740_mmc_get_ro(struct mmc_host *mmc)
722 +{
723 + struct jz4740_mmc_host *host = mmc_priv(mmc);
724 + if (!gpio_is_valid(host->pdata->gpio_read_only))
725 + return -ENOSYS;
726 +
727 + return gpio_get_value(host->pdata->gpio_read_only) ^
728 + host->pdata->read_only_active_low;
729 +}
730 +
731 +static int jz4740_mmc_get_cd(struct mmc_host *mmc)
732 +{
733 + struct jz4740_mmc_host *host = mmc_priv(mmc);
734 + if (!gpio_is_valid(host->pdata->gpio_card_detect))
735 + return -ENOSYS;
736 +
737 + return gpio_get_value(host->pdata->gpio_card_detect) ^
738 + host->pdata->card_detect_active_low;
739 +}
740 +
741 +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
742 +{
743 + struct jz4740_mmc_host *host = devid;
744 +
745 + mmc_detect_change(host->mmc, HZ / 2);
746 +
747 + return IRQ_HANDLED;
748 +}
749 +
750 +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
751 +{
752 + struct jz4740_mmc_host *host = mmc_priv(mmc);
753 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
754 +}
755 +
756 +static const struct mmc_host_ops jz4740_mmc_ops = {
757 + .request = jz4740_mmc_request,
758 + .set_ios = jz4740_mmc_set_ios,
759 + .get_ro = jz4740_mmc_get_ro,
760 + .get_cd = jz4740_mmc_get_cd,
761 + .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
762 +};
763 +
764 +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
765 + JZ_GPIO_BULK_PIN(MSC_CMD),
766 + JZ_GPIO_BULK_PIN(MSC_CLK),
767 + JZ_GPIO_BULK_PIN(MSC_DATA0),
768 + JZ_GPIO_BULK_PIN(MSC_DATA1),
769 + JZ_GPIO_BULK_PIN(MSC_DATA2),
770 + JZ_GPIO_BULK_PIN(MSC_DATA3),
771 +};
772 +
773 +static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio,
774 + const char *name, bool output, int value)
775 +{
776 + int ret;
777 +
778 + if (!gpio_is_valid(gpio))
779 + return 0;
780 +
781 + ret = gpio_request(gpio, name);
782 + if (ret) {
783 + dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
784 + return ret;
785 + }
786 +
787 + if (output)
788 + gpio_direction_output(gpio, value);
789 + else
790 + gpio_direction_input(gpio);
791 +
792 + return 0;
793 +}
794 +
795 +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
796 +{
797 + int ret;
798 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
799 +
800 + if (!pdata)
801 + return 0;
802 +
803 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect,
804 + "MMC detect change", false, 0);
805 + if (ret)
806 + goto err;
807 +
808 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only,
809 + "MMC read only", false, 0);
810 + if (ret)
811 + goto err_free_gpio_card_detect;
812 +
813 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
814 + "MMC read only", true, pdata->power_active_low);
815 + if (ret)
816 + goto err_free_gpio_read_only;
817 +
818 + return 0;
819 +
820 +err_free_gpio_read_only:
821 + if (gpio_is_valid(pdata->gpio_read_only))
822 + gpio_free(pdata->gpio_read_only);
823 +err_free_gpio_card_detect:
824 + if (gpio_is_valid(pdata->gpio_card_detect))
825 + gpio_free(pdata->gpio_card_detect);
826 +err:
827 + return ret;
828 +}
829 +
830 +static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev,
831 + struct jz4740_mmc_host *host)
832 +{
833 + int ret;
834 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
835 +
836 + if (gpio_is_valid(pdata->gpio_card_detect))
837 + return 0;
838 +
839 + host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
840 +
841 + if (host->card_detect_irq < 0) {
842 + dev_warn(&pdev->dev, "Failed to get card detect irq\n");
843 + return 0;
844 + }
845 + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq,
846 + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
847 + "MMC card detect", host);
848 +
849 +
850 + return ret;
851 +}
852 +
853 +static void jz4740_mmc_free_gpios(struct platform_device *pdev)
854 +{
855 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
856 +
857 + if (!pdata)
858 + return;
859 +
860 + if (gpio_is_valid(pdata->gpio_power))
861 + gpio_free(pdata->gpio_power);
862 + if (gpio_is_valid(pdata->gpio_read_only))
863 + gpio_free(pdata->gpio_read_only);
864 + if (gpio_is_valid(pdata->gpio_card_detect))
865 + gpio_free(pdata->gpio_card_detect);
866 +}
867 +
868 +static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
869 +{
870 + size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
871 + if (host->pdata && host->pdata->data_1bit)
872 + num_pins -= 3;
873 +
874 + return num_pins;
875 +}
876 +
877 +static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
878 +{
879 + int ret;
880 + struct mmc_host *mmc;
881 + struct jz4740_mmc_host *host;
882 + struct jz4740_mmc_platform_data *pdata;
883 +
884 + pdata = pdev->dev.platform_data;
885 +
886 + mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
887 + if (!mmc) {
888 + dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
889 + return -ENOMEM;
890 + }
891 +
892 + host = mmc_priv(mmc);
893 + host->pdata = pdata;
894 +
895 + host->irq = platform_get_irq(pdev, 0);
896 + if (host->irq < 0) {
897 + ret = host->irq;
898 + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
899 + goto err_free_host;
900 + }
901 +
902 + host->clk = clk_get(&pdev->dev, "mmc");
903 + if (!host->clk) {
904 + ret = -ENOENT;
905 + dev_err(&pdev->dev, "Failed to get mmc clock\n");
906 + goto err_free_host;
907 + }
908 +
909 + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910 + if (!host->mem) {
911 + ret = -ENOENT;
912 + dev_err(&pdev->dev, "Failed to get base platform memory\n");
913 + goto err_clk_put;
914 + }
915 +
916 + host->mem = request_mem_region(host->mem->start,
917 + resource_size(host->mem), pdev->name);
918 + if (!host->mem) {
919 + ret = -EBUSY;
920 + dev_err(&pdev->dev, "Failed to request base memory region\n");
921 + goto err_clk_put;
922 + }
923 +
924 + host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
925 + if (!host->base) {
926 + ret = -EBUSY;
927 + dev_err(&pdev->dev, "Failed to ioremap base memory\n");
928 + goto err_release_mem_region;
929 + }
930 +
931 + ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
932 + if (ret) {
933 + dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
934 + goto err_iounmap;
935 + }
936 +
937 + ret = jz4740_mmc_request_gpios(pdev);
938 + if (ret)
939 + goto err_gpio_bulk_free;
940 +
941 + mmc->ops = &jz4740_mmc_ops;
942 + mmc->f_min = JZ_MMC_CLK_RATE / 128;
943 + mmc->f_max = JZ_MMC_CLK_RATE;
944 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
945 + mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
946 + mmc->caps |= MMC_CAP_SDIO_IRQ;
947 +
948 + mmc->max_blk_size = (1 << 10) - 1;
949 + mmc->max_blk_count = (1 << 15) - 1;
950 + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
951 +
952 + mmc->max_phys_segs = 128;
953 + mmc->max_hw_segs = 128;
954 + mmc->max_seg_size = mmc->max_req_size;
955 +
956 + host->mmc = mmc;
957 + host->pdev = pdev;
958 + spin_lock_init(&host->lock);
959 + host->irq_mask = 0xffff;
960 +
961 + ret = jz4740_mmc_request_cd_irq(pdev, host);
962 + if (ret) {
963 + dev_err(&pdev->dev, "Failed to request card detect irq\n");
964 + goto err_free_gpios;
965 + }
966 +
967 + ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
968 + dev_name(&pdev->dev), host);
969 + if (ret) {
970 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
971 + goto err_free_card_detect_irq;
972 + }
973 +
974 + jz4740_mmc_reset(host);
975 + jz4740_mmc_clock_disable(host);
976 + setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
977 + (unsigned long)host);
978 + /* It is not important when it times out, it just needs to timeout. */
979 + set_timer_slack(&host->timeout_timer, HZ);
980 +
981 + platform_set_drvdata(pdev, host);
982 + ret = mmc_add_host(mmc);
983 +
984 + if (ret) {
985 + dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
986 + goto err_free_irq;
987 + }
988 + dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
989 +
990 + return 0;
991 +
992 +err_free_irq:
993 + free_irq(host->irq, host);
994 +err_free_card_detect_irq:
995 + if (host->card_detect_irq >= 0)
996 + free_irq(host->card_detect_irq, host);
997 +err_free_gpios:
998 + jz4740_mmc_free_gpios(pdev);
999 +err_gpio_bulk_free:
1000 + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1001 +err_iounmap:
1002 + iounmap(host->base);
1003 +err_release_mem_region:
1004 + release_mem_region(host->mem->start, resource_size(host->mem));
1005 +err_clk_put:
1006 + clk_put(host->clk);
1007 +err_free_host:
1008 + platform_set_drvdata(pdev, NULL);
1009 + mmc_free_host(mmc);
1010 +
1011 + return ret;
1012 +}
1013 +
1014 +static int __devexit jz4740_mmc_remove(struct platform_device *pdev)
1015 +{
1016 + struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1017 +
1018 + del_timer_sync(&host->timeout_timer);
1019 + jz4740_mmc_set_irq_enabled(host, 0xff, false);
1020 + jz4740_mmc_reset(host);
1021 +
1022 + mmc_remove_host(host->mmc);
1023 +
1024 + free_irq(host->irq, host);
1025 + if (host->card_detect_irq >= 0)
1026 + free_irq(host->card_detect_irq, host);
1027 +
1028 + jz4740_mmc_free_gpios(pdev);
1029 + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1030 +
1031 + iounmap(host->base);
1032 + release_mem_region(host->mem->start, resource_size(host->mem));
1033 +
1034 + clk_put(host->clk);
1035 +
1036 + platform_set_drvdata(pdev, NULL);
1037 + mmc_free_host(host->mmc);
1038 +
1039 + return 0;
1040 +}
1041 +
1042 +#ifdef CONFIG_PM
1043 +
1044 +static int jz4740_mmc_suspend(struct device *dev)
1045 +{
1046 + struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1047 +
1048 + mmc_suspend_host(host->mmc);
1049 +
1050 + jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1051 +
1052 + return 0;
1053 +}
1054 +
1055 +static int jz4740_mmc_resume(struct device *dev)
1056 +{
1057 + struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1058 +
1059 + jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1060 +
1061 + mmc_resume_host(host->mmc);
1062 +
1063 + return 0;
1064 +}
1065 +
1066 +const struct dev_pm_ops jz4740_mmc_pm_ops = {
1067 + .suspend = jz4740_mmc_suspend,
1068 + .resume = jz4740_mmc_resume,
1069 + .poweroff = jz4740_mmc_suspend,
1070 + .restore = jz4740_mmc_resume,
1071 +};
1072 +
1073 +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1074 +#else
1075 +#define JZ4740_MMC_PM_OPS NULL
1076 +#endif
1077 +
1078 +static struct platform_driver jz4740_mmc_driver = {
1079 + .probe = jz4740_mmc_probe,
1080 + .remove = __devexit_p(jz4740_mmc_remove),
1081 + .driver = {
1082 + .name = "jz4740-mmc",
1083 + .owner = THIS_MODULE,
1084 + .pm = JZ4740_MMC_PM_OPS,
1085 + },
1086 +};
1087 +
1088 +static int __init jz4740_mmc_init(void)
1089 +{
1090 + return platform_driver_register(&jz4740_mmc_driver);
1091 +}
1092 +module_init(jz4740_mmc_init);
1093 +
1094 +static void __exit jz4740_mmc_exit(void)
1095 +{
1096 + platform_driver_unregister(&jz4740_mmc_driver);
1097 +}
1098 +module_exit(jz4740_mmc_exit);
1099 +
1100 +MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1101 +MODULE_LICENSE("GPL");
1102 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");