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xburst: switch to 3.3 and add broken flag
[openwrt/svn-archive/archive.git] / target / linux / xburst / patches-3.2 / 0002-Add-jz4740-udc-driver.patch
1 From 537082e01849ca85227c5b462b8ac9aceb11b77a Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH 02/21] Add jz4740 udc driver
5
6 History:
7 - driver by Ingenic
8 - patch by Lars-Peter Clausen.
9 - updated to 3.1 by Maarten ter Huurne
10 ---
11 drivers/usb/gadget/Kconfig | 8 +
12 drivers/usb/gadget/Makefile | 1 +
13 drivers/usb/gadget/gadget_chips.h | 3 +
14 drivers/usb/gadget/jz4740_udc.c | 2199 +++++++++++++++++++++++++++++++++++++
15 drivers/usb/gadget/jz4740_udc.h | 101 ++
16 5 files changed, 2312 insertions(+), 0 deletions(-)
17 create mode 100644 drivers/usb/gadget/jz4740_udc.c
18 create mode 100644 drivers/usb/gadget/jz4740_udc.h
19
20 --- a/drivers/usb/gadget/Kconfig
21 +++ b/drivers/usb/gadget/Kconfig
22 @@ -178,6 +178,14 @@ config USB_FUSB300
23 help
24 Faraday usb device controller FUSB300 driver
25
26 +config USB_JZ4740
27 + tristate "JZ4740 UDC"
28 + depends on MACH_JZ4740
29 + select USB_GADGET_DUALSPEED
30 + help
31 + Select this to support the Ingenic JZ4740 processor
32 + high speed USB device controller.
33 +
34 config USB_OMAP
35 tristate "OMAP USB Device Controller"
36 depends on ARCH_OMAP
37 --- a/drivers/usb/gadget/Makefile
38 +++ b/drivers/usb/gadget/Makefile
39 @@ -31,6 +31,7 @@ obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
40 mv_udc-y := mv_udc_core.o
41 obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
42 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
43 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
44
45 #
46 # USB gadget drivers
47 --- a/drivers/usb/gadget/gadget_chips.h
48 +++ b/drivers/usb/gadget/gadget_chips.h
49 @@ -36,6 +36,7 @@
50 #define gadget_is_fsl_usb2(g) (!strcmp("fsl-usb2-udc", (g)->name))
51 #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
52 #define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name))
53 +#define gadget_is_jz4740(g) (!strcmp("ingenic_hsusb", (g)->name))
54 #define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
55 #define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name))
56 #define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
57 @@ -118,6 +119,8 @@ static inline int usb_gadget_controller_
58 return 0x31;
59 else if (gadget_is_dwc3(gadget))
60 return 0x32;
61 + else if (gadget_is_jz4740(gadget))
62 + return 0x33;
63
64 return -ENOENT;
65 }
66 --- /dev/null
67 +++ b/drivers/usb/gadget/jz4740_udc.c
68 @@ -0,0 +1,2199 @@
69 +/*
70 + * linux/drivers/usb/gadget/jz4740_udc.c
71 + *
72 + * Ingenic JZ4740 on-chip high speed USB device controller
73 + *
74 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
75 + * Author: <jlwei@ingenic.cn>
76 + *
77 + * This program is free software; you can redistribute it and/or modify
78 + * it under the terms of the GNU General Public License as published by
79 + * the Free Software Foundation; either version 2 of the License, or
80 + * (at your option) any later version.
81 + */
82 +
83 +/*
84 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
85 + *
86 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
87 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
88 + */
89 +
90 +#include <linux/kernel.h>
91 +#include <linux/module.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/delay.h>
94 +#include <linux/ioport.h>
95 +#include <linux/slab.h>
96 +#include <linux/errno.h>
97 +#include <linux/init.h>
98 +#include <linux/list.h>
99 +#include <linux/interrupt.h>
100 +#include <linux/proc_fs.h>
101 +#include <linux/usb.h>
102 +#include <linux/usb/gadget.h>
103 +#include <linux/clk.h>
104 +
105 +#include <asm/byteorder.h>
106 +#include <asm/io.h>
107 +#include <asm/irq.h>
108 +#include <asm/system.h>
109 +#include <asm/mach-jz4740/clock.h>
110 +
111 +#include "jz4740_udc.h"
112 +
113 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
114 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
115 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
116 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
117 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
118 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
119 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
120 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
121 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
122 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
123 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
124 +
125 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
126 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
127 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
128 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
129 +
130 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
131 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
132 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
133 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
134 +
135 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
136 +
137 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
138 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
139 +
140 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
141 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
142 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
143 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
144 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
145 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
146 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
147 +
148 +/* Power register bit masks */
149 +#define USB_POWER_SUSPENDM 0x01
150 +#define USB_POWER_RESUME 0x04
151 +#define USB_POWER_HSMODE 0x10
152 +#define USB_POWER_HSENAB 0x20
153 +#define USB_POWER_SOFTCONN 0x40
154 +
155 +/* Interrupt register bit masks */
156 +#define USB_INTR_SUSPEND 0x01
157 +#define USB_INTR_RESUME 0x02
158 +#define USB_INTR_RESET 0x04
159 +
160 +#define USB_INTR_EP0 0x0001
161 +#define USB_INTR_INEP1 0x0002
162 +#define USB_INTR_INEP2 0x0004
163 +#define USB_INTR_OUTEP1 0x0002
164 +
165 +/* CSR0 bit masks */
166 +#define USB_CSR0_OUTPKTRDY 0x01
167 +#define USB_CSR0_INPKTRDY 0x02
168 +#define USB_CSR0_SENTSTALL 0x04
169 +#define USB_CSR0_DATAEND 0x08
170 +#define USB_CSR0_SETUPEND 0x10
171 +#define USB_CSR0_SENDSTALL 0x20
172 +#define USB_CSR0_SVDOUTPKTRDY 0x40
173 +#define USB_CSR0_SVDSETUPEND 0x80
174 +
175 +/* Endpoint CSR register bits */
176 +#define USB_INCSRH_AUTOSET 0x80
177 +#define USB_INCSRH_ISO 0x40
178 +#define USB_INCSRH_MODE 0x20
179 +#define USB_INCSRH_DMAREQENAB 0x10
180 +#define USB_INCSRH_DMAREQMODE 0x04
181 +#define USB_INCSR_CDT 0x40
182 +#define USB_INCSR_SENTSTALL 0x20
183 +#define USB_INCSR_SENDSTALL 0x10
184 +#define USB_INCSR_FF 0x08
185 +#define USB_INCSR_UNDERRUN 0x04
186 +#define USB_INCSR_FFNOTEMPT 0x02
187 +#define USB_INCSR_INPKTRDY 0x01
188 +
189 +#define USB_OUTCSRH_AUTOCLR 0x80
190 +#define USB_OUTCSRH_ISO 0x40
191 +#define USB_OUTCSRH_DMAREQENAB 0x20
192 +#define USB_OUTCSRH_DNYT 0x10
193 +#define USB_OUTCSRH_DMAREQMODE 0x08
194 +#define USB_OUTCSR_CDT 0x80
195 +#define USB_OUTCSR_SENTSTALL 0x40
196 +#define USB_OUTCSR_SENDSTALL 0x20
197 +#define USB_OUTCSR_FF 0x10
198 +#define USB_OUTCSR_DATAERR 0x08
199 +#define USB_OUTCSR_OVERRUN 0x04
200 +#define USB_OUTCSR_FFFULL 0x02
201 +#define USB_OUTCSR_OUTPKTRDY 0x01
202 +
203 +/* DMA control bits */
204 +#define USB_CNTL_ENA 0x01
205 +#define USB_CNTL_DIR_IN 0x02
206 +#define USB_CNTL_MODE_1 0x04
207 +#define USB_CNTL_INTR_EN 0x08
208 +#define USB_CNTL_EP(n) ((n) << 4)
209 +#define USB_CNTL_BURST_0 (0 << 9)
210 +#define USB_CNTL_BURST_4 (1 << 9)
211 +#define USB_CNTL_BURST_8 (2 << 9)
212 +#define USB_CNTL_BURST_16 (3 << 9)
213 +
214 +
215 +#ifndef DEBUG
216 +# define DEBUG(fmt,args...) do {} while(0)
217 +#endif
218 +#ifndef DEBUG_EP0
219 +# define NO_STATES
220 +# define DEBUG_EP0(fmt,args...) do {} while(0)
221 +#endif
222 +#ifndef DEBUG_SETUP
223 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
224 +#endif
225 +
226 +static struct jz4740_udc jz4740_udc_controller;
227 +
228 +/*
229 + * Local declarations.
230 + */
231 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
232 + int (*bind)(struct usb_gadget *));
233 +static int jz4740_udc_stop(struct usb_gadget_driver *driver);
234 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
235 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
236 +
237 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
238 + int status);
239 +static void pio_irq_enable(struct jz4740_ep *ep);
240 +static void pio_irq_disable(struct jz4740_ep *ep);
241 +static void stop_activity(struct jz4740_udc *dev,
242 + struct usb_gadget_driver *driver);
243 +static void nuke(struct jz4740_ep *ep, int status);
244 +static void flush(struct jz4740_ep *ep);
245 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
246 +
247 +/*-------------------------------------------------------------------------*/
248 +
249 +/* inline functions of register read/write/set/clear */
250 +
251 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
252 +{
253 + return readb(udc->base + reg);
254 +}
255 +
256 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
257 +{
258 + return readw(udc->base + reg);
259 +}
260 +
261 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
262 +{
263 + return readl(udc->base + reg);
264 +}
265 +
266 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
267 +{
268 + writeb(val, udc->base + reg);
269 +}
270 +
271 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
272 +{
273 + writew(val, udc->base + reg);
274 +}
275 +
276 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
277 +{
278 + writel(val, udc->base + reg);
279 +}
280 +
281 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
282 +{
283 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
284 +}
285 +
286 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
287 +{
288 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
289 +}
290 +
291 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
292 +{
293 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
294 +}
295 +
296 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
297 +{
298 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
299 +}
300 +
301 +/*-------------------------------------------------------------------------*/
302 +
303 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
304 +{
305 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
306 +}
307 +
308 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
309 +{
310 + jz_udc_set_index(ep->dev, ep_index(ep));
311 +}
312 +
313 +static inline int write_packet(struct jz4740_ep *ep,
314 + struct jz4740_request *req, unsigned int count)
315 +{
316 + uint8_t *buf;
317 + unsigned int length;
318 + void __iomem *fifo = ep->dev->base + ep->fifo;
319 +
320 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
321 +
322 + buf = req->req.buf + req->req.actual;
323 +
324 + length = req->req.length - req->req.actual;
325 + if (length > count)
326 + length = count;
327 + req->req.actual += length;
328 +
329 + DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
330 +
331 + writesl(fifo, buf, length >> 2);
332 + writesb(fifo, &buf[length - (length & 3)], length & 3);
333 +
334 + return length;
335 +}
336 +
337 +static int read_packet(struct jz4740_ep *ep,
338 + struct jz4740_request *req, unsigned int count)
339 +{
340 + uint8_t *buf;
341 + unsigned int length;
342 + void __iomem *fifo = ep->dev->base + ep->fifo;
343 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
344 +
345 + buf = req->req.buf + req->req.actual;
346 +
347 + length = req->req.length - req->req.actual;
348 + if (length > count)
349 + length = count;
350 + req->req.actual += length;
351 +
352 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
353 +
354 + readsl(fifo, buf, length >> 2);
355 + readsb(fifo, &buf[length - (length & 3)], length & 3);
356 +
357 + return length;
358 +}
359 +
360 +/*-------------------------------------------------------------------------*/
361 +
362 +/*
363 + * udc_disable - disable USB device controller
364 + */
365 +static void udc_disable(struct jz4740_udc *dev)
366 +{
367 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
368 +
369 + udc_set_address(dev, 0);
370 +
371 + /* Disable interrupts */
372 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
373 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
374 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
375 +
376 + /* Disable DMA */
377 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
378 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
379 +
380 + /* Disconnect from usb */
381 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
382 +
383 + /* Disable the USB PHY */
384 + clk_disable(dev->clk);
385 +
386 + dev->ep0state = WAIT_FOR_SETUP;
387 + dev->gadget.speed = USB_SPEED_UNKNOWN;
388 +
389 + return;
390 +}
391 +
392 +/*
393 + * udc_reinit - initialize software state
394 + */
395 +static void udc_reinit(struct jz4740_udc *dev)
396 +{
397 + int i;
398 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
399 +
400 + /* device/ep0 records init */
401 + INIT_LIST_HEAD(&dev->gadget.ep_list);
402 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
403 + dev->ep0state = WAIT_FOR_SETUP;
404 +
405 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
406 + struct jz4740_ep *ep = &dev->ep[i];
407 +
408 + if (i != 0)
409 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
410 +
411 + INIT_LIST_HEAD(&ep->queue);
412 + ep->desc = 0;
413 + ep->stopped = 0;
414 + }
415 +}
416 +
417 +/* until it's enabled, this UDC should be completely invisible
418 + * to any USB host.
419 + */
420 +static void udc_enable(struct jz4740_udc *dev)
421 +{
422 + int i;
423 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
424 +
425 + /* UDC state is incorrect - Added by River */
426 + if (dev->state != UDC_STATE_ENABLE) {
427 + return;
428 + }
429 +
430 + dev->gadget.speed = USB_SPEED_UNKNOWN;
431 +
432 + /* Flush FIFO for each */
433 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
434 + struct jz4740_ep *ep = &dev->ep[i];
435 +
436 + jz_udc_select_ep(ep);
437 + flush(ep);
438 + }
439 +
440 + /* Set this bit to allow the UDC entering low-power mode when
441 + * there are no actions on the USB bus.
442 + * UDC still works during this bit was set.
443 + */
444 + jz4740_clock_udc_enable_auto_suspend();
445 +
446 + /* Enable the USB PHY */
447 + clk_enable(dev->clk);
448 +
449 + /* Disable interrupts */
450 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
451 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
452 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
453 +
454 + /* Enable interrupts */
455 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
456 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
457 + /* Don't enable rest of the interrupts */
458 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
459 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
460 +
461 + /* Enable SUSPEND */
462 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
463 +
464 + /* Enable HS Mode */
465 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
466 +
467 + /* Let host detect UDC:
468 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
469 + * transistor on and pull the USBDP pin HIGH.
470 + */
471 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
472 +
473 + return;
474 +}
475 +
476 +/*-------------------------------------------------------------------------*/
477 +
478 +/* keeping it simple:
479 + * - one bus driver, initted first;
480 + * - one function driver, initted second
481 + */
482 +
483 +/*
484 + * Register entry point for the peripheral controller driver.
485 + */
486 +
487 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
488 + int (*bind)(struct usb_gadget *))
489 +{
490 + struct jz4740_udc *dev = &jz4740_udc_controller;
491 + int retval;
492 +
493 + if (!driver || !bind)
494 + return -EINVAL;
495 +
496 + if (!dev)
497 + return -ENODEV;
498 +
499 + if (dev->driver)
500 + return -EBUSY;
501 +
502 + /* hook up the driver */
503 + dev->driver = driver;
504 + dev->gadget.dev.driver = &driver->driver;
505 +
506 + retval = bind(&dev->gadget);
507 + if (retval) {
508 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
509 + driver->driver.name, retval);
510 + dev->driver = 0;
511 + return retval;
512 + }
513 +
514 + /* then enable host detection and ep0; and we're ready
515 + * for set_configuration as well as eventual disconnect.
516 + */
517 + udc_enable(dev);
518 +
519 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
520 + driver->driver.name);
521 +
522 + return 0;
523 +}
524 +
525 +static void stop_activity(struct jz4740_udc *dev,
526 + struct usb_gadget_driver *driver)
527 +{
528 + int i;
529 +
530 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
531 +
532 + /* don't disconnect drivers more than once */
533 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
534 + driver = 0;
535 + dev->gadget.speed = USB_SPEED_UNKNOWN;
536 +
537 + /* prevent new request submissions, kill any outstanding requests */
538 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
539 + struct jz4740_ep *ep = &dev->ep[i];
540 +
541 + ep->stopped = 1;
542 +
543 + jz_udc_select_ep(ep);
544 + nuke(ep, -ESHUTDOWN);
545 + }
546 +
547 + /* report disconnect; the driver is already quiesced */
548 + if (driver) {
549 + spin_unlock(&dev->lock);
550 + driver->disconnect(&dev->gadget);
551 + spin_lock(&dev->lock);
552 + }
553 +
554 + /* re-init driver-visible data structures */
555 + udc_reinit(dev);
556 +}
557 +
558 +
559 +/*
560 + * Unregister entry point for the peripheral controller driver.
561 + */
562 +static int jz4740_udc_stop(struct usb_gadget_driver *driver)
563 +{
564 + struct jz4740_udc *dev = &jz4740_udc_controller;
565 + unsigned long flags;
566 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
567 +
568 + if (!dev)
569 + return -ENODEV;
570 + if (!driver || driver != dev->driver)
571 + return -EINVAL;
572 + if (!driver->unbind)
573 + return -EBUSY;
574 +
575 + spin_lock_irqsave(&dev->lock, flags);
576 + dev->driver = 0;
577 + stop_activity(dev, driver);
578 + spin_unlock_irqrestore(&dev->lock, flags);
579 +
580 + driver->unbind(&dev->gadget);
581 +
582 + udc_disable(dev);
583 +
584 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
585 +
586 + return 0;
587 +}
588 +
589 +/*-------------------------------------------------------------------------*/
590 +
591 +/** Write request to FIFO (max write == maxp size)
592 + * Return: 0 = still running, 1 = completed, negative = errno
593 + * NOTE: INDEX register must be set for EP
594 + */
595 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
596 +{
597 + struct jz4740_udc *dev = ep->dev;
598 + uint32_t max, csr;
599 +
600 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
601 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
602 +
603 + csr = usb_readb(dev, ep->csr);
604 +
605 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
606 + unsigned count;
607 + int is_last, is_short;
608 +
609 + count = write_packet(ep, req, max);
610 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
611 +
612 + /* last packet is usually short (or a zlp) */
613 + if (unlikely(count != max))
614 + is_last = is_short = 1;
615 + else {
616 + if (likely(req->req.length != req->req.actual)
617 + || req->req.zero)
618 + is_last = 0;
619 + else
620 + is_last = 1;
621 + /* interrupt/iso maxpacket may not fill the fifo */
622 + is_short = unlikely(max < ep_maxpacket(ep));
623 + }
624 +
625 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
626 + ep->ep.name, count,
627 + is_last ? "/L" : "", is_short ? "/S" : "",
628 + req->req.length - req->req.actual, req);
629 +
630 + /* requests complete when all IN data is in the FIFO */
631 + if (is_last) {
632 + done(ep, req, 0);
633 + if (list_empty(&ep->queue)) {
634 + pio_irq_disable(ep);
635 + }
636 + return 1;
637 + }
638 + } else {
639 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
640 + }
641 +
642 + return 0;
643 +}
644 +
645 +/** Read to request from FIFO (max read == bytes in fifo)
646 + * Return: 0 = still running, 1 = completed, negative = errno
647 + * NOTE: INDEX register must be set for EP
648 + */
649 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
650 +{
651 + struct jz4740_udc *dev = ep->dev;
652 + uint32_t csr;
653 + unsigned count, is_short;
654 +
655 + /* make sure there's a packet in the FIFO. */
656 + csr = usb_readb(dev, ep->csr);
657 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
658 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
659 + return -EINVAL;
660 + }
661 +
662 + /* read all bytes from this packet */
663 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
664 +
665 + is_short = (count < ep->ep.maxpacket);
666 +
667 + count = read_packet(ep, req, count);
668 +
669 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
670 + ep->ep.name, csr, count,
671 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
672 +
673 + /* Clear OutPktRdy */
674 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
675 +
676 + /* completion */
677 + if (is_short || req->req.actual == req->req.length) {
678 + done(ep, req, 0);
679 +
680 + if (list_empty(&ep->queue))
681 + pio_irq_disable(ep);
682 + return 1;
683 + }
684 +
685 + /* finished that packet. the next one may be waiting... */
686 + return 0;
687 +}
688 +
689 +/*
690 + * done - retire a request; caller blocked irqs
691 + * INDEX register is preserved to keep same
692 + */
693 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
694 +{
695 + unsigned int stopped = ep->stopped;
696 + uint32_t index;
697 +
698 + DEBUG("%s, %p\n", __FUNCTION__, ep);
699 + list_del_init(&req->queue);
700 +
701 + if (likely(req->req.status == -EINPROGRESS))
702 + req->req.status = status;
703 + else
704 + status = req->req.status;
705 +
706 + if (status && status != -ESHUTDOWN)
707 + DEBUG("complete %s req %p stat %d len %u/%u\n",
708 + ep->ep.name, &req->req, status,
709 + req->req.actual, req->req.length);
710 +
711 + /* don't modify queue heads during completion callback */
712 + ep->stopped = 1;
713 + /* Read current index (completion may modify it) */
714 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
715 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
716 +
717 + req->req.complete(&ep->ep, &req->req);
718 +
719 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
720 + /* Restore index */
721 + jz_udc_set_index(ep->dev, index);
722 + ep->stopped = stopped;
723 +}
724 +
725 +static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
726 +{
727 + if (ep_is_in(ep))
728 + return JZ_REG_UDC_INTRINE;
729 + else
730 + return JZ_REG_UDC_INTROUTE;
731 +}
732 +
733 +/** Enable EP interrupt */
734 +static void pio_irq_enable(struct jz4740_ep *ep)
735 +{
736 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
737 +
738 + usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
739 +}
740 +
741 +/** Disable EP interrupt */
742 +static void pio_irq_disable(struct jz4740_ep *ep)
743 +{
744 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
745 +
746 + usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
747 +}
748 +
749 +/*
750 + * nuke - dequeue ALL requests
751 + */
752 +static void nuke(struct jz4740_ep *ep, int status)
753 +{
754 + struct jz4740_request *req;
755 +
756 + DEBUG("%s, %p\n", __FUNCTION__, ep);
757 +
758 + /* Flush FIFO */
759 + flush(ep);
760 +
761 + /* called with irqs blocked */
762 + while (!list_empty(&ep->queue)) {
763 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
764 + done(ep, req, status);
765 + }
766 +
767 + /* Disable IRQ if EP is enabled (has descriptor) */
768 + if (ep->desc)
769 + pio_irq_disable(ep);
770 +}
771 +
772 +/** Flush EP FIFO
773 + * NOTE: INDEX register must be set before this call
774 + */
775 +static void flush(struct jz4740_ep *ep)
776 +{
777 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
778 +
779 + switch (ep->type) {
780 + case ep_bulk_in:
781 + case ep_interrupt:
782 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
783 + break;
784 + case ep_bulk_out:
785 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
786 + break;
787 + case ep_control:
788 + break;
789 + }
790 +}
791 +
792 +/**
793 + * jz4740_in_epn - handle IN interrupt
794 + */
795 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
796 +{
797 + uint32_t csr;
798 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
799 + struct jz4740_request *req;
800 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
801 +
802 + jz_udc_select_ep(ep);
803 +
804 + csr = usb_readb(dev, ep->csr);
805 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
806 +
807 + if (csr & USB_INCSR_SENTSTALL) {
808 + DEBUG("USB_INCSR_SENTSTALL\n");
809 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
810 + return;
811 + }
812 +
813 + if (!ep->desc) {
814 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
815 + return;
816 + }
817 +
818 + if (!list_empty(&ep->queue)) {
819 + req = list_first_entry(&ep->queue, struct jz4740_request, queue);
820 + write_fifo(ep, req);
821 + }
822 +}
823 +
824 +/*
825 + * Bulk OUT (recv)
826 + */
827 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
828 +{
829 + struct jz4740_ep *ep = &dev->ep[ep_idx];
830 + struct jz4740_request *req;
831 +
832 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
833 +
834 + jz_udc_select_ep(ep);
835 + if (ep->desc) {
836 + uint32_t csr;
837 +
838 + while ((csr = usb_readb(dev, ep->csr)) &
839 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
840 + DEBUG("%s: %x\n", __FUNCTION__, csr);
841 +
842 + if (csr & USB_OUTCSR_SENTSTALL) {
843 + DEBUG("%s: stall sent, flush fifo\n",
844 + __FUNCTION__);
845 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
846 + flush(ep);
847 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
848 + if (list_empty(&ep->queue))
849 + req = 0;
850 + else
851 + req =
852 + list_entry(ep->queue.next,
853 + struct jz4740_request,
854 + queue);
855 +
856 + if (!req) {
857 + DEBUG("%s: NULL REQ %d\n",
858 + __FUNCTION__, ep_idx);
859 + break;
860 + } else {
861 + read_fifo(ep, req);
862 + }
863 + }
864 + }
865 + } else {
866 + /* Throw packet away.. */
867 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
868 + flush(ep);
869 + }
870 +}
871 +
872 +/** Halt specific EP
873 + * Return 0 if success
874 + * NOTE: Sets INDEX register to EP !
875 + */
876 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
877 +{
878 + struct jz4740_udc *dev;
879 + struct jz4740_ep *ep;
880 + unsigned long flags;
881 +
882 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
883 +
884 + ep = container_of(_ep, struct jz4740_ep, ep);
885 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
886 + DEBUG("%s, bad ep\n", __FUNCTION__);
887 + return -EINVAL;
888 + }
889 +
890 + dev = ep->dev;
891 +
892 + spin_lock_irqsave(&dev->lock, flags);
893 +
894 + jz_udc_select_ep(ep);
895 +
896 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
897 +
898 + if (ep_index(ep) == 0) {
899 + /* EP0 */
900 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
901 + } else if (ep_is_in(ep)) {
902 + uint32_t csr = usb_readb(dev, ep->csr);
903 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
904 + || !list_empty(&ep->queue))) {
905 + /*
906 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
907 + * if any transfer requests are still queued, or if the controller
908 + * FIFO still holds bytes that the host hasn\92t collected.
909 + */
910 + spin_unlock_irqrestore(&dev->lock, flags);
911 + DEBUG
912 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
913 + (csr & USB_INCSR_FFNOTEMPT),
914 + !list_empty(&ep->queue));
915 + return -EAGAIN;
916 + }
917 + flush(ep);
918 + if (value) {
919 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
920 + } else {
921 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
922 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
923 + }
924 + } else {
925 +
926 + flush(ep);
927 + if (value) {
928 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
929 + } else {
930 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
931 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
932 + }
933 + }
934 +
935 + ep->stopped = value;
936 +
937 + spin_unlock_irqrestore(&dev->lock, flags);
938 +
939 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
940 +
941 + return 0;
942 +}
943 +
944 +
945 +static int jz4740_ep_enable(struct usb_ep *_ep,
946 + const struct usb_endpoint_descriptor *desc)
947 +{
948 + struct jz4740_ep *ep;
949 + struct jz4740_udc *dev;
950 + unsigned long flags;
951 + uint32_t max, csrh = 0;
952 +
953 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
954 +
955 + if (!_ep || !desc)
956 + return -EINVAL;
957 +
958 + ep = container_of(_ep, struct jz4740_ep, ep);
959 + if (ep->desc || ep->type == ep_control
960 + || desc->bDescriptorType != USB_DT_ENDPOINT
961 + || ep->bEndpointAddress != desc->bEndpointAddress) {
962 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
963 + return -EINVAL;
964 + }
965 +
966 + /* xfer types must match, except that interrupt ~= bulk */
967 + if (ep->bmAttributes != desc->bmAttributes
968 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
969 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
970 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
971 + return -EINVAL;
972 + }
973 +
974 + dev = ep->dev;
975 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
976 + DEBUG("%s, bogus device state\n", __FUNCTION__);
977 + return -ESHUTDOWN;
978 + }
979 +
980 + max = le16_to_cpu(desc->wMaxPacketSize);
981 +
982 + spin_lock_irqsave(&ep->dev->lock, flags);
983 +
984 + /* Configure the endpoint */
985 + jz_udc_select_ep(ep);
986 + if (ep_is_in(ep)) {
987 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
988 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
989 + case USB_ENDPOINT_XFER_BULK:
990 + case USB_ENDPOINT_XFER_INT:
991 + csrh &= ~USB_INCSRH_ISO;
992 + break;
993 + case USB_ENDPOINT_XFER_ISOC:
994 + csrh |= USB_INCSRH_ISO;
995 + break;
996 + }
997 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
998 + }
999 + else {
1000 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1001 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1002 + case USB_ENDPOINT_XFER_BULK:
1003 + csrh &= ~USB_OUTCSRH_ISO;
1004 + break;
1005 + case USB_ENDPOINT_XFER_INT:
1006 + csrh &= ~USB_OUTCSRH_ISO;
1007 + csrh |= USB_OUTCSRH_DNYT;
1008 + break;
1009 + case USB_ENDPOINT_XFER_ISOC:
1010 + csrh |= USB_OUTCSRH_ISO;
1011 + break;
1012 + }
1013 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1014 + }
1015 +
1016 +
1017 + ep->stopped = 0;
1018 + ep->desc = desc;
1019 + ep->ep.maxpacket = max;
1020 +
1021 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1022 +
1023 + /* Reset halt state (does flush) */
1024 + jz4740_set_halt(_ep, 0);
1025 +
1026 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1027 +
1028 + return 0;
1029 +}
1030 +
1031 +/** Disable EP
1032 + * NOTE: Sets INDEX register
1033 + */
1034 +static int jz4740_ep_disable(struct usb_ep *_ep)
1035 +{
1036 + struct jz4740_ep *ep;
1037 + unsigned long flags;
1038 +
1039 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1040 +
1041 + ep = container_of(_ep, struct jz4740_ep, ep);
1042 + if (!_ep || !ep->desc) {
1043 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1044 + _ep ? ep->ep.name : NULL);
1045 + return -EINVAL;
1046 + }
1047 +
1048 + spin_lock_irqsave(&ep->dev->lock, flags);
1049 +
1050 + jz_udc_select_ep(ep);
1051 +
1052 + /* Nuke all pending requests (does flush) */
1053 + nuke(ep, -ESHUTDOWN);
1054 +
1055 + /* Disable ep IRQ */
1056 + pio_irq_disable(ep);
1057 +
1058 + ep->desc = 0;
1059 + ep->stopped = 1;
1060 +
1061 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1062 +
1063 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1064 + return 0;
1065 +}
1066 +
1067 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1068 +{
1069 + struct jz4740_request *req;
1070 +
1071 + req = kzalloc(sizeof(*req), gfp_flags);
1072 + if (!req)
1073 + return NULL;
1074 +
1075 + INIT_LIST_HEAD(&req->queue);
1076 +
1077 + return &req->req;
1078 +}
1079 +
1080 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1081 +{
1082 + struct jz4740_request *req;
1083 +
1084 + req = container_of(_req, struct jz4740_request, req);
1085 + WARN_ON(!list_empty(&req->queue));
1086 +
1087 + kfree(req);
1088 +}
1089 +
1090 +/*--------------------------------------------------------------------*/
1091 +
1092 +/** Queue one request
1093 + * Kickstart transfer if needed
1094 + * NOTE: Sets INDEX register
1095 + */
1096 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1097 + gfp_t gfp_flags)
1098 +{
1099 + struct jz4740_request *req;
1100 + struct jz4740_ep *ep;
1101 + struct jz4740_udc *dev;
1102 +
1103 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1104 +
1105 + req = container_of(_req, struct jz4740_request, req);
1106 + if (unlikely
1107 + (!_req || !_req->complete || !_req->buf
1108 + || !list_empty(&req->queue))) {
1109 + DEBUG("%s, bad params\n", __FUNCTION__);
1110 + return -EINVAL;
1111 + }
1112 +
1113 + ep = container_of(_ep, struct jz4740_ep, ep);
1114 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1115 + DEBUG("%s, bad ep\n", __FUNCTION__);
1116 + return -EINVAL;
1117 + }
1118 +
1119 + dev = ep->dev;
1120 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1121 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1122 + return -ESHUTDOWN;
1123 + }
1124 +
1125 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1126 + _req->buf);
1127 +
1128 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1129 +
1130 + _req->status = -EINPROGRESS;
1131 + _req->actual = 0;
1132 +
1133 + /* kickstart this i/o queue? */
1134 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1135 + ep->stopped);
1136 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1137 + uint32_t csr;
1138 +
1139 + if (unlikely(ep_index(ep) == 0)) {
1140 + /* EP0 */
1141 + list_add_tail(&req->queue, &ep->queue);
1142 + jz4740_ep0_kick(dev, ep);
1143 + req = 0;
1144 + }
1145 + else if (ep_is_in(ep)) {
1146 + /* EP1 & EP2 */
1147 + jz_udc_select_ep(ep);
1148 + csr = usb_readb(dev, ep->csr);
1149 + pio_irq_enable(ep);
1150 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1151 + if (write_fifo(ep, req) == 1)
1152 + req = 0;
1153 + }
1154 + } else {
1155 + /* EP1 */
1156 + jz_udc_select_ep(ep);
1157 + csr = usb_readb(dev, ep->csr);
1158 + pio_irq_enable(ep);
1159 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1160 + if (read_fifo(ep, req) == 1)
1161 + req = 0;
1162 + }
1163 + }
1164 + }
1165 +
1166 + /* pio or dma irq handler advances the queue. */
1167 + if (likely(req != 0))
1168 + list_add_tail(&req->queue, &ep->queue);
1169 +
1170 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1171 +
1172 + return 0;
1173 +}
1174 +
1175 +/* dequeue JUST ONE request */
1176 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1177 +{
1178 + struct jz4740_ep *ep;
1179 + struct jz4740_request *req;
1180 + unsigned long flags;
1181 +
1182 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1183 +
1184 + ep = container_of(_ep, struct jz4740_ep, ep);
1185 + if (!_ep || ep->type == ep_control)
1186 + return -EINVAL;
1187 +
1188 + spin_lock_irqsave(&ep->dev->lock, flags);
1189 +
1190 + /* make sure it's actually queued on this endpoint */
1191 + list_for_each_entry(req, &ep->queue, queue) {
1192 + if (&req->req == _req)
1193 + break;
1194 + }
1195 + if (&req->req != _req) {
1196 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1197 + return -EINVAL;
1198 + }
1199 + done(ep, req, -ECONNRESET);
1200 +
1201 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1202 + return 0;
1203 +}
1204 +
1205 +/** Return bytes in EP FIFO
1206 + * NOTE: Sets INDEX register to EP
1207 + */
1208 +static int jz4740_fifo_status(struct usb_ep *_ep)
1209 +{
1210 + uint32_t csr;
1211 + int count = 0;
1212 + struct jz4740_ep *ep;
1213 + unsigned long flags;
1214 +
1215 + ep = container_of(_ep, struct jz4740_ep, ep);
1216 + if (!_ep) {
1217 + DEBUG("%s, bad ep\n", __FUNCTION__);
1218 + return -ENODEV;
1219 + }
1220 +
1221 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1222 +
1223 + /* LPD can't report unclaimed bytes from IN fifos */
1224 + if (ep_is_in(ep))
1225 + return -EOPNOTSUPP;
1226 +
1227 + spin_lock_irqsave(&ep->dev->lock, flags);
1228 + jz_udc_select_ep(ep);
1229 +
1230 + csr = usb_readb(ep->dev, ep->csr);
1231 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1232 + csr & 0x1) {
1233 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1234 + }
1235 +
1236 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1237 +
1238 + return count;
1239 +}
1240 +
1241 +/** Flush EP FIFO
1242 + * NOTE: Sets INDEX register to EP
1243 + */
1244 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1245 +{
1246 + struct jz4740_ep *ep;
1247 + unsigned long flags;
1248 +
1249 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1250 +
1251 + ep = container_of(_ep, struct jz4740_ep, ep);
1252 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1253 + DEBUG("%s, bad ep\n", __FUNCTION__);
1254 + return;
1255 + }
1256 +
1257 + spin_lock_irqsave(&ep->dev->lock, flags);
1258 +
1259 + jz_udc_select_ep(ep);
1260 + flush(ep);
1261 +
1262 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1263 +}
1264 +
1265 +/****************************************************************/
1266 +/* End Point 0 related functions */
1267 +/****************************************************************/
1268 +
1269 +/* return: 0 = still running, 1 = completed, negative = errno */
1270 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1271 +{
1272 + uint32_t max;
1273 + unsigned count;
1274 + int is_last;
1275 +
1276 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1277 + max = ep_maxpacket(ep);
1278 +
1279 + count = write_packet(ep, req, max);
1280 +
1281 + /* last packet is usually short (or a zlp) */
1282 + if (unlikely(count != max))
1283 + is_last = 1;
1284 + else {
1285 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1286 + is_last = 0;
1287 + else
1288 + is_last = 1;
1289 + }
1290 +
1291 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1292 + ep->ep.name, count,
1293 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1294 +
1295 + /* requests complete when all IN data is in the FIFO */
1296 + if (is_last) {
1297 + done(ep, req, 0);
1298 + return 1;
1299 + }
1300 +
1301 + return 0;
1302 +}
1303 +
1304 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1305 + unsigned char *cp, int max)
1306 +{
1307 + int bytes;
1308 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1309 +
1310 + if (count > max)
1311 + count = max;
1312 + bytes = count;
1313 + while (count--)
1314 + *cp++ = usb_readb(ep->dev, ep->fifo);
1315 +
1316 + return bytes;
1317 +}
1318 +
1319 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1320 + unsigned char *cp, int count)
1321 +{
1322 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1323 + while (count--)
1324 + usb_writeb(ep->dev, ep->fifo, *cp++);
1325 +}
1326 +
1327 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1328 +{
1329 + struct jz4740_udc *dev = ep->dev;
1330 + uint32_t csr;
1331 + uint8_t *buf;
1332 + unsigned bufferspace, count, is_short;
1333 +
1334 + DEBUG_EP0("%s\n", __FUNCTION__);
1335 +
1336 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1337 + if (!(csr & USB_CSR0_OUTPKTRDY))
1338 + return 0;
1339 +
1340 + buf = req->req.buf + req->req.actual;
1341 + prefetchw(buf);
1342 + bufferspace = req->req.length - req->req.actual;
1343 +
1344 + /* read all bytes from this packet */
1345 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1346 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1347 + req->req.actual += min(count, bufferspace);
1348 + } else /* zlp */
1349 + count = 0;
1350 +
1351 + is_short = (count < ep->ep.maxpacket);
1352 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1353 + ep->ep.name, csr, count,
1354 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1355 +
1356 + while (likely(count-- != 0)) {
1357 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1358 +
1359 + if (unlikely(bufferspace == 0)) {
1360 + /* this happens when the driver's buffer
1361 + * is smaller than what the host sent.
1362 + * discard the extra data.
1363 + */
1364 + if (req->req.status != -EOVERFLOW)
1365 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1366 + count);
1367 + req->req.status = -EOVERFLOW;
1368 + } else {
1369 + *buf++ = byte;
1370 + bufferspace--;
1371 + }
1372 + }
1373 +
1374 + /* completion */
1375 + if (is_short || req->req.actual == req->req.length) {
1376 + done(ep, req, 0);
1377 + return 1;
1378 + }
1379 +
1380 + /* finished that packet. the next one may be waiting... */
1381 + return 0;
1382 +}
1383 +
1384 +/**
1385 + * udc_set_address - set the USB address for this device
1386 + * @address:
1387 + *
1388 + * Called from control endpoint function after it decodes a set address setup packet.
1389 + */
1390 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1391 +{
1392 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1393 +
1394 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1395 +}
1396 +
1397 +/*
1398 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1399 + * - if error
1400 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1401 + * - else
1402 + * set USB_CSR0_SVDOUTPKTRDY bit
1403 + if last set USB_CSR0_DATAEND bit
1404 + */
1405 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1406 +{
1407 + struct jz4740_request *req;
1408 + struct jz4740_ep *ep = &dev->ep[0];
1409 + int ret;
1410 +
1411 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1412 +
1413 + if (list_empty(&ep->queue))
1414 + req = 0;
1415 + else
1416 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1417 +
1418 + if (req) {
1419 + if (req->req.length == 0) {
1420 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1421 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1422 + dev->ep0state = WAIT_FOR_SETUP;
1423 + return;
1424 + } else if (kickstart) {
1425 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1426 + return;
1427 + }
1428 + ret = read_fifo_ep0(ep, req);
1429 + if (ret) {
1430 + /* Done! */
1431 + DEBUG_EP0("%s: finished, waiting for status\n",
1432 + __FUNCTION__);
1433 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1434 + dev->ep0state = WAIT_FOR_SETUP;
1435 + } else {
1436 + /* Not done yet.. */
1437 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1438 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1439 + }
1440 + } else {
1441 + DEBUG_EP0("NO REQ??!\n");
1442 + }
1443 +}
1444 +
1445 +/*
1446 + * DATA_STATE_XMIT
1447 + */
1448 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1449 +{
1450 + struct jz4740_request *req;
1451 + struct jz4740_ep *ep = &dev->ep[0];
1452 + int ret, need_zlp = 0;
1453 +
1454 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1455 +
1456 + if (list_empty(&ep->queue))
1457 + req = 0;
1458 + else
1459 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1460 +
1461 + if (!req) {
1462 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1463 + return 0;
1464 + }
1465 +
1466 + if (req->req.length == 0) {
1467 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1468 + dev->ep0state = WAIT_FOR_SETUP;
1469 + return 1;
1470 + }
1471 +
1472 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1473 + /* Next write will end with the packet size, */
1474 + /* so we need zero-length-packet */
1475 + need_zlp = 1;
1476 + }
1477 +
1478 + ret = write_fifo_ep0(ep, req);
1479 +
1480 + if (ret == 1 && !need_zlp) {
1481 + /* Last packet */
1482 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1483 +
1484 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1485 + dev->ep0state = WAIT_FOR_SETUP;
1486 + } else {
1487 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1488 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1489 + }
1490 +
1491 + if (need_zlp) {
1492 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1493 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1494 + dev->ep0state = DATA_STATE_NEED_ZLP;
1495 + }
1496 +
1497 + return 1;
1498 +}
1499 +
1500 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1501 + struct usb_ctrlrequest *ctrl)
1502 +{
1503 + struct jz4740_ep *ep0 = &dev->ep[0];
1504 + struct jz4740_ep *qep;
1505 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1506 + uint16_t val = 0;
1507 +
1508 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1509 +
1510 + if (reqtype == USB_RECIP_INTERFACE) {
1511 + /* This is not supported.
1512 + * And according to the USB spec, this one does nothing..
1513 + * Just return 0
1514 + */
1515 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1516 + } else if (reqtype == USB_RECIP_DEVICE) {
1517 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1518 + val |= (1 << 0); /* Self powered */
1519 + /*val |= (1<<1); *//* Remote wakeup */
1520 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1521 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1522 +
1523 + DEBUG_SETUP
1524 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1525 + ep_num, ctrl->wLength);
1526 +
1527 + if (ctrl->wLength > 2 || ep_num > 3)
1528 + return -EOPNOTSUPP;
1529 +
1530 + qep = &dev->ep[ep_num];
1531 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1532 + && ep_index(qep) != 0) {
1533 + return -EOPNOTSUPP;
1534 + }
1535 +
1536 + jz_udc_select_ep(qep);
1537 +
1538 + /* Return status on next IN token */
1539 + switch (qep->type) {
1540 + case ep_control:
1541 + val =
1542 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1543 + USB_CSR0_SENDSTALL;
1544 + break;
1545 + case ep_bulk_in:
1546 + case ep_interrupt:
1547 + val =
1548 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1549 + USB_INCSR_SENDSTALL;
1550 + break;
1551 + case ep_bulk_out:
1552 + val =
1553 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1554 + USB_OUTCSR_SENDSTALL;
1555 + break;
1556 + }
1557 +
1558 + /* Back to EP0 index */
1559 + jz_udc_set_index(dev, 0);
1560 +
1561 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1562 + ctrl->wIndex, val);
1563 + } else {
1564 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1565 + return -EOPNOTSUPP;
1566 + }
1567 +
1568 + /* Clear "out packet ready" */
1569 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1570 + /* Put status to FIFO */
1571 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1572 + /* Issue "In packet ready" */
1573 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1574 +
1575 + return 0;
1576 +}
1577 +
1578 +/*
1579 + * WAIT_FOR_SETUP (OUTPKTRDY)
1580 + * - read data packet from EP0 FIFO
1581 + * - decode command
1582 + * - if error
1583 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1584 + * - else
1585 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1586 + */
1587 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1588 +{
1589 + struct jz4740_ep *ep = &dev->ep[0];
1590 + struct usb_ctrlrequest ctrl;
1591 + int i;
1592 +
1593 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1594 +
1595 + /* Nuke all previous transfers */
1596 + nuke(ep, -EPROTO);
1597 +
1598 + /* read control req from fifo (8 bytes) */
1599 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1600 +
1601 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1602 + ctrl.bRequestType, ctrl.bRequest,
1603 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1604 +
1605 + /* Set direction of EP0 */
1606 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1607 + ep->bEndpointAddress |= USB_DIR_IN;
1608 + } else {
1609 + ep->bEndpointAddress &= ~USB_DIR_IN;
1610 + }
1611 +
1612 + /* Handle some SETUP packets ourselves */
1613 + switch (ctrl.bRequest) {
1614 + case USB_REQ_SET_ADDRESS:
1615 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1616 + break;
1617 +
1618 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1619 + udc_set_address(dev, ctrl.wValue);
1620 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1621 + return;
1622 +
1623 + case USB_REQ_SET_CONFIGURATION:
1624 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1625 + break;
1626 +
1627 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1628 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1629 +
1630 + /* Enable RESUME and SUSPEND interrupts */
1631 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1632 + break;
1633 +
1634 + case USB_REQ_SET_INTERFACE:
1635 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1636 + break;
1637 +
1638 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1639 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1640 + break;
1641 +
1642 + case USB_REQ_GET_STATUS:
1643 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1644 + return;
1645 +
1646 + case USB_REQ_CLEAR_FEATURE:
1647 + case USB_REQ_SET_FEATURE:
1648 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1649 + struct jz4740_ep *qep;
1650 + int ep_num = (ctrl.wIndex & 0x0f);
1651 +
1652 + /* Support only HALT feature */
1653 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1654 + || ep_num > 3 || ep_num < 1)
1655 + break;
1656 +
1657 + qep = &dev->ep[ep_num];
1658 + spin_unlock(&dev->lock);
1659 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1660 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1661 + ep_num);
1662 + jz4740_set_halt(&qep->ep, 1);
1663 + } else {
1664 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1665 + ep_num);
1666 + jz4740_set_halt(&qep->ep, 0);
1667 + }
1668 + spin_lock(&dev->lock);
1669 +
1670 + jz_udc_set_index(dev, 0);
1671 +
1672 + /* Reply with a ZLP on next IN token */
1673 + usb_setb(dev, JZ_REG_UDC_CSR0,
1674 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1675 + return;
1676 + }
1677 + break;
1678 +
1679 + default:
1680 + break;
1681 + }
1682 +
1683 + /* gadget drivers see class/vendor specific requests,
1684 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1685 + * and more.
1686 + */
1687 + if (dev->driver) {
1688 + /* device-2-host (IN) or no data setup command, process immediately */
1689 + spin_unlock(&dev->lock);
1690 +
1691 + i = dev->driver->setup(&dev->gadget, &ctrl);
1692 + spin_lock(&dev->lock);
1693 +
1694 + if (unlikely(i < 0)) {
1695 + /* setup processing failed, force stall */
1696 + DEBUG_SETUP
1697 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1698 + i);
1699 + jz_udc_set_index(dev, 0);
1700 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1701 +
1702 + /* ep->stopped = 1; */
1703 + dev->ep0state = WAIT_FOR_SETUP;
1704 + }
1705 + else {
1706 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1707 +/* if (!ctrl.wLength) {
1708 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1709 + }*/
1710 + }
1711 + }
1712 +}
1713 +
1714 +/*
1715 + * DATA_STATE_NEED_ZLP
1716 + */
1717 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1718 +{
1719 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1720 +
1721 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1722 + dev->ep0state = WAIT_FOR_SETUP;
1723 +}
1724 +
1725 +/*
1726 + * handle ep0 interrupt
1727 + */
1728 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1729 +{
1730 + struct jz4740_ep *ep = &dev->ep[0];
1731 + uint32_t csr;
1732 +
1733 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1734 + /* Set index 0 */
1735 + jz_udc_set_index(dev, 0);
1736 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1737 +
1738 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1739 +
1740 + /*
1741 + * if SENT_STALL is set
1742 + * - clear the SENT_STALL bit
1743 + */
1744 + if (csr & USB_CSR0_SENTSTALL) {
1745 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1746 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1747 + nuke(ep, -ECONNABORTED);
1748 + dev->ep0state = WAIT_FOR_SETUP;
1749 + return;
1750 + }
1751 +
1752 + /*
1753 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1754 + * - fill EP0 FIFO
1755 + * - if last packet
1756 + * - set IN_PKT_RDY | DATA_END
1757 + * - else
1758 + * set IN_PKT_RDY
1759 + */
1760 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1761 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1762 + __FUNCTION__);
1763 +
1764 + switch (dev->ep0state) {
1765 + case DATA_STATE_XMIT:
1766 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1767 + jz4740_ep0_in(dev, csr);
1768 + return;
1769 + case DATA_STATE_NEED_ZLP:
1770 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1771 + jz4740_ep0_in_zlp(dev, csr);
1772 + return;
1773 + default:
1774 + /* Stall? */
1775 +// DEBUG_EP0("Odd state!! state = %s\n",
1776 +// state_names[dev->ep0state]);
1777 + dev->ep0state = WAIT_FOR_SETUP;
1778 + /* nuke(ep, 0); */
1779 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1780 +// break;
1781 + return;
1782 + }
1783 + }
1784 +
1785 + /*
1786 + * if SETUPEND is set
1787 + * - abort the last transfer
1788 + * - set SERVICED_SETUP_END_BIT
1789 + */
1790 + if (csr & USB_CSR0_SETUPEND) {
1791 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1792 +
1793 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1794 + nuke(ep, 0);
1795 + dev->ep0state = WAIT_FOR_SETUP;
1796 + }
1797 +
1798 + /*
1799 + * if USB_CSR0_OUTPKTRDY is set
1800 + * - read data packet from EP0 FIFO
1801 + * - decode command
1802 + * - if error
1803 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1804 + * - else
1805 + * set SVDOUTPKTRDY | DATAEND bits
1806 + */
1807 + if (csr & USB_CSR0_OUTPKTRDY) {
1808 +
1809 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1810 + csr);
1811 +
1812 + switch (dev->ep0state) {
1813 + case WAIT_FOR_SETUP:
1814 + DEBUG_EP0("WAIT_FOR_SETUP\n");
1815 + jz4740_ep0_setup(dev, csr);
1816 + break;
1817 +
1818 + case DATA_STATE_RECV:
1819 + DEBUG_EP0("DATA_STATE_RECV\n");
1820 + jz4740_ep0_out(dev, csr, 0);
1821 + break;
1822 +
1823 + default:
1824 + /* send stall? */
1825 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1826 + dev->ep0state);
1827 + break;
1828 + }
1829 + }
1830 +}
1831 +
1832 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1833 +{
1834 + uint32_t csr;
1835 +
1836 + jz_udc_set_index(dev, 0);
1837 +
1838 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1839 +
1840 + /* Clear "out packet ready" */
1841 +
1842 + if (ep_is_in(ep)) {
1843 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1844 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1845 + dev->ep0state = DATA_STATE_XMIT;
1846 + jz4740_ep0_in(dev, csr);
1847 + } else {
1848 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1849 + dev->ep0state = DATA_STATE_RECV;
1850 + jz4740_ep0_out(dev, csr, 1);
1851 + }
1852 +}
1853 +
1854 +/** Handle USB RESET interrupt
1855 + */
1856 +static void jz4740_reset_irq(struct jz4740_udc *dev)
1857 +{
1858 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1859 + USB_SPEED_HIGH : USB_SPEED_FULL;
1860 +
1861 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1862 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1863 +}
1864 +
1865 +/*
1866 + * jz4740 usb device interrupt handler.
1867 + */
1868 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1869 +{
1870 + struct jz4740_udc *jz4740_udc = devid;
1871 + uint8_t index;
1872 +
1873 + uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1874 + uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1875 + uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1876 + uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1877 +
1878 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1879 + return IRQ_HANDLED;
1880 +
1881 +
1882 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1883 + intr_out, intr_in, intr_usb);
1884 +
1885 + spin_lock(&jz4740_udc->lock);
1886 + index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1887 +
1888 + /* Check for resume from suspend mode */
1889 + if ((intr_usb & USB_INTR_RESUME) &&
1890 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1891 + DEBUG("USB resume\n");
1892 + jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1893 + }
1894 +
1895 + /* Check for system interrupts */
1896 + if (intr_usb & USB_INTR_RESET) {
1897 + DEBUG("USB reset\n");
1898 + jz4740_reset_irq(jz4740_udc);
1899 + }
1900 +
1901 + /* Check for endpoint 0 interrupt */
1902 + if (intr_in & USB_INTR_EP0) {
1903 + DEBUG("USB_INTR_EP0 (control)\n");
1904 + jz4740_handle_ep0(jz4740_udc, intr_in);
1905 + }
1906 +
1907 + /* Check for Bulk-IN DMA interrupt */
1908 + if (intr_dma & 0x1) {
1909 + int ep_num;
1910 + struct jz4740_ep *ep;
1911 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1912 + ep = &jz4740_udc->ep[ep_num + 1];
1913 + jz_udc_select_ep(ep);
1914 + usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1915 +/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1916 + }
1917 +
1918 + /* Check for Bulk-OUT DMA interrupt */
1919 + if (intr_dma & 0x2) {
1920 + int ep_num;
1921 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1922 + jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1923 + }
1924 +
1925 + /* Check for each configured endpoint interrupt */
1926 + if (intr_in & USB_INTR_INEP1) {
1927 + DEBUG("USB_INTR_INEP1\n");
1928 + jz4740_in_epn(jz4740_udc, 1, intr_in);
1929 + }
1930 +
1931 + if (intr_in & USB_INTR_INEP2) {
1932 + DEBUG("USB_INTR_INEP2\n");
1933 + jz4740_in_epn(jz4740_udc, 2, intr_in);
1934 + }
1935 +
1936 + if (intr_out & USB_INTR_OUTEP1) {
1937 + DEBUG("USB_INTR_OUTEP1\n");
1938 + jz4740_out_epn(jz4740_udc, 1, intr_out);
1939 + }
1940 +
1941 + /* Check for suspend mode */
1942 + if ((intr_usb & USB_INTR_SUSPEND) &&
1943 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1944 + DEBUG("USB suspend\n");
1945 + jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1946 + /* Host unloaded from us, can do something, such as flushing
1947 + the NAND block cache etc. */
1948 + }
1949 +
1950 + jz_udc_set_index(jz4740_udc, index);
1951 +
1952 + spin_unlock(&jz4740_udc->lock);
1953 +
1954 + return IRQ_HANDLED;
1955 +}
1956 +
1957 +
1958 +
1959 +/*-------------------------------------------------------------------------*/
1960 +
1961 +
1962 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1963 +{
1964 + return container_of(gadget, struct jz4740_udc, gadget);
1965 +}
1966 +
1967 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1968 +{
1969 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1970 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1971 +}
1972 +
1973 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1974 +{
1975 + /* host may not have enabled remote wakeup */
1976 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1977 + return -EHOSTUNREACH;
1978 + udc_set_mask_UDCCR(UDCCR_RSM); */
1979 + return -ENOTSUPP;
1980 +}
1981 +
1982 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1983 +{
1984 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
1985 + unsigned long flags;
1986 +
1987 + local_irq_save(flags);
1988 +
1989 + if (on) {
1990 + udc->state = UDC_STATE_ENABLE;
1991 + udc_enable(udc);
1992 + } else {
1993 + udc->state = UDC_STATE_DISABLE;
1994 + udc_disable(udc);
1995 + }
1996 +
1997 + local_irq_restore(flags);
1998 +
1999 + return 0;
2000 +}
2001 +
2002 +
2003 +static const struct usb_gadget_ops jz4740_udc_ops = {
2004 + .get_frame = jz4740_udc_get_frame,
2005 + .wakeup = jz4740_udc_wakeup,
2006 + .pullup = jz4740_udc_pullup,
2007 + .start = jz4740_udc_start,
2008 + .stop = jz4740_udc_stop,
2009 +};
2010 +
2011 +static struct usb_ep_ops jz4740_ep_ops = {
2012 + .enable = jz4740_ep_enable,
2013 + .disable = jz4740_ep_disable,
2014 +
2015 + .alloc_request = jz4740_alloc_request,
2016 + .free_request = jz4740_free_request,
2017 +
2018 + .queue = jz4740_queue,
2019 + .dequeue = jz4740_dequeue,
2020 +
2021 + .set_halt = jz4740_set_halt,
2022 + .fifo_status = jz4740_fifo_status,
2023 + .fifo_flush = jz4740_fifo_flush,
2024 +};
2025 +
2026 +
2027 +/*-------------------------------------------------------------------------*/
2028 +
2029 +static struct jz4740_udc jz4740_udc_controller = {
2030 + .gadget = {
2031 + .ops = &jz4740_udc_ops,
2032 + .ep0 = &jz4740_udc_controller.ep[0].ep,
2033 + .name = "jz4740-udc",
2034 + .dev = {
2035 + .init_name = "gadget",
2036 + },
2037 + },
2038 +
2039 + /* control endpoint */
2040 + .ep[0] = {
2041 + .ep = {
2042 + .name = "ep0",
2043 + .ops = &jz4740_ep_ops,
2044 + .maxpacket = EP0_MAXPACKETSIZE,
2045 + },
2046 + .dev = &jz4740_udc_controller,
2047 +
2048 + .bEndpointAddress = 0,
2049 + .bmAttributes = 0,
2050 +
2051 + .type = ep_control,
2052 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2053 + .csr = JZ_REG_UDC_CSR0,
2054 + },
2055 +
2056 + /* bulk out endpoint */
2057 + .ep[1] = {
2058 + .ep = {
2059 + .name = "ep1out-bulk",
2060 + .ops = &jz4740_ep_ops,
2061 + .maxpacket = EPBULK_MAXPACKETSIZE,
2062 + },
2063 + .dev = &jz4740_udc_controller,
2064 +
2065 + .bEndpointAddress = 1,
2066 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2067 +
2068 + .type = ep_bulk_out,
2069 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2070 + .csr = JZ_REG_UDC_OUTCSR,
2071 + },
2072 +
2073 + /* bulk in endpoint */
2074 + .ep[2] = {
2075 + .ep = {
2076 + .name = "ep1in-bulk",
2077 + .ops = &jz4740_ep_ops,
2078 + .maxpacket = EPBULK_MAXPACKETSIZE,
2079 + },
2080 + .dev = &jz4740_udc_controller,
2081 +
2082 + .bEndpointAddress = 1 | USB_DIR_IN,
2083 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2084 +
2085 + .type = ep_bulk_in,
2086 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2087 + .csr = JZ_REG_UDC_INCSR,
2088 + },
2089 +
2090 + /* interrupt in endpoint */
2091 + .ep[3] = {
2092 + .ep = {
2093 + .name = "ep2in-int",
2094 + .ops = &jz4740_ep_ops,
2095 + .maxpacket = EPINTR_MAXPACKETSIZE,
2096 + },
2097 + .dev = &jz4740_udc_controller,
2098 +
2099 + .bEndpointAddress = 2 | USB_DIR_IN,
2100 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2101 +
2102 + .type = ep_interrupt,
2103 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2104 + .csr = JZ_REG_UDC_INCSR,
2105 + },
2106 +};
2107 +
2108 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2109 +{
2110 + struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2111 + int ret;
2112 +
2113 + spin_lock_init(&jz4740_udc->lock);
2114 +
2115 + jz4740_udc->dev = &pdev->dev;
2116 + jz4740_udc->gadget.dev.parent = &pdev->dev;
2117 + jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2118 +
2119 + ret = device_register(&jz4740_udc->gadget.dev);
2120 + if (ret)
2121 + return ret;
2122 +
2123 + jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2124 + if (IS_ERR(jz4740_udc->clk)) {
2125 + ret = PTR_ERR(jz4740_udc->clk);
2126 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2127 + goto err_device_unregister;
2128 + }
2129 +
2130 + platform_set_drvdata(pdev, jz4740_udc);
2131 +
2132 + jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2133 +
2134 + if (!jz4740_udc->mem) {
2135 + ret = -ENOENT;
2136 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2137 + goto err_clk_put;
2138 + }
2139 +
2140 + jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2141 + resource_size(jz4740_udc->mem), pdev->name);
2142 +
2143 + if (!jz4740_udc->mem) {
2144 + ret = -EBUSY;
2145 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2146 + goto err_device_unregister;
2147 + }
2148 +
2149 + jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2150 +
2151 + if (!jz4740_udc->base) {
2152 + ret = -EBUSY;
2153 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2154 + goto err_release_mem_region;
2155 + }
2156 +
2157 + jz4740_udc->irq = platform_get_irq(pdev, 0);
2158 + ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2159 + jz4740_udc);
2160 + if (ret) {
2161 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2162 + goto err_iounmap;
2163 + }
2164 +
2165 + ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2166 + if (ret) {
2167 + dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2168 + goto err_free_irq;
2169 + }
2170 +
2171 + udc_disable(jz4740_udc);
2172 + udc_reinit(jz4740_udc);
2173 +
2174 + return 0;
2175 +
2176 +err_free_irq:
2177 + free_irq(jz4740_udc->irq, pdev);
2178 +err_iounmap:
2179 + iounmap(jz4740_udc->base);
2180 +err_release_mem_region:
2181 + release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2182 +err_clk_put:
2183 + clk_put(jz4740_udc->clk);
2184 +err_device_unregister:
2185 + device_unregister(&jz4740_udc->gadget.dev);
2186 + platform_set_drvdata(pdev, NULL);
2187 +
2188 + return ret;
2189 +}
2190 +
2191 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2192 +{
2193 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2194 +
2195 + usb_del_gadget_udc(&dev->gadget);
2196 + if (dev->driver)
2197 + return -EBUSY;
2198 +
2199 + udc_disable(dev);
2200 +
2201 + free_irq(dev->irq, dev);
2202 + iounmap(dev->base);
2203 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2204 + clk_put(dev->clk);
2205 +
2206 + platform_set_drvdata(pdev, NULL);
2207 + device_unregister(&dev->gadget.dev);
2208 +
2209 + return 0;
2210 +}
2211 +
2212 +#ifdef CONFIG_PM
2213 +
2214 +static int jz4740_udc_suspend(struct device *dev)
2215 +{
2216 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2217 +
2218 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2219 + udc_disable(jz4740_udc);
2220 +
2221 + return 0;
2222 +}
2223 +
2224 +static int jz4740_udc_resume(struct device *dev)
2225 +{
2226 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2227 +
2228 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2229 + udc_enable(jz4740_udc);
2230 +
2231 + return 0;
2232 +}
2233 +
2234 +static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2235 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2236 +
2237 +#else
2238 +#define JZ4740_UDC_PM_OPS NULL
2239 +#endif
2240 +
2241 +static struct platform_driver udc_driver = {
2242 + .probe = jz4740_udc_probe,
2243 + .remove = __devexit_p(jz4740_udc_remove),
2244 + .driver = {
2245 + .name = "jz-udc",
2246 + .owner = THIS_MODULE,
2247 + .pm = JZ4740_UDC_PM_OPS,
2248 + },
2249 +};
2250 +
2251 +/*-------------------------------------------------------------------------*/
2252 +
2253 +static int __init udc_init (void)
2254 +{
2255 + return platform_driver_register(&udc_driver);
2256 +}
2257 +module_init(udc_init);
2258 +
2259 +static void __exit udc_exit (void)
2260 +{
2261 + platform_driver_unregister(&udc_driver);
2262 +}
2263 +module_exit(udc_exit);
2264 +
2265 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2266 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2267 +MODULE_LICENSE("GPL");
2268 --- /dev/null
2269 +++ b/drivers/usb/gadget/jz4740_udc.h
2270 @@ -0,0 +1,101 @@
2271 +/*
2272 + * linux/drivers/usb/gadget/jz4740_udc.h
2273 + *
2274 + * Ingenic JZ4740 on-chip high speed USB device controller
2275 + *
2276 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2277 + * Author: <jlwei@ingenic.cn>
2278 + *
2279 + * This program is free software; you can redistribute it and/or modify
2280 + * it under the terms of the GNU General Public License as published by
2281 + * the Free Software Foundation; either version 2 of the License, or
2282 + * (at your option) any later version.
2283 + */
2284 +
2285 +#ifndef __USB_GADGET_JZ4740_H__
2286 +#define __USB_GADGET_JZ4740_H__
2287 +
2288 +/*-------------------------------------------------------------------------*/
2289 +
2290 +// Max packet size
2291 +#define EP0_MAXPACKETSIZE 64
2292 +#define EPBULK_MAXPACKETSIZE 512
2293 +#define EPINTR_MAXPACKETSIZE 64
2294 +
2295 +#define UDC_MAX_ENDPOINTS 4
2296 +
2297 +/*-------------------------------------------------------------------------*/
2298 +
2299 +enum ep_type {
2300 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2301 +};
2302 +
2303 +struct jz4740_ep {
2304 + struct usb_ep ep;
2305 + struct jz4740_udc *dev;
2306 +
2307 + const struct usb_endpoint_descriptor *desc;
2308 +
2309 + uint8_t stopped;
2310 + uint8_t bEndpointAddress;
2311 + uint8_t bmAttributes;
2312 +
2313 + enum ep_type type;
2314 + size_t fifo;
2315 + uint32_t csr;
2316 +
2317 + uint32_t reg_addr;
2318 + struct list_head queue;
2319 +};
2320 +
2321 +struct jz4740_request {
2322 + struct usb_request req;
2323 + struct list_head queue;
2324 +};
2325 +
2326 +enum ep0state {
2327 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2328 + DATA_STATE_XMIT, /* data tx stage */
2329 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2330 + WAIT_FOR_OUT_STATUS, /* status stages */
2331 + DATA_STATE_RECV, /* data rx stage */
2332 +};
2333 +
2334 +/* For function binding with UDC Disable - Added by River */
2335 +typedef enum {
2336 + UDC_STATE_ENABLE = 0,
2337 + UDC_STATE_DISABLE,
2338 +}udc_state_t;
2339 +
2340 +struct jz4740_udc {
2341 + struct usb_gadget gadget;
2342 + struct usb_gadget_driver *driver;
2343 + struct device *dev;
2344 + spinlock_t lock;
2345 + unsigned long lock_flags;
2346 +
2347 + enum ep0state ep0state;
2348 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2349 +
2350 + udc_state_t state;
2351 +
2352 + struct resource *mem;
2353 + void __iomem *base;
2354 + int irq;
2355 +
2356 + struct clk *clk;
2357 +};
2358 +
2359 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2360 +
2361 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2362 +{
2363 + return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2364 +}
2365 +
2366 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2367 +{
2368 + return ep->bEndpointAddress & 0xf;
2369 +}
2370 +
2371 +#endif /* __USB_GADGET_JZ4740_H__ */
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