3 @@ -373,6 +373,12 @@ DESCRIPTION
4 .#define bfd_mach_avr5 5
5 .#define bfd_mach_avr51 51
6 .#define bfd_mach_avr6 6
7 +. bfd_arch_avr32, {* Atmel AVR32 *}
8 +.#define bfd_mach_avr32_ap 7000
9 +.#define bfd_mach_avr32_uc 3000
10 +.#define bfd_mach_avr32_ucr1 3001
11 +.#define bfd_mach_avr32_ucr2 3002
12 +.#define bfd_mach_avr32_ucr3 3003
13 . bfd_arch_bfin, {* ADI Blackfin *}
14 .#define bfd_mach_bfin 1
15 . bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}
16 @@ -469,6 +475,7 @@ extern const bfd_arch_info_type bfd_alph
17 extern const bfd_arch_info_type bfd_arc_arch;
18 extern const bfd_arch_info_type bfd_arm_arch;
19 extern const bfd_arch_info_type bfd_avr_arch;
20 +extern const bfd_arch_info_type bfd_avr32_arch;
21 extern const bfd_arch_info_type bfd_bfin_arch;
22 extern const bfd_arch_info_type bfd_cr16_arch;
23 extern const bfd_arch_info_type bfd_cr16c_arch;
24 @@ -546,6 +553,7 @@ static const bfd_arch_info_type * const
34 @@ -2053,6 +2053,12 @@ enum bfd_architecture
35 #define bfd_mach_avr5 5
36 #define bfd_mach_avr51 51
37 #define bfd_mach_avr6 6
38 + bfd_arch_avr32, /* Atmel AVR32 */
39 +#define bfd_mach_avr32_ap 7000
40 +#define bfd_mach_avr32_uc 3000
41 +#define bfd_mach_avr32_ucr1 3001
42 +#define bfd_mach_avr32_ucr2 3002
43 +#define bfd_mach_avr32_ucr3 3003
44 bfd_arch_bfin, /* ADI Blackfin */
45 #define bfd_mach_bfin 1
46 bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
47 @@ -3989,6 +3995,88 @@ instructions */
51 +/* Difference between two labels: L2 - L1. The value of L1 is encoded
52 +as sym + addend, while the initial difference after assembly is
53 +inserted into the object file by the assembler. */
54 + BFD_RELOC_AVR32_DIFF32,
55 + BFD_RELOC_AVR32_DIFF16,
56 + BFD_RELOC_AVR32_DIFF8,
58 +/* Reference to a symbol through the Global Offset Table. The linker
59 +will allocate an entry for symbol in the GOT and insert the offset
60 +of this entry as the relocation value. */
61 + BFD_RELOC_AVR32_GOT32,
62 + BFD_RELOC_AVR32_GOT16,
63 + BFD_RELOC_AVR32_GOT8,
65 +/* Normal (non-pc-relative) code relocations. Alignment and signedness
66 +is indicated by the suffixes. S means signed, U means unsigned. W
67 +means word-aligned, H means halfword-aligned, neither means
68 +byte-aligned (no alignment.) SUB5 is the same relocation as 16S. */
69 + BFD_RELOC_AVR32_21S,
70 + BFD_RELOC_AVR32_16U,
71 + BFD_RELOC_AVR32_16S,
72 + BFD_RELOC_AVR32_SUB5,
73 + BFD_RELOC_AVR32_8S_EXT,
75 + BFD_RELOC_AVR32_15S,
77 +/* PC-relative relocations are signed if neither 'U' nor 'S' is
78 +specified. However, we explicitly tack on a 'B' to indicate no
79 +alignment, to avoid confusion with data relocs. All of these resolve
80 +to sym + addend - offset, except the one with 'N' (negated) suffix.
81 +This particular one resolves to offset - sym - addend. */
82 + BFD_RELOC_AVR32_22H_PCREL,
83 + BFD_RELOC_AVR32_18W_PCREL,
84 + BFD_RELOC_AVR32_16B_PCREL,
85 + BFD_RELOC_AVR32_16N_PCREL,
86 + BFD_RELOC_AVR32_14UW_PCREL,
87 + BFD_RELOC_AVR32_11H_PCREL,
88 + BFD_RELOC_AVR32_10UW_PCREL,
89 + BFD_RELOC_AVR32_9H_PCREL,
90 + BFD_RELOC_AVR32_9UW_PCREL,
92 +/* Subtract the link-time address of the GOT from (symbol + addend)
93 +and insert the result. */
94 + BFD_RELOC_AVR32_GOTPC,
96 +/* Reference to a symbol through the GOT. The linker will allocate an
97 +entry for symbol in the GOT and insert the offset of this entry as
98 +the relocation value. addend must be zero. As usual, 'S' means
99 +signed, 'W' means word-aligned, etc. */
100 + BFD_RELOC_AVR32_GOTCALL,
101 + BFD_RELOC_AVR32_LDA_GOT,
102 + BFD_RELOC_AVR32_GOT21S,
103 + BFD_RELOC_AVR32_GOT18SW,
104 + BFD_RELOC_AVR32_GOT16S,
106 +/* 32-bit constant pool entry. I don't think 8- and 16-bit entries make
107 +a whole lot of sense. */
108 + BFD_RELOC_AVR32_32_CPENT,
110 +/* Constant pool references. Some of these relocations are signed,
111 +others are unsigned. It doesn't really matter, since the constant
112 +pool always comes after the code that references it. */
113 + BFD_RELOC_AVR32_CPCALL,
114 + BFD_RELOC_AVR32_16_CP,
115 + BFD_RELOC_AVR32_9W_CP,
117 +/* sym must be the absolute symbol. The addend specifies the alignment
118 +order, e.g. if addend is 2, the linker must add padding so that the
119 +next address is aligned to a 4-byte boundary. */
120 + BFD_RELOC_AVR32_ALIGN,
122 +/* Code relocations that will never make it to the output file. */
123 + BFD_RELOC_AVR32_14UW,
124 + BFD_RELOC_AVR32_10UW,
125 + BFD_RELOC_AVR32_10SW,
126 + BFD_RELOC_AVR32_STHH_W,
127 + BFD_RELOC_AVR32_7UW,
128 + BFD_RELOC_AVR32_6S,
129 + BFD_RELOC_AVR32_6UW,
130 + BFD_RELOC_AVR32_4UH,
131 + BFD_RELOC_AVR32_3U,
138 @@ -346,6 +346,10 @@ case "${targ}" in
143 + targ_defvec=bfd_elf32_avr32_vec
146 c30-*-*aout* | tic30-*-*aout*)
147 targ_defvec=tic30_aout_vec
151 @@ -15040,6 +15040,7 @@ do
152 bfd_pei_ia64_vec) tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
153 bfd_elf32_am33lin_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
154 bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
155 + bfd_elf32_avr32_vec) tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
156 bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
157 bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
158 bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
159 --- a/bfd/configure.in
160 +++ b/bfd/configure.in
161 @@ -675,6 +675,7 @@ do
162 bfd_pei_ia64_vec) tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
163 bfd_elf32_am33lin_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
164 bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
165 + bfd_elf32_avr32_vec) tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
166 bfd_elf32_bfin_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
167 bfd_elf32_bfinfdpic_vec) tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
168 bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;;
170 +++ b/bfd/cpu-avr32.c
172 +/* BFD library support routines for AVR32.
173 + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
175 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
177 + This is part of BFD, the Binary File Descriptor library.
179 + This program is free software; you can redistribute it and/or modify
180 + it under the terms of the GNU General Public License as published by
181 + the Free Software Foundation; either version 2 of the License, or
182 + (at your option) any later version.
184 + This program is distributed in the hope that it will be useful,
185 + but WITHOUT ANY WARRANTY; without even the implied warranty of
186 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
187 + GNU General Public License for more details.
189 + You should have received a copy of the GNU General Public License
190 + along with this program; if not, write to the Free Software
191 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
197 +#define N(machine, print, default, next) \
199 + 32, /* 32 bits in a word */ \
200 + 32, /* 32 bits in an address */ \
201 + 8, /* 8 bits in a byte */ \
202 + bfd_arch_avr32, /* architecture */ \
203 + machine, /* machine */ \
204 + "avr32", /* arch name */ \
205 + print, /* printable name */ \
206 + 1, /* section align power */ \
207 + default, /* the default machine? */ \
208 + bfd_default_compatible, \
209 + bfd_default_scan, \
213 +static const bfd_arch_info_type cpu_info[] =
215 + N(bfd_mach_avr32_ap, "avr32:ap", FALSE, &cpu_info[1]),
216 + N(bfd_mach_avr32_uc, "avr32:uc", FALSE, &cpu_info[2]),
217 + N(bfd_mach_avr32_ucr1, "avr32:ucr1", FALSE, &cpu_info[3]),
218 + N(bfd_mach_avr32_ucr2, "avr32:ucr2", FALSE, &cpu_info[4]),
219 + N(bfd_mach_avr32_ucr3, "avr32:ucr3", FALSE, NULL),
222 +const bfd_arch_info_type bfd_avr32_arch =
223 + N(bfd_mach_avr32_ap, "avr32", TRUE, &cpu_info[0]);
225 +++ b/bfd/elf32-avr32.c
227 +/* AVR32-specific support for 32-bit ELF.
228 + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
230 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
232 + This file is part of BFD, the Binary File Descriptor library.
234 + This program is free software; you can redistribute it and/or modify
235 + it under the terms of the GNU General Public License as published by
236 + the Free Software Foundation; either version 2 of the License, or
237 + (at your option) any later version.
239 + This program is distributed in the hope that it will be useful,
240 + but WITHOUT ANY WARRANTY; without even the implied warranty of
241 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
242 + GNU General Public License for more details.
244 + You should have received a copy of the GNU General Public License
245 + along with this program; if not, write to the Free Software
246 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
250 +#include "bfdlink.h"
252 +#include "elf-bfd.h"
253 +#include "elf/avr32.h"
254 +#include "elf32-avr32.h"
257 +#define xRELAX_DEBUG
260 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
262 +# define pr_debug(fmt, args...) do { } while (0)
266 +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args)
268 +# define RDBG(fmt, args...) do { } while (0)
271 +/* When things go wrong, we want it to blow up, damnit! */
274 +#define BFD_ASSERT(expr) \
279 + bfd_assert(__FILE__, __LINE__); \
285 +/* The name of the dynamic interpreter. This is put in the .interp section. */
286 +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1"
288 +#define AVR32_GOT_HEADER_SIZE 8
289 +#define AVR32_FUNCTION_STUB_SIZE 8
291 +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y)
292 +#define ELF_R_TYPE(x) ELF32_R_TYPE(x)
293 +#define ELF_R_SYM(x) ELF32_R_SYM(x)
295 +#define NOP_OPCODE 0xd703
298 +/* Mapping between BFD relocations and ELF relocations */
300 +static reloc_howto_type *
301 +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code);
303 +static reloc_howto_type *
304 +bfd_elf32_bfd_reloc_name_lookup(bfd *abfd, const char *r_name);
307 +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst);
310 +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask) \
311 + HOWTO(name, align, size, bitsize, pcrel, bitpos, \
312 + complain_overflow_##complain, bfd_elf_generic_reloc, #name, \
313 + FALSE, 0, mask, pcrel)
315 +static reloc_howto_type elf_avr32_howto_table[] = {
316 + /* NAME ALN SZ BSZ PCREL BP COMPLAIN MASK */
317 + GENH(R_AVR32_NONE, 0, 0, 0, FALSE, 0, dont, 0x00000000),
319 + GENH(R_AVR32_32, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
320 + GENH(R_AVR32_16, 0, 1, 16, FALSE, 0, bitfield, 0x0000ffff),
321 + GENH(R_AVR32_8, 0, 0, 8, FALSE, 0, bitfield, 0x000000ff),
322 + GENH(R_AVR32_32_PCREL, 0, 2, 32, TRUE, 0, signed, 0xffffffff),
323 + GENH(R_AVR32_16_PCREL, 0, 1, 16, TRUE, 0, signed, 0x0000ffff),
324 + GENH(R_AVR32_8_PCREL, 0, 0, 8, TRUE, 0, signed, 0x000000ff),
326 + /* Difference between two symbol (sym2 - sym1). The reloc encodes
327 + the value of sym1. The field contains the difference before any
328 + relaxing is done. */
329 + GENH(R_AVR32_DIFF32, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
330 + GENH(R_AVR32_DIFF16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff),
331 + GENH(R_AVR32_DIFF8, 0, 0, 8, FALSE, 0, signed, 0x000000ff),
333 + GENH(R_AVR32_GOT32, 0, 2, 32, FALSE, 0, signed, 0xffffffff),
334 + GENH(R_AVR32_GOT16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff),
335 + GENH(R_AVR32_GOT8, 0, 0, 8, FALSE, 0, signed, 0x000000ff),
337 + GENH(R_AVR32_21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff),
338 + GENH(R_AVR32_16U, 0, 2, 16, FALSE, 0, unsigned, 0x0000ffff),
339 + GENH(R_AVR32_16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff),
340 + GENH(R_AVR32_8S, 0, 1, 8, FALSE, 4, signed, 0x00000ff0),
341 + GENH(R_AVR32_8S_EXT, 0, 2, 8, FALSE, 0, signed, 0x000000ff),
343 + GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE, 0, signed, 0x1e10ffff),
344 + GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff),
345 + GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
346 + GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
347 + GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff),
348 + GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE, 4, signed, 0x00000ff3),
349 + GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE, 0, unsigned, 0x000000ff),
350 + GENH(R_AVR32_9H_PCREL, 1, 1, 8, TRUE, 4, signed, 0x00000ff0),
351 + GENH(R_AVR32_9UW_PCREL, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0),
353 + GENH(R_AVR32_HI16, 16, 2, 16, FALSE, 0, dont, 0x0000ffff),
354 + GENH(R_AVR32_LO16, 0, 2, 16, FALSE, 0, dont, 0x0000ffff),
356 + GENH(R_AVR32_GOTPC, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
357 + GENH(R_AVR32_GOTCALL, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff),
358 + GENH(R_AVR32_LDA_GOT, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff),
359 + GENH(R_AVR32_GOT21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff),
360 + GENH(R_AVR32_GOT18SW, 2, 2, 16, FALSE, 0, signed, 0x0000ffff),
361 + GENH(R_AVR32_GOT16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff),
362 + GENH(R_AVR32_GOT7UW, 2, 1, 5, FALSE, 4, unsigned, 0x000001f0),
364 + GENH(R_AVR32_32_CPENT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
365 + GENH(R_AVR32_CPCALL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff),
366 + GENH(R_AVR32_16_CP, 0, 2, 16, TRUE, 0, signed, 0x0000ffff),
367 + GENH(R_AVR32_9W_CP, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0),
369 + GENH(R_AVR32_RELATIVE, 0, 2, 32, FALSE, 0, signed, 0xffffffff),
370 + GENH(R_AVR32_GLOB_DAT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
371 + GENH(R_AVR32_JMP_SLOT, 0, 2, 32, FALSE, 0, dont, 0xffffffff),
373 + GENH(R_AVR32_ALIGN, 0, 1, 0, FALSE, 0, unsigned, 0x00000000),
375 + GENH(R_AVR32_15S, 2, 2, 15, FALSE, 0, signed, 0x00007fff),
378 +struct elf_reloc_map
380 + bfd_reloc_code_real_type bfd_reloc_val;
381 + unsigned char elf_reloc_val;
384 +static const struct elf_reloc_map avr32_reloc_map[] =
386 + { BFD_RELOC_NONE, R_AVR32_NONE },
388 + { BFD_RELOC_32, R_AVR32_32 },
389 + { BFD_RELOC_16, R_AVR32_16 },
390 + { BFD_RELOC_8, R_AVR32_8 },
391 + { BFD_RELOC_32_PCREL, R_AVR32_32_PCREL },
392 + { BFD_RELOC_16_PCREL, R_AVR32_16_PCREL },
393 + { BFD_RELOC_8_PCREL, R_AVR32_8_PCREL },
394 + { BFD_RELOC_AVR32_DIFF32, R_AVR32_DIFF32 },
395 + { BFD_RELOC_AVR32_DIFF16, R_AVR32_DIFF16 },
396 + { BFD_RELOC_AVR32_DIFF8, R_AVR32_DIFF8 },
397 + { BFD_RELOC_AVR32_GOT32, R_AVR32_GOT32 },
398 + { BFD_RELOC_AVR32_GOT16, R_AVR32_GOT16 },
399 + { BFD_RELOC_AVR32_GOT8, R_AVR32_GOT8 },
401 + { BFD_RELOC_AVR32_21S, R_AVR32_21S },
402 + { BFD_RELOC_AVR32_16U, R_AVR32_16U },
403 + { BFD_RELOC_AVR32_16S, R_AVR32_16S },
404 + { BFD_RELOC_AVR32_SUB5, R_AVR32_16S },
405 + { BFD_RELOC_AVR32_8S_EXT, R_AVR32_8S_EXT },
406 + { BFD_RELOC_AVR32_8S, R_AVR32_8S },
408 + { BFD_RELOC_AVR32_22H_PCREL, R_AVR32_22H_PCREL },
409 + { BFD_RELOC_AVR32_18W_PCREL, R_AVR32_18W_PCREL },
410 + { BFD_RELOC_AVR32_16B_PCREL, R_AVR32_16B_PCREL },
411 + { BFD_RELOC_AVR32_16N_PCREL, R_AVR32_16N_PCREL },
412 + { BFD_RELOC_AVR32_11H_PCREL, R_AVR32_11H_PCREL },
413 + { BFD_RELOC_AVR32_10UW_PCREL, R_AVR32_10UW_PCREL },
414 + { BFD_RELOC_AVR32_9H_PCREL, R_AVR32_9H_PCREL },
415 + { BFD_RELOC_AVR32_9UW_PCREL, R_AVR32_9UW_PCREL },
417 + { BFD_RELOC_HI16, R_AVR32_HI16 },
418 + { BFD_RELOC_LO16, R_AVR32_LO16 },
420 + { BFD_RELOC_AVR32_GOTPC, R_AVR32_GOTPC },
421 + { BFD_RELOC_AVR32_GOTCALL, R_AVR32_GOTCALL },
422 + { BFD_RELOC_AVR32_LDA_GOT, R_AVR32_LDA_GOT },
423 + { BFD_RELOC_AVR32_GOT21S, R_AVR32_GOT21S },
424 + { BFD_RELOC_AVR32_GOT18SW, R_AVR32_GOT18SW },
425 + { BFD_RELOC_AVR32_GOT16S, R_AVR32_GOT16S },
426 + /* GOT7UW should never be generated by the assembler */
428 + { BFD_RELOC_AVR32_32_CPENT, R_AVR32_32_CPENT },
429 + { BFD_RELOC_AVR32_CPCALL, R_AVR32_CPCALL },
430 + { BFD_RELOC_AVR32_16_CP, R_AVR32_16_CP },
431 + { BFD_RELOC_AVR32_9W_CP, R_AVR32_9W_CP },
433 + { BFD_RELOC_AVR32_ALIGN, R_AVR32_ALIGN },
435 + { BFD_RELOC_AVR32_15S, R_AVR32_15S },
438 +static reloc_howto_type *
439 +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
440 + bfd_reloc_code_real_type code)
444 + for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++)
446 + if (avr32_reloc_map[i].bfd_reloc_val == code)
447 + return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val];
453 +static reloc_howto_type *
454 +bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
455 + const char *r_name)
460 + i < sizeof (elf_avr32_howto_table) / sizeof (elf_avr32_howto_table[0]);
462 + if (elf_avr32_howto_table[i].name != NULL
463 + && strcasecmp (elf_avr32_howto_table[i].name, r_name) == 0)
464 + return &elf_avr32_howto_table[i];
469 +/* Set the howto pointer for an AVR32 ELF reloc. */
471 +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
472 + arelent *cache_ptr,
473 + Elf_Internal_Rela *dst)
475 + unsigned int r_type;
477 + r_type = ELF32_R_TYPE (dst->r_info);
478 + BFD_ASSERT (r_type < (unsigned int) R_AVR32_max);
479 + cache_ptr->howto = &elf_avr32_howto_table[r_type];
483 +/* AVR32 ELF linker hash table and associated hash entries. */
485 +static struct bfd_hash_entry *
486 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
487 + struct bfd_hash_table *table,
488 + const char *string);
490 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
491 + struct elf_link_hash_entry *dir,
492 + struct elf_link_hash_entry *ind);
493 +static struct bfd_link_hash_table *
494 +avr32_elf_link_hash_table_create(bfd *abfd);
497 + Try to limit memory usage to something reasonable when sorting the
498 + GOT. If just a couple of entries end up getting more references
499 + than this, it won't affect performance at all, but if there are many
500 + of them, we could end up with the wrong symbols being assigned the
503 +#define MAX_NR_GOT_HOLES 2048
506 + AVR32 GOT entry. We need to keep track of refcounts and offsets
507 + simultaneously, since we need the offsets during relaxation, and we
508 + also want to be able to drop GOT entries during relaxation. In
509 + addition to this, we want to keep the list of GOT entries sorted so
510 + that we can keep the most-used entries at the lowest offsets.
514 + struct got_entry *next;
515 + struct got_entry **pprev;
517 + bfd_signed_vma offset;
520 +struct elf_avr32_link_hash_entry
522 + struct elf_link_hash_entry root;
524 + /* Number of runtime relocations against this symbol. */
525 + unsigned int possibly_dynamic_relocs;
527 + /* If there are anything but R_AVR32_GOT18 relocations against this
528 + symbol, it means that someone may be taking the address of the
529 + function, and we should therefore not create a stub. */
530 + bfd_boolean no_fn_stub;
532 + /* If there is a R_AVR32_32 relocation in a read-only section
533 + against this symbol, we could be in trouble. If we're linking a
534 + shared library or this symbol is defined in one, it means we must
535 + emit a run-time reloc for it and that's not allowed in read-only
537 + asection *readonly_reloc_sec;
538 + bfd_vma readonly_reloc_offset;
540 + /* Record which frag (if any) contains the symbol. This is used
541 + during relaxation in order to avoid having to update all symbols
542 + whenever we move something. For local symbols, this information
543 + is in the local_sym_frag member of struct elf_obj_tdata. */
544 + struct fragment *sym_frag;
546 +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent))
548 +struct elf_avr32_link_hash_table
550 + struct elf_link_hash_table root;
552 + /* Shortcuts to get to dynamic linker sections. */
557 + /* We use a variation of Pigeonhole Sort to sort the GOT. After the
558 + initial refcounts have been determined, we initialize
559 + nr_got_holes to the highest refcount ever seen and allocate an
560 + array of nr_got_holes entries for got_hole. Each GOT entry is
561 + then stored in this array at the index given by its refcount.
563 + When a GOT entry has its refcount decremented during relaxation,
564 + it is moved to a lower index in the got_hole array.
566 + struct got_entry **got_hole;
569 + /* Dynamic relocations to local symbols. Only used when linking a
570 + shared library and -Bsymbolic is not given. */
571 + unsigned int local_dynamic_relocs;
573 + bfd_boolean relocations_analyzed;
574 + bfd_boolean symbols_adjusted;
575 + bfd_boolean repeat_pass;
576 + bfd_boolean direct_data_refs;
577 + unsigned int relax_iteration;
578 + unsigned int relax_pass;
580 +#define avr32_elf_hash_table(p) \
581 + ((struct elf_avr32_link_hash_table *)((p)->hash))
583 +static struct bfd_hash_entry *
584 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
585 + struct bfd_hash_table *table,
586 + const char *string)
588 + struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry);
590 + /* Allocate the structure if it hasn't already been allocated by a
593 + ret = (struct elf_avr32_link_hash_entry *)
594 + bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry));
599 + memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry));
601 + /* Give the superclass a chance */
602 + ret = (struct elf_avr32_link_hash_entry *)
603 + _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string);
605 + return (struct bfd_hash_entry *)ret;
608 +/* Copy data from an indirect symbol to its direct symbol, hiding the
609 + old indirect symbol. Process additional relocation information.
610 + Also called for weakdefs, in which case we just let
611 + _bfd_elf_link_hash_copy_indirect copy the flags for us. */
614 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
615 + struct elf_link_hash_entry *dir,
616 + struct elf_link_hash_entry *ind)
618 + struct elf_avr32_link_hash_entry *edir, *eind;
620 + _bfd_elf_link_hash_copy_indirect (info, dir, ind);
622 + if (ind->root.type != bfd_link_hash_indirect)
625 + edir = (struct elf_avr32_link_hash_entry *)dir;
626 + eind = (struct elf_avr32_link_hash_entry *)ind;
628 + edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs;
629 + edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub;
632 +static struct bfd_link_hash_table *
633 +avr32_elf_link_hash_table_create(bfd *abfd)
635 + struct elf_avr32_link_hash_table *ret;
637 + ret = bfd_zmalloc(sizeof(*ret));
641 + if (! _bfd_elf_link_hash_table_init(&ret->root, abfd,
642 + avr32_elf_link_hash_newfunc,
643 + sizeof (struct elf_avr32_link_hash_entry)))
649 + /* Prevent the BFD core from creating bogus got_entry pointers */
650 + ret->root.init_got_refcount.glist = NULL;
651 + ret->root.init_plt_refcount.glist = NULL;
652 + ret->root.init_got_offset.glist = NULL;
653 + ret->root.init_plt_offset.glist = NULL;
655 + return &ret->root.root;
659 +/* Initial analysis and creation of dynamic sections and symbols */
662 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
663 + unsigned int align_power);
664 +static struct elf_link_hash_entry *
665 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
666 + const char *name, asection *sec,
669 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info);
671 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info);
673 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
674 + const Elf_Internal_Rela *relocs);
676 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
677 + struct elf_link_hash_entry *h);
680 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
681 + unsigned int align_power)
685 + sec = bfd_make_section(dynobj, name);
687 + || !bfd_set_section_flags(dynobj, sec, flags)
688 + || !bfd_set_section_alignment(dynobj, sec, align_power))
694 +static struct elf_link_hash_entry *
695 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
696 + const char *name, asection *sec,
699 + struct bfd_link_hash_entry *bh = NULL;
700 + struct elf_link_hash_entry *h;
701 + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
703 + if (!(_bfd_generic_link_add_one_symbol
704 + (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE,
705 + bed->collect, &bh)))
708 + h = (struct elf_link_hash_entry *)bh;
709 + h->def_regular = 1;
710 + h->type = STT_OBJECT;
711 + h->other = STV_HIDDEN;
717 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
719 + struct elf_avr32_link_hash_table *htab;
721 + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
723 + htab = avr32_elf_hash_table(info);
724 + flags = bed->dynamic_sec_flags;
729 + htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2);
730 + if (!htab->srelgot)
731 + htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
732 + flags | SEC_READONLY, 2);
734 + if (!htab->sgot || !htab->srelgot)
737 + htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_",
739 + if (!htab->root.hgot)
742 + /* Make room for the GOT header */
743 + htab->sgot->size += bed->got_header_size;
748 +/* (1) Create all dynamic (i.e. linker generated) sections that we may
749 + need during the link */
752 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
754 + struct elf_avr32_link_hash_table *htab;
756 + const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
758 + pr_debug("(1) create dynamic sections\n");
760 + htab = avr32_elf_hash_table(info);
761 + flags = bed->dynamic_sec_flags;
763 + if (!avr32_elf_create_got_section (dynobj, info))
767 + htab->sstub = create_dynamic_section(dynobj, ".stub",
768 + flags | SEC_READONLY | SEC_CODE, 2);
776 +/* (2) Go through all the relocs and count any potential GOT- or
777 + PLT-references to each symbol */
780 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
781 + const Elf_Internal_Rela *relocs)
783 + Elf_Internal_Shdr *symtab_hdr;
784 + struct elf_avr32_link_hash_table *htab;
785 + struct elf_link_hash_entry **sym_hashes;
786 + const Elf_Internal_Rela *rel, *rel_end;
787 + struct got_entry **local_got_ents;
788 + struct got_entry *got;
789 + const struct elf_backend_data *bed = get_elf_backend_data (abfd);
793 + pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n",
794 + abfd->filename, sec->name, sec->size);
796 + if (info->relocatable)
799 + dynobj = elf_hash_table(info)->dynobj;
800 + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
801 + sym_hashes = elf_sym_hashes(abfd);
802 + htab = avr32_elf_hash_table(info);
803 + local_got_ents = elf_local_got_ents(abfd);
806 + rel_end = relocs + sec->reloc_count;
807 + for (rel = relocs; rel < rel_end; rel++)
809 + unsigned long r_symndx, r_type;
810 + struct elf_avr32_link_hash_entry *h;
812 + r_symndx = ELF32_R_SYM(rel->r_info);
813 + r_type = ELF32_R_TYPE(rel->r_info);
815 + /* Local symbols use local_got_ents, while others store the same
816 + information in the hash entry */
817 + if (r_symndx < symtab_hdr->sh_info)
819 + pr_debug(" (2a) processing local symbol %lu\n", r_symndx);
824 + h = (struct elf_avr32_link_hash_entry *)
825 + sym_hashes[r_symndx - symtab_hdr->sh_info];
826 + while (h->root.type == bfd_link_hash_indirect
827 + || h->root.type == bfd_link_hash_warning)
828 + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
829 + pr_debug(" (2a) processing symbol %s\n", h->root.root.root.string);
832 + /* Some relocs require special sections to be created. */
835 + case R_AVR32_GOT32:
836 + case R_AVR32_GOT16:
838 + case R_AVR32_GOT21S:
839 + case R_AVR32_GOT18SW:
840 + case R_AVR32_GOT16S:
841 + case R_AVR32_GOT7UW:
842 + case R_AVR32_LDA_GOT:
843 + case R_AVR32_GOTCALL:
846 + if (info->callbacks->reloc_dangerous
847 + (info, _("Non-zero addend on GOT-relative relocation"),
848 + abfd, sec, rel->r_offset) == FALSE)
852 + case R_AVR32_GOTPC:
853 + if (dynobj == NULL)
854 + elf_hash_table(info)->dynobj = dynobj = abfd;
855 + if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info))
859 + /* We may need to create .rela.dyn later on. */
861 + && (info->shared || h != NULL)
862 + && (sec->flags & SEC_ALLOC))
863 + elf_hash_table(info)->dynobj = dynobj = abfd;
867 + if (h != NULL && r_type != R_AVR32_GOT18SW)
868 + h->no_fn_stub = TRUE;
872 + case R_AVR32_GOT32:
873 + case R_AVR32_GOT16:
875 + case R_AVR32_GOT21S:
876 + case R_AVR32_GOT18SW:
877 + case R_AVR32_GOT16S:
878 + case R_AVR32_GOT7UW:
879 + case R_AVR32_LDA_GOT:
880 + case R_AVR32_GOTCALL:
883 + got = h->root.got.glist;
886 + got = bfd_zalloc(abfd, sizeof(struct got_entry));
889 + h->root.got.glist = got;
894 + if (!local_got_ents)
896 + bfd_size_type size;
898 + struct got_entry *tmp_entry;
900 + size = symtab_hdr->sh_info;
901 + size *= sizeof(struct got_entry *) + sizeof(struct got_entry);
902 + local_got_ents = bfd_zalloc(abfd, size);
903 + if (!local_got_ents)
906 + elf_local_got_ents(abfd) = local_got_ents;
908 + tmp_entry = (struct got_entry *)(local_got_ents
909 + + symtab_hdr->sh_info);
910 + for (i = 0; i < symtab_hdr->sh_info; i++)
911 + local_got_ents[i] = &tmp_entry[i];
914 + got = local_got_ents[r_symndx];
918 + if (got->refcount > htab->nr_got_holes)
919 + htab->nr_got_holes = got->refcount;
923 + if ((info->shared || h != NULL)
924 + && (sec->flags & SEC_ALLOC))
926 + if (htab->srelgot == NULL)
928 + htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
929 + bed->dynamic_sec_flags
930 + | SEC_READONLY, 2);
931 + if (htab->srelgot == NULL)
935 + if (sec->flags & SEC_READONLY
936 + && !h->readonly_reloc_sec)
938 + h->readonly_reloc_sec = sec;
939 + h->readonly_reloc_offset = rel->r_offset;
944 + pr_debug("Non-GOT reference to symbol %s\n",
945 + h->root.root.root.string);
946 + h->possibly_dynamic_relocs++;
950 + pr_debug("Non-GOT reference to local symbol %lu\n",
952 + htab->local_dynamic_relocs++;
958 + /* TODO: GNU_VTINHERIT and GNU_VTENTRY */
965 +/* (3) Adjust a symbol defined by a dynamic object and referenced by a
966 + regular object. The current definition is in some section of the
967 + dynamic object, but we're not including those sections. We have to
968 + change the definition to something the rest of the link can
972 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
973 + struct elf_link_hash_entry *h)
975 + struct elf_avr32_link_hash_table *htab;
976 + struct elf_avr32_link_hash_entry *havr;
979 + pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string);
981 + htab = avr32_elf_hash_table(info);
982 + havr = (struct elf_avr32_link_hash_entry *)h;
983 + dynobj = elf_hash_table(info)->dynobj;
985 + /* Make sure we know what is going on here. */
986 + BFD_ASSERT (dynobj != NULL
987 + && (h->u.weakdef != NULL
990 + && !h->def_regular)));
992 + /* We don't want dynamic relocations in read-only sections. */
993 + if (havr->readonly_reloc_sec)
995 + if (info->callbacks->reloc_dangerous
996 + (info, _("dynamic relocation in read-only section"),
997 + havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec,
998 + havr->readonly_reloc_offset) == FALSE)
1002 + /* If this is a function, create a stub if possible and set the
1003 + symbol to the stub location. */
1004 + if (0 && !havr->no_fn_stub)
1006 + if (!h->def_regular)
1008 + asection *s = htab->sstub;
1010 + BFD_ASSERT(s != NULL);
1012 + h->root.u.def.section = s;
1013 + h->root.u.def.value = s->size;
1014 + h->plt.offset = s->size;
1015 + s->size += AVR32_FUNCTION_STUB_SIZE;
1020 + else if (h->type == STT_FUNC)
1022 + /* This will set the entry for this symbol in the GOT to 0, and
1023 + the dynamic linker will take care of this. */
1024 + h->root.u.def.value = 0;
1028 + /* If this is a weak symbol, and there is a real definition, the
1029 + processor independent code will have arranged for us to see the
1030 + real definition first, and we can just use the same value. */
1031 + if (h->u.weakdef != NULL)
1033 + BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined
1034 + || h->u.weakdef->root.type == bfd_link_hash_defweak);
1035 + h->root.u.def.section = h->u.weakdef->root.u.def.section;
1036 + h->root.u.def.value = h->u.weakdef->root.u.def.value;
1040 + /* This is a reference to a symbol defined by a dynamic object which
1041 + is not a function. */
1047 +/* Garbage-collection of unused sections */
1050 +avr32_elf_gc_mark_hook(asection *sec,
1051 + struct bfd_link_info *info ATTRIBUTE_UNUSED,
1052 + Elf_Internal_Rela *rel,
1053 + struct elf_link_hash_entry *h,
1054 + Elf_Internal_Sym *sym)
1058 + switch (ELF32_R_TYPE(rel->r_info))
1060 + /* TODO: VTINHERIT/VTENTRY */
1062 + switch (h->root.type)
1064 + case bfd_link_hash_defined:
1065 + case bfd_link_hash_defweak:
1066 + return h->root.u.def.section;
1068 + case bfd_link_hash_common:
1069 + return h->root.u.c.p->section;
1077 + return bfd_section_from_elf_index(sec->owner, sym->st_shndx);
1082 +/* Update the GOT entry reference counts for the section being removed. */
1084 +avr32_elf_gc_sweep_hook(bfd *abfd,
1085 + struct bfd_link_info *info ATTRIBUTE_UNUSED,
1087 + const Elf_Internal_Rela *relocs)
1089 + Elf_Internal_Shdr *symtab_hdr;
1090 + struct elf_avr32_link_hash_entry **sym_hashes;
1091 + struct got_entry **local_got_ents;
1092 + const Elf_Internal_Rela *rel, *relend;
1094 + if (!(sec->flags & SEC_ALLOC))
1097 + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
1098 + sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd);
1099 + local_got_ents = elf_local_got_ents(abfd);
1101 + relend = relocs + sec->reloc_count;
1102 + for (rel = relocs; rel < relend; rel++)
1104 + unsigned long r_symndx;
1105 + unsigned int r_type;
1106 + struct elf_avr32_link_hash_entry *h = NULL;
1108 + r_symndx = ELF32_R_SYM(rel->r_info);
1109 + if (r_symndx >= symtab_hdr->sh_info)
1111 + h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1112 + while (h->root.root.type == bfd_link_hash_indirect
1113 + || h->root.root.type == bfd_link_hash_warning)
1114 + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
1117 + r_type = ELF32_R_TYPE(rel->r_info);
1121 + case R_AVR32_GOT32:
1122 + case R_AVR32_GOT16:
1123 + case R_AVR32_GOT8:
1124 + case R_AVR32_GOT21S:
1125 + case R_AVR32_GOT18SW:
1126 + case R_AVR32_GOT16S:
1127 + case R_AVR32_GOT7UW:
1128 + case R_AVR32_LDA_GOT:
1129 + case R_AVR32_GOTCALL:
1131 + h->root.got.glist->refcount--;
1133 + local_got_ents[r_symndx]->refcount--;
1137 + if (info->shared || h)
1140 + h->possibly_dynamic_relocs--;
1142 + avr32_elf_hash_table(info)->local_dynamic_relocs--;
1153 +/* Sizing and refcounting of dynamic sections */
1156 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1158 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1160 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1162 +assign_got_offsets(struct elf_avr32_link_hash_table *htab);
1164 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info);
1166 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1167 + struct bfd_link_info *info);
1170 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1172 + /* Any entries with got_refcount > htab->nr_got_holes end up in the
1173 + * last pigeonhole without any sorting. We expect the number of such
1174 + * entries to be small, so it is very unlikely to affect
1176 + int entry = got->refcount;
1178 + if (entry > htab->nr_got_holes)
1179 + entry = htab->nr_got_holes;
1181 + got->pprev = &htab->got_hole[entry];
1182 + got->next = htab->got_hole[entry];
1185 + got->next->pprev = &got->next;
1187 + htab->got_hole[entry] = got;
1190 +/* Decrement the refcount of a GOT entry and update its position in
1191 + the pigeonhole array. */
1193 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1195 + BFD_ASSERT(got->refcount > 0);
1198 + got->next->pprev = got->pprev;
1200 + *(got->pprev) = got->next;
1202 + insert_got_entry(htab, got);
1206 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1209 + got->next->pprev = got->pprev;
1211 + *(got->pprev) = got->next;
1213 + insert_got_entry(htab, got);
1215 + BFD_ASSERT(got->refcount > 0);
1218 +/* Assign offsets to all GOT entries we intend to keep. The entries
1219 + that are referenced most often are placed at low offsets so that we
1220 + can use compact instructions as much as possible.
1222 + Returns TRUE if any offsets or the total size of the GOT changed. */
1225 +assign_got_offsets(struct elf_avr32_link_hash_table *htab)
1227 + struct got_entry *got;
1228 + bfd_size_type got_size = 0;
1229 + bfd_boolean changed = FALSE;
1230 + bfd_signed_vma offset;
1233 + /* The GOT header provides the address of the DYNAMIC segment, so
1234 + we need that even if the GOT is otherwise empty. */
1235 + if (htab->root.dynamic_sections_created)
1236 + got_size = AVR32_GOT_HEADER_SIZE;
1238 + for (i = htab->nr_got_holes; i > 0; i--)
1240 + got = htab->got_hole[i];
1243 + if (got->refcount > 0)
1245 + offset = got_size;
1246 + if (got->offset != offset)
1248 + RDBG("GOT offset changed: %ld -> %ld\n",
1249 + got->offset, offset);
1252 + got->offset = offset;
1259 + if (htab->sgot->size != got_size)
1261 + RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size,
1265 + htab->sgot->size = got_size;
1267 + RDBG("assign_got_offsets: total size %lu (%s)\n",
1268 + got_size, changed ? "changed" : "no change");
1274 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info)
1276 + struct bfd_link_info *info = _info;
1277 + struct elf_avr32_link_hash_table *htab;
1278 + struct elf_avr32_link_hash_entry *havr;
1279 + struct got_entry *got;
1281 + pr_debug(" (4b) allocate_dynrelocs: %s\n", h->root.root.string);
1283 + if (h->root.type == bfd_link_hash_indirect)
1286 + if (h->root.type == bfd_link_hash_warning)
1287 + /* When warning symbols are created, they **replace** the "real"
1288 + entry in the hash table, thus we never get to see the real
1289 + symbol in a hash traversal. So look at it now. */
1290 + h = (struct elf_link_hash_entry *) h->root.u.i.link;
1292 + htab = avr32_elf_hash_table(info);
1293 + havr = (struct elf_avr32_link_hash_entry *)h;
1295 + got = h->got.glist;
1297 + /* If got is NULL, the symbol is never referenced through the GOT */
1298 + if (got && got->refcount > 0)
1300 + insert_got_entry(htab, got);
1302 + /* Shared libraries need relocs for all GOT entries unless the
1303 + symbol is forced local or -Bsymbolic is used. Others need
1304 + relocs for everything that is not guaranteed to be defined in
1305 + a regular object. */
1307 + && !info->symbolic
1308 + && h->dynindx != -1)
1309 + || (htab->root.dynamic_sections_created
1311 + && !h->def_regular))
1312 + htab->srelgot->size += sizeof(Elf32_External_Rela);
1315 + if (havr->possibly_dynamic_relocs
1317 + || (elf_hash_table(info)->dynamic_sections_created
1319 + && !h->def_regular)))
1321 + pr_debug("Allocating %d dynamic reloc against symbol %s...\n",
1322 + havr->possibly_dynamic_relocs, h->root.root.string);
1323 + htab->srelgot->size += (havr->possibly_dynamic_relocs
1324 + * sizeof(Elf32_External_Rela));
1330 +/* (4) Calculate the sizes of the linker-generated sections and
1331 + allocate memory for them. */
1334 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1335 + struct bfd_link_info *info)
1337 + struct elf_avr32_link_hash_table *htab;
1341 + bfd_boolean relocs;
1343 + pr_debug("(4) size dynamic sections\n");
1345 + htab = avr32_elf_hash_table(info);
1346 + dynobj = htab->root.dynobj;
1347 + BFD_ASSERT(dynobj != NULL);
1349 + if (htab->root.dynamic_sections_created)
1351 + /* Initialize the contents of the .interp section to the name of
1352 + the dynamic loader */
1353 + if (info->executable)
1355 + s = bfd_get_section_by_name(dynobj, ".interp");
1356 + BFD_ASSERT(s != NULL);
1357 + s->size = sizeof(ELF_DYNAMIC_INTERPRETER);
1358 + s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER;
1362 + if (htab->nr_got_holes > 0)
1364 + /* Allocate holes for the pigeonhole sort algorithm */
1365 + pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes);
1367 + /* Limit the memory usage by clipping the number of pigeonholes
1368 + * at a predefined maximum. All entries with a higher refcount
1369 + * will end up in the last pigeonhole. */
1370 + if (htab->nr_got_holes >= MAX_NR_GOT_HOLES)
1372 + htab->nr_got_holes = MAX_NR_GOT_HOLES - 1;
1374 + pr_debug("Limiting maximum number of GOT pigeonholes to %u\n",
1375 + htab->nr_got_holes);
1377 + htab->got_hole = bfd_zalloc(output_bfd,
1378 + sizeof(struct got_entry *)
1379 + * (htab->nr_got_holes + 1));
1380 + if (!htab->got_hole)
1383 + /* Set up .got offsets for local syms. */
1384 + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
1386 + struct got_entry **local_got;
1387 + struct got_entry **end_local_got;
1388 + Elf_Internal_Shdr *symtab_hdr;
1389 + bfd_size_type locsymcount;
1391 + pr_debug(" (4a) processing file %s...\n", ibfd->filename);
1393 + BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour);
1395 + local_got = elf_local_got_ents(ibfd);
1399 + symtab_hdr = &elf_tdata(ibfd)->symtab_hdr;
1400 + locsymcount = symtab_hdr->sh_info;
1401 + end_local_got = local_got + locsymcount;
1403 + for (; local_got < end_local_got; ++local_got)
1404 + insert_got_entry(htab, *local_got);
1408 + /* Allocate global sym .got entries and space for global sym
1410 + elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info);
1412 + /* Now that we have sorted the GOT entries, we are ready to
1413 + assign offsets and determine the initial size of the GOT. */
1415 + assign_got_offsets(htab);
1417 + /* Allocate space for local sym dynamic relocs */
1418 + BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared);
1419 + if (htab->local_dynamic_relocs)
1420 + htab->srelgot->size += (htab->local_dynamic_relocs
1421 + * sizeof(Elf32_External_Rela));
1423 + /* We now have determined the sizes of the various dynamic
1424 + sections. Allocate memory for them. */
1426 + for (s = dynobj->sections; s; s = s->next)
1428 + if ((s->flags & SEC_LINKER_CREATED) == 0)
1431 + if (s == htab->sgot
1432 + || s == htab->sstub)
1434 + /* Strip this section if we don't need it */
1436 + else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0)
1441 + s->reloc_count = 0;
1445 + /* It's not one of our sections */
1451 + /* Strip unneeded sections */
1452 + pr_debug("Stripping section %s from output...\n", s->name);
1453 + /* deleted function in 2.17
1454 + _bfd_strip_section_from_output(info, s);
1459 + s->contents = bfd_zalloc(dynobj, s->size);
1460 + if (s->contents == NULL)
1464 + if (htab->root.dynamic_sections_created)
1466 + /* Add some entries to the .dynamic section. We fill in the
1467 + values later, in sh_elf_finish_dynamic_sections, but we
1468 + must add the entries now so that we get the correct size for
1469 + the .dynamic section. The DT_DEBUG entry is filled in by the
1470 + dynamic linker and used by the debugger. */
1471 +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL)
1473 + if (!add_dynamic_entry(DT_PLTGOT, 0))
1475 + if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0))
1478 + if (info->executable)
1480 + if (!add_dynamic_entry(DT_DEBUG, 0))
1485 + if (!add_dynamic_entry(DT_RELA, 0)
1486 + || !add_dynamic_entry(DT_RELASZ, 0)
1487 + || !add_dynamic_entry(DT_RELAENT,
1488 + sizeof(Elf32_External_Rela)))
1492 +#undef add_dynamic_entry
1498 +/* Access to internal relocations, section contents and symbols.
1499 + (stolen from the xtensa port) */
1501 +static Elf_Internal_Rela *
1502 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1504 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1506 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1508 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1511 +pin_contents (asection *sec, bfd_byte *contents);
1514 +release_contents (asection *sec, bfd_byte *contents);
1515 +static Elf_Internal_Sym *
1516 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory);
1519 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1522 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1524 +/* During relaxation, we need to modify relocations, section contents,
1525 + and symbol definitions, and we need to keep the original values from
1526 + being reloaded from the input files, i.e., we need to "pin" the
1527 + modified values in memory. We also want to continue to observe the
1528 + setting of the "keep-memory" flag. The following functions wrap the
1529 + standard BFD functions to take care of this for us. */
1531 +static Elf_Internal_Rela *
1532 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1534 + /* _bfd_elf_link_read_relocs knows about caching, so no need for us
1535 + to be clever here. */
1536 + return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory);
1540 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1542 + elf_section_data (sec)->relocs = internal_relocs;
1546 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1548 + if (internal_relocs
1549 + && elf_section_data (sec)->relocs != internal_relocs)
1550 + free (internal_relocs);
1554 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1556 + bfd_byte *contents;
1557 + bfd_size_type sec_size;
1559 + sec_size = bfd_get_section_limit (abfd, sec);
1560 + contents = elf_section_data (sec)->this_hdr.contents;
1562 + if (contents == NULL && sec_size != 0)
1564 + if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1571 + elf_section_data (sec)->this_hdr.contents = contents;
1578 +pin_contents (asection *sec, bfd_byte *contents)
1580 + elf_section_data (sec)->this_hdr.contents = contents;
1584 +release_contents (asection *sec, bfd_byte *contents)
1586 + if (contents && elf_section_data (sec)->this_hdr.contents != contents)
1590 +static Elf_Internal_Sym *
1591 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory)
1593 + Elf_Internal_Shdr *symtab_hdr;
1594 + Elf_Internal_Sym *isymbuf;
1595 + size_t locsymcount;
1597 + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1598 + locsymcount = symtab_hdr->sh_info;
1600 + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1601 + if (isymbuf == NULL && locsymcount != 0)
1603 + isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
1604 + NULL, NULL, NULL);
1605 + if (isymbuf && keep_memory)
1606 + symtab_hdr->contents = (unsigned char *) isymbuf;
1614 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1616 + elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf;
1621 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1623 + if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents
1624 + != (unsigned char *)isymbuf))
1628 +
\f/* Data structures used during relaxation. */
1630 +enum relax_state_id {
1660 +enum reference_type {
1670 + enum relax_state_id id;
1671 + enum relax_state_id direct;
1672 + enum relax_state_id next;
1673 + enum relax_state_id prev;
1675 + enum reference_type reftype;
1677 + unsigned int r_type;
1680 + bfd_vma opcode_mask;
1682 + bfd_signed_vma range_min;
1683 + bfd_signed_vma range_max;
1685 + bfd_size_type size;
1689 + * This is for relocs that
1690 + * a) has an addend or is of type R_AVR32_DIFF32, and
1691 + * b) references a different section than it's in, and
1692 + * c) references a section that is relaxable
1694 + * as well as relocs that references the constant pool, in which case
1695 + * the add_frag member points to the frag containing the constant pool
1698 + * Such relocs must be fixed up whenever we delete any code. Sections
1699 + * that don't have any relocs with all of the above properties don't
1700 + * have any additional reloc data, but sections that do will have
1701 + * additional data for all its relocs.
1703 +struct avr32_reloc_data
1705 + struct fragment *add_frag;
1706 + struct fragment *sub_frag;
1710 + * A 'fragment' is a relaxable entity, that is, code may be added or
1711 + * deleted at the end of a fragment. When this happens, all subsequent
1712 + * fragments in the list will have their offsets updated.
1716 + enum relax_state_id state;
1717 + enum relax_state_id initial_state;
1719 + Elf_Internal_Rela *rela;
1720 + bfd_size_type size;
1723 + int offset_adjust;
1724 + bfd_boolean has_grown;
1726 + /* Only used by constant pool entries. When this drops to zero, the
1727 + frag is discarded (i.e. size_adjust is set to -4.) */
1731 +struct avr32_relax_data
1733 + unsigned int frag_count;
1734 + struct fragment *frag;
1735 + struct avr32_reloc_data *reloc_data;
1737 + /* TRUE if this section has one or more relaxable relocations */
1738 + bfd_boolean is_relaxable;
1739 + unsigned int iteration;
1742 +struct avr32_section_data
1744 + struct bfd_elf_section_data elf;
1745 + struct avr32_relax_data relax_data;
1748 +
\f/* Relax state definitions */
1750 +#define PIC_MOV2_OPCODE 0xe0600000
1751 +#define PIC_MOV2_MASK 0xe1e00000
1752 +#define PIC_MOV2_RANGE_MIN (-1048576 * 4)
1753 +#define PIC_MOV2_RANGE_MAX (1048575 * 4)
1754 +#define PIC_MCALL_OPCODE 0xf0160000
1755 +#define PIC_MCALL_MASK 0xffff0000
1756 +#define PIC_MCALL_RANGE_MIN (-131072)
1757 +#define PIC_MCALL_RANGE_MAX (131068)
1758 +#define RCALL2_OPCODE 0xe0a00000
1759 +#define RCALL2_MASK 0xe1ef0000
1760 +#define RCALL2_RANGE_MIN (-2097152)
1761 +#define RCALL2_RANGE_MAX (2097150)
1762 +#define RCALL1_OPCODE 0xc00c0000
1763 +#define RCALL1_MASK 0xf00c0000
1764 +#define RCALL1_RANGE_MIN (-1024)
1765 +#define RCALL1_RANGE_MAX (1022)
1766 +#define PIC_LDW4_OPCODE 0xecf00000
1767 +#define PIC_LDW4_MASK 0xfff00000
1768 +#define PIC_LDW4_RANGE_MIN (-32768)
1769 +#define PIC_LDW4_RANGE_MAX (32767)
1770 +#define PIC_LDW3_OPCODE 0x6c000000
1771 +#define PIC_LDW3_MASK 0xfe000000
1772 +#define PIC_LDW3_RANGE_MIN (0)
1773 +#define PIC_LDW3_RANGE_MAX (124)
1774 +#define SUB5_PC_OPCODE 0xfec00000
1775 +#define SUB5_PC_MASK 0xfff00000
1776 +#define SUB5_PC_RANGE_MIN (-32768)
1777 +#define SUB5_PC_RANGE_MAX (32767)
1778 +#define NOPIC_MCALL_OPCODE 0xf01f0000
1779 +#define NOPIC_MCALL_MASK 0xffff0000
1780 +#define NOPIC_MCALL_RANGE_MIN PIC_MCALL_RANGE_MIN
1781 +#define NOPIC_MCALL_RANGE_MAX PIC_MCALL_RANGE_MAX
1782 +#define NOPIC_LDW4_OPCODE 0xfef00000
1783 +#define NOPIC_LDW4_MASK 0xfff00000
1784 +#define NOPIC_LDW4_RANGE_MIN PIC_LDW4_RANGE_MIN
1785 +#define NOPIC_LDW4_RANGE_MAX PIC_LDW4_RANGE_MAX
1786 +#define LDDPC_OPCODE 0x48000000
1787 +#define LDDPC_MASK 0xf8000000
1788 +#define LDDPC_RANGE_MIN 0
1789 +#define LDDPC_RANGE_MAX 508
1791 +#define NOPIC_MOV2_OPCODE 0xe0600000
1792 +#define NOPIC_MOV2_MASK 0xe1e00000
1793 +#define NOPIC_MOV2_RANGE_MIN (-1048576)
1794 +#define NOPIC_MOV2_RANGE_MAX (1048575)
1795 +#define NOPIC_MOV1_OPCODE 0x30000000
1796 +#define NOPIC_MOV1_MASK 0xf0000000
1797 +#define NOPIC_MOV1_RANGE_MIN (-128)
1798 +#define NOPIC_MOV1_RANGE_MAX (127)
1800 +/* Only brc2 variants with cond[3] == 0 is considered, since the
1801 + others are not relaxable. bral is a special case and is handled
1803 +#define BRC2_OPCODE 0xe0800000
1804 +#define BRC2_MASK 0xe1e80000
1805 +#define BRC2_RANGE_MIN (-2097152)
1806 +#define BRC2_RANGE_MAX (2097150)
1807 +#define BRC1_OPCODE 0xc0000000
1808 +#define BRC1_MASK 0xf0080000
1809 +#define BRC1_RANGE_MIN (-256)
1810 +#define BRC1_RANGE_MAX (254)
1811 +#define BRAL_OPCODE 0xe08f0000
1812 +#define BRAL_MASK 0xe1ef0000
1813 +#define BRAL_RANGE_MIN BRC2_RANGE_MIN
1814 +#define BRAL_RANGE_MAX BRC2_RANGE_MAX
1815 +#define RJMP_OPCODE 0xc0080000
1816 +#define RJMP_MASK 0xf00c0000
1817 +#define RJMP_RANGE_MIN (-1024)
1818 +#define RJMP_RANGE_MAX (1022)
1820 +/* Define a relax state using the GOT */
1821 +#define RG(id, dir, next, prev, r_type, opc, size) \
1822 + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT, \
1823 + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
1824 + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1825 +/* Define a relax state using the Constant Pool */
1826 +#define RC(id, dir, next, prev, r_type, opc, size) \
1827 + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL, \
1828 + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
1829 + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1831 +/* Define a relax state using pc-relative direct reference */
1832 +#define RP(id, dir, next, prev, r_type, opc, size) \
1833 + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL, \
1834 + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
1835 + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1837 +/* Define a relax state using non-pc-relative direct reference */
1838 +#define RD(id, dir, next, prev, r_type, opc, size) \
1839 + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_ABSOLUTE, \
1840 + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \
1841 + opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1843 +/* Define a relax state that will be handled specially */
1844 +#define RS(id, r_type, size) \
1845 + { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE, \
1846 + R_AVR32_##r_type, 0, 0, 0, 0, size }
1848 +const struct relax_state relax_state[RS_MAX] = {
1849 + RS(NONE, NONE, 0),
1850 + RS(ALIGN, ALIGN, 0),
1851 + RS(CPENT, 32_CPENT, 4),
1853 + RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10),
1854 + RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4),
1855 + RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4),
1856 + RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2),
1858 + RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8),
1859 + RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4),
1860 + RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2),
1861 + RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4),
1863 + RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4),
1864 + RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4),
1865 + RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2),
1867 + RC(NOPIC_LDW4, NOPIC_MOV1, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4),
1868 + RC(NOPIC_LDDPC, NOPIC_MOV1, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2),
1869 + RP(NOPIC_SUB5, NOPIC_MOV1, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4),
1870 + RD(NOPIC_MOV2, NONE, NOPIC_MOV1, NOPIC_SUB5, 21S, NOPIC_MOV2, 4),
1871 + RD(NOPIC_MOV1, NONE, NONE, NOPIC_MOV2, 8S, NOPIC_MOV1, 2),
1873 + RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4),
1874 + RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2),
1875 + RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4),
1876 + RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2),
1877 + RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4),
1878 + RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2),
1882 +avr32_elf_new_section_hook(bfd *abfd, asection *sec)
1884 + struct avr32_section_data *sdata;
1886 + sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data));
1890 + sec->used_by_bfd = sdata;
1891 + return _bfd_elf_new_section_hook(abfd, sec);
1894 +static struct avr32_relax_data *
1895 +avr32_relax_data(asection *sec)
1897 + struct avr32_section_data *sdata;
1899 + BFD_ASSERT(sec->used_by_bfd);
1901 + sdata = (struct avr32_section_data *)elf_section_data(sec);
1902 + return &sdata->relax_data;
1905 +
\f/* Link-time relaxation */
1908 +avr32_elf_relax_section(bfd *abfd, asection *sec,
1909 + struct bfd_link_info *info, bfd_boolean *again);
1911 +enum relax_pass_id {
1912 + RELAX_PASS_SIZE_FRAGS,
1913 + RELAX_PASS_MOVE_DATA,
1916 +/* Stolen from the xtensa port */
1918 +internal_reloc_compare (const void *ap, const void *bp)
1920 + const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap;
1921 + const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp;
1923 + if (a->r_offset != b->r_offset)
1924 + return (a->r_offset - b->r_offset);
1926 + /* We don't need to sort on these criteria for correctness,
1927 + but enforcing a more strict ordering prevents unstable qsort
1928 + from behaving differently with different implementations.
1929 + Without the code below we get correct but different results
1930 + on Solaris 2.7 and 2.8. We would like to always produce the
1931 + same results no matter the host. */
1933 + if (a->r_info != b->r_info)
1934 + return (a->r_info - b->r_info);
1936 + return (a->r_addend - b->r_addend);
1939 +static enum relax_state_id
1940 +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1941 + const Elf_Internal_Rela *rela)
1943 + bfd_byte *contents;
1945 + enum relax_state_id rs = RS_NONE;
1947 + contents = retrieve_contents(abfd, sec, info->keep_memory);
1951 + insn = bfd_get_32(abfd, contents + rela->r_offset);
1952 + if ((insn & RCALL2_MASK) == RCALL2_OPCODE)
1954 + else if ((insn & BRAL_MASK) == BRAL_OPCODE)
1955 + /* Optimizing bral -> rjmp gets us into all kinds of
1956 + trouble with jump tables. Better not do it. */
1958 + else if ((insn & BRC2_MASK) == BRC2_OPCODE)
1961 + release_contents(sec, contents);
1966 +static enum relax_state_id
1967 +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1968 + const Elf_Internal_Rela *rela)
1970 + switch (ELF_R_TYPE(rela->r_info))
1972 + case R_AVR32_GOTCALL:
1973 + return RS_PIC_CALL;
1974 + case R_AVR32_GOT18SW:
1975 + return RS_PIC_MCALL;
1976 + case R_AVR32_LDA_GOT:
1977 + return RS_PIC_LDA;
1978 + case R_AVR32_GOT16S:
1979 + return RS_PIC_LDW4;
1980 + case R_AVR32_CPCALL:
1981 + return RS_NOPIC_MCALL;
1982 + case R_AVR32_16_CP:
1983 + return RS_NOPIC_LDW4;
1984 + case R_AVR32_9W_CP:
1985 + return RS_NOPIC_LDDPC;
1986 + case R_AVR32_ALIGN:
1988 + case R_AVR32_32_CPENT:
1990 + case R_AVR32_22H_PCREL:
1991 + return get_pcrel22_relax_state(abfd, sec, info, rela);
1992 + case R_AVR32_9H_PCREL:
2000 +reloc_is_cpool_ref(const Elf_Internal_Rela *rela)
2002 + switch (ELF_R_TYPE(rela->r_info))
2004 + case R_AVR32_CPCALL:
2005 + case R_AVR32_16_CP:
2006 + case R_AVR32_9W_CP:
2013 +static struct fragment *
2014 +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
2015 + struct avr32_relax_data *rd, enum relax_state_id state,
2016 + Elf_Internal_Rela *rela)
2018 + struct fragment *frag;
2019 + bfd_size_type r_size;
2021 + unsigned int i = rd->frag_count;
2023 + BFD_ASSERT(state >= RS_NONE && state < RS_MAX);
2026 + frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count);
2032 + memset(frag, 0, sizeof(struct fragment));
2034 + if (state == RS_ALIGN)
2035 + r_size = (((rela->r_offset + (1 << rela->r_addend) - 1)
2036 + & ~((1 << rela->r_addend) - 1)) - rela->r_offset);
2038 + r_size = relax_state[state].size;
2041 + r_offset = rela->r_offset;
2043 + r_offset = sec->size;
2048 + frag->size = r_offset + r_size;
2052 + frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size;
2053 + frag->size = r_offset + r_size - frag->offset;
2056 + if (state != RS_CPENT)
2057 + /* Make sure we don't discard this frag */
2058 + frag->refcount = 1;
2060 + frag->initial_state = frag->state = state;
2061 + frag->rela = rela;
2066 +static struct fragment *
2067 +find_frag(asection *sec, bfd_vma offset)
2069 + struct fragment *first, *last;
2070 + struct avr32_relax_data *rd = avr32_relax_data(sec);
2072 + if (rd->frag_count == 0)
2075 + first = &rd->frag[0];
2076 + last = &rd->frag[rd->frag_count - 1];
2078 + /* This may be a reloc referencing the end of a section. The last
2079 + frag will never have a reloc associated with it, so its size will
2080 + never change, thus the offset adjustment of the last frag will
2081 + always be the same as the offset adjustment of the end of the
2083 + if (offset == sec->size)
2085 + BFD_ASSERT(last->offset + last->size == sec->size);
2086 + BFD_ASSERT(!last->rela);
2090 + while (first <= last)
2092 + struct fragment *mid;
2094 + mid = (last - first) / 2 + first;
2095 + if ((mid->offset + mid->size) <= offset)
2097 + else if (mid->offset > offset)
2106 +/* Look through all relocs in a section and determine if any relocs
2107 + may be affected by relaxation in other sections. If so, allocate
2108 + an array of additional relocation data which links the affected
2109 + relocations to the frag(s) where the relaxation may occur.
2111 + This function also links cpool references to cpool entries and
2112 + increments the refcount of the latter when this happens. */
2115 +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs,
2116 + struct bfd_link_info *info)
2118 + Elf_Internal_Shdr *symtab_hdr;
2119 + Elf_Internal_Sym *isymbuf = NULL;
2120 + struct avr32_relax_data *rd;
2122 + bfd_boolean ret = FALSE;
2124 + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2125 + rd = avr32_relax_data(sec);
2127 + RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name);
2129 + for (i = 0; i < sec->reloc_count; i++)
2131 + Elf_Internal_Rela *rel = &relocs[i];
2132 + asection *sym_sec;
2133 + unsigned long r_symndx;
2134 + bfd_vma sym_value;
2136 + if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32
2137 + && !reloc_is_cpool_ref(rel))
2140 + r_symndx = ELF_R_SYM(rel->r_info);
2142 + if (r_symndx < symtab_hdr->sh_info)
2144 + Elf_Internal_Sym *isym;
2147 + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2151 + isym = &isymbuf[r_symndx];
2152 + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2153 + sym_value = isym->st_value;
2157 + struct elf_link_hash_entry *h;
2159 + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2161 + while (h->root.type == bfd_link_hash_indirect
2162 + || h->root.type == bfd_link_hash_warning)
2163 + h = (struct elf_link_hash_entry *)h->root.u.i.link;
2165 + if (h->root.type != bfd_link_hash_defined
2166 + && h->root.type != bfd_link_hash_defweak)
2169 + sym_sec = h->root.u.def.section;
2170 + sym_value = h->root.u.def.value;
2173 + if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable)
2175 + bfd_size_type size;
2176 + struct fragment *frag;
2178 + if (!rd->reloc_data)
2180 + size = sizeof(struct avr32_reloc_data) * sec->reloc_count;
2181 + rd->reloc_data = bfd_zalloc(abfd, size);
2182 + if (!rd->reloc_data)
2186 + RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx",
2187 + i, rel->r_offset, sym_value, rel->r_addend);
2189 + frag = find_frag(sym_sec, sym_value + rel->r_addend);
2191 + rd->reloc_data[i].add_frag = frag;
2193 + RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name,
2194 + frag->rela ? frag->rela->r_offset : sym_sec->size);
2196 + if (reloc_is_cpool_ref(rel))
2198 + BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT);
2202 + if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32)
2204 + bfd_byte *contents;
2205 + bfd_signed_vma diff;
2207 + contents = retrieve_contents(abfd, sec, info->keep_memory);
2211 + diff = bfd_get_signed_32(abfd, contents + rel->r_offset);
2212 + frag = find_frag(sym_sec, sym_value + rel->r_addend + diff);
2214 + rd->reloc_data[i].sub_frag = frag;
2216 + release_contents(sec, contents);
2224 + release_local_syms(abfd, isymbuf);
2229 +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr,
2230 + struct bfd_link_info *info ATTRIBUTE_UNUSED)
2232 + struct fragment *frag;
2235 + if (havr->root.root.type != bfd_link_hash_defined
2236 + && havr->root.root.type != bfd_link_hash_defweak)
2239 + sec = havr->root.root.u.def.section;
2240 + if (bfd_is_const_section(sec)
2241 + || !avr32_relax_data(sec)->is_relaxable)
2244 + frag = find_frag(sec, havr->root.root.u.def.value);
2248 + struct avr32_relax_data *rd = avr32_relax_data(sec);
2250 + RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n",
2251 + sec->owner->filename, havr->root.root.root.string,
2252 + sec->name, havr->root.root.u.def.value, sec->size);
2253 + for (i = 0; i < rd->frag_count; i++)
2254 + RDBG(" %8lu - %8lu\n", rd->frag[i].offset,
2255 + rd->frag[i].offset + rd->frag[i].size);
2259 + havr->sym_frag = frag;
2264 +analyze_relocations(struct bfd_link_info *info)
2269 + /* Divide all relaxable sections into fragments */
2270 + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2272 + if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX))
2274 + if (!(*info->callbacks->warning)
2275 + (info, _("input is not relaxable"), NULL, abfd, NULL, 0))
2280 + for (sec = abfd->sections; sec; sec = sec->next)
2282 + struct avr32_relax_data *rd;
2283 + struct fragment *frag;
2284 + Elf_Internal_Rela *relocs;
2286 + bfd_boolean ret = TRUE;
2288 + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2291 + rd = avr32_relax_data(sec);
2293 + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2297 + qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela),
2298 + internal_reloc_compare);
2300 + for (i = 0; i < sec->reloc_count; i++)
2302 + enum relax_state_id state;
2305 + state = get_initial_relax_state(abfd, sec, info, &relocs[i]);
2306 + if (state == RS_ERROR)
2311 + frag = new_frag(abfd, sec, rd, state, &relocs[i]);
2315 + pin_internal_relocs(sec, relocs);
2316 + rd->is_relaxable = TRUE;
2322 + release_internal_relocs(sec, relocs);
2326 + if (rd->is_relaxable)
2328 + frag = new_frag(abfd, sec, rd, RS_NONE, NULL);
2335 + /* Link each global symbol to the fragment where it's defined. */
2336 + elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info);
2338 + /* Do the same for local symbols. */
2339 + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2341 + Elf_Internal_Sym *isymbuf, *isym;
2342 + struct fragment **local_sym_frag;
2343 + unsigned int i, sym_count;
2345 + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2346 + if (sym_count == 0)
2349 + local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *));
2350 + if (!local_sym_frag)
2352 + elf_tdata(abfd)->local_sym_frag = local_sym_frag;
2354 + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2358 + for (i = 0; i < sym_count; i++)
2360 + struct avr32_relax_data *rd;
2361 + struct fragment *frag;
2364 + isym = &isymbuf[i];
2366 + sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2370 + rd = avr32_relax_data(sec);
2371 + if (!rd->is_relaxable)
2374 + frag = find_frag(sec, isym->st_value);
2377 + local_sym_frag[i] = frag;
2380 + release_local_syms(abfd, isymbuf);
2383 + /* And again for relocs with addends and constant pool references */
2384 + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2385 + for (sec = abfd->sections; sec; sec = sec->next)
2387 + Elf_Internal_Rela *relocs;
2390 + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2393 + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2397 + ret = allocate_reloc_data(abfd, sec, relocs, info);
2399 + release_internal_relocs(sec, relocs);
2408 +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag,
2409 + bfd_vma symval, bfd_vma addr, struct got_entry *got,
2410 + struct avr32_reloc_data *ind_data,
2411 + bfd_signed_vma offset_adjust)
2413 + bfd_signed_vma target = 0;
2415 + switch (rs->reftype)
2417 + case REF_ABSOLUTE:
2421 + target = symval - addr;
2424 + /* cpool frags are always in the same section and always after
2425 + all frags referring to it. So it's always correct to add in
2426 + offset_adjust here. */
2427 + target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust
2428 + + offset_adjust - frag->offset - frag->offset_adjust);
2431 + target = got->offset;
2437 + if (target >= rs->range_min && target <= rs->range_max)
2444 +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info)
2446 + struct elf_avr32_link_hash_table *htab;
2447 + struct avr32_relax_data *rd;
2448 + Elf_Internal_Shdr *symtab_hdr;
2449 + Elf_Internal_Rela *relocs = NULL;
2450 + Elf_Internal_Sym *isymbuf = NULL;
2451 + struct got_entry **local_got_ents;
2452 + struct fragment **local_sym_frag;
2453 + bfd_boolean ret = FALSE;
2454 + bfd_signed_vma delta = 0;
2457 + htab = avr32_elf_hash_table(info);
2458 + rd = avr32_relax_data(sec);
2460 + if (sec == htab->sgot)
2462 + RDBG("Relaxing GOT section (vma: 0x%lx)\n",
2463 + sec->output_section->vma + sec->output_offset);
2464 + if (assign_got_offsets(htab))
2465 + htab->repeat_pass = TRUE;
2469 + if (!rd->is_relaxable)
2472 + if (!sec->rawsize)
2473 + sec->rawsize = sec->size;
2475 + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2476 + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2480 + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2484 + local_got_ents = elf_local_got_ents(abfd);
2485 + local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2487 + RDBG("size_frags: %s<%s>\n vma: 0x%08lx, size: 0x%08lx\n",
2488 + abfd->filename, sec->name,
2489 + sec->output_section->vma + sec->output_offset, sec->size);
2491 + for (i = 0; i < rd->frag_count; i++)
2493 + struct fragment *frag = &rd->frag[i];
2494 + struct avr32_reloc_data *r_data = NULL, *ind_data = NULL;
2495 + const struct relax_state *state, *next_state;
2496 + struct fragment *target_frag = NULL;
2497 + asection *sym_sec = NULL;
2498 + Elf_Internal_Rela *rela;
2499 + struct got_entry *got;
2500 + bfd_vma symval, r_offset, addend, addr;
2501 + bfd_signed_vma size_adjust = 0, distance;
2502 + unsigned long r_symndx;
2503 + bfd_boolean defined = TRUE, dynamic = FALSE;
2504 + unsigned char sym_type;
2506 + frag->offset_adjust += delta;
2507 + state = next_state = &relax_state[frag->state];
2508 + rela = frag->rela;
2510 + BFD_ASSERT(state->id == frag->state);
2512 + RDBG(" 0x%04lx%c%d: %s [size %ld]", rela ? rela->r_offset : sec->rawsize,
2513 + (frag->offset_adjust < 0)?'-':'+',
2514 + abs(frag->offset_adjust), state->name, state->size);
2518 + RDBG(": no reloc, ignoring\n");
2522 + BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count);
2523 + BFD_ASSERT(state != RS_NONE);
2525 + r_offset = rela->r_offset + frag->offset_adjust;
2526 + addr = sec->output_section->vma + sec->output_offset + r_offset;
2528 + switch (frag->state)
2531 + size_adjust = ((addr + (1 << rela->r_addend) - 1)
2532 + & ~((1 << rela->r_addend) - 1));
2533 + size_adjust -= (sec->output_section->vma + sec->output_offset
2534 + + frag->offset + frag->offset_adjust
2535 + + frag->size + frag->size_adjust);
2537 + RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust,
2538 + frag->size + frag->size_adjust + size_adjust);
2542 + if (frag->refcount == 0 && frag->size_adjust == 0)
2544 + RDBG(": discarding frag\n");
2547 + else if (frag->refcount > 0 && frag->size_adjust < 0)
2549 + RDBG(": un-discarding frag\n");
2555 + if (rd->reloc_data)
2556 + r_data = &rd->reloc_data[frag->rela - relocs];
2558 + /* If this is a cpool reference, we want the symbol that the
2559 + cpool entry refers to, not the symbol for the cpool entry
2560 + itself, as we already know what frag it's in. */
2561 + if (relax_state[frag->initial_state].reftype == REF_CPOOL)
2563 + Elf_Internal_Rela *irela = r_data->add_frag->rela;
2565 + r_symndx = ELF_R_SYM(irela->r_info);
2566 + addend = irela->r_addend;
2568 + /* The constant pool must be in the same section as the
2569 + reloc referring to it. */
2570 + BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count);
2572 + ind_data = r_data;
2573 + r_data = &rd->reloc_data[irela - relocs];
2577 + r_symndx = ELF_R_SYM(rela->r_info);
2578 + addend = rela->r_addend;
2581 + /* Get the value of the symbol referred to by the reloc. */
2582 + if (r_symndx < symtab_hdr->sh_info)
2584 + Elf_Internal_Sym *isym;
2586 + isym = isymbuf + r_symndx;
2589 + RDBG(" local sym %lu: ", r_symndx);
2591 + if (isym->st_shndx == SHN_UNDEF)
2593 + else if (isym->st_shndx == SHN_ABS)
2594 + sym_sec = bfd_abs_section_ptr;
2595 + else if (isym->st_shndx == SHN_COMMON)
2596 + sym_sec = bfd_com_section_ptr;
2598 + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2600 + symval = isym->st_value;
2601 + sym_type = ELF_ST_TYPE(isym->st_info);
2602 + target_frag = local_sym_frag[r_symndx];
2604 + if (local_got_ents)
2605 + got = local_got_ents[r_symndx];
2611 + /* Global symbol */
2612 + unsigned long index;
2613 + struct elf_link_hash_entry *h;
2614 + struct elf_avr32_link_hash_entry *havr;
2616 + index = r_symndx - symtab_hdr->sh_info;
2617 + h = elf_sym_hashes(abfd)[index];
2618 + BFD_ASSERT(h != NULL);
2620 + while (h->root.type == bfd_link_hash_indirect
2621 + || h->root.type == bfd_link_hash_warning)
2622 + h = (struct elf_link_hash_entry *)h->root.u.i.link;
2624 + havr = (struct elf_avr32_link_hash_entry *)h;
2625 + got = h->got.glist;
2629 + RDBG(" %s: ", h->root.root.string);
2631 + if (h->root.type != bfd_link_hash_defined
2632 + && h->root.type != bfd_link_hash_defweak)
2637 + else if ((info->shared && !info->symbolic && h->dynindx != -1)
2638 + || (htab->root.dynamic_sections_created
2639 + && h->def_dynamic && !h->def_regular))
2641 + RDBG("(dynamic)");
2643 + sym_sec = h->root.u.def.section;
2647 + sym_sec = h->root.u.def.section;
2648 + symval = h->root.u.def.value;
2649 + target_frag = havr->sym_frag;
2652 + sym_type = h->type;
2655 + /* Thanks to elf32-ppc for this one. */
2656 + if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE)
2658 + /* At this stage in linking, no SEC_MERGE symbol has been
2659 + adjusted, so all references to such symbols need to be
2660 + passed through _bfd_merged_section_offset. (Later, in
2661 + relocate_section, all SEC_MERGE symbols *except* for
2662 + section symbols have been adjusted.)
2664 + SEC_MERGE sections are not relaxed by us, as they
2665 + shouldn't contain any code. */
2667 + BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag));
2669 + /* gas may reduce relocations against symbols in SEC_MERGE
2670 + sections to a relocation against the section symbol when
2671 + the original addend was zero. When the reloc is against
2672 + a section symbol we should include the addend in the
2673 + offset passed to _bfd_merged_section_offset, since the
2674 + location of interest is the original symbol. On the
2675 + other hand, an access to "sym+addend" where "sym" is not
2676 + a section symbol should not include the addend; Such an
2677 + access is presumed to be an offset from "sym"; The
2678 + location of interest is just "sym". */
2679 + RDBG("\n MERGE: %s: 0x%lx+0x%lx+0x%lx -> ",
2680 + (sym_type == STT_SECTION)?"section":"not section",
2681 + sym_sec->output_section->vma + sym_sec->output_offset,
2684 + if (sym_type == STT_SECTION)
2687 + symval = (_bfd_merged_section_offset
2689 + elf_section_data(sym_sec)->sec_info, symval));
2691 + if (sym_type != STT_SECTION)
2697 + if (defined && !dynamic)
2699 + RDBG("0x%lx+0x%lx",
2700 + sym_sec->output_section->vma + sym_sec->output_offset,
2702 + symval += sym_sec->output_section->vma + sym_sec->output_offset;
2705 + if (r_data && r_data->add_frag)
2706 + /* If the add_frag pointer is set, it means that this reloc
2707 + has an addend that may be affected by relaxation. */
2708 + target_frag = r_data->add_frag;
2712 + symval += target_frag->offset_adjust;
2714 + /* If target_frag comes after this frag in the same
2715 + section, we should assume that it will be moved by
2716 + the same amount we are. */
2717 + if ((target_frag - rd->frag) < (int)rd->frag_count
2718 + && target_frag > frag)
2722 + distance = symval - addr;
2724 + /* First, try to make a direct reference. If the symbol is
2725 + dynamic or undefined, we must take care not to change its
2726 + reference type, that is, we can't make it direct.
2728 + Also, it seems like some sections may actually be resized
2729 + after the relaxation code is done, so we can't really
2730 + trust that our "distance" is correct. There's really no
2731 + easy solution to this problem, so we'll just disallow
2732 + direct references to SEC_DATA sections.
2734 + Oh, and .bss isn't actually SEC_DATA, so we disallow
2735 + !SEC_HAS_CONTENTS as well. */
2736 + if (!dynamic && defined
2737 + && (htab->direct_data_refs
2738 + || (!(sym_sec->flags & SEC_DATA)
2739 + && (sym_sec->flags & SEC_HAS_CONTENTS)))
2740 + && next_state->direct)
2742 + next_state = &relax_state[next_state->direct];
2743 + RDBG(" D-> %s", next_state->name);
2746 + /* Iterate backwards until we find a state that fits. */
2747 + while (next_state->prev
2748 + && !rs_is_good_enough(next_state, frag, symval, addr,
2749 + got, ind_data, delta))
2751 + next_state = &relax_state[next_state->prev];
2752 + RDBG(" P-> %s", next_state->name);
2755 + /* Then try to find the best possible state. */
2756 + while (next_state->next)
2758 + const struct relax_state *candidate;
2760 + candidate = &relax_state[next_state->next];
2761 + if (!rs_is_good_enough(candidate, frag, symval, addr, got,
2765 + next_state = candidate;
2766 + RDBG(" N-> %s", next_state->name);
2769 + RDBG(" [size %ld]\n", next_state->size);
2771 + BFD_ASSERT(next_state->id);
2772 + BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT);
2774 + size_adjust = next_state->size - state->size;
2776 + /* There's a theoretical possibility that shrinking one frag
2777 + may cause another to grow, which may cause the first one to
2778 + grow as well, and we're back where we started. Avoid this
2779 + scenario by disallowing a frag that has grown to ever
2781 + if (state->reftype == REF_GOT && next_state->reftype != REF_GOT)
2783 + if (frag->has_grown)
2784 + next_state = state;
2786 + unref_got_entry(htab, got);
2788 + else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT)
2790 + ref_got_entry(htab, got);
2791 + frag->has_grown = TRUE;
2793 + else if (state->reftype == REF_CPOOL
2794 + && next_state->reftype != REF_CPOOL)
2796 + if (frag->has_grown)
2797 + next_state = state;
2799 + ind_data->add_frag->refcount--;
2801 + else if (state->reftype != REF_CPOOL
2802 + && next_state->reftype == REF_CPOOL)
2804 + ind_data->add_frag->refcount++;
2805 + frag->has_grown = TRUE;
2809 + if (frag->has_grown && size_adjust < 0)
2810 + next_state = state;
2811 + else if (size_adjust > 0)
2812 + frag->has_grown = TRUE;
2815 + size_adjust = next_state->size - state->size;
2816 + frag->state = next_state->id;
2822 + htab->repeat_pass = TRUE;
2824 + frag->size_adjust += size_adjust;
2825 + sec->size += size_adjust;
2826 + delta += size_adjust;
2828 + BFD_ASSERT((frag->offset + frag->offset_adjust
2829 + + frag->size + frag->size_adjust)
2830 + == (frag[1].offset + frag[1].offset_adjust + delta));
2836 + release_local_syms(abfd, isymbuf);
2837 + release_internal_relocs(sec, relocs);
2842 +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr,
2843 + struct bfd_link_info *info ATTRIBUTE_UNUSED)
2845 + struct elf_link_hash_entry *h = &havr->root;
2847 + if (havr->sym_frag && (h->root.type == bfd_link_hash_defined
2848 + || h->root.type == bfd_link_hash_defweak))
2850 + RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n",
2851 + h->root.root.string, h->root.u.def.value,
2852 + h->root.u.def.value + havr->sym_frag->offset_adjust);
2853 + h->root.u.def.value += havr->sym_frag->offset_adjust;
2859 +adjust_syms(struct bfd_link_info *info)
2861 + struct elf_avr32_link_hash_table *htab;
2864 + htab = avr32_elf_hash_table(info);
2865 + elf_link_hash_traverse(&htab->root, adjust_global_symbol, info);
2867 + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2869 + Elf_Internal_Sym *isymbuf;
2870 + struct fragment **local_sym_frag, *frag;
2871 + unsigned int i, sym_count;
2873 + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2874 + if (sym_count == 0)
2877 + isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2881 + local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2883 + for (i = 0; i < sym_count; i++)
2885 + frag = local_sym_frag[i];
2888 + RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n",
2889 + abfd->filename, i, isymbuf[i].st_value,
2890 + isymbuf[i].st_value + frag->offset_adjust);
2891 + isymbuf[i].st_value += frag->offset_adjust;
2895 + release_local_syms(abfd, isymbuf);
2898 + htab->symbols_adjusted = TRUE;
2903 +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info)
2905 + struct avr32_relax_data *rd;
2906 + Elf_Internal_Rela *relocs;
2907 + Elf_Internal_Shdr *symtab_hdr;
2909 + bfd_boolean ret = FALSE;
2911 + rd = avr32_relax_data(sec);
2912 + if (!rd->reloc_data)
2915 + RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name,
2916 + sec->reloc_count);
2918 + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2922 + symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2924 + for (i = 0; i < sec->reloc_count; i++)
2926 + Elf_Internal_Rela *rela = &relocs[i];
2927 + struct avr32_reloc_data *r_data = &rd->reloc_data[i];
2928 + struct fragment *sym_frag;
2929 + unsigned long r_symndx;
2931 + if (r_data->add_frag)
2933 + r_symndx = ELF_R_SYM(rela->r_info);
2935 + if (r_symndx < symtab_hdr->sh_info)
2936 + sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx];
2939 + struct elf_link_hash_entry *h;
2941 + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2943 + while (h->root.type == bfd_link_hash_indirect
2944 + || h->root.type == bfd_link_hash_warning)
2945 + h = (struct elf_link_hash_entry *)h->root.u.i.link;
2947 + BFD_ASSERT(h->root.type == bfd_link_hash_defined
2948 + || h->root.type == bfd_link_hash_defweak);
2950 + sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag;
2953 + RDBG(" addend: 0x%08lx -> 0x%08lx\n",
2955 + rela->r_addend + r_data->add_frag->offset_adjust
2956 + - (sym_frag ? sym_frag->offset_adjust : 0));
2958 + /* If this is against a section symbol, we won't find any
2959 + sym_frag, so we'll just adjust the addend. */
2960 + rela->r_addend += r_data->add_frag->offset_adjust;
2962 + rela->r_addend -= sym_frag->offset_adjust;
2964 + if (r_data->sub_frag)
2966 + bfd_byte *contents;
2967 + bfd_signed_vma diff;
2969 + contents = retrieve_contents(abfd, sec, info->keep_memory);
2973 + /* I realize now that sub_frag is misnamed. It's
2974 + actually add_frag which is subtracted in this
2976 + diff = bfd_get_signed_32(abfd, contents + rela->r_offset);
2977 + diff += (r_data->sub_frag->offset_adjust
2978 + - r_data->add_frag->offset_adjust);
2979 + bfd_put_32(abfd, diff, contents + rela->r_offset);
2981 + RDBG(" 0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff);
2983 + release_contents(sec, contents);
2987 + BFD_ASSERT(!r_data->sub_frag);
2993 + release_internal_relocs(sec, relocs);
2998 +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info)
3000 + struct elf_avr32_link_hash_table *htab;
3001 + struct avr32_relax_data *rd;
3002 + struct fragment *frag, *fragend;
3003 + Elf_Internal_Rela *relocs = NULL;
3004 + bfd_byte *contents = NULL;
3006 + bfd_boolean ret = FALSE;
3008 + htab = avr32_elf_hash_table(info);
3009 + rd = avr32_relax_data(sec);
3011 + if (!htab->symbols_adjusted)
3012 + if (!adjust_syms(info))
3015 + if (rd->is_relaxable)
3017 + /* Resize the section first, so that we can be sure that enough
3018 + memory is allocated in case the section has grown. */
3019 + if (sec->size > sec->rawsize
3020 + && elf_section_data(sec)->this_hdr.contents)
3022 + /* We must not use cached data if the section has grown. */
3023 + free(elf_section_data(sec)->this_hdr.contents);
3024 + elf_section_data(sec)->this_hdr.contents = NULL;
3027 + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
3030 + contents = retrieve_contents(abfd, sec, info->keep_memory);
3034 + fragend = rd->frag + rd->frag_count;
3036 + RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n",
3037 + abfd->filename, sec->name, relocs, contents);
3039 + /* First, move the data into place. We must take care to move
3040 + frags in the right order so that we don't accidentally
3041 + overwrite parts of the next frag. */
3042 + for (frag = rd->frag; frag < fragend; frag++)
3044 + RDBG(" 0x%08lx%c0x%x: size 0x%lx%c0x%x\n",
3045 + frag->offset, frag->offset_adjust >= 0 ? '+' : '-',
3046 + abs(frag->offset_adjust),
3047 + frag->size, frag->size_adjust >= 0 ? '+' : '-',
3048 + abs(frag->size_adjust));
3049 + if (frag->offset_adjust > 0)
3051 + struct fragment *prev = frag - 1;
3052 + struct fragment *last;
3054 + for (last = frag; last < fragend && last->offset_adjust > 0;
3057 + if (last == fragend)
3060 + for (frag = last; frag != prev; frag--)
3062 + if (frag->offset_adjust
3063 + && frag->size + frag->size_adjust > 0)
3065 + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3066 + frag->offset, frag->offset + frag->offset_adjust,
3067 + frag->size + frag->size_adjust);
3068 + memmove(contents + frag->offset + frag->offset_adjust,
3069 + contents + frag->offset,
3070 + frag->size + frag->size_adjust);
3075 + else if (frag->offset_adjust && frag->size + frag->size_adjust > 0)
3077 + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3078 + frag->offset, frag->offset + frag->offset_adjust,
3079 + frag->size + frag->size_adjust);
3080 + memmove(contents + frag->offset + frag->offset_adjust,
3081 + contents + frag->offset,
3082 + frag->size + frag->size_adjust);
3088 + for (frag = rd->frag; frag < fragend; frag++)
3090 + const struct relax_state *state, *istate;
3091 + struct avr32_reloc_data *r_data = NULL;
3093 + istate = &relax_state[frag->initial_state];
3094 + state = &relax_state[frag->state];
3096 + if (rd->reloc_data)
3097 + r_data = &rd->reloc_data[frag->rela - relocs];
3099 + BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0);
3100 + BFD_ASSERT(state->reftype != REF_CPOOL
3101 + || r_data->add_frag->refcount > 0);
3103 + if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL)
3105 + struct fragment *ifrag;
3107 + /* An indirect reference through the cpool has been
3108 + converted to a direct reference. We must update the
3109 + reloc to point to the symbol itself instead of the
3110 + constant pool entry. The reloc type will be updated
3112 + ifrag = r_data->add_frag;
3113 + frag->rela->r_info = ifrag->rela->r_info;
3114 + frag->rela->r_addend = ifrag->rela->r_addend;
3116 + /* Copy the reloc data so the addend will be adjusted
3117 + correctly later. */
3118 + *r_data = rd->reloc_data[ifrag->rela - relocs];
3121 + /* Move all relocs covered by this frag. */
3123 + BFD_ASSERT(&relocs[i] <= frag->rela);
3125 + BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE);
3127 + if (frag == rd->frag)
3128 + BFD_ASSERT(i == 0);
3130 + BFD_ASSERT(&relocs[i] > frag[-1].rela);
3132 + /* If non-null, frag->rela is the last relocation in the
3133 + fragment. frag->rela can only be null in the last
3134 + fragment, so in that case, we'll just do the rest. */
3135 + for (; (i < sec->reloc_count
3136 + && (!frag->rela || &relocs[i] <= frag->rela)); i++)
3138 + RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset,
3139 + relocs[i].r_offset + frag->offset_adjust);
3140 + relocs[i].r_offset += frag->offset_adjust;
3143 + if (frag->refcount == 0)
3145 + /* If this frag is to be discarded, make sure we won't
3146 + relocate it later on. */
3147 + BFD_ASSERT(frag->state == RS_CPENT);
3148 + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3151 + else if (frag->state == RS_ALIGN)
3153 + bfd_vma addr, addr_end;
3155 + addr = frag->rela->r_offset;
3156 + addr_end = (frag->offset + frag->offset_adjust
3157 + + frag->size + frag->size_adjust);
3159 + /* If the section is executable, insert NOPs.
3160 + Otherwise, insert zeroes. */
3161 + if (sec->flags & SEC_CODE)
3165 + bfd_put_8(abfd, 0, contents + addr);
3169 + BFD_ASSERT(!((addr_end - addr) & 1));
3171 + while (addr < addr_end)
3173 + bfd_put_16(abfd, NOP_OPCODE, contents + addr);
3178 + memset(contents + addr, 0, addr_end - addr);
3180 + else if (state->opcode_mask)
3184 + /* Update the opcode and the relocation type unless it's a
3185 + "special" relax state (i.e. RS_NONE, RS_ALIGN or
3186 + RS_CPENT.), in which case the opcode mask is zero. */
3187 + insn = bfd_get_32(abfd, contents + frag->rela->r_offset);
3188 + insn &= ~state->opcode_mask;
3189 + insn |= state->opcode;
3190 + RDBG(" 0x%lx: inserting insn %08lx\n",
3191 + frag->rela->r_offset, insn);
3192 + bfd_put_32(abfd, insn, contents + frag->rela->r_offset);
3194 + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3198 + if ((frag + 1) == fragend)
3199 + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3200 + + frag->size_adjust) == sec->size);
3202 + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3203 + + frag->size_adjust)
3204 + == (frag[1].offset + frag[1].offset_adjust));
3208 + /* Adjust reloc addends and DIFF32 differences */
3209 + if (!adjust_relocs(abfd, sec, info))
3215 + release_contents(sec, contents);
3216 + release_internal_relocs(sec, relocs);
3221 +avr32_elf_relax_section(bfd *abfd, asection *sec,
3222 + struct bfd_link_info *info, bfd_boolean *again)
3224 + struct elf_avr32_link_hash_table *htab;
3225 + struct avr32_relax_data *rd;
3228 + if (info->relocatable)
3231 + htab = avr32_elf_hash_table(info);
3232 + if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
3233 + && sec != htab->sgot)
3236 + if (!htab->relocations_analyzed)
3238 + if (!analyze_relocations(info))
3240 + htab->relocations_analyzed = TRUE;
3243 + rd = avr32_relax_data(sec);
3245 + if (rd->iteration != htab->relax_iteration)
3247 + if (!htab->repeat_pass)
3248 + htab->relax_pass++;
3249 + htab->relax_iteration++;
3250 + htab->repeat_pass = FALSE;
3255 + switch (htab->relax_pass)
3257 + case RELAX_PASS_SIZE_FRAGS:
3258 + if (!avr32_size_frags(abfd, sec, info))
3262 + case RELAX_PASS_MOVE_DATA:
3263 + if (!avr32_move_data(abfd, sec, info))
3274 +static bfd_reloc_status_type
3275 +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela,
3276 + bfd_signed_vma relocation, reloc_howto_type *howto);
3277 +static bfd_reloc_status_type
3278 +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd,
3279 + asection *input_section, bfd_byte *contents,
3280 + Elf_Internal_Rela *rel, bfd_vma value);
3282 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3283 + bfd *input_bfd, asection *input_section,
3284 + bfd_byte *contents, Elf_Internal_Rela *relocs,
3285 + Elf_Internal_Sym *local_syms,
3286 + asection **local_sections);
3289 +#define symbol_address(symbol) \
3290 + symbol->value + symbol->section->output_section->vma \
3291 + + symbol->section->output_offset
3293 +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data) \
3296 + unsigned long x; \
3297 + x = bfd_get_##size (abfd, data + reloc_entry->address); \
3298 + x &= ~reloc_entry->howto->dst_mask; \
3299 + x |= field & reloc_entry->howto->dst_mask; \
3300 + bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \
3304 +static bfd_reloc_status_type
3305 +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED,
3306 + Elf_Internal_Rela *rela ATTRIBUTE_UNUSED,
3307 + bfd_signed_vma relocation,
3308 + reloc_howto_type *howto)
3312 + /* We take "complain_overflow_dont" to mean "don't complain on
3313 + alignment either". This way, we don't have to special-case
3315 + if (howto->complain_on_overflow == complain_overflow_dont)
3316 + return bfd_reloc_ok;
3318 + /* Check if the value is correctly aligned */
3319 + if (relocation & ((1 << howto->rightshift) - 1))
3321 + RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n",
3322 + sec->owner->filename, sec->name, rela->r_offset,
3323 + howto->name, relocation, howto->rightshift);
3324 + return bfd_reloc_overflow;
3327 + /* Now, get rid of the unnecessary bits */
3328 + relocation >>= howto->rightshift;
3329 + reloc_u = (bfd_vma)relocation;
3331 + switch (howto->complain_on_overflow)
3333 + case complain_overflow_unsigned:
3334 + case complain_overflow_bitfield:
3335 + if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1))
3337 + RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3338 + sec->owner->filename, sec->name, rela->r_offset,
3339 + howto->name, reloc_u, howto->bitsize);
3340 + RDBG("reloc vma: 0x%lx\n",
3341 + sec->output_section->vma + sec->output_offset + rela->r_offset);
3343 + return bfd_reloc_overflow;
3346 + case complain_overflow_signed:
3347 + if (relocation > (1 << (howto->bitsize - 1)) - 1)
3349 + RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3350 + sec->owner->filename, sec->name, rela->r_offset,
3351 + howto->name, reloc_u, howto->bitsize);
3352 + RDBG("reloc vma: 0x%lx\n",
3353 + sec->output_section->vma + sec->output_offset + rela->r_offset);
3355 + return bfd_reloc_overflow;
3357 + if (relocation < -(1 << (howto->bitsize - 1)))
3359 + RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n",
3360 + sec->owner->filename, sec->name, rela->r_offset,
3361 + howto->name, -relocation, howto->bitsize);
3362 + RDBG("reloc vma: 0x%lx\n",
3363 + sec->output_section->vma + sec->output_offset + rela->r_offset);
3365 + return bfd_reloc_overflow;
3372 + return bfd_reloc_ok;
3376 +static bfd_reloc_status_type
3377 +avr32_final_link_relocate(reloc_howto_type *howto,
3379 + asection *input_section,
3380 + bfd_byte *contents,
3381 + Elf_Internal_Rela *rel,
3385 + bfd_vma relocation;
3386 + bfd_reloc_status_type status;
3387 + bfd_byte *p = contents + rel->r_offset;
3390 + pr_debug(" (6b) final link relocate\n");
3392 + /* Sanity check the address */
3393 + if (rel->r_offset > input_section->size)
3395 + (*_bfd_error_handler)
3396 + ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)",
3397 + input_bfd, input_section, rel->r_offset, input_section->size);
3398 + return bfd_reloc_outofrange;
3401 + relocation = value + rel->r_addend;
3403 + if (howto->pc_relative)
3407 + addr = input_section->output_section->vma
3408 + + input_section->output_offset + rel->r_offset;
3409 + addr &= ~0UL << howto->rightshift;
3410 + relocation -= addr;
3413 + switch (ELF32_R_TYPE(rel->r_info))
3415 + case R_AVR32_16N_PCREL:
3416 + /* sub reg, pc, . - (sym + addend) */
3417 + relocation = -relocation;
3421 + status = avr32_check_reloc_value(input_section, rel, relocation, howto);
3423 + relocation >>= howto->rightshift;
3424 + if (howto->bitsize == 21)
3425 + field = (relocation & 0xffff)
3426 + | ((relocation & 0x10000) << 4)
3427 + | ((relocation & 0x1e0000) << 8);
3428 + else if (howto->bitsize == 12)
3429 + field = (relocation & 0xff) | ((relocation & 0xf00) << 4);
3430 + else if (howto->bitsize == 10)
3431 + field = ((relocation & 0xff) << 4)
3432 + | ((relocation & 0x300) >> 8);
3434 + field = relocation << howto->bitpos;
3436 + switch (howto->size)
3439 + x = bfd_get_8 (input_bfd, p);
3440 + x &= ~howto->dst_mask;
3441 + x |= field & howto->dst_mask;
3442 + bfd_put_8 (input_bfd, (bfd_vma) x, p);
3445 + x = bfd_get_16 (input_bfd, p);
3446 + x &= ~howto->dst_mask;
3447 + x |= field & howto->dst_mask;
3448 + bfd_put_16 (input_bfd, (bfd_vma) x, p);
3451 + x = bfd_get_32 (input_bfd, p);
3452 + x &= ~howto->dst_mask;
3453 + x |= field & howto->dst_mask;
3454 + bfd_put_32 (input_bfd, (bfd_vma) x, p);
3463 +/* (6) Apply relocations to the normal (non-dynamic) sections */
3466 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3467 + bfd *input_bfd, asection *input_section,
3468 + bfd_byte *contents, Elf_Internal_Rela *relocs,
3469 + Elf_Internal_Sym *local_syms,
3470 + asection **local_sections)
3472 + struct elf_avr32_link_hash_table *htab;
3473 + Elf_Internal_Shdr *symtab_hdr;
3474 + Elf_Internal_Rela *rel, *relend;
3475 + struct elf_link_hash_entry **sym_hashes;
3476 + struct got_entry **local_got_ents;
3478 + asection *srelgot;
3480 + pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n",
3481 + input_bfd->filename, input_section->name, input_section->size);
3483 + /* If we're doing a partial link, we don't have to do anything since
3484 + we're using RELA relocations */
3485 + if (info->relocatable)
3488 + htab = avr32_elf_hash_table(info);
3489 + symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
3490 + sym_hashes = elf_sym_hashes(input_bfd);
3491 + local_got_ents = elf_local_got_ents(input_bfd);
3492 + sgot = htab->sgot;
3493 + srelgot = htab->srelgot;
3495 + relend = relocs + input_section->reloc_count;
3496 + for (rel = relocs; rel < relend; rel++)
3498 + unsigned long r_type, r_symndx;
3499 + reloc_howto_type *howto;
3500 + Elf_Internal_Sym *sym = NULL;
3501 + struct elf_link_hash_entry *h = NULL;
3502 + asection *sec = NULL;
3505 + bfd_reloc_status_type status;
3507 + r_type = ELF32_R_TYPE(rel->r_info);
3508 + r_symndx = ELF32_R_SYM(rel->r_info);
3510 + if (r_type == R_AVR32_NONE
3511 + || r_type == R_AVR32_ALIGN
3512 + || r_type == R_AVR32_DIFF32
3513 + || r_type == R_AVR32_DIFF16
3514 + || r_type == R_AVR32_DIFF8)
3517 + /* Sanity check */
3518 + if (r_type > R_AVR32_max)
3520 + bfd_set_error(bfd_error_bad_value);
3524 + howto = &elf_avr32_howto_table[r_type];
3526 + if (r_symndx < symtab_hdr->sh_info)
3528 + sym = local_syms + r_symndx;
3529 + sec = local_sections[r_symndx];
3531 + pr_debug(" (6a) processing %s against local symbol %lu\n",
3532 + howto->name, r_symndx);
3534 + /* The following function changes rel->r_addend behind our back. */
3535 + value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
3536 + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend);
3540 + if (sym_hashes == NULL)
3543 + h = sym_hashes[r_symndx - symtab_hdr->sh_info];
3544 + while (h->root.type == bfd_link_hash_indirect
3545 + || h->root.type == bfd_link_hash_warning)
3546 + h = (struct elf_link_hash_entry *)h->root.u.i.link;
3548 + pr_debug(" (6a) processing %s against symbol %s\n",
3549 + howto->name, h->root.root.string);
3551 + if (h->root.type == bfd_link_hash_defined
3552 + || h->root.type == bfd_link_hash_defweak)
3556 + dyn = htab->root.dynamic_sections_created;
3557 + sec = h->root.u.def.section;
3559 + if (sec->output_section)
3560 + value = (h->root.u.def.value
3561 + + sec->output_section->vma
3562 + + sec->output_offset);
3564 + value = h->root.u.def.value;
3566 + else if (h->root.type == bfd_link_hash_undefweak)
3568 + else if (info->unresolved_syms_in_objects == RM_IGNORE
3569 + && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT)
3574 + err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
3575 + || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT);
3576 + if (!info->callbacks->undefined_symbol
3577 + (info, h->root.root.string, input_bfd,
3578 + input_section, rel->r_offset, err))
3583 + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend);
3588 + case R_AVR32_GOT32:
3589 + case R_AVR32_GOT16:
3590 + case R_AVR32_GOT8:
3591 + case R_AVR32_GOT21S:
3592 + case R_AVR32_GOT18SW:
3593 + case R_AVR32_GOT16S:
3594 + case R_AVR32_GOT7UW:
3595 + case R_AVR32_LDA_GOT:
3596 + case R_AVR32_GOTCALL:
3597 + BFD_ASSERT(sgot != NULL);
3601 + BFD_ASSERT(h->got.glist->refcount > 0);
3602 + offset = h->got.glist->offset;
3604 + BFD_ASSERT(offset < sgot->size);
3605 + if (!elf_hash_table(info)->dynamic_sections_created
3606 + || (h->def_regular
3609 + || h->dynindx == -1)))
3611 + /* This is actually a static link, or it is a
3612 + -Bsymbolic link and the symbol is defined
3613 + locally, or the symbol was forced to be local. */
3614 + bfd_put_32(output_bfd, value, sgot->contents + offset);
3619 + BFD_ASSERT(local_got_ents &&
3620 + local_got_ents[r_symndx]->refcount > 0);
3621 + offset = local_got_ents[r_symndx]->offset;
3623 + /* Local GOT entries don't have relocs. If this is a
3624 + shared library, the dynamic linker will add the load
3625 + address to the initial value at startup. */
3626 + BFD_ASSERT(offset < sgot->size);
3627 + pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n",
3629 + bfd_put_32 (output_bfd, value, sgot->contents + offset);
3632 + value = sgot->output_offset + offset;
3633 + pr_debug("GOT reference: New value %lx\n", value);
3636 + case R_AVR32_GOTPC:
3637 + /* This relocation type is for constant pool entries used in
3638 + the calculation "Rd = PC - (PC - GOT)", where the
3639 + constant pool supplies the constant (PC - GOT)
3640 + offset. The symbol value + addend indicates where the
3641 + value of PC is taken. */
3642 + value -= sgot->output_section->vma;
3645 + case R_AVR32_32_PCREL:
3646 + /* We must adjust r_offset to account for discarded data in
3647 + the .eh_frame section. This is probably not the right
3648 + way to do this, since AFAICS all other architectures do
3649 + it some other way. I just can't figure out how... */
3653 + r_offset = _bfd_elf_section_offset(output_bfd, info,
3656 + if (r_offset == (bfd_vma)-1
3657 + || r_offset == (bfd_vma)-2)
3659 + rel->r_offset = r_offset;
3664 + /* We need to emit a run-time relocation in the following cases:
3665 + - we're creating a shared library
3666 + - the symbol is not defined in any regular objects
3668 + Of course, sections that aren't going to be part of the
3669 + run-time image will not get any relocs, and undefined
3670 + symbols won't have any either (only weak undefined
3671 + symbols should get this far). */
3673 + || (elf_hash_table(info)->dynamic_sections_created
3676 + && !h->def_regular))
3678 + && (input_section->flags & SEC_ALLOC))
3680 + Elf_Internal_Rela outrel;
3682 + bfd_boolean skip, relocate;
3683 + struct elf_avr32_link_hash_entry *avrh;
3685 + pr_debug("Going to generate dynamic reloc...\n");
3690 + outrel.r_offset = _bfd_elf_section_offset(output_bfd, info,
3693 + if (outrel.r_offset == (bfd_vma)-1)
3695 + else if (outrel.r_offset == (bfd_vma)-2)
3696 + skip = TRUE, relocate = TRUE;
3698 + outrel.r_offset += (input_section->output_section->vma
3699 + + input_section->output_offset);
3701 + pr_debug(" ... offset %lx, dynindx %ld\n",
3702 + outrel.r_offset, h ? h->dynindx : -1);
3705 + memset(&outrel, 0, sizeof(outrel));
3708 + avrh = (struct elf_avr32_link_hash_entry *)h;
3709 + /* h->dynindx may be -1 if this symbol was marked to
3712 + || ((info->symbolic || h->dynindx == -1)
3713 + && h->def_regular))
3716 + outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE);
3717 + outrel.r_addend = value + rel->r_addend;
3718 + pr_debug(" ... R_AVR32_RELATIVE\n");
3722 + BFD_ASSERT(h->dynindx != -1);
3724 + outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3725 + outrel.r_addend = rel->r_addend;
3726 + pr_debug(" ... R_AVR32_GLOB_DAT\n");
3730 + pr_debug("srelgot reloc_count: %d, size %lu\n",
3731 + srelgot->reloc_count, srelgot->size);
3733 + loc = srelgot->contents;
3734 + loc += srelgot->reloc_count++ * sizeof(Elf32_External_Rela);
3735 + bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc);
3737 + BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3738 + <= srelgot->size);
3746 + status = avr32_final_link_relocate(howto, input_bfd, input_section,
3747 + contents, rel, value);
3751 + case bfd_reloc_ok:
3754 + case bfd_reloc_overflow:
3759 + name = h->root.root.string;
3762 + name = bfd_elf_string_from_elf_section(input_bfd,
3763 + symtab_hdr->sh_link,
3767 + if (*name == '\0')
3768 + name = bfd_section_name(input_bfd, sec);
3770 + if (!((*info->callbacks->reloc_overflow)
3771 + (info, (h ? &h->root : NULL), name, howto->name,
3772 + rel->r_addend, input_bfd, input_section, rel->r_offset)))
3777 + case bfd_reloc_outofrange:
3787 +/* Additional processing of dynamic sections after relocation */
3790 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3791 + struct elf_link_hash_entry *h,
3792 + Elf_Internal_Sym *sym);
3794 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info);
3797 +/* (7) Initialize the contents of a dynamic symbol and/or emit
3798 + relocations for it */
3801 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3802 + struct elf_link_hash_entry *h,
3803 + Elf_Internal_Sym *sym)
3805 + struct elf_avr32_link_hash_table *htab;
3806 + struct got_entry *got;
3808 + pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string);
3810 + htab = avr32_elf_hash_table(info);
3811 + got = h->got.glist;
3813 + if (got && got->refcount > 0)
3816 + asection *srelgot;
3817 + Elf_Internal_Rela rel;
3820 + /* This symbol has an entry in the GOT. Set it up. */
3821 + sgot = htab->sgot;
3822 + srelgot = htab->srelgot;
3823 + BFD_ASSERT(sgot && srelgot);
3825 + rel.r_offset = (sgot->output_section->vma
3826 + + sgot->output_offset
3829 + /* If this is a static link, or it is a -Bsymbolic link and the
3830 + symbol is defined locally or was forced to be local because
3831 + of a version file, we just want to emit a RELATIVE reloc. The
3832 + entry in the global offset table will already have been
3833 + initialized in the relocate_section function. */
3835 + && !info->symbolic
3836 + && h->dynindx != -1)
3837 + || (htab->root.dynamic_sections_created
3839 + && !h->def_regular))
3841 + bfd_put_32(output_bfd, 0, sgot->contents + got->offset);
3842 + rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3845 + pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx);
3846 + pr_debug(" srelgot reloc_count: %d, size: %lu\n",
3847 + srelgot->reloc_count, srelgot->size);
3849 + loc = (srelgot->contents
3850 + + srelgot->reloc_count++ * sizeof(Elf32_External_Rela));
3851 + bfd_elf32_swap_reloca_out(output_bfd, &rel, loc);
3853 + BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3854 + <= srelgot->size);
3858 + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */
3859 + if (strcmp(h->root.root.string, "_DYNAMIC") == 0
3860 + || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
3861 + sym->st_shndx = SHN_ABS;
3866 +/* (8) Do any remaining initialization of the dynamic sections */
3869 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info)
3871 + struct elf_avr32_link_hash_table *htab;
3872 + asection *sgot, *sdyn;
3874 + pr_debug("(8) finish dynamic sections\n");
3876 + htab = avr32_elf_hash_table(info);
3877 + sgot = htab->sgot;
3878 + sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic");
3880 + if (htab->root.dynamic_sections_created)
3882 + Elf32_External_Dyn *dyncon, *dynconend;
3884 + BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE);
3886 + dyncon = (Elf32_External_Dyn *)sdyn->contents;
3887 + dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size);
3888 + for (; dyncon < dynconend; dyncon++)
3890 + Elf_Internal_Dyn dyn;
3893 + bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn);
3895 + switch (dyn.d_tag)
3901 + s = sgot->output_section;
3902 + BFD_ASSERT(s != NULL);
3903 + dyn.d_un.d_ptr = s->vma;
3904 + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3907 + case DT_AVR32_GOTSZ:
3908 + s = sgot->output_section;
3909 + BFD_ASSERT(s != NULL);
3910 + dyn.d_un.d_val = s->size;
3911 + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3916 + /* Fill in the first two entries in the global offset table */
3917 + bfd_put_32(output_bfd,
3918 + sdyn->output_section->vma + sdyn->output_offset,
3921 + /* The runtime linker will fill this one in with the address of
3922 + the run-time link map */
3923 + bfd_put_32(output_bfd, 0, sgot->contents + 4);
3927 + elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4;
3933 +/* AVR32-specific private ELF data */
3936 +avr32_elf_set_private_flags(bfd *abfd, flagword flags);
3938 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd);
3940 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd);
3942 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr);
3945 +avr32_elf_set_private_flags(bfd *abfd, flagword flags)
3947 + elf_elfheader(abfd)->e_flags = flags;
3948 + elf_flags_init(abfd) = TRUE;
3953 +/* Copy backend specific data from one object module to another. */
3956 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd)
3958 + elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags;
3962 +/* Merge backend specific data from an object file to the output
3963 + object file when linking. */
3966 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd)
3968 + flagword out_flags, in_flags;
3970 + pr_debug("(0) merge_private_bfd_data: %s -> %s\n",
3971 + ibfd->filename, obfd->filename);
3973 + in_flags = elf_elfheader(ibfd)->e_flags;
3974 + out_flags = elf_elfheader(obfd)->e_flags;
3976 + if (elf_flags_init(obfd))
3978 + /* If one of the inputs are non-PIC, the output must be
3979 + considered non-PIC. The same applies to linkrelax. */
3980 + if (!(in_flags & EF_AVR32_PIC))
3981 + out_flags &= ~EF_AVR32_PIC;
3982 + if (!(in_flags & EF_AVR32_LINKRELAX))
3983 + out_flags &= ~EF_AVR32_LINKRELAX;
3987 + elf_flags_init(obfd) = TRUE;
3988 + out_flags = in_flags;
3991 + elf_elfheader(obfd)->e_flags = out_flags;
3997 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr)
3999 + FILE *file = (FILE *)ptr;
4000 + unsigned long flags;
4002 + BFD_ASSERT(abfd != NULL && ptr != NULL);
4004 + _bfd_elf_print_private_bfd_data(abfd, ptr);
4006 + flags = elf_elfheader(abfd)->e_flags;
4008 + fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags);
4010 + if (flags & EF_AVR32_PIC)
4011 + fprintf(file, " [PIC]");
4012 + if (flags & EF_AVR32_LINKRELAX)
4013 + fprintf(file, " [linker relaxable]");
4015 + flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX);
4018 + fprintf(file, _("<Unrecognized flag bits set>"));
4020 + fputc('\n', file);
4025 +/* Set avr32-specific linker options. */
4026 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4027 + int direct_data_refs)
4029 + struct elf_avr32_link_hash_table *htab;
4031 + htab = avr32_elf_hash_table (info);
4032 + htab->direct_data_refs = !!direct_data_refs;
4037 +/* Understanding core dumps */
4040 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note);
4042 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note);
4045 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note)
4047 + /* Linux/AVR32B elf_prstatus */
4048 + if (note->descsz != 148)
4052 + elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12);
4055 + elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24);
4057 + /* Make a ".reg/999" section for pr_reg. The size is for 16
4058 + general-purpose registers, SR and r12_orig (18 * 4 = 72). */
4059 + return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72,
4060 + note->descpos + 72);
4064 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note)
4066 + /* Linux/AVR32B elf_prpsinfo */
4067 + if (note->descsz != 128)
4070 + elf_tdata(abfd)->core_program
4071 + = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16);
4072 + elf_tdata(abfd)->core_command
4073 + = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80);
4075 + /* Note that for some reason, a spurious space is tacked
4076 + onto the end of the args in some (at least one anyway)
4077 + implementations, so strip it off if it exists. */
4080 + char *command = elf_tdata (abfd)->core_command;
4081 + int n = strlen (command);
4083 + if (0 < n && command[n - 1] == ' ')
4084 + command[n - 1] = '\0';
4091 +#define ELF_ARCH bfd_arch_avr32
4092 +#define ELF_MACHINE_CODE EM_AVR32
4093 +#define ELF_MAXPAGESIZE 1024
4095 +#define TARGET_BIG_SYM bfd_elf32_avr32_vec
4096 +#define TARGET_BIG_NAME "elf32-avr32"
4098 +#define elf_backend_grok_prstatus avr32_elf_grok_prstatus
4099 +#define elf_backend_grok_psinfo avr32_elf_grok_psinfo
4101 +/* Only RELA relocations are used */
4102 +#define elf_backend_may_use_rel_p 0
4103 +#define elf_backend_may_use_rela_p 1
4104 +#define elf_backend_default_use_rela_p 1
4105 +#define elf_backend_rela_normal 1
4106 +#define elf_info_to_howto_rel NULL
4107 +#define elf_info_to_howto avr32_info_to_howto
4109 +#define bfd_elf32_bfd_copy_private_bfd_data avr32_elf_copy_private_bfd_data
4110 +#define bfd_elf32_bfd_merge_private_bfd_data avr32_elf_merge_private_bfd_data
4111 +#define bfd_elf32_bfd_set_private_flags avr32_elf_set_private_flags
4112 +#define bfd_elf32_bfd_print_private_bfd_data avr32_elf_print_private_bfd_data
4113 +#define bfd_elf32_new_section_hook avr32_elf_new_section_hook
4115 +#define elf_backend_gc_mark_hook avr32_elf_gc_mark_hook
4116 +#define elf_backend_gc_sweep_hook avr32_elf_gc_sweep_hook
4117 +#define elf_backend_relocate_section avr32_elf_relocate_section
4118 +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol
4119 +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections
4120 +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create
4121 +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol
4122 +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections
4123 +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol
4124 +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections
4126 +#define bfd_elf32_bfd_relax_section avr32_elf_relax_section
4128 +/* Find out which symbols need an entry in .got. */
4129 +#define elf_backend_check_relocs avr32_check_relocs
4130 +#define elf_backend_can_refcount 1
4131 +#define elf_backend_can_gc_sections 1
4132 +#define elf_backend_plt_readonly 1
4133 +#define elf_backend_plt_not_loaded 1
4134 +#define elf_backend_want_plt_sym 0
4135 +#define elf_backend_plt_alignment 2
4136 +#define elf_backend_want_dynbss 0
4137 +#define elf_backend_want_got_plt 0
4138 +#define elf_backend_want_got_sym 1
4139 +#define elf_backend_got_header_size AVR32_GOT_HEADER_SIZE
4141 +#include "elf32-target.h"
4143 +++ b/bfd/elf32-avr32.h
4145 +/* AVR32-specific support for 32-bit ELF.
4146 + Copyright 2007,2008,2009 Atmel Corporation.
4148 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4150 + This file is part of BFD, the Binary File Descriptor library.
4152 + This program is free software; you can redistribute it and/or modify
4153 + it under the terms of the GNU General Public License as published by
4154 + the Free Software Foundation; either version 2 of the License, or
4155 + (at your option) any later version.
4157 + This program is distributed in the hope that it will be useful,
4158 + but WITHOUT ANY WARRANTY; without even the implied warranty of
4159 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4160 + GNU General Public License for more details.
4162 + You should have received a copy of the GNU General Public License
4163 + along with this program; if not, write to the Free Software
4164 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
4166 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4167 + int direct_data_refs);
4170 @@ -1553,6 +1553,10 @@ struct elf_obj_tdata
4171 find_nearest_line. */
4172 struct mips_elf_find_line *find_line_info;
4174 + /* Used by AVR32 ELF relaxation code. Contains an array of pointers
4175 + for each local symbol to the fragment where it is defined. */
4176 + struct fragment **local_sym_frag;
4178 /* A place to stash dwarf1 info for this bfd. */
4179 struct dwarf1_debug *dwarf1_find_line_info;
4183 @@ -1783,6 +1783,48 @@ static const char *const bfd_reloc_code_
4184 "BFD_RELOC_AVR_LDI",
4186 "BFD_RELOC_AVR_6_ADIW",
4187 + "BFD_RELOC_AVR32_DIFF32",
4188 + "BFD_RELOC_AVR32_DIFF16",
4189 + "BFD_RELOC_AVR32_DIFF8",
4190 + "BFD_RELOC_AVR32_GOT32",
4191 + "BFD_RELOC_AVR32_GOT16",
4192 + "BFD_RELOC_AVR32_GOT8",
4193 + "BFD_RELOC_AVR32_21S",
4194 + "BFD_RELOC_AVR32_16U",
4195 + "BFD_RELOC_AVR32_16S",
4196 + "BFD_RELOC_AVR32_SUB5",
4197 + "BFD_RELOC_AVR32_8S_EXT",
4198 + "BFD_RELOC_AVR32_8S",
4199 + "BFD_RELOC_AVR32_15S",
4200 + "BFD_RELOC_AVR32_22H_PCREL",
4201 + "BFD_RELOC_AVR32_18W_PCREL",
4202 + "BFD_RELOC_AVR32_16B_PCREL",
4203 + "BFD_RELOC_AVR32_16N_PCREL",
4204 + "BFD_RELOC_AVR32_14UW_PCREL",
4205 + "BFD_RELOC_AVR32_11H_PCREL",
4206 + "BFD_RELOC_AVR32_10UW_PCREL",
4207 + "BFD_RELOC_AVR32_9H_PCREL",
4208 + "BFD_RELOC_AVR32_9UW_PCREL",
4209 + "BFD_RELOC_AVR32_GOTPC",
4210 + "BFD_RELOC_AVR32_GOTCALL",
4211 + "BFD_RELOC_AVR32_LDA_GOT",
4212 + "BFD_RELOC_AVR32_GOT21S",
4213 + "BFD_RELOC_AVR32_GOT18SW",
4214 + "BFD_RELOC_AVR32_GOT16S",
4215 + "BFD_RELOC_AVR32_32_CPENT",
4216 + "BFD_RELOC_AVR32_CPCALL",
4217 + "BFD_RELOC_AVR32_16_CP",
4218 + "BFD_RELOC_AVR32_9W_CP",
4219 + "BFD_RELOC_AVR32_ALIGN",
4220 + "BFD_RELOC_AVR32_14UW",
4221 + "BFD_RELOC_AVR32_10UW",
4222 + "BFD_RELOC_AVR32_10SW",
4223 + "BFD_RELOC_AVR32_STHH_W",
4224 + "BFD_RELOC_AVR32_7UW",
4225 + "BFD_RELOC_AVR32_6S",
4226 + "BFD_RELOC_AVR32_6UW",
4227 + "BFD_RELOC_AVR32_4UH",
4228 + "BFD_RELOC_AVR32_3U",
4229 "BFD_RELOC_RX_NEG8",
4230 "BFD_RELOC_RX_NEG16",
4231 "BFD_RELOC_RX_NEG24",
4232 --- a/bfd/Makefile.am
4233 +++ b/bfd/Makefile.am
4234 @@ -75,6 +75,7 @@ ALL_MACHINES = \
4242 @@ -272,6 +273,7 @@ BFD32_BACKENDS = \
4252 @@ -4275,6 +4275,131 @@ ENUMDOC
4253 Renesas RX Relocations.
4256 + BFD_RELOC_AVR32_DIFF32
4258 + BFD_RELOC_AVR32_DIFF16
4260 + BFD_RELOC_AVR32_DIFF8
4262 + Difference between two labels: L2 - L1. The value of L1 is encoded
4263 + as sym + addend, while the initial difference after assembly is
4264 + inserted into the object file by the assembler.
4266 + BFD_RELOC_AVR32_GOT32
4268 + BFD_RELOC_AVR32_GOT16
4270 + BFD_RELOC_AVR32_GOT8
4272 + Reference to a symbol through the Global Offset Table. The linker
4273 + will allocate an entry for symbol in the GOT and insert the offset
4274 + of this entry as the relocation value.
4276 + BFD_RELOC_AVR32_21S
4278 + BFD_RELOC_AVR32_16U
4280 + BFD_RELOC_AVR32_16S
4282 + BFD_RELOC_AVR32_SUB5
4284 + BFD_RELOC_AVR32_8S_EXT
4286 + BFD_RELOC_AVR32_8S
4288 + BFD_RELOC_AVR32_15S
4290 + Normal (non-pc-relative) code relocations. Alignment and signedness
4291 + is indicated by the suffixes. S means signed, U means unsigned. W
4292 + means word-aligned, H means halfword-aligned, neither means
4293 + byte-aligned (no alignment.) SUB5 is the same relocation as 16S.
4295 + BFD_RELOC_AVR32_22H_PCREL
4297 + BFD_RELOC_AVR32_18W_PCREL
4299 + BFD_RELOC_AVR32_16B_PCREL
4301 + BFD_RELOC_AVR32_16N_PCREL
4303 + BFD_RELOC_AVR32_14UW_PCREL
4305 + BFD_RELOC_AVR32_11H_PCREL
4307 + BFD_RELOC_AVR32_10UW_PCREL
4309 + BFD_RELOC_AVR32_9H_PCREL
4311 + BFD_RELOC_AVR32_9UW_PCREL
4313 + PC-relative relocations are signed if neither 'U' nor 'S' is
4314 + specified. However, we explicitly tack on a 'B' to indicate no
4315 + alignment, to avoid confusion with data relocs. All of these resolve
4316 + to sym + addend - offset, except the one with 'N' (negated) suffix.
4317 + This particular one resolves to offset - sym - addend.
4319 + BFD_RELOC_AVR32_GOTPC
4321 + Subtract the link-time address of the GOT from (symbol + addend)
4322 + and insert the result.
4324 + BFD_RELOC_AVR32_GOTCALL
4326 + BFD_RELOC_AVR32_LDA_GOT
4328 + BFD_RELOC_AVR32_GOT21S
4330 + BFD_RELOC_AVR32_GOT18SW
4332 + BFD_RELOC_AVR32_GOT16S
4334 + Reference to a symbol through the GOT. The linker will allocate an
4335 + entry for symbol in the GOT and insert the offset of this entry as
4336 + the relocation value. addend must be zero. As usual, 'S' means
4337 + signed, 'W' means word-aligned, etc.
4339 + BFD_RELOC_AVR32_32_CPENT
4341 + 32-bit constant pool entry. I don't think 8- and 16-bit entries make
4342 + a whole lot of sense.
4344 + BFD_RELOC_AVR32_CPCALL
4346 + BFD_RELOC_AVR32_16_CP
4348 + BFD_RELOC_AVR32_9W_CP
4350 + Constant pool references. Some of these relocations are signed,
4351 + others are unsigned. It doesn't really matter, since the constant
4352 + pool always comes after the code that references it.
4354 + BFD_RELOC_AVR32_ALIGN
4356 + sym must be the absolute symbol. The addend specifies the alignment
4357 + order, e.g. if addend is 2, the linker must add padding so that the
4358 + next address is aligned to a 4-byte boundary.
4360 + BFD_RELOC_AVR32_14UW
4362 + BFD_RELOC_AVR32_10UW
4364 + BFD_RELOC_AVR32_10SW
4366 + BFD_RELOC_AVR32_STHH_W
4368 + BFD_RELOC_AVR32_7UW
4370 + BFD_RELOC_AVR32_6S
4372 + BFD_RELOC_AVR32_6UW
4374 + BFD_RELOC_AVR32_4UH
4376 + BFD_RELOC_AVR32_3U
4378 + Code relocations that will never make it to the output file.
4386 @@ -579,6 +579,7 @@ extern const bfd_target b_out_vec_big_ho
4387 extern const bfd_target b_out_vec_little_host;
4388 extern const bfd_target bfd_pei_ia64_vec;
4389 extern const bfd_target bfd_elf32_avr_vec;
4390 +extern const bfd_target bfd_elf32_avr32_vec;
4391 extern const bfd_target bfd_elf32_bfin_vec;
4392 extern const bfd_target bfd_elf32_bfinfdpic_vec;
4393 extern const bfd_target bfd_elf32_big_generic_vec;
4394 @@ -917,6 +918,7 @@ static const bfd_target * const _bfd_tar
4398 + &bfd_elf32_avr32_vec,
4399 &bfd_elf32_bfin_vec,
4400 &bfd_elf32_bfinfdpic_vec,
4402 --- a/binutils/doc/binutils.info
4403 +++ b/binutils/doc/binutils.info
4404 @@ -1705,6 +1705,10 @@ equivalent. At least one option from th
4405 useful when attempting to disassemble thumb code produced by other
4408 + For the AVR32 architectures that support Floating point unit (FPU),
4409 + specifying '-M decode-fpu' will enable disassembler to print the
4410 + floating point instruction instead of 'cop' instructions.
4412 For the x86, some of the options duplicate functions of the `-m'
4413 switch, but allow finer grained control. Multiple selections from
4414 the following may be specified as a comma separated string.
4415 --- a/binutils/doc/binutils.texi
4416 +++ b/binutils/doc/binutils.texi
4417 @@ -1980,6 +1980,10 @@ using the switch @option{--disassembler-
4418 useful when attempting to disassemble thumb code produced by other
4421 +For the AVR32 architectures that support Floating point unit (FPU),
4422 +specifying @option{-M decode-fpu} will enable disassembler to print the
4423 +floating point instructions instead of 'cop' instructions.
4425 For the x86, some of the options duplicate functions of the @option{-m}
4426 switch, but allow finer grained control. Multiple selections from the
4427 following may be specified as a comma separated string.
4428 --- a/binutils/doc/objdump.1
4429 +++ b/binutils/doc/objdump.1
4430 @@ -425,6 +425,10 @@ using the switch \fB\-\-disassembler\-op
4431 useful when attempting to disassemble thumb code produced by other
4434 +For the \s-1AVR32\s0 architectures that support Floating point unit (FPU),
4435 +specifying \fB\-M decode\-fpu\fR will enable disassembler to print the
4436 +floating point instructions instead of 'cop' instructions.
4438 For the x86, some of the options duplicate functions of the \fB\-m\fR
4439 switch, but allow finer grained control. Multiple selections from the
4440 following may be specified as a comma separated string.
4441 --- a/binutils/readelf.c
4442 +++ b/binutils/readelf.c
4444 #include "elf/arc.h"
4445 #include "elf/arm.h"
4446 #include "elf/avr.h"
4447 +#include "elf/avr32.h"
4448 #include "elf/bfin.h"
4449 #include "elf/cr16.h"
4450 #include "elf/cris.h"
4451 @@ -619,6 +620,7 @@ guess_is_rela (unsigned int e_machine)
4453 case EM_ALTERA_NIOS2:
4459 @@ -1072,6 +1074,10 @@ dump_relocations (FILE * file,
4460 rtype = elf_avr_reloc_type (type);
4464 + rtype = elf_avr32_reloc_type (type);
4467 case EM_OLD_SPARCV9:
4468 case EM_SPARC32PLUS:
4472 @@ -459,10 +459,10 @@ parse_args (int * pargc, char *** pargv)
4473 the end of the preceeding line so that it is simpler to
4474 selectively add and remove lines from this list. */
4475 {"alternate", no_argument, NULL, OPTION_ALTERNATE}
4476 - /* The entry for "a" is here to prevent getopt_long_only() from
4477 - considering that -a is an abbreviation for --alternate. This is
4478 - necessary because -a=<FILE> is a valid switch but getopt would
4479 - normally reject it since --alternate does not take an argument. */
4480 + /* The next two entries are here to prevent getopt_long_only() from
4481 + considering that -a or -al is an abbreviation for --alternate.
4482 + This is necessary because -a=<FILE> is a valid switch but getopt
4483 + would normally reject it since --alternate does not take an argument. */
4484 ,{"a", optional_argument, NULL, 'a'}
4485 /* Handle -al=<FILE>. */
4486 ,{"al", optional_argument, NULL, OPTION_AL}
4487 @@ -839,8 +839,15 @@ This program has absolutely no warranty.
4491 - if (optarg != old_argv[optind] && optarg[-1] == '=')
4492 + /* If optarg is part of the -a switch and not a separate argument
4493 + in its own right, then scan backwards to the just after the -a.
4494 + This means skipping over both '=' and 'l' which might have been
4495 + taken to be part of the -a switch itself. */
4496 + if (optarg != old_argv[optind])
4498 + while (optarg[-1] == '=' || optarg[-1] == 'l')
4502 if (md_parse_option (optc, optarg) != 0)
4508 #define gas_assert(P) \
4509 ((void) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0)))
4510 +#define assert(P) gas_assert(P)
4512 #define abort() as_abort (__FILE__, __LINE__, __PRETTY_FUNCTION__)
4514 --- a/gas/atof-generic.c
4515 +++ b/gas/atof-generic.c
4516 @@ -121,6 +121,21 @@ atof_generic (/* return pointer to just
4518 switch (first_digit[0])
4524 + if (!strncasecmp ("nan", first_digit+1, 3))
4526 + address_of_generic_floating_point_number->sign = 0;
4527 + address_of_generic_floating_point_number->exponent = 0;
4528 + address_of_generic_floating_point_number->leader =
4529 + address_of_generic_floating_point_number->low;
4530 + *address_of_string_pointer = first_digit + 4;
4537 if (!strncasecmp ("nan", first_digit, 3))
4538 --- a/gas/config/atof-vax.c
4539 +++ b/gas/config/atof-vax.c
4540 @@ -268,9 +268,27 @@ flonum_gen2vax (int format_letter, /* On
4541 int exponent_skippage;
4542 LITTLENUM_TYPE word1;
4544 - /* JF: Deal with new Nan, +Inf and -Inf codes. */
4545 + /* JF: Deal with new +/-(q/Q/s/S)Nan, +Inf and -Inf codes. */
4546 if (f->sign != '-' && f->sign != '+')
4550 + /* All NaNs are 0. */
4551 + memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4553 + else if (f->sign == 'P')
4555 + /* Positive Infinity. */
4556 + memset (words, 0xff, sizeof (LITTLENUM_TYPE) * precision);
4557 + words[0] &= 0x7fff;
4559 + else if (f->sign == 'N')
4561 + /* Negative Infinity. */
4562 + memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4563 + words[0] = 0x0080;
4566 make_invalid_floating_point_number (words);
4567 return return_value;
4570 +++ b/gas/config/tc-avr32.c
4572 +/* Assembler implementation for AVR32.
4573 + Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
4575 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4577 + This file is part of GAS, the GNU Assembler.
4579 + GAS is free software; you can redistribute it and/or modify it
4580 + under the terms of the GNU General Public License as published by
4581 + the Free Software Foundation; either version 2, or (at your option)
4582 + any later version.
4584 + GAS is distributed in the hope that it will be useful, but WITHOUT
4585 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
4586 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
4587 + License for more details.
4589 + You should have received a copy of the GNU General Public License
4590 + along with GAS; see the file COPYING. If not, write to the Free
4591 + Software Foundation, 59 Temple Place - Suite 330, Boston, MA
4592 + 02111-1307, USA. */
4596 +#include "safe-ctype.h"
4597 +#include "subsegs.h"
4598 +#include "symcat.h"
4599 +#include "opcodes/avr32-opc.h"
4600 +#include "opcodes/avr32-asm.h"
4601 +#include "elf/avr32.h"
4602 +#include "dwarf2dbg.h"
4605 +#define xOPC_CONSISTENCY_CHECK
4608 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
4610 +# define pr_debug(fmt, args...)
4613 +/* 3 MSB of instruction word indicate group. Group 7 -> extended */
4614 +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0)
4616 +#define streq(a, b) (strcmp(a, b) == 0)
4617 +#define skip_whitespace(str) do { while(*(str) == ' ') ++(str); } while(0)
4619 +/* Flags given on the command line */
4620 +static int avr32_pic = FALSE;
4621 +int linkrelax = FALSE;
4622 +int avr32_iarcompat = FALSE;
4624 +/* This array holds the chars that always start a comment. */
4625 +const char comment_chars[] = "#";
4627 +/* This array holds the chars that only start a comment at the
4628 + beginning of a line. We must include '#' here because the compiler
4629 + may produce #APP and #NO_APP in its output. */
4630 +const char line_comment_chars[] = "#";
4632 +/* These may be used instead of newline (same as ';' in C). */
4633 +const char line_separator_chars[] = ";";
4635 +/* Chars that can be used to separate mantissa from exponent in
4636 + floating point numbers. */
4637 +const char EXP_CHARS[] = "eE";
4639 +/* Chars that mean this number is a floating point constant. */
4640 +const char FLT_CHARS[] = "dD";
4642 +/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
4643 +symbolS *GOT_symbol;
4645 +static struct hash_control *avr32_mnemonic_htab;
4647 +struct avr32_ifield_data
4650 + /* FIXME: Get rid of align_order and complain. complain is never
4651 + used, align_order is used in one place. Try to use the relax
4653 + unsigned int align_order;
4658 + const struct avr32_syntax *syntax;
4659 + expressionS immediate;
4661 + int force_extended;
4662 + unsigned int next_slot;
4663 + bfd_reloc_code_real_type r_type;
4664 + struct avr32_ifield_data field_value[AVR32_MAX_FIELDS];
4667 +static struct avr32_insn current_insn;
4669 +/* The target specific pseudo-ops we support. */
4670 +static void s_rseg (int);
4671 +static void s_cpool(int);
4673 +const pseudo_typeS md_pseudo_table[] =
4675 + /* Make sure that .word is 32 bits */
4676 + { "word", cons, 4 },
4677 + { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
4678 + { "loc", dwarf2_directive_loc, 0 },
4680 + /* .lcomm requires an explicit alignment parameter */
4681 + { "lcomm", s_lcomm, 1 },
4683 + /* AVR32-specific pseudo-ops */
4684 + { "cpool", s_cpool, 0},
4686 + /* IAR compatible pseudo-ops */
4687 + { "program", s_ignore, 0 },
4688 + { "public", s_globl, 0 },
4689 + { "extern", s_ignore, 0 },
4690 + { "module", s_ignore, 0 },
4691 + { "rseg", s_rseg, 0 },
4692 + { "dc8", cons, 1 },
4693 + { "dc16", cons, 2 },
4694 + { "dc32", cons, 4 },
4699 +/* Questionable stuff starts here */
4701 +enum avr32_opinfo {
4702 + AVR32_OPINFO_NONE = BFD_RELOC_NONE,
4704 + AVR32_OPINFO_TLSGD,
4719 + /* Architecture name */
4721 + /* Instruction Set Architecture Flags */
4722 + unsigned long isa_flags;
4729 + /* Architecture type */
4730 + unsigned int arch;
4733 +static struct arch_type_s arch_types[] =
4735 + {"ap", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_PICO},
4736 + {"ucr1", AVR32_V1 | AVR32_DSP | AVR32_RMW},
4737 + {"ucr2", AVR32_V1 | AVR32_V2 | AVR32_DSP | AVR32_RMW},
4738 + {"ucr3", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW},
4739 + {"ucr3fp", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW | AVR32_V3FP},
4740 + {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO},
4744 +static struct part_type_s part_types[] =
4746 + {"ap7000", ARCH_TYPE_AP},
4747 + {"ap7001", ARCH_TYPE_AP},
4748 + {"ap7002", ARCH_TYPE_AP},
4749 + {"ap7200", ARCH_TYPE_AP},
4750 + {"uc3a0128", ARCH_TYPE_UCR2},
4751 + {"uc3a0256", ARCH_TYPE_UCR2},
4752 + {"uc3a0512es", ARCH_TYPE_UCR1},
4753 + {"uc3a0512", ARCH_TYPE_UCR2},
4754 + {"uc3a1128", ARCH_TYPE_UCR2},
4755 + {"uc3a1256es", ARCH_TYPE_UCR1},
4756 + {"uc3a1256", ARCH_TYPE_UCR2},
4757 + {"uc3a1512es", ARCH_TYPE_UCR1},
4758 + {"uc3a1512", ARCH_TYPE_UCR2},
4759 + {"uc3a364", ARCH_TYPE_UCR2},
4760 + {"uc3a364s", ARCH_TYPE_UCR2},
4761 + {"uc3a3128", ARCH_TYPE_UCR2},
4762 + {"uc3a3128s", ARCH_TYPE_UCR2},
4763 + {"uc3a3256", ARCH_TYPE_UCR2},
4764 + {"uc3a3256s", ARCH_TYPE_UCR2},
4765 + {"uc3b064", ARCH_TYPE_UCR1},
4766 + {"uc3b0128", ARCH_TYPE_UCR1},
4767 + {"uc3b0256es", ARCH_TYPE_UCR1},
4768 + {"uc3b0256", ARCH_TYPE_UCR1},
4769 + {"uc3b0512", ARCH_TYPE_UCR2},
4770 + {"uc3b0512revc", ARCH_TYPE_UCR2},
4771 + {"uc3b164", ARCH_TYPE_UCR1},
4772 + {"uc3b1128", ARCH_TYPE_UCR1},
4773 + {"uc3b1256", ARCH_TYPE_UCR1},
4774 + {"uc3b1256es", ARCH_TYPE_UCR1},
4775 + {"uc3b1512", ARCH_TYPE_UCR2},
4776 + {"uc3b1512revc", ARCH_TYPE_UCR2},
4777 + {"uc3c0512crevc", ARCH_TYPE_UCR3},
4778 + {"uc3c1512crevc", ARCH_TYPE_UCR3},
4779 + {"uc3c2512crevc", ARCH_TYPE_UCR3},
4780 + {"atuc3l0256", ARCH_TYPE_UCR3},
4781 + {"mxt768e", ARCH_TYPE_UCR3},
4782 + {"uc3l064", ARCH_TYPE_UCR3},
4783 + {"uc3l032", ARCH_TYPE_UCR3},
4784 + {"uc3l016", ARCH_TYPE_UCR3},
4785 + {"uc3l064revb", ARCH_TYPE_UCR3},
4786 + {"uc3c064c", ARCH_TYPE_UCR3FP},
4787 + {"uc3c0128c", ARCH_TYPE_UCR3FP},
4788 + {"uc3c0256c", ARCH_TYPE_UCR3FP},
4789 + {"uc3c0512c", ARCH_TYPE_UCR3FP},
4790 + {"uc3c164c", ARCH_TYPE_UCR3FP},
4791 + {"uc3c1128c", ARCH_TYPE_UCR3FP},
4792 + {"uc3c1256c", ARCH_TYPE_UCR3FP},
4793 + {"uc3c1512c", ARCH_TYPE_UCR3FP},
4794 + {"uc3c264c", ARCH_TYPE_UCR3FP},
4795 + {"uc3c2128c", ARCH_TYPE_UCR3FP},
4796 + {"uc3c2256c", ARCH_TYPE_UCR3FP},
4797 + {"uc3c2512c", ARCH_TYPE_UCR3FP},
4801 +/* Current architecture type. */
4802 +static struct arch_type_s default_arch = {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO };
4803 +static struct arch_type_s *avr32_arch = &default_arch;
4805 +/* Display nicely formatted list of known part- and architecture names. */
4808 +show_arch_list (FILE *stream)
4812 + fprintf (stream, _("Known architecture names:"));
4815 + for (i = 0; arch_types[i].name; i++)
4817 + int len = strlen (arch_types[i].name);
4822 + fprintf (stream, " %s", arch_types[i].name);
4825 + fprintf (stream, "\n %s", arch_types[i].name);
4830 + fprintf (stream, "\n");
4834 +show_part_list (FILE *stream)
4838 + fprintf (stream, _("Known part names:"));
4841 + for (i = 0; part_types[i].name; i++)
4843 + int len = strlen(part_types[i].name);
4848 + fprintf (stream, " %s", part_types[i].name);
4851 + fprintf(stream, "\n %s", part_types[i].name);
4856 + fprintf (stream, "\n");
4859 +const char *md_shortopts = "";
4860 +struct option md_longopts[] =
4862 +#define OPTION_ARCH (OPTION_MD_BASE)
4863 +#define OPTION_PART (OPTION_ARCH + 1)
4864 +#define OPTION_IAR (OPTION_PART + 1)
4865 +#define OPTION_PIC (OPTION_IAR + 1)
4866 +#define OPTION_NOPIC (OPTION_PIC + 1)
4867 +#define OPTION_LINKRELAX (OPTION_NOPIC + 1)
4868 +#define OPTION_NOLINKRELAX (OPTION_LINKRELAX + 1)
4869 +#define OPTION_DIRECT_DATA_REFS (OPTION_NOLINKRELAX + 1)
4870 + {"march", required_argument, NULL, OPTION_ARCH},
4871 + {"mpart", required_argument, NULL, OPTION_PART},
4872 + {"iar", no_argument, NULL, OPTION_IAR},
4873 + {"pic", no_argument, NULL, OPTION_PIC},
4874 + {"no-pic", no_argument, NULL, OPTION_NOPIC},
4875 + {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
4876 + {"no-linkrelax", no_argument, NULL, OPTION_NOLINKRELAX},
4877 + /* deprecated alias for -mpart=xxx */
4878 + {"mcpu", required_argument, NULL, OPTION_PART},
4879 + {NULL, no_argument, NULL, 0}
4882 +size_t md_longopts_size = sizeof (md_longopts);
4885 +md_show_usage (FILE *stream)
4887 + fprintf (stream, _("\
4889 + -march=[arch-name] Select cpu architecture. [Default `all-insn']\n\
4890 + -mpart=[part-name] Select specific part. [Default `none']\n\
4891 + --pic Produce Position-Independent Code\n\
4892 + --no-pic Don't produce Position-Independent Code\n\
4893 + --linkrelax Produce output suitable for linker relaxing\n\
4894 + --no-linkrelax Don't produce output suitable for linker relaxing\n"));
4895 + show_arch_list(stream);
4899 +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
4906 + char *s = alloca (strlen (arg) + 1);
4913 + *t = TOLOWER (*arg1++);
4917 + /* Add backward compability */
4918 + if (strcmp ("uc", s)== 0)
4920 + as_warn("Deprecated arch `%s' specified. "
4921 + "Please use '-march=ucr1' instead. "
4922 + "Converting to arch 'ucr1'\n",
4927 + for (i = 0; arch_types[i].name; ++i)
4928 + if (strcmp (arch_types[i].name, s) == 0)
4931 + if (!arch_types[i].name)
4933 + show_arch_list (stderr);
4934 + as_fatal (_("unknown architecture: %s\n"), arg);
4937 + avr32_arch = &arch_types[i];
4943 + char *s = alloca (strlen (arg) + 1);
4947 + /* If arch type has already been set, don't bother.
4948 + -march= always overrides -mpart= */
4949 + if (avr32_arch != &default_arch)
4953 + *t = TOLOWER (*p++);
4956 + for (i = 0; part_types[i].name; ++i)
4957 + if (strcmp (part_types[i].name, s) == 0)
4960 + if (!part_types[i].name)
4962 + show_part_list (stderr);
4963 + as_fatal (_("unknown part: %s\n"), arg);
4966 + avr32_arch = &arch_types[part_types[i].arch];
4970 + avr32_iarcompat = 1;
4975 + case OPTION_NOPIC:
4978 + case OPTION_LINKRELAX:
4981 + case OPTION_NOLINKRELAX:
4990 +/* Can't use symbol_new here, so have to create a symbol and then at
4991 + a later date assign it a value. Thats what these functions do.
4993 + Shamelessly stolen from ARM. */
4996 +symbol_locate (symbolS * symbolP,
4997 + const char * name, /* It is copied, the caller can modify. */
4998 + segT segment, /* Segment identifier (SEG_<something>). */
4999 + valueT valu, /* Symbol value. */
5000 + fragS * frag) /* Associated fragment. */
5002 + unsigned int name_length;
5003 + char * preserved_copy_of_name;
5005 + name_length = strlen (name) + 1; /* +1 for \0. */
5006 + obstack_grow (¬es, name, name_length);
5007 + preserved_copy_of_name = obstack_finish (¬es);
5008 +#ifdef STRIP_UNDERSCORE
5009 + if (preserved_copy_of_name[0] == '_')
5010 + preserved_copy_of_name++;
5013 +#ifdef tc_canonicalize_symbol_name
5014 + preserved_copy_of_name =
5015 + tc_canonicalize_symbol_name (preserved_copy_of_name);
5018 + S_SET_NAME (symbolP, preserved_copy_of_name);
5020 + S_SET_SEGMENT (symbolP, segment);
5021 + S_SET_VALUE (symbolP, valu);
5022 + symbol_clear_list_pointers (symbolP);
5024 + symbol_set_frag (symbolP, frag);
5026 + /* Link to end of symbol chain. */
5028 + extern int symbol_table_frozen;
5030 + if (symbol_table_frozen)
5034 + symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
5036 + obj_symbol_new_hook (symbolP);
5038 +#ifdef tc_symbol_new_hook
5039 + tc_symbol_new_hook (symbolP);
5043 + verify_symbol_chain (symbol_rootP, symbol_lastP);
5044 +#endif /* DEBUG_SYMS */
5056 + struct cpool *next;
5058 + struct cpool_entry *literals;
5059 + unsigned int padding;
5060 + unsigned int next_free_entry;
5064 + subsegT sub_section;
5067 +struct cpool *cpool_list = NULL;
5069 +static struct cpool *
5070 +find_cpool(segT section, subsegT sub_section)
5072 + struct cpool *pool;
5074 + for (pool = cpool_list; pool != NULL; pool = pool->next)
5077 + && pool->section == section
5078 + && pool->sub_section == sub_section)
5085 +static struct cpool *
5086 +find_or_make_cpool(segT section, subsegT sub_section)
5088 + static unsigned int next_cpool_id = 0;
5089 + struct cpool *pool;
5091 + pool = find_cpool(section, sub_section);
5095 + pool = xmalloc(sizeof(*pool));
5100 + pool->literals = NULL;
5101 + pool->padding = 0;
5102 + pool->next_free_entry = 0;
5103 + pool->section = section;
5104 + pool->sub_section = sub_section;
5105 + pool->next = cpool_list;
5106 + pool->symbol = NULL;
5108 + cpool_list = pool;
5111 + /* NULL symbol means that the pool is new or has just been emptied. */
5112 + if (!pool->symbol)
5114 + pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section,
5115 + 0, &zero_address_frag);
5116 + pool->id = next_cpool_id++;
5122 +static struct cpool *
5123 +add_to_cpool(expressionS *exp, unsigned int *index, int ref)
5125 + struct cpool *pool;
5126 + unsigned int entry;
5128 + pool = find_or_make_cpool(now_seg, now_subseg);
5130 + /* Check if this constant is already in the pool. */
5131 + for (entry = 0; entry < pool->next_free_entry; entry++)
5133 + if ((pool->literals[entry].exp.X_op == exp->X_op)
5134 + && (exp->X_op == O_constant)
5135 + && (pool->literals[entry].exp.X_add_number
5136 + == exp->X_add_number)
5137 + && (pool->literals[entry].exp.X_unsigned
5138 + == exp->X_unsigned))
5141 + if ((pool->literals[entry].exp.X_op == exp->X_op)
5142 + && (exp->X_op == O_symbol)
5143 + && (pool->literals[entry].exp.X_add_number
5144 + == exp->X_add_number)
5145 + && (pool->literals[entry].exp.X_add_symbol
5146 + == exp->X_add_symbol)
5147 + && (pool->literals[entry].exp.X_op_symbol
5148 + == exp->X_op_symbol))
5152 + /* Create an entry if we didn't find a match */
5153 + if (entry == pool->next_free_entry)
5155 + pool->literals = xrealloc(pool->literals,
5156 + sizeof(struct cpool_entry) * (entry + 1));
5157 + pool->literals[entry].exp = *exp;
5158 + pool->literals[entry].refcount = 0;
5159 + pool->next_free_entry++;
5165 + pool->literals[entry].refcount++;
5170 +struct avr32_operand
5176 + int (*match)(char *str);
5177 + void (*parse)(const struct avr32_operand *op, char *str, int opindex);
5181 +match_anything(char *str ATTRIBUTE_UNUSED)
5187 +match_intreg(char *str)
5189 + int regid, ret = 1;
5191 + regid = avr32_parse_intreg(str);
5195 + pr_debug("match_intreg: `%s': %d\n", str, ret);
5201 +match_intreg_predec(char *str)
5205 + if (str[0] != '-' || str[1] != '-')
5208 + regid = avr32_parse_intreg(str + 2);
5216 +match_intreg_postinc(char *str)
5218 + int regid, ret = 1;
5221 + for (p = str; *p; p++)
5225 + if (p[0] != '+' || p[1] != '+')
5229 + regid = avr32_parse_intreg(str);
5238 +match_intreg_lsl(char *str)
5240 + int regid, ret = 1;
5243 + for (p = str; *p; p++)
5247 + if (p[0] && p[1] != '<')
5251 + regid = avr32_parse_intreg(str);
5260 +match_intreg_lsr(char *str)
5262 + int regid, ret = 1;
5265 + for (p = str; *p; p++)
5269 + if (p[0] && p[1] != '>')
5274 + regid = avr32_parse_intreg(str);
5283 +match_intreg_part(char *str)
5285 + int regid, ret = 1;
5288 + for (p = str; *p; p++)
5292 + if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0')
5296 + regid = avr32_parse_intreg(str);
5305 +#define match_intreg_disp match_anything
5308 +match_intreg_index(char *str)
5310 + int regid, ret = 1;
5313 + for (p = str; *p; p++)
5317 + /* don't allow empty displacement here (it makes no sense) */
5321 + for (end = p + 1; *end; end++) ;
5322 + if (*(--end) != ']')
5325 + c = *end, *end = 0;
5326 + if (!match_intreg_lsl(p + 1))
5333 + regid = avr32_parse_intreg(str);
5343 +match_intreg_xindex(char *str)
5345 + int regid, ret = 1;
5348 + for (p = str; *p; p++)
5352 + /* empty displacement makes no sense here either */
5356 + for (end = p + 1; *end; end++)
5360 + if (!streq(end, "<<2]"))
5363 + c = *end, *end = 0;
5364 + if (!match_intreg_part(p + 1))
5371 + regid = avr32_parse_intreg(str);
5380 +/* The PC_UDISP_W operator may show up as a label or as a pc[disp]
5381 + expression. So there's no point in attempting to match this... */
5382 +#define match_pc_disp match_anything
5385 +match_sp(char *str)
5387 + /* SP in any form will do */
5388 + return avr32_parse_intreg(str) == AVR32_REG_SP;
5392 +match_sp_disp(char *str)
5394 + int regid, ret = 1;
5397 + for (p = str; *p; p++)
5401 + /* allow empty displacement, meaning zero */
5405 + for (end = p + 1; *end; end++) ;
5406 + if (end[-1] != ']')
5411 + regid = avr32_parse_intreg(str);
5412 + if (regid != AVR32_REG_SP)
5420 +match_cpno(char *str)
5422 + if (strncasecmp(str, "cp", 2) != 0)
5428 +match_cpreg(char *str)
5430 + if (strncasecmp(str, "cr", 2) != 0)
5435 +/* We allow complex expressions, and register names may show up as
5436 + symbols. Just make sure immediate expressions are always matched
5438 +#define match_const match_anything
5439 +#define match_jmplabel match_anything
5440 +#define match_number match_anything
5442 +/* Mnemonics that take reglists never accept anything else */
5443 +#define match_reglist8 match_anything
5444 +#define match_reglist9 match_anything
5445 +#define match_reglist16 match_anything
5446 +#define match_reglist_ldm match_anything
5447 +#define match_reglist_cp8 match_anything
5448 +#define match_reglist_cpd8 match_anything
5450 +/* Ditto for retval, jospinc and mcall */
5451 +#define match_retval match_anything
5452 +#define match_jospinc match_anything
5453 +#define match_mcall match_anything
5455 +/* COH is used to select between two different syntaxes */
5457 +match_coh(char *str)
5459 + return strcasecmp(str, "coh") == 0;
5463 +match_fpreg(char *str)
5465 + unsigned long regid;
5468 + if ((str[0] != 'f' && str[0] != 'F')
5469 + || (str[1] != 'r' && str[1] != 'R'))
5473 + regid = strtoul(str, &endptr, 10);
5474 + if (!*str || *endptr)
5482 +match_picoreg(char *str)
5486 + regid = avr32_parse_picoreg(str);
5492 +#define match_pico_reglist_w match_anything
5493 +#define match_pico_reglist_d match_anything
5496 +match_pico_in(char *str)
5498 + unsigned long regid;
5501 + if (strncasecmp(str, "in", 2) != 0)
5505 + regid = strtoul(str, &end, 10);
5506 + if (!*str || *end)
5513 +match_pico_out0(char *str)
5515 + if (strcasecmp(str, "out0") != 0)
5521 +match_pico_out1(char *str)
5523 + if (strcasecmp(str, "out1") != 0)
5529 +match_pico_out2(char *str)
5531 + if (strcasecmp(str, "out2") != 0)
5537 +match_pico_out3(char *str)
5539 + if (strcasecmp(str, "out3") != 0)
5544 +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5545 + char *str ATTRIBUTE_UNUSED,
5546 + int opindex ATTRIBUTE_UNUSED)
5548 + /* Do nothing (this is used for "match-only" operands like COH) */
5552 +parse_const(const struct avr32_operand *op, char *str,
5553 + int opindex ATTRIBUTE_UNUSED)
5555 + expressionS *exp = ¤t_insn.immediate;
5556 + expressionS *sym_exp;
5560 + pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5561 + str, op->is_signed, op->is_pcrel, op->align_order);
5563 + save = input_line_pointer;
5564 + input_line_pointer = str;
5568 + slot = current_insn.next_slot++;
5569 + current_insn.field_value[slot].align_order = op->align_order;
5570 + current_insn.pcrel = op->is_pcrel;
5572 + switch (exp->X_op)
5575 + as_bad(_("illegal operand"));
5578 + as_bad(_("missing operand"));
5581 + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number);
5582 + current_insn.field_value[slot].value = exp->X_add_number;
5585 + pr_debug(" -> uminus\n");
5586 + sym_exp = symbol_get_value_expression(exp->X_add_symbol);
5587 + switch (sym_exp->X_op) {
5589 + pr_debug(" -> subtract: switching operands\n");
5590 + exp->X_op_symbol = sym_exp->X_add_symbol;
5591 + exp->X_add_symbol = sym_exp->X_op_symbol;
5592 + exp->X_op = O_subtract;
5593 + /* TODO: Remove the old X_add_symbol */
5596 + as_bad(_("Expression too complex\n"));
5602 + /* Any expression subtracting a symbol from the current section
5603 + can be made PC-relative by adding the right offset. */
5604 + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5605 + current_insn.pcrel = TRUE;
5606 + pr_debug(" -> subtract: pcrel? %s\n",
5607 + current_insn.pcrel ? "yes" : "no");
5608 + /* fall through */
5611 + pr_debug(" -> (%p <%d> %p + %d)\n",
5612 + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5613 + exp->X_add_number);
5614 + current_insn.field_value[slot].value = 0;
5618 + input_line_pointer = save;
5622 +parse_jmplabel(const struct avr32_operand *op, char *str,
5623 + int opindex ATTRIBUTE_UNUSED)
5625 + expressionS *exp = ¤t_insn.immediate;
5629 + pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5630 + str, op->is_signed, op->is_pcrel, op->align_order);
5632 + save = input_line_pointer;
5633 + input_line_pointer = str;
5637 + slot = current_insn.next_slot++;
5638 + current_insn.field_value[slot].align_order = op->align_order;
5639 + current_insn.pcrel = TRUE;
5641 + switch (exp->X_op)
5644 + as_bad(_("illegal operand"));
5647 + as_bad(_("missing operand"));
5650 + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number);
5651 + current_insn.field_value[slot].value = exp->X_add_number;
5652 + current_insn.pcrel = 0;
5655 + pr_debug(" -> (%p <%d> %p + %d)\n",
5656 + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5657 + exp->X_add_number);
5658 + current_insn.field_value[slot].value = 0;
5662 + input_line_pointer = save;
5666 +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5667 + char *str, int opindex ATTRIBUTE_UNUSED)
5671 + pr_debug("parse_intreg: `%s'\n", str);
5673 + regid = avr32_parse_intreg(str);
5674 + assert(regid >= 0);
5676 + slot = current_insn.next_slot++;
5677 + current_insn.field_value[slot].value = regid;
5678 + current_insn.field_value[slot].align_order = op->align_order;
5682 +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex)
5684 + parse_intreg(op, str + 2, opindex);
5688 +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex)
5692 + pr_debug("parse_intreg_postinc: `%s'\n", str);
5694 + for (p = str; *p != '+'; p++) ;
5697 + parse_intreg(op, str, opindex);
5702 +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5703 + char *str, int opindex ATTRIBUTE_UNUSED)
5705 + int regid, slot, shift = 0;
5709 + pr_debug("parse Ry<<sa: `%s'\n", str);
5711 + for (p = str; *p; p++)
5712 + if (*p == '<' || *p == '>')
5718 + regid = avr32_parse_intreg(str);
5719 + assert(regid >= 0);
5724 + if (p[0] != shiftop || p[1] != shiftop)
5725 + as_bad(_("expected shift operator in `%s'"), p);
5731 + saved = input_line_pointer;
5732 + input_line_pointer = p + 2;
5734 + input_line_pointer = saved;
5736 + if (exp.X_op != O_constant)
5737 + as_bad(_("shift amount must be a numeric constant"));
5739 + shift = exp.X_add_number;
5743 + slot = current_insn.next_slot++;
5744 + current_insn.field_value[slot].value = regid;
5745 + slot = current_insn.next_slot++;
5746 + current_insn.field_value[slot].value = shift;
5749 +/* The match() function selected the right opcode, so it doesn't
5750 + matter which way we shift any more. */
5751 +#define parse_intreg_lsl parse_intreg_shift
5752 +#define parse_intreg_lsr parse_intreg_shift
5755 +parse_intreg_part(const struct avr32_operand *op, char *str,
5756 + int opindex ATTRIBUTE_UNUSED)
5758 + static const char bparts[] = { 'b', 'l', 'u', 't' };
5759 + static const char hparts[] = { 'b', 't' };
5760 + unsigned int slot, sel;
5764 + pr_debug("parse reg:part `%s'\n", str);
5766 + for (p = str; *p; p++)
5771 + regid = avr32_parse_intreg(str);
5772 + assert(regid >= 0);
5777 + if (op->align_order)
5779 + for (sel = 0; sel < sizeof(hparts); sel++)
5780 + if (TOLOWER(p[1]) == hparts[sel])
5783 + if (sel >= sizeof(hparts))
5785 + as_bad(_("invalid halfword selector `%c' (must be either b or t)"),
5792 + for (sel = 0; sel < sizeof(bparts); sel++)
5793 + if (TOLOWER(p[1]) == bparts[sel])
5796 + if (sel >= sizeof(bparts))
5798 + as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"),
5804 + slot = current_insn.next_slot++;
5805 + current_insn.field_value[slot].value = regid;
5806 + slot = current_insn.next_slot++;
5807 + current_insn.field_value[slot].value = sel;
5810 +/* This is the parser for "Rp[displacement]" expressions. In addition
5811 + to the "official" syntax, we accept a label as a replacement for
5812 + the register expression. This syntax implies Rp=PC and the
5813 + displacement is the pc-relative distance to the label. */
5815 +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex)
5817 + expressionS *exp = ¤t_insn.immediate;
5819 + char *save, *p, c;
5821 + pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5822 + str, op->is_signed, op->is_pcrel, op->align_order);
5824 + for (p = str; *p; p++)
5828 + slot = current_insn.next_slot++;
5830 + /* First, check if we have a valid register either before '[' or as
5831 + the sole expression. If so, we use the Rp[disp] syntax. */
5833 + regid = avr32_parse_intreg(str);
5838 + current_insn.field_value[slot].value = regid;
5840 + slot = current_insn.next_slot++;
5841 + current_insn.field_value[slot].align_order = op->align_order;
5845 + save = input_line_pointer;
5846 + input_line_pointer = p + 1;
5850 + if (*input_line_pointer != ']')
5851 + as_bad(_("junk after displacement expression"));
5853 + input_line_pointer = save;
5855 + switch (exp->X_op)
5858 + as_bad(_("illegal displacement expression"));
5861 + as_bad(_("missing displacement expression"));
5864 + pr_debug(" -> constant: %ld\n", exp->X_add_number);
5865 + current_insn.field_value[slot].value = exp->X_add_number;
5869 + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5870 + current_insn.pcrel = TRUE;
5871 + pr_debug(" -> subtract: pcrel? %s\n",
5872 + current_insn.pcrel ? "yes" : "no");
5873 + /* fall through */
5876 + pr_debug(" -> (%p <%d> %p + %d)\n",
5877 + exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5878 + exp->X_add_number);
5879 + current_insn.field_value[slot].value = 0;
5884 + exp->X_op = O_constant;
5885 + exp->X_add_number = 0;
5886 + current_insn.field_value[slot].value = 0;
5891 + /* Didn't find a valid register. Try parsing it as a label. */
5892 + current_insn.field_value[slot].value = AVR32_REG_PC;
5893 + parse_jmplabel(op, str, opindex);
5898 +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5899 + char *str, int opindex ATTRIBUTE_UNUSED)
5904 + for (p = str; *p; p++)
5911 + regid = avr32_parse_intreg(str);
5912 + assert(regid >= 0);
5915 + slot = current_insn.next_slot++;
5916 + current_insn.field_value[slot].value = regid;
5919 + for (end = p; *end; end++)
5920 + if (*end == ']' || *end == '<')
5925 + c = *end, *end = 0;
5926 + regid = avr32_parse_intreg(p);
5927 + assert(regid >= 0);
5930 + slot = current_insn.next_slot++;
5931 + current_insn.field_value[slot].value = regid;
5933 + slot = current_insn.next_slot++;
5934 + current_insn.field_value[slot].value = 0;
5942 + for (end = p; *end; end++)
5946 + assert(*end == ']');
5948 + c = *end, *end = 0;
5949 + save = input_line_pointer;
5950 + input_line_pointer = p;
5953 + if (*input_line_pointer)
5954 + as_bad(_("junk after shift expression"));
5957 + input_line_pointer = save;
5959 + if (exp.X_op == O_constant)
5960 + current_insn.field_value[slot].value = exp.X_add_number;
5962 + as_bad(_("shift expression too complex"));
5967 +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex)
5972 + for (p = str; *p; p++)
5979 + regid = avr32_parse_intreg(str);
5980 + assert(regid >= 0);
5983 + slot = current_insn.next_slot++;
5984 + current_insn.field_value[slot].value = regid;
5987 + for (end = p; *end; end++)
5993 + c = *end, *end = 0;
5994 + parse_intreg_part(op, p, opindex);
5999 +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex)
6003 + for (p = str; *p; p++)
6007 + /* The lddpc instruction comes in two different syntax variants:
6008 + lddpc reg, expression
6009 + lddpc reg, pc[disp]
6010 + If the operand contains a '[', we use the second form. */
6016 + regid = avr32_parse_intreg(str);
6018 + if (regid == AVR32_REG_PC)
6022 + for (end = ++p; *end; end++) ;
6023 + if (*(--end) != ']')
6024 + as_bad(_("unrecognized form of instruction: `%s'"), str);
6027 + c = *end, *end = 0;
6028 + parse_const(op, p, opindex);
6030 + current_insn.pcrel = 0;
6034 + as_bad(_("unrecognized form of instruction: `%s'"), str);
6038 + parse_jmplabel(op, str, opindex);
6042 +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6043 + char *str ATTRIBUTE_UNUSED,
6044 + int opindex ATTRIBUTE_UNUSED)
6048 + slot = current_insn.next_slot++;
6049 + current_insn.field_value[slot].value = AVR32_REG_SP;
6053 +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex)
6057 + for (; *str; str++)
6063 + for (p = ++str; *p; p++)
6068 + parse_const(op, str, opindex);
6073 +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str,
6074 + int opindex ATTRIBUTE_UNUSED)
6081 + if (*str < '0' || *str > '7' || str[1])
6082 + as_bad(_("invalid coprocessor `%s'"), str);
6084 + slot = current_insn.next_slot++;
6085 + current_insn.field_value[slot].value = *str - '0';
6089 +parse_cpreg(const struct avr32_operand *op, char *str,
6090 + int opindex ATTRIBUTE_UNUSED)
6092 + unsigned int crid;
6097 + crid = strtoul(str, &endptr, 10);
6098 + if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1))
6099 + as_bad(_("invalid coprocessor register `%s'"), str);
6101 + crid >>= op->align_order;
6103 + slot = current_insn.next_slot++;
6104 + current_insn.field_value[slot].value = crid;
6108 +parse_number(const struct avr32_operand *op, char *str,
6109 + int opindex ATTRIBUTE_UNUSED)
6115 + save = input_line_pointer;
6116 + input_line_pointer = str;
6118 + input_line_pointer = save;
6120 + slot = current_insn.next_slot++;
6121 + current_insn.field_value[slot].align_order = op->align_order;
6123 + if (exp.X_op == O_constant)
6124 + current_insn.field_value[slot].value = exp.X_add_number;
6126 + as_bad(_("invalid numeric expression `%s'"), str);
6130 +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6131 + char *str, int opindex ATTRIBUTE_UNUSED)
6133 + unsigned long regmask;
6134 + unsigned long value = 0;
6138 + regmask = avr32_parse_reglist(str, &tail);
6140 + as_bad(_("invalid register list `%s'"), str);
6143 + if (avr32_make_regmask8(regmask, &value))
6144 + as_bad(_("register list `%s' doesn't fit"), str);
6147 + slot = current_insn.next_slot++;
6148 + current_insn.field_value[slot].value = value;
6152 +parse_reglist_tail(char *str, unsigned long regmask)
6155 + char *save, *p, c;
6158 + for (p = str + 1; *p; p++)
6164 + as_bad(_("invalid register list `%s'"), str);
6169 + regid = avr32_parse_intreg(str);
6174 + as_bad(_("invalid register list `%s'"), str);
6178 + /* If we have an assignment, we must pop PC and we must _not_
6180 + if (!(regmask & (1 << AVR32_REG_PC)))
6182 + as_bad(_("return value specified for non-return instruction"));
6185 + else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR)))
6187 + as_bad(_("can't pop LR or R12 when specifying return value"));
6191 + save = input_line_pointer;
6192 + input_line_pointer = p + 1;
6194 + input_line_pointer = save;
6196 + if (exp.X_op != O_constant
6197 + || exp.X_add_number < -1
6198 + || exp.X_add_number > 1)
6200 + as_bad(_("invalid return value `%s'"), str);
6204 + return exp.X_add_number;
6208 +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6209 + char *str, int opindex ATTRIBUTE_UNUSED)
6211 + unsigned long regmask;
6212 + unsigned long value = 0, kbit = 0;
6216 + regmask = avr32_parse_reglist(str, &tail);
6217 + /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */
6222 + retval = parse_reglist_tail(tail, regmask);
6227 + regmask |= 1 << AVR32_REG_LR;
6232 + regmask |= 1 << AVR32_REG_R12;
6241 + if (avr32_make_regmask8(regmask, &value))
6242 + as_bad(_("register list `%s' doesn't fit"), str);
6245 + slot = current_insn.next_slot++;
6246 + current_insn.field_value[slot].value = (value << 1) | kbit;
6250 +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6251 + char *str, int opindex ATTRIBUTE_UNUSED)
6253 + unsigned long regmask;
6257 + regmask = avr32_parse_reglist(str, &tail);
6259 + as_bad(_("invalid register list `%s'"), str);
6261 + slot = current_insn.next_slot++;
6262 + current_insn.field_value[slot].value = regmask;
6266 +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6267 + char *str, int opindex ATTRIBUTE_UNUSED)
6269 + unsigned long regmask;
6270 + int slot, rp, w_bit = 0;
6271 + char *tail, *p, c;
6273 + for (p = str; *p && *p != ','; p++)
6278 + rp = avr32_parse_intreg(str);
6282 + as_bad(_("invalid destination register in `%s'"), str);
6286 + if (p[0] == '+' && p[1] == '+')
6294 + as_bad(_("expected `,' after destination register in `%s'"), str);
6299 + regmask = avr32_parse_reglist(str, &tail);
6304 + if (rp != AVR32_REG_SP)
6306 + as_bad(_("junk at end of line: `%s'"), tail);
6310 + rp = AVR32_REG_PC;
6312 + retval = parse_reglist_tail(tail, regmask);
6317 + regmask |= 1 << AVR32_REG_LR;
6322 + regmask |= 1 << AVR32_REG_R12;
6329 + slot = current_insn.next_slot++;
6330 + current_insn.field_value[slot].value = rp;
6331 + slot = current_insn.next_slot++;
6332 + current_insn.field_value[slot].value = w_bit;
6333 + slot = current_insn.next_slot++;
6334 + current_insn.field_value[slot].value = regmask;
6338 +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6339 + char *str, int opindex ATTRIBUTE_UNUSED)
6341 + unsigned long regmask;
6342 + int slot, h_bit = 0;
6345 + regmask = avr32_parse_cpreglist(str, &tail);
6347 + as_bad(_("junk at end of line: `%s'"), tail);
6348 + else if (regmask & 0xffUL)
6350 + if (regmask & 0xff00UL)
6351 + as_bad(_("register list `%s' doesn't fit"), str);
6354 + else if (regmask & 0xff00UL)
6360 + as_warn(_("register list is empty"));
6362 + slot = current_insn.next_slot++;
6363 + current_insn.field_value[slot].value = regmask;
6364 + slot = current_insn.next_slot++;
6365 + current_insn.field_value[slot].value = h_bit;
6369 +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6370 + char *str, int opindex ATTRIBUTE_UNUSED)
6372 + unsigned long regmask, regmask_d = 0;
6376 + regmask = avr32_parse_cpreglist(str, &tail);
6378 + as_bad(_("junk at end of line: `%s'"), tail);
6380 + for (i = 0; i < 8; i++)
6384 + if (!(regmask & 2))
6386 + as_bad(_("register list `%s' doesn't fit"), str);
6389 + regmask_d |= 1 << i;
6391 + else if (regmask & 2)
6393 + as_bad(_("register list `%s' doesn't fit"), str);
6400 + slot = current_insn.next_slot++;
6401 + current_insn.field_value[slot].value = regmask_d;
6405 +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6406 + char *str, int opindex ATTRIBUTE_UNUSED)
6410 + regid = avr32_parse_intreg(str);
6418 + save = input_line_pointer;
6419 + input_line_pointer = str;
6421 + input_line_pointer = save;
6423 + if (exp.X_op != O_constant)
6424 + as_bad(_("invalid return value `%s'"), str);
6426 + switch (exp.X_add_number)
6429 + regid = AVR32_REG_LR;
6432 + regid = AVR32_REG_SP;
6435 + regid = AVR32_REG_PC;
6438 + as_bad(_("invalid return value `%s'"), str);
6443 + slot = current_insn.next_slot++;
6444 + current_insn.field_value[slot].value = regid;
6447 +#define parse_mcall parse_intreg_disp
6450 +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6451 + char *str, int opindex ATTRIBUTE_UNUSED)
6457 + save = input_line_pointer;
6458 + input_line_pointer = str;
6460 + input_line_pointer = save;
6462 + slot = current_insn.next_slot++;
6464 + if (exp.X_op == O_constant)
6466 + if (exp.X_add_number > 0)
6467 + exp.X_add_number--;
6468 + current_insn.field_value[slot].value = exp.X_add_number;
6471 + as_bad(_("invalid numeric expression `%s'"), str);
6474 +#define parse_coh parse_nothing
6477 +parse_fpreg(const struct avr32_operand *op,
6478 + char *str, int opindex ATTRIBUTE_UNUSED)
6480 + unsigned long regid;
6483 + regid = strtoul(str + 2, NULL, 10);
6485 + if ((regid >= 16) || (regid & ((1 << op->align_order) - 1)))
6486 + as_bad(_("invalid floating-point register `%s'"), str);
6488 + slot = current_insn.next_slot++;
6489 + current_insn.field_value[slot].value = regid;
6490 + current_insn.field_value[slot].align_order = op->align_order;
6495 +parse_picoreg(const struct avr32_operand *op,
6496 + char *str, int opindex ATTRIBUTE_UNUSED)
6498 + unsigned long regid;
6501 + regid = avr32_parse_picoreg(str);
6502 + if (regid & ((1 << op->align_order) - 1))
6503 + as_bad(_("invalid double-word PiCo register `%s'"), str);
6505 + slot = current_insn.next_slot++;
6506 + current_insn.field_value[slot].value = regid;
6507 + current_insn.field_value[slot].align_order = op->align_order;
6511 +parse_pico_reglist_w(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6512 + char *str, int opindex ATTRIBUTE_UNUSED)
6514 + unsigned long regmask;
6515 + int slot, h_bit = 0;
6518 + regmask = avr32_parse_pico_reglist(str, &tail);
6520 + as_bad(_("junk at end of line: `%s'"), tail);
6522 + if (regmask & 0x00ffUL)
6524 + if (regmask & 0xff00UL)
6525 + as_bad(_("register list `%s' doesn't fit"), str);
6526 + regmask &= 0x00ffUL;
6528 + else if (regmask & 0xff00UL)
6534 + as_warn(_("register list is empty"));
6536 + slot = current_insn.next_slot++;
6537 + current_insn.field_value[slot].value = regmask;
6538 + slot = current_insn.next_slot++;
6539 + current_insn.field_value[slot].value = h_bit;
6543 +parse_pico_reglist_d(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6544 + char *str, int opindex ATTRIBUTE_UNUSED)
6546 + unsigned long regmask, regmask_d = 0;
6550 + regmask = avr32_parse_pico_reglist(str, &tail);
6552 + as_bad(_("junk at end of line: `%s'"), tail);
6554 + for (i = 0; i < 8; i++)
6558 + if (!(regmask & 2))
6560 + as_bad(_("register list `%s' doesn't fit"), str);
6563 + regmask_d |= 1 << i;
6565 + else if (regmask & 2)
6567 + as_bad(_("register list `%s' doesn't fit"), str);
6574 + slot = current_insn.next_slot++;
6575 + current_insn.field_value[slot].value = regmask_d;
6579 +parse_pico_in(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6580 + char *str, int opindex ATTRIBUTE_UNUSED)
6582 + unsigned long regid;
6585 + regid = strtoul(str + 2, NULL, 10);
6588 + as_bad(_("invalid PiCo IN register `%s'"), str);
6590 + slot = current_insn.next_slot++;
6591 + current_insn.field_value[slot].value = regid;
6592 + current_insn.field_value[slot].align_order = 0;
6595 +#define parse_pico_out0 parse_nothing
6596 +#define parse_pico_out1 parse_nothing
6597 +#define parse_pico_out2 parse_nothing
6598 +#define parse_pico_out3 parse_nothing
6600 +#define OP(name, sgn, pcrel, align, func) \
6601 + { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func }
6603 +struct avr32_operand avr32_operand_table[] = {
6604 + OP(INTREG, 0, 0, 0, intreg),
6605 + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
6606 + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
6607 + OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
6608 + OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
6609 + OP(INTREG_BSEL, 0, 0, 0, intreg_part),
6610 + OP(INTREG_HSEL, 0, 0, 1, intreg_part),
6611 + OP(INTREG_SDISP, 1, 0, 0, intreg_disp),
6612 + OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp),
6613 + OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp),
6614 + OP(INTREG_UDISP, 0, 0, 0, intreg_disp),
6615 + OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp),
6616 + OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp),
6617 + OP(INTREG_INDEX, 0, 0, 0, intreg_index),
6618 + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
6619 + OP(DWREG, 0, 0, 1, intreg),
6620 + OP(PC_UDISP_W, 0, 1, 2, pc_disp),
6621 + OP(SP, 0, 0, 0, sp),
6622 + OP(SP_UDISP_W, 0, 0, 2, sp_disp),
6623 + OP(CPNO, 0, 0, 0, cpno),
6624 + OP(CPREG, 0, 0, 0, cpreg),
6625 + OP(CPREG_D, 0, 0, 1, cpreg),
6626 + OP(UNSIGNED_CONST, 0, 0, 0, const),
6627 + OP(UNSIGNED_CONST_W, 0, 0, 2, const),
6628 + OP(SIGNED_CONST, 1, 0, 0, const),
6629 + OP(SIGNED_CONST_W, 1, 0, 2, const),
6630 + OP(JMPLABEL, 1, 1, 1, jmplabel),
6631 + OP(UNSIGNED_NUMBER, 0, 0, 0, number),
6632 + OP(UNSIGNED_NUMBER_W, 0, 0, 2, number),
6633 + OP(REGLIST8, 0, 0, 0, reglist8),
6634 + OP(REGLIST9, 0, 0, 0, reglist9),
6635 + OP(REGLIST16, 0, 0, 0, reglist16),
6636 + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
6637 + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
6638 + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
6639 + OP(RETVAL, 0, 0, 0, retval),
6640 + OP(MCALL, 1, 0, 2, mcall),
6641 + OP(JOSPINC, 0, 0, 0, jospinc),
6642 + OP(COH, 0, 0, 0, coh),
6643 + OP(PICO_REG_W, 0, 0, 0, picoreg),
6644 + OP(PICO_REG_D, 0, 0, 1, picoreg),
6645 + OP(PICO_REGLIST_W, 0, 0, 0, pico_reglist_w),
6646 + OP(PICO_REGLIST_D, 0, 0, 0, pico_reglist_d),
6647 + OP(PICO_IN, 0, 0, 0, pico_in),
6648 + OP(PICO_OUT0, 0, 0, 0, pico_out0),
6649 + OP(PICO_OUT1, 0, 0, 0, pico_out1),
6650 + OP(PICO_OUT2, 0, 0, 0, pico_out2),
6651 + OP(PICO_OUT3, 0, 0, 0, pico_out3),
6655 +md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6657 + pr_debug("md_undefined_symbol: %s\n", name);
6661 +struct avr32_relax_type
6665 + unsigned char align;
6666 + unsigned char length;
6667 + signed short next;
6670 +#define EMPTY { 0, 0, 0, 0, -1 }
6671 +#define C(lower, upper, align, next) \
6672 + { (lower), (upper), (align), 2, AVR32_OPC_##next }
6673 +#define E(lower, upper, align) \
6674 + { (lower), (upper), (align), 4, -1 }
6676 +static const struct avr32_relax_type avr32_relax_table[] =
6679 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6680 + EMPTY, EMPTY, EMPTY,
6681 + E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0),
6684 + EMPTY, EMPTY, EMPTY, EMPTY,
6686 + C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2),
6687 + C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2),
6688 + C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2),
6689 + C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2),
6690 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6691 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6693 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6694 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6695 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6696 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6697 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6698 + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6700 + EMPTY, EMPTY, EMPTY, EMPTY,
6702 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6703 + EMPTY, EMPTY, EMPTY,
6705 + C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0),
6707 + EMPTY, EMPTY, EMPTY,
6709 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6710 + E(0, 65535, 0), E(0, 65535, 0),
6711 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6712 + E(-32768, 32767, 0),
6714 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6716 + C(0, 7, 0, LD_UB4), E(-32768, 32767, 0),
6721 + C(0, 14, 1, LD_SH4), E(-32768, 32767, 0),
6723 + EMPTY, EMPTY, EMPTY,
6725 + C(0, 14, 1, LD_UH4),
6728 + E(-32768, 32767, 0),
6730 + EMPTY, EMPTY, EMPTY, EMPTY,
6732 + C(0, 124, 2, LD_W4), E(-32768, 32767, 0),
6734 + E(0, 1020, 2), /* LDC_D1 */
6736 + E(0, 1020, 2), /* LDC_W1 */
6738 + E(0, 16380, 2), /* LDC0_D */
6739 + E(0, 16380, 2), /* LDC0_W */
6742 + /* 112: LDCM_D_PU */
6743 + EMPTY, EMPTY, EMPTY,
6745 + C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0),
6747 + EMPTY,EMPTY, EMPTY,
6748 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6750 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6751 + /* 134: MACHH_W */
6752 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6753 + E(-131072, 131068, 2), /* MCALL */
6754 + E(0, 1020, 2), /* MFDR */
6755 + E(0, 1020, 2), /* MFSR */
6758 + C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0),
6760 + EMPTY, EMPTY, EMPTY,
6761 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6762 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6764 + E(-128, 127, 0), /* MOVEQ2 */
6765 + E(-128, 127, 0), /* MOVNE2 */
6766 + E(-128, 127, 0), /* MOVCC2 */
6767 + E(-128, 127, 0), /* 166: MOVCS2 */
6768 + E(-128, 127, 0), /* MOVGE2 */
6769 + E(-128, 127, 0), /* MOVLT2 */
6770 + E(-128, 127, 0), /* MOVMI2 */
6771 + E(-128, 127, 0), /* MOVPL2 */
6772 + E(-128, 127, 0), /* MOVLS2 */
6773 + E(-128, 127, 0), /* MOVGT2 */
6774 + E(-128, 127, 0), /* MOVLE2 */
6775 + E(-128, 127, 0), /* MOVHI2 */
6776 + E(-128, 127, 0), /* MOVVS2 */
6777 + E(-128, 127, 0), /* MOVVC2 */
6778 + E(-128, 127, 0), /* MOVQS2 */
6779 + E(-128, 127, 0), /* MOVAL2 */
6781 + E(0, 1020, 2), /* MTDR */
6782 + E(0, 1020, 2), /* MTSR */
6785 + E(-128, 127, 0), /* MUL3 */
6786 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6787 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6789 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6790 + E(0, 65535, 0), E(0, 65535, 0),
6791 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6792 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6793 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6795 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6796 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6797 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6798 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6799 + /* 262: PUNPCKSB_H */
6800 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6802 + C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1),
6805 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6806 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6807 + EMPTY, EMPTY, EMPTY,
6809 + C(-1024, 1022, 1, BRAL),
6811 + EMPTY, EMPTY, EMPTY,
6812 + E(-128, 127, 0), /* RSUB2 */
6813 + /* 294: SATADD_H */
6814 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6815 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6816 + E(0, 255, 0), /* SLEEP */
6818 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6819 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6822 + C(0, 7, 0, ST_B4), E(-32768, 32767, 0),
6823 + EMPTY, EMPTY, EMPTY, EMPTY,
6824 + E(-32768, 32767, 0),
6825 + EMPTY, EMPTY, EMPTY,
6826 + C(0, 14, 1, ST_H4), E(-32768, 32767, 0),
6829 + C(0, 60, 2, ST_W4), E(-32768, 32767, 0),
6830 + E(0, 1020, 2), /* STC_D1 */
6832 + E(0, 1020, 2), /* STC_W1 */
6834 + E(0, 16380, 2), /* STC0_D */
6835 + E(0, 16380, 2), /* STC0_W */
6837 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6840 + E(0, 1020, 2), /* STHH_W1 */
6841 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6842 + EMPTY, EMPTY, EMPTY,
6843 + E(-32768, 32767, 0),
6844 + C(-512, 508, 2, SUB4),
6845 + C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0),
6847 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6848 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6849 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6850 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6852 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6853 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6854 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6855 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6859 + EMPTY, EMPTY, EMPTY,
6860 + E(0, 255, 0), /* SYNC */
6861 + EMPTY, EMPTY, EMPTY, EMPTY,
6863 + EMPTY, EMPTY, E(-65536, 65535, 2), E(-65536, 65535, 2), E(-65536, 65535, 2), EMPTY, EMPTY, EMPTY,
6864 + /* 422: RSUB{cond} */
6865 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6866 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6867 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6868 + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6869 + /* 436: ADD{cond} */
6870 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6871 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6872 + /* 454: SUB{cond} */
6873 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6874 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6875 + /* 472: AND{cond} */
6876 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6877 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6878 + /* 486: OR{cond} */
6879 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6880 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6881 + /* 502: EOR{cond} */
6882 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6883 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6884 + /* 518: LD.w{cond} */
6885 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6886 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6887 + /* 534: LD.sh{cond} */
6888 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6889 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6890 + /* 550: LD.uh{cond} */
6891 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6892 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6893 + /* 566: LD.sb{cond} */
6894 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6895 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6896 + /* 582: LD.ub{cond} */
6897 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6898 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6899 + /* 596: ST.w{cond} */
6900 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6901 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6902 + /* 614: ST.h{cond} */
6903 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6904 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6905 + /* 630: ST.b{cond} */
6906 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6907 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6909 + E(0, 65535, 0), EMPTY, EMPTY,
6911 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6912 + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6919 +#define AVR32_RS_NONE (-1)
6921 +#define avr32_rs_size(state) (avr32_relax_table[(state)].length)
6922 +#define avr32_rs_align(state) (avr32_relax_table[(state)].align)
6923 +#define relax_more(state) (avr32_relax_table[(state)].next)
6925 +#define opc_initial_substate(opc) ((opc)->id)
6927 +static int need_relax(int subtype, offsetT distance)
6929 + offsetT upper_bound, lower_bound;
6931 + upper_bound = avr32_relax_table[subtype].upper_bound;
6932 + lower_bound = avr32_relax_table[subtype].lower_bound;
6934 + if (distance & ((1 << avr32_rs_align(subtype)) - 1))
6936 + if ((distance > upper_bound) || (distance < lower_bound))
6946 + LDA_SUBTYPE_LDDPC,
6948 + LDA_SUBTYPE_GOTLOAD,
6949 + LDA_SUBTYPE_GOTLOAD_LARGE,
6953 + CALL_SUBTYPE_RCALL1,
6954 + CALL_SUBTYPE_RCALL2,
6955 + CALL_SUBTYPE_MCALL_CP,
6956 + CALL_SUBTYPE_MCALL_GOT,
6957 + CALL_SUBTYPE_MCALL_LARGE,
6960 +#define LDA_INITIAL_SIZE (avr32_pic ? 4 : 2)
6961 +#define CALL_INITIAL_SIZE 2
6963 +#define need_reloc(sym, seg, pcrel) \
6964 + (!(S_IS_DEFINED(sym) \
6965 + && ((pcrel && S_GET_SEGMENT(sym) == seg) \
6966 + || (!pcrel && S_GET_SEGMENT(sym) == absolute_section))) \
6967 + || S_FORCE_RELOC(sym, 1))
6969 +/* Return an initial guess of the length by which a fragment must grow to
6970 + hold a branch to reach its destination.
6971 + Also updates fr_type/fr_subtype as necessary.
6973 + Called just before doing relaxation.
6974 + Any symbol that is now undefined will not become defined.
6975 + The guess for fr_var is ACTUALLY the growth beyond fr_fix.
6976 + Whatever we do to grow fr_fix or fr_var contributes to our returned value.
6977 + Although it may not be explicit in the frag, pretend fr_var starts with a
6981 +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment)
6986 + assert(fragP->fr_symbol);
6988 + if (fragP->tc_frag_data.force_extended
6989 + || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel))
6991 + int largest_state = fragP->fr_subtype;
6992 + while (relax_more(largest_state) != AVR32_RS_NONE)
6993 + largest_state = relax_more(largest_state);
6994 + growth = avr32_rs_size(largest_state) - fragP->fr_var;
6998 + growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var;
7001 + pr_debug("%s:%d: md_estimate_size_before_relax: %d\n",
7002 + fragP->fr_file, fragP->fr_line, growth);
7008 +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
7010 + return fragP->fr_var - LDA_INITIAL_SIZE;
7014 +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
7016 + return fragP->fr_var - CALL_INITIAL_SIZE;
7020 +avr32_cpool_estimate_size_before_relax(fragS *fragP,
7021 + segT segment ATTRIBUTE_UNUSED)
7023 + return fragP->fr_var;
7026 +/* This macro may be defined to relax a frag. GAS will call this with the
7027 + * segment, the frag, and the change in size of all previous frags;
7028 + * md_relax_frag should return the change in size of the frag. */
7030 +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch)
7032 + int state, next_state;
7033 + symbolS *symbolP; /* The target symbol */
7036 + state = next_state = fragP->fr_subtype;
7038 + symbolP = fragP->fr_symbol;
7040 + if (fragP->tc_frag_data.force_extended
7041 + || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel))
7043 + /* Symbol must be resolved by the linker. Emit the largest
7044 + possible opcode. */
7045 + while (relax_more(next_state) != AVR32_RS_NONE)
7046 + next_state = relax_more(next_state);
7050 + addressT address; /* The address of fragP */
7051 + addressT target; /* The address of the target symbol */
7052 + offsetT distance; /* The distance between the insn and the symbol */
7055 + address = fragP->fr_address;
7056 + target = fragP->fr_offset;
7057 + symbolP = fragP->fr_symbol;
7058 + sym_frag = symbol_get_frag(symbolP);
7060 + address += fragP->fr_fix - fragP->fr_var;
7061 + target += S_GET_VALUE(symbolP);
7064 + && sym_frag->relax_marker != fragP->relax_marker
7065 + && S_GET_SEGMENT(symbolP) == segment)
7066 + /* if it was correctly aligned before, make sure it stays aligned */
7067 + target += stretch & (~0UL << avr32_rs_align(state));
7069 + if (fragP->tc_frag_data.pcrel)
7070 + distance = target - (address & (~0UL << avr32_rs_align(state)));
7072 + distance = target;
7074 + pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n",
7075 + fragP->fr_file, fragP->fr_line, target, address,
7076 + distance, distance, avr32_rs_align(state));
7078 + if (need_relax(state, distance))
7080 + if (relax_more(state) != AVR32_RS_NONE)
7081 + next_state = relax_more(state);
7082 + pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n",
7083 + fragP->fr_file, fragP->fr_line, state, next_state,
7084 + target, address, avr32_rs_align(state));
7088 + growth = avr32_rs_size(next_state) - avr32_rs_size(state);
7089 + fragP->fr_subtype = next_state;
7091 + pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n",
7092 + fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype,
7093 + avr32_opc_table[next_state].value);
7099 +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch)
7101 + struct cpool *pool= NULL;
7102 + unsigned int entry = 0;
7103 + addressT address, target;
7107 + long old_size, new_size;
7109 + symbolP = fragP->fr_symbol;
7110 + old_size = fragP->fr_var;
7113 + pool = fragP->tc_frag_data.pool;
7114 + entry = fragP->tc_frag_data.pool_entry;
7117 + address = fragP->fr_address;
7118 + address += fragP->fr_fix - LDA_INITIAL_SIZE;
7120 + if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1))
7123 + target = fragP->fr_offset;
7124 + sym_frag = symbol_get_frag(symbolP);
7125 + target += S_GET_VALUE(symbolP);
7127 + if (sym_frag->relax_marker != fragP->relax_marker
7128 + && S_GET_SEGMENT(symbolP) == segment)
7129 + target += stretch;
7131 + distance = target - address;
7133 + pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n",
7134 + target, address, fragP->fr_var);
7136 + if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7137 + && target <= 127 && (offsetT)target >= -128)
7139 + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7140 + || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7141 + pool->literals[entry].refcount--;
7143 + fragP->fr_subtype = LDA_SUBTYPE_MOV1;
7145 + else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7146 + && target <= 1048575 && (offsetT)target >= -1048576)
7148 + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7149 + || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7150 + pool->literals[entry].refcount--;
7152 + fragP->fr_subtype = LDA_SUBTYPE_MOV2;
7154 + else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment
7155 + /* the field will be negated, so this is really -(-32768)
7157 + && distance <= 32768 && distance >= -32767)
7160 + && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7161 + || fragP->fr_subtype == LDA_SUBTYPE_LDW))
7162 + pool->literals[entry].refcount--;
7164 + fragP->fr_subtype = LDA_SUBTYPE_SUB;
7174 + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE;
7179 + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD;
7184 + if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC
7185 + && fragP->fr_subtype != LDA_SUBTYPE_LDW)
7186 + pool->literals[entry].refcount++;
7188 + sym_frag = symbol_get_frag(pool->symbol);
7189 + target = (sym_frag->fr_address + sym_frag->fr_fix
7190 + + pool->padding + pool->literals[entry].offset);
7192 + pr_debug("cpool sym address: 0x%lx\n",
7193 + sym_frag->fr_address + sym_frag->fr_fix);
7195 + know(pool->section == segment);
7197 + if (sym_frag->relax_marker != fragP->relax_marker)
7198 + target += stretch;
7200 + distance = target - address;
7201 + if (distance <= 508 && distance >= 0)
7204 + fragP->fr_subtype = LDA_SUBTYPE_LDDPC;
7209 + fragP->fr_subtype = LDA_SUBTYPE_LDW;
7212 + pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n",
7213 + target, address, pool->literals[entry].refcount);
7217 + fragP->fr_var = new_size;
7219 + pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n",
7220 + fragP->fr_file, fragP->fr_line,
7221 + fragP->fr_subtype, new_size - old_size);
7223 + return new_size - old_size;
7227 +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch)
7229 + struct cpool *pool = NULL;
7230 + unsigned int entry = 0;
7231 + addressT address, target;
7235 + long old_size, new_size;
7237 + symbolP = fragP->fr_symbol;
7238 + old_size = fragP->fr_var;
7241 + pool = fragP->tc_frag_data.pool;
7242 + entry = fragP->tc_frag_data.pool_entry;
7245 + address = fragP->fr_address;
7246 + address += fragP->fr_fix - CALL_INITIAL_SIZE;
7248 + if (need_reloc(symbolP, segment, 1))
7250 + pr_debug("call: must emit reloc\n");
7254 + target = fragP->fr_offset;
7255 + sym_frag = symbol_get_frag(symbolP);
7256 + target += S_GET_VALUE(symbolP);
7258 + if (sym_frag->relax_marker != fragP->relax_marker
7259 + && S_GET_SEGMENT(symbolP) == segment)
7260 + target += stretch;
7262 + distance = target - address;
7264 + if (distance <= 1022 && distance >= -1024)
7266 + pr_debug("call: distance is %d, emitting short rcall\n", distance);
7267 + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7268 + pool->literals[entry].refcount--;
7270 + fragP->fr_subtype = CALL_SUBTYPE_RCALL1;
7272 + else if (distance <= 2097150 && distance >= -2097152)
7274 + pr_debug("call: distance is %d, emitting long rcall\n", distance);
7275 + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7276 + pool->literals[entry].refcount--;
7278 + fragP->fr_subtype = CALL_SUBTYPE_RCALL2;
7282 + pr_debug("call: distance %d too far, emitting something big\n", distance);
7290 + fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE;
7295 + fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT;
7300 + if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP)
7301 + pool->literals[entry].refcount++;
7304 + fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP;
7308 + fragP->fr_var = new_size;
7310 + pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n",
7311 + fragP->fr_file, fragP->fr_line,
7312 + new_size - old_size, fragP->fr_var);
7314 + return new_size - old_size;
7318 +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED,
7320 + long stretch ATTRIBUTE_UNUSED)
7322 + struct cpool *pool;
7324 + long old_size, new_size;
7325 + unsigned int entry;
7327 + pool = fragP->tc_frag_data.pool;
7328 + address = fragP->fr_address + fragP->fr_fix;
7329 + old_size = fragP->fr_var;
7332 + for (entry = 0; entry < pool->next_free_entry; entry++)
7334 + if (pool->literals[entry].refcount > 0)
7336 + pool->literals[entry].offset = new_size;
7341 + fragP->fr_var = new_size;
7343 + return new_size - old_size;
7346 +/* *fragP has been relaxed to its final size, and now needs to have
7347 + the bytes inside it modified to conform to the new size.
7349 + Called after relaxation is finished.
7350 + fragP->fr_type == rs_machine_dependent.
7351 + fragP->fr_subtype is the subtype of what the address relaxed to. */
7354 +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
7355 + segT segment ATTRIBUTE_UNUSED,
7358 + const struct avr32_opcode *opc;
7359 + const struct avr32_ifield *ifield;
7360 + bfd_reloc_code_real_type r_type;
7366 + opc = &avr32_opc_table[fragP->fr_subtype];
7367 + ifield = opc->fields[opc->var_field];
7368 + symbolP = fragP->fr_symbol;
7369 + subtype = fragP->fr_subtype;
7370 + r_type = opc->reloc_type;
7372 + /* Clear the opcode bits and the bits belonging to the relaxed
7373 + field. We assume all other fields stay the same. */
7374 + value = bfd_getb32(fragP->fr_opcode);
7375 + value &= ~(opc->mask | ifield->mask);
7377 + /* Insert the new opcode */
7378 + value |= opc->value;
7379 + bfd_putb32(value, fragP->fr_opcode);
7381 + fragP->fr_fix += opc->size - fragP->fr_var;
7383 + if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE)
7385 + switch (fragP->tc_frag_data.reloc_info)
7387 + case AVR32_OPINFO_HI:
7388 + r_type = BFD_RELOC_HI16;
7390 + case AVR32_OPINFO_LO:
7391 + r_type = BFD_RELOC_LO16;
7393 + case AVR32_OPINFO_GOT:
7396 + case BFD_RELOC_AVR32_18W_PCREL:
7397 + r_type = BFD_RELOC_AVR32_GOT18SW;
7399 + case BFD_RELOC_AVR32_16S:
7400 + r_type = BFD_RELOC_AVR32_GOT16S;
7408 + BAD_CASE(fragP->tc_frag_data.reloc_info);
7413 + pr_debug("%s:%d: convert_frag: new %s fixup\n",
7414 + fragP->fr_file, fragP->fr_line,
7415 + bfd_get_reloc_code_name(r_type));
7418 + fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size,
7419 + &fragP->tc_frag_data.exp,
7420 + fragP->tc_frag_data.pcrel, r_type);
7422 + fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP,
7423 + fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type);
7426 + /* Revert fix_new brain damage. "dot_value" is the value of PC at
7427 + the point of the fixup, relative to the frag address. fix_new()
7428 + and friends think they are only being called during the assembly
7429 + pass, not during relaxation or similar, so fx_dot_value, fx_file
7430 + and fx_line are all initialized to the wrong value. But we don't
7431 + know the size of the fixup until now, so we really can't live up
7432 + to the assumptions these functions make about the target. What
7433 + do these functions think the "where" and "frag" argument mean
7435 + fixP->fx_dot_value = fragP->fr_fix - opc->size;
7436 + fixP->fx_file = fragP->fr_file;
7437 + fixP->fx_line = fragP->fr_line;
7439 + fixP->tc_fix_data.ifield = ifield;
7440 + fixP->tc_fix_data.align = avr32_rs_align(subtype);
7441 + fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound;
7442 + fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound;
7446 +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7447 + segT segment ATTRIBUTE_UNUSED,
7450 + const struct avr32_opcode *opc;
7451 + const struct avr32_ifield *ifield;
7452 + bfd_reloc_code_real_type r_type;
7454 + struct cpool *pool;
7457 + int regid, pcrel = 0, align = 0;
7460 + r_type = BFD_RELOC_NONE;
7461 + regid = fragP->tc_frag_data.reloc_info;
7462 + p = fragP->fr_opcode;
7463 + exp.X_add_symbol = fragP->fr_symbol;
7464 + exp.X_add_number = fragP->fr_offset;
7465 + exp.X_op = O_symbol;
7467 + pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n",
7468 + fragP->fr_file, fragP->fr_line,
7469 + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid);
7471 + switch (fragP->fr_subtype)
7473 + case LDA_SUBTYPE_MOV1:
7474 + opc = &avr32_opc_table[AVR32_OPC_MOV1];
7475 + opc->fields[0]->insert(opc->fields[0], p, regid);
7476 + ifield = opc->fields[1];
7477 + r_type = opc->reloc_type;
7479 + case LDA_SUBTYPE_MOV2:
7480 + opc = &avr32_opc_table[AVR32_OPC_MOV2];
7481 + opc->fields[0]->insert(opc->fields[0], p, regid);
7482 + ifield = opc->fields[1];
7483 + r_type = opc->reloc_type;
7485 + case LDA_SUBTYPE_SUB:
7486 + opc = &avr32_opc_table[AVR32_OPC_SUB5];
7487 + opc->fields[0]->insert(opc->fields[0], p, regid);
7488 + opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC);
7489 + ifield = opc->fields[2];
7490 + r_type = BFD_RELOC_AVR32_16N_PCREL;
7492 + /* Pretend that SUB5 isn't a "negated" pcrel expression for now.
7493 + We'll have to fix it up later when we know whether to
7494 + generate a reloc for it (in which case the linker will negate
7495 + it, so we shouldn't). */
7498 + case LDA_SUBTYPE_LDDPC:
7499 + opc = &avr32_opc_table[AVR32_OPC_LDDPC];
7501 + r_type = BFD_RELOC_AVR32_9W_CP;
7502 + goto cpool_common;
7503 + case LDA_SUBTYPE_LDW:
7504 + opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT];
7505 + r_type = BFD_RELOC_AVR32_16_CP;
7507 + opc->fields[0]->insert(opc->fields[0], p, regid);
7508 + ifield = opc->fields[1];
7509 + pool = fragP->tc_frag_data.pool;
7510 + exp.X_add_symbol = pool->symbol;
7511 + exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset;
7514 + case LDA_SUBTYPE_GOTLOAD_LARGE:
7515 + /* ld.w Rd, r6[Rd << 2] (last) */
7516 + opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7517 + bfd_putb32(opc->value, p + 4);
7518 + opc->fields[0]->insert(opc->fields[0], p + 4, regid);
7519 + opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7520 + opc->fields[2]->insert(opc->fields[2], p + 4, regid);
7521 + opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7523 + /* mov Rd, (got_offset / 4) */
7524 + opc = &avr32_opc_table[AVR32_OPC_MOV2];
7525 + opc->fields[0]->insert(opc->fields[0], p, regid);
7526 + ifield = opc->fields[1];
7527 + r_type = BFD_RELOC_AVR32_LDA_GOT;
7529 + case LDA_SUBTYPE_GOTLOAD:
7530 + opc = &avr32_opc_table[AVR32_OPC_LD_W4];
7531 + opc->fields[0]->insert(opc->fields[0], p, regid);
7532 + opc->fields[1]->insert(opc->fields[1], p, 6);
7533 + ifield = opc->fields[2];
7534 + if (r_type == BFD_RELOC_NONE)
7535 + r_type = BFD_RELOC_AVR32_GOT16S;
7538 + BAD_CASE(fragP->fr_subtype);
7541 + value = bfd_getb32(p);
7542 + value &= ~(opc->mask | ifield->mask);
7543 + value |= opc->value;
7544 + bfd_putb32(value, p);
7546 + fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE;
7548 + if (fragP->fr_next
7549 + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7550 + != fragP->fr_fix))
7552 + fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n",
7553 + fragP->fr_var, bfd_get_reloc_code_name(r_type));
7557 + fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7558 + &exp, pcrel, r_type);
7560 + /* Revert fix_new brain damage. "dot_value" is the value of PC at
7561 + the point of the fixup, relative to the frag address. fix_new()
7562 + and friends think they are only being called during the assembly
7563 + pass, not during relaxation or similar, so fx_dot_value, fx_file
7564 + and fx_line are all initialized to the wrong value. But we don't
7565 + know the size of the fixup until now, so we really can't live up
7566 + to the assumptions these functions make about the target. What
7567 + do these functions think the "where" and "frag" argument mean
7569 + fixP->fx_dot_value = fragP->fr_fix - opc->size;
7570 + fixP->fx_file = fragP->fr_file;
7571 + fixP->fx_line = fragP->fr_line;
7573 + fixP->tc_fix_data.ifield = ifield;
7574 + fixP->tc_fix_data.align = align;
7575 + /* these are only used if the fixup can actually be resolved */
7576 + fixP->tc_fix_data.min = -32768;
7577 + fixP->tc_fix_data.max = 32767;
7581 +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7582 + segT segment ATTRIBUTE_UNUSED,
7585 + const struct avr32_opcode *opc = NULL;
7586 + const struct avr32_ifield *ifield;
7587 + bfd_reloc_code_real_type r_type;
7592 + int pcrel = 0, align = 0;
7595 + symbol = fragP->fr_symbol;
7596 + offset = fragP->fr_offset;
7597 + r_type = BFD_RELOC_NONE;
7598 + p = fragP->fr_opcode;
7600 + pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n",
7601 + fragP->fr_file, fragP->fr_line,
7602 + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
7604 + switch (fragP->fr_subtype)
7606 + case CALL_SUBTYPE_RCALL1:
7607 + opc = &avr32_opc_table[AVR32_OPC_RCALL1];
7608 + /* fall through */
7609 + case CALL_SUBTYPE_RCALL2:
7611 + opc = &avr32_opc_table[AVR32_OPC_RCALL2];
7612 + ifield = opc->fields[0];
7613 + r_type = opc->reloc_type;
7617 + case CALL_SUBTYPE_MCALL_CP:
7618 + opc = &avr32_opc_table[AVR32_OPC_MCALL];
7619 + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC);
7620 + ifield = opc->fields[1];
7621 + r_type = BFD_RELOC_AVR32_CPCALL;
7622 + symbol = fragP->tc_frag_data.pool->symbol;
7623 + offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset;
7624 + assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0);
7628 + case CALL_SUBTYPE_MCALL_GOT:
7629 + opc = &avr32_opc_table[AVR32_OPC_MCALL];
7630 + opc->fields[0]->insert(opc->fields[0], p, 6);
7631 + ifield = opc->fields[1];
7632 + r_type = BFD_RELOC_AVR32_GOT18SW;
7634 + case CALL_SUBTYPE_MCALL_LARGE:
7635 + assert(fragP->fr_var == 10);
7636 + /* ld.w lr, r6[lr << 2] */
7637 + opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7638 + bfd_putb32(opc->value, p + 4);
7639 + opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR);
7640 + opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7641 + opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR);
7642 + opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7645 + opc = &avr32_opc_table[AVR32_OPC_ICALL];
7646 + bfd_putb16(opc->value >> 16, p + 8);
7647 + opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR);
7649 + /* mov lr, (got_offset / 4) */
7650 + opc = &avr32_opc_table[AVR32_OPC_MOV2];
7651 + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR);
7652 + ifield = opc->fields[1];
7653 + r_type = BFD_RELOC_AVR32_GOTCALL;
7656 + BAD_CASE(fragP->fr_subtype);
7659 + /* Insert the opcode and clear the variable ifield */
7660 + value = bfd_getb32(p);
7661 + value &= ~(opc->mask | ifield->mask);
7662 + value |= opc->value;
7663 + bfd_putb32(value, p);
7665 + fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE;
7667 + if (fragP->fr_next
7668 + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7669 + != fragP->fr_fix))
7671 + fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n",
7672 + fragP->fr_file, fragP->fr_line,
7673 + fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type));
7674 + fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n",
7675 + (offsetT)(fragP->fr_next->fr_address - fragP->fr_address),
7676 + fragP->fr_next->fr_file, fragP->fr_next->fr_line);
7679 + fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7680 + symbol, offset, pcrel, r_type);
7682 + /* Revert fix_new brain damage. "dot_value" is the value of PC at
7683 + the point of the fixup, relative to the frag address. fix_new()
7684 + and friends think they are only being called during the assembly
7685 + pass, not during relaxation or similar, so fx_dot_value, fx_file
7686 + and fx_line are all initialized to the wrong value. But we don't
7687 + know the size of the fixup until now, so we really can't live up
7688 + to the assumptions these functions make about the target. What
7689 + do these functions think the "where" and "frag" argument mean
7691 + fixP->fx_dot_value = fragP->fr_fix - opc->size;
7692 + fixP->fx_file = fragP->fr_file;
7693 + fixP->fx_line = fragP->fr_line;
7695 + fixP->tc_fix_data.ifield = ifield;
7696 + fixP->tc_fix_data.align = align;
7697 + /* these are only used if the fixup can actually be resolved */
7698 + fixP->tc_fix_data.min = -2097152;
7699 + fixP->tc_fix_data.max = 2097150;
7703 +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7704 + segT segment ATTRIBUTE_UNUSED,
7707 + struct cpool *pool;
7709 + unsigned int entry;
7711 + char sym_name[20];
7713 + /* Did we get rid of the frag altogether? */
7714 + if (!fragP->fr_var)
7717 + pool = fragP->tc_frag_data.pool;
7718 + address = fragP->fr_address + fragP->fr_fix;
7719 + p = fragP->fr_literal + fragP->fr_fix;
7721 + sprintf(sym_name, "$$cp_\002%x", pool->id);
7722 + symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP);
7723 + symbol_table_insert(pool->symbol);
7725 + for (entry = 0; entry < pool->next_free_entry; entry++)
7727 + if (pool->literals[entry].refcount > 0)
7729 + fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp,
7730 + FALSE, BFD_RELOC_AVR32_32_CPENT);
7731 + fragP->fr_fix += 4;
7736 +static struct avr32_relaxer avr32_default_relaxer = {
7737 + .estimate_size = avr32_default_estimate_size_before_relax,
7738 + .relax_frag = avr32_default_relax_frag,
7739 + .convert_frag = avr32_default_convert_frag,
7741 +static struct avr32_relaxer avr32_lda_relaxer = {
7742 + .estimate_size = avr32_lda_estimate_size_before_relax,
7743 + .relax_frag = avr32_lda_relax_frag,
7744 + .convert_frag = avr32_lda_convert_frag,
7746 +static struct avr32_relaxer avr32_call_relaxer = {
7747 + .estimate_size = avr32_call_estimate_size_before_relax,
7748 + .relax_frag = avr32_call_relax_frag,
7749 + .convert_frag = avr32_call_convert_frag,
7751 +static struct avr32_relaxer avr32_cpool_relaxer = {
7752 + .estimate_size = avr32_cpool_estimate_size_before_relax,
7753 + .relax_frag = avr32_cpool_relax_frag,
7754 + .convert_frag = avr32_cpool_convert_frag,
7757 +static void s_cpool(int arg ATTRIBUTE_UNUSED)
7759 + struct cpool *pool;
7760 + unsigned int max_size;
7763 + pool = find_cpool(now_seg, now_subseg);
7764 + if (!pool || !pool->symbol || pool->next_free_entry == 0)
7767 + /* Make sure the constant pool is properly aligned */
7768 + frag_align_code(2, 0);
7769 + if (bfd_get_section_alignment(stdoutput, pool->section) < 2)
7770 + bfd_set_section_alignment(stdoutput, pool->section, 2);
7772 + /* Assume none of the entries are discarded, and that we need the
7773 + maximum amount of alignment. But we're not going to allocate
7774 + anything up front. */
7775 + max_size = pool->next_free_entry * 4 + 2;
7776 + frag_grow(max_size);
7777 + buf = frag_more(0);
7779 + frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer;
7780 + frag_now->tc_frag_data.pool = pool;
7782 + symbol_set_frag(pool->symbol, frag_now);
7784 + /* Assume zero initial size, allowing other relaxers to be
7785 + optimistic about things. */
7786 + frag_var(rs_machine_dependent, max_size, 0,
7787 + 0, pool->symbol, 0, NULL);
7789 + /* Mark the pool as empty. */
7793 +/* The location from which a PC relative jump should be calculated,
7794 + given a PC relative reloc. */
7797 +md_pcrel_from_section (fixS *fixP, segT sec)
7799 + pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset);
7801 + if (fixP->fx_addsy != NULL
7802 + && (! S_IS_DEFINED (fixP->fx_addsy)
7803 + || S_GET_SEGMENT (fixP->fx_addsy) != sec
7804 + || S_FORCE_RELOC(fixP->fx_addsy, 1)))
7806 + pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy));
7808 + /* The symbol is undefined (or is defined but not in this section).
7809 + Let the linker figure it out. */
7813 + pr_debug("pcrel from %x + %x, symbol: %s (%x)\n",
7814 + fixP->fx_frag->fr_address, fixP->fx_where,
7815 + fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)",
7816 + fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0);
7818 + return ((fixP->fx_frag->fr_address + fixP->fx_where)
7819 + & (~0UL << fixP->tc_fix_data.align));
7823 +md_section_align (segT segment, valueT size)
7825 + int align = bfd_get_section_alignment (stdoutput, segment);
7826 + return ((size + (1 << align) - 1) & (-1 << align));
7829 +static int syntax_matches(const struct avr32_syntax *syntax,
7834 + pr_debug("syntax %d matches `%s'?\n", syntax->id, str);
7836 + if (syntax->nr_operands < 0)
7838 + struct avr32_operand *op;
7841 + for (i = 0; i < (-syntax->nr_operands - 1); i++)
7846 + optype = syntax->operand[i];
7847 + assert(optype < AVR32_NR_OPERANDS);
7848 + op = &avr32_operand_table[optype];
7850 + for (p = str; *p; p++)
7860 + if (!op->match(str))
7872 + optype = syntax->operand[i];
7873 + assert(optype < AVR32_NR_OPERANDS);
7874 + op = &avr32_operand_table[optype];
7876 + if (!op->match(str))
7881 + for (i = 0; i < syntax->nr_operands; i++)
7883 + struct avr32_operand *op;
7884 + int optype = syntax->operand[i];
7888 + assert(optype < AVR32_NR_OPERANDS);
7889 + op = &avr32_operand_table[optype];
7891 + for (p = str; *p; p++)
7901 + if (!op->match(str))
7916 + if ((*str == 'e' || *str == 'E') && !str[1])
7922 +static int parse_operands(char *str)
7926 + if (current_insn.syntax->nr_operands < 0)
7929 + struct avr32_operand *op;
7931 + for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++)
7936 + optype = current_insn.syntax->operand[i];
7937 + op = &avr32_operand_table[optype];
7939 + for (p = str; *p; p++)
7946 + op->parse(op, str, i);
7953 + /* give the rest of the line to the last operand */
7954 + optype = current_insn.syntax->operand[i];
7955 + op = &avr32_operand_table[optype];
7956 + op->parse(op, str, i);
7960 + for (i = 0; i < current_insn.syntax->nr_operands; i++)
7962 + int optype = current_insn.syntax->operand[i];
7963 + struct avr32_operand *op = &avr32_operand_table[optype];
7967 + skip_whitespace(str);
7969 + for (p = str; *p; p++)
7976 + op->parse(op, str, i);
7983 + if (*str == 'E' || *str == 'e')
7984 + current_insn.force_extended = 1;
7990 +static const char *
7991 +finish_insn(const struct avr32_opcode *opc)
7993 + expressionS *exp = ¤t_insn.immediate;
7995 + int will_relax = 0;
7998 + assert(current_insn.next_slot == opc->nr_fields);
8000 + pr_debug("%s:%d: finish_insn: trying opcode %d\n",
8001 + frag_now->fr_file, frag_now->fr_line, opc->id);
8003 + /* Go through the relaxation stage for all instructions that can
8004 + possibly take a symbolic immediate. The relax code will take
8005 + care of range checking and alignment. */
8006 + if (opc->var_field != -1)
8008 + int substate, largest_substate;
8013 + substate = largest_substate = opc_initial_substate(opc);
8015 + while (relax_more(largest_substate) != AVR32_RS_NONE)
8016 + largest_substate = relax_more(largest_substate);
8018 + pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n",
8019 + substate, avr32_rs_size(substate),
8020 + largest_substate, avr32_rs_size(largest_substate));
8022 + /* make sure we have enough room for the largest possible opcode */
8023 + frag_grow(avr32_rs_size(largest_substate));
8024 + buf = frag_more(opc->size);
8026 + dwarf2_emit_insn(opc->size);
8028 + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE;
8029 + frag_now->tc_frag_data.pcrel = current_insn.pcrel;
8030 + frag_now->tc_frag_data.force_extended = current_insn.force_extended;
8031 + frag_now->tc_frag_data.relaxer = &avr32_default_relaxer;
8033 + if (exp->X_op == O_hi)
8035 + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI;
8036 + exp->X_op = exp->X_md;
8038 + else if (exp->X_op == O_lo)
8040 + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO;
8041 + exp->X_op = exp->X_md;
8043 + else if (exp->X_op == O_got)
8045 + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT;
8046 + exp->X_op = O_symbol;
8050 + if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5)
8051 + && exp->X_op == O_subtract)
8054 + tmp = exp->X_add_symbol;
8055 + exp->X_add_symbol = exp->X_op_symbol;
8056 + exp->X_op_symbol = tmp;
8060 + frag_now->tc_frag_data.exp = current_insn.immediate;
8062 + sym = exp->X_add_symbol;
8063 + off = exp->X_add_number;
8064 + if (exp->X_op != O_symbol)
8066 + sym = make_expr_symbol(exp);
8070 + frag_var(rs_machine_dependent,
8071 + avr32_rs_size(largest_substate) - opc->size,
8073 + substate, sym, off, buf);
8077 + assert(avr32_rs_size(opc_initial_substate(opc)) == 0);
8079 + /* Make sure we always have room for another whole word, as the ifield
8080 + inserters can only write words. */
8082 + buf = frag_more(opc->size);
8083 + dwarf2_emit_insn(opc->size);
8086 + assert(!(opc->value & ~opc->mask));
8088 + pr_debug("inserting opcode: 0x%lx\n", opc->value);
8089 + bfd_putb32(opc->value, buf);
8091 + for (i = 0; i < opc->nr_fields; i++)
8093 + const struct avr32_ifield *f = opc->fields[i];
8094 + const struct avr32_ifield_data *fd = ¤t_insn.field_value[i];
8096 + pr_debug("inserting field: 0x%lx & 0x%lx\n",
8097 + fd->value >> fd->align_order, f->mask);
8099 + f->insert(f, buf, fd->value >> fd->align_order);
8102 + assert(will_relax || !current_insn.immediate.X_add_symbol);
8106 +static const char *
8107 +finish_alias(const struct avr32_alias *alias)
8109 + const struct avr32_opcode *opc;
8111 + unsigned long value;
8112 + unsigned long align;
8113 + } mapped_operand[AVR32_MAX_OPERANDS];
8118 + /* Remap the operands from the alias to the real opcode */
8119 + for (i = 0; i < opc->nr_fields; i++)
8121 + if (alias->operand_map[i].is_opindex)
8123 + struct avr32_ifield_data *fd;
8124 + fd = ¤t_insn.field_value[alias->operand_map[i].value];
8125 + mapped_operand[i].value = fd->value;
8126 + mapped_operand[i].align = fd->align_order;
8130 + mapped_operand[i].value = alias->operand_map[i].value;
8131 + mapped_operand[i].align = 0;
8135 + for (i = 0; i < opc->nr_fields; i++)
8137 + current_insn.field_value[i].value = mapped_operand[i].value;
8138 + if (opc->id == AVR32_OPC_COP)
8139 + current_insn.field_value[i].align_order = 0;
8141 + current_insn.field_value[i].align_order
8142 + = mapped_operand[i].align;
8145 + current_insn.next_slot = opc->nr_fields;
8147 + return finish_insn(opc);
8150 +static const char *
8151 +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8153 + expressionS *exp = ¤t_insn.immediate;
8154 + relax_substateT initial_subtype;
8157 + int initial_size, max_size;
8160 + initial_size = LDA_INITIAL_SIZE;
8164 + initial_subtype = LDA_SUBTYPE_SUB;
8172 + initial_subtype = LDA_SUBTYPE_MOV1;
8176 + frag_grow(max_size);
8177 + buf = frag_more(initial_size);
8178 + dwarf2_emit_insn(initial_size);
8180 + if (exp->X_op == O_symbol)
8182 + sym = exp->X_add_symbol;
8183 + off = exp->X_add_number;
8187 + sym = make_expr_symbol(exp);
8191 + frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value;
8192 + frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer;
8196 + /* The relaxer will bump the refcount if necessary */
8197 + frag_now->tc_frag_data.pool
8198 + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8201 + frag_var(rs_machine_dependent, max_size - initial_size,
8202 + initial_size, initial_subtype, sym, off, buf);
8207 +static const char *
8208 +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8210 + expressionS *exp = ¤t_insn.immediate;
8213 + int initial_size, max_size;
8216 + initial_size = CALL_INITIAL_SIZE;
8228 + frag_grow(max_size);
8229 + buf = frag_more(initial_size);
8230 + dwarf2_emit_insn(initial_size);
8232 + frag_now->tc_frag_data.relaxer = &avr32_call_relaxer;
8234 + if (exp->X_op == O_symbol)
8236 + sym = exp->X_add_symbol;
8237 + off = exp->X_add_number;
8241 + sym = make_expr_symbol(exp);
8247 + /* The relaxer will bump the refcount if necessary */
8248 + frag_now->tc_frag_data.pool
8249 + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8252 + frag_var(rs_machine_dependent, max_size - initial_size,
8253 + initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf);
8261 + unsigned long flags = 0;
8264 + avr32_mnemonic_htab = hash_new();
8266 + if (!avr32_mnemonic_htab)
8267 + as_fatal(_("virtual memory exhausted"));
8269 + for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8271 + hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name,
8272 + (void *)&avr32_mnemonic_table[i]);
8276 + flags |= EF_AVR32_LINKRELAX;
8278 + flags |= EF_AVR32_PIC;
8280 + bfd_set_private_flags(stdoutput, flags);
8282 +#ifdef OPC_CONSISTENCY_CHECK
8283 + if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0])
8284 + < AVR32_NR_OPERANDS)
8285 + as_fatal(_("operand table is incomplete"));
8287 + for (i = 0; i < AVR32_NR_OPERANDS; i++)
8288 + if (avr32_operand_table[i].id != i)
8289 + as_fatal(_("operand table inconsistency found at index %d\n"), i);
8290 + pr_debug("%d operands verified\n", AVR32_NR_OPERANDS);
8292 + for (i = 0; i < AVR32_NR_IFIELDS; i++)
8293 + if (avr32_ifield_table[i].id != i)
8294 + as_fatal(_("ifield table inconsistency found at index %d\n"), i);
8295 + pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS);
8297 + for (i = 0; i < AVR32_NR_OPCODES; i++)
8299 + if (avr32_opc_table[i].id != i)
8300 + as_fatal(_("opcode table inconsistency found at index %d\n"), i);
8301 + if ((avr32_opc_table[i].var_field == -1
8302 + && avr32_relax_table[i].length != 0)
8303 + || (avr32_opc_table[i].var_field != -1
8304 + && avr32_relax_table[i].length == 0))
8305 + as_fatal(_("relax table inconsistency found at index %d\n"), i);
8307 + pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES);
8309 + for (i = 0; i < AVR32_NR_SYNTAX; i++)
8310 + if (avr32_syntax_table[i].id != i)
8311 + as_fatal(_("syntax table inconsistency found at index %d\n"), i);
8312 + pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX);
8314 + for (i = 0; i < AVR32_NR_ALIAS; i++)
8315 + if (avr32_alias_table[i].id != i)
8316 + as_fatal(_("alias table inconsistency found at index %d\n"), i);
8317 + pr_debug("%d aliases verified\n", AVR32_NR_ALIAS);
8319 + for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8320 + if (avr32_mnemonic_table[i].id != i)
8321 + as_fatal(_("mnemonic table inconsistency found at index %d\n"), i);
8322 + pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS);
8327 +md_assemble (char *str)
8329 + struct avr32_mnemonic *mnemonic;
8332 + memset(¤t_insn, 0, sizeof(current_insn));
8333 + current_insn.immediate.X_op = O_constant;
8335 + skip_whitespace(str);
8336 + for (p = str; *p; p++)
8342 + mnemonic = hash_find(avr32_mnemonic_htab, str);
8348 + const struct avr32_syntax *syntax;
8350 + for (syntax = mnemonic->syntax; syntax; syntax = syntax->next)
8352 + const char *errmsg = NULL;
8354 + if (syntax_matches(syntax, p))
8356 + if (!(syntax->isa_flags & avr32_arch->isa_flags))
8358 + as_bad(_("Selected architecture `%s' does not support `%s'"),
8359 + avr32_arch->name, str);
8363 + current_insn.syntax = syntax;
8364 + parse_operands(p);
8366 + switch (syntax->type)
8368 + case AVR32_PARSER_NORMAL:
8369 + errmsg = finish_insn(syntax->u.opc);
8371 + case AVR32_PARSER_ALIAS:
8372 + errmsg = finish_alias(syntax->u.alias);
8374 + case AVR32_PARSER_LDA:
8375 + errmsg = finish_lda(syntax);
8377 + case AVR32_PARSER_CALL:
8378 + errmsg = finish_call(syntax);
8381 + BAD_CASE(syntax->type);
8386 + as_bad("%s in `%s'", errmsg, str);
8392 + as_bad(_("unrecognized form of instruction: `%s'"), str);
8395 + as_bad(_("unrecognized instruction `%s'"), str);
8398 +void avr32_cleanup(void)
8400 + struct cpool *pool;
8402 + /* Emit any constant pools that haven't been explicitly flushed with
8403 + a .cpool directive. */
8404 + for (pool = cpool_list; pool; pool = pool->next)
8406 + subseg_set(pool->section, pool->sub_section);
8411 +/* Handle any PIC-related operands in data allocation pseudo-ops */
8413 +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
8415 + bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
8418 + pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n",
8419 + frag->fr_file, frag->fr_line,
8420 + exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)",
8421 + exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)",
8422 + exp->X_op, exp->X_add_number);
8424 + if (exp->X_op == O_subtract && exp->X_op_symbol)
8426 + if (exp->X_op_symbol == GOT_symbol)
8430 + r_type = BFD_RELOC_AVR32_GOTPC;
8431 + exp->X_op = O_symbol;
8432 + exp->X_op_symbol = NULL;
8435 + else if (exp->X_op == O_got)
8440 + r_type = BFD_RELOC_AVR32_GOT8;
8443 + r_type = BFD_RELOC_AVR32_GOT16;
8446 + r_type = BFD_RELOC_AVR32_GOT32;
8452 + exp->X_op = O_symbol;
8455 + if (r_type == BFD_RELOC_UNUSED)
8459 + r_type = BFD_RELOC_8;
8462 + r_type = BFD_RELOC_16;
8465 + r_type = BFD_RELOC_32;
8470 + else if (size != 4)
8473 + as_bad(_("unsupported BFD relocation size %u"), size);
8474 + r_type = BFD_RELOC_UNUSED;
8477 + fix_new_exp (frag, off, size, exp, pcrel, r_type);
8481 +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec,
8482 + void *ignore ATTRIBUTE_UNUSED)
8484 + segment_info_type *seginfo;
8487 + seginfo = seg_info(sec);
8491 + for (fix = seginfo->fix_root; fix; fix = fix->fx_next)
8496 + if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5
8497 + && fix->fx_addsy && fix->fx_subsy)
8499 + if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy)
8504 + fprintf(stderr, "Swapping symbols in fixup:\n");
8507 + tmp = fix->fx_addsy;
8508 + fix->fx_addsy = fix->fx_subsy;
8509 + fix->fx_subsy = tmp;
8510 + fix->fx_offset = -fix->fx_offset;
8516 +/* We need to look for SUB5 instructions with expressions that will be
8517 + made PC-relative and switch fx_addsy with fx_subsy. This has to be
8518 + done before adjustment or the wrong symbol might be adjusted.
8520 + This applies to fixups that are a result of expressions like -(sym
8521 + - .) and that will make it all the way to md_apply_fix3(). LDA
8522 + does the right thing in convert_frag, so we must not convert
8525 +avr32_frob_file(void)
8527 + /* if (1 || !linkrelax)
8530 + bfd_map_over_sections(stdoutput, avr32_frob_section, NULL);
8534 +convert_to_diff_reloc(fixS *fixP)
8536 + switch (fixP->fx_r_type)
8538 + case BFD_RELOC_32:
8539 + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8541 + case BFD_RELOC_16:
8542 + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16;
8545 + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8;
8554 +/* Simplify a fixup. If possible, the fixup is reduced to a single
8555 + constant which is written to the output file. Otherwise, a
8556 + relocation is generated so that the linker can take care of the
8559 + ELF relocations have certain constraints: They can only take a
8560 + single symbol and a single addend. This means that for difference
8561 + expressions, we _must_ get rid of the fx_subsy symbol somehow.
8563 + The difference between two labels in the same section can be
8564 + calculated directly unless 'linkrelax' is set, or a relocation is
8565 + forced. If so, we must emit a R_AVR32_DIFFxx relocation. If there
8566 + are addends involved at this point, we must be especially careful
8567 + as the relocation must point exactly to the symbol being
8570 + When subtracting a symbol defined in the same section as the fixup,
8571 + we might be able to convert it to a PC-relative expression, unless
8572 + linkrelax is set. If this is the case, there's no way we can make
8573 + sure that the difference between the fixup and fx_subsy stays
8574 + constant. So for now, we're just going to disallow that.
8577 +avr32_process_fixup(fixS *fixP, segT this_segment)
8579 + segT add_symbol_segment = absolute_section;
8580 + segT sub_symbol_segment = absolute_section;
8581 + symbolS *fx_addsy, *fx_subsy;
8582 + offsetT value = 0, fx_offset;
8583 + bfd_boolean apply = FALSE;
8585 + assert(this_segment != absolute_section);
8587 + if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8589 + as_bad_where(fixP->fx_file, fixP->fx_line,
8590 + _("Bad relocation type %d\n"), fixP->fx_r_type);
8594 + /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */
8595 + fx_addsy = fixP->fx_addsy;
8596 + fx_subsy = fixP->fx_subsy;
8597 + fx_offset = fixP->fx_offset;
8600 + add_symbol_segment = S_GET_SEGMENT(fx_addsy);
8604 + resolve_symbol_value(fx_subsy);
8605 + sub_symbol_segment = S_GET_SEGMENT(fx_subsy);
8607 + if (sub_symbol_segment == this_segment
8609 + || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address
8610 + + fixP->fx_where)))
8612 + fixP->fx_pcrel = TRUE;
8613 + fx_offset += (fixP->fx_frag->fr_address + fixP->fx_where
8614 + - S_GET_VALUE(fx_subsy));
8617 + else if (sub_symbol_segment == absolute_section)
8619 + /* The symbol is really a constant. */
8620 + fx_offset -= S_GET_VALUE(fx_subsy);
8623 + else if (SEG_NORMAL(add_symbol_segment)
8624 + && sub_symbol_segment == add_symbol_segment
8625 + && (!linkrelax || convert_to_diff_reloc(fixP)))
8627 + /* Difference between two labels in the same section. */
8630 + /* convert_to_diff() has ensured that the reloc type is
8631 + either DIFF32, DIFF16 or DIFF8. */
8632 + value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset
8633 + - S_GET_VALUE(fx_subsy));
8635 + /* Try to convert it to a section symbol if possible */
8636 + if (!S_FORCE_RELOC(fx_addsy, 1)
8637 + && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL))
8639 + fx_offset = S_GET_VALUE(fx_subsy);
8640 + fx_addsy = section_symbol(sub_symbol_segment);
8644 + fx_addsy = fx_subsy;
8653 + fx_offset += S_GET_VALUE(fx_addsy);
8654 + fx_offset -= S_GET_VALUE(fx_subsy);
8661 + as_bad_where(fixP->fx_file, fixP->fx_line,
8662 + _("can't resolve `%s' {%s section} - `%s' {%s section}"),
8663 + fx_addsy ? S_GET_NAME (fx_addsy) : "0",
8664 + segment_name (add_symbol_segment),
8665 + S_GET_NAME (fx_subsy),
8666 + segment_name (sub_symbol_segment));
8671 + if (fx_addsy && !TC_FORCE_RELOCATION(fixP))
8673 + if (add_symbol_segment == this_segment
8674 + && fixP->fx_pcrel)
8676 + value += S_GET_VALUE(fx_addsy);
8677 + value -= md_pcrel_from_section(fixP, this_segment);
8679 + fixP->fx_pcrel = FALSE;
8681 + else if (add_symbol_segment == absolute_section)
8683 + fx_offset += S_GET_VALUE(fixP->fx_addsy);
8689 + fixP->fx_done = TRUE;
8691 + if (fixP->fx_pcrel)
8693 + if (fx_addsy != NULL
8694 + && S_IS_DEFINED(fx_addsy)
8695 + && S_GET_SEGMENT(fx_addsy) != this_segment)
8696 + value += md_pcrel_from_section(fixP, this_segment);
8698 + switch (fixP->fx_r_type)
8700 + case BFD_RELOC_32:
8701 + fixP->fx_r_type = BFD_RELOC_32_PCREL;
8703 + case BFD_RELOC_16:
8704 + fixP->fx_r_type = BFD_RELOC_16_PCREL;
8707 + fixP->fx_r_type = BFD_RELOC_8_PCREL;
8709 + case BFD_RELOC_AVR32_SUB5:
8710 + fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL;
8712 + case BFD_RELOC_AVR32_16S:
8713 + fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL;
8715 + case BFD_RELOC_AVR32_14UW:
8716 + fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL;
8718 + case BFD_RELOC_AVR32_10UW:
8719 + fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL;
8722 + /* Should have been taken care of already */
8727 + if (fixP->fx_done || apply)
8729 + const struct avr32_ifield *ifield;
8730 + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8732 + if (fixP->fx_done)
8733 + value += fx_offset;
8735 + /* For hosts with longs bigger than 32-bits make sure that the top
8736 + bits of a 32-bit negative value read in by the parser are set,
8737 + so that the correct comparisons are made. */
8738 + if (value & 0x80000000)
8739 + value |= (-1L << 31);
8741 + switch (fixP->fx_r_type)
8743 + case BFD_RELOC_32:
8744 + case BFD_RELOC_16:
8746 + case BFD_RELOC_AVR32_DIFF32:
8747 + case BFD_RELOC_AVR32_DIFF16:
8748 + case BFD_RELOC_AVR32_DIFF8:
8749 + md_number_to_chars(buf, value, fixP->fx_size);
8751 + case BFD_RELOC_HI16:
8753 + case BFD_RELOC_LO16:
8755 + md_number_to_chars(buf + 2, value, 2);
8757 + case BFD_RELOC_AVR32_16N_PCREL:
8759 + /* fall through */
8760 + case BFD_RELOC_AVR32_22H_PCREL:
8761 + case BFD_RELOC_AVR32_18W_PCREL:
8762 + case BFD_RELOC_AVR32_16B_PCREL:
8763 + case BFD_RELOC_AVR32_11H_PCREL:
8764 + case BFD_RELOC_AVR32_9H_PCREL:
8765 + case BFD_RELOC_AVR32_9UW_PCREL:
8766 + case BFD_RELOC_AVR32_3U:
8767 + case BFD_RELOC_AVR32_4UH:
8768 + case BFD_RELOC_AVR32_6UW:
8769 + case BFD_RELOC_AVR32_6S:
8770 + case BFD_RELOC_AVR32_7UW:
8771 + case BFD_RELOC_AVR32_8S_EXT:
8772 + case BFD_RELOC_AVR32_8S:
8773 + case BFD_RELOC_AVR32_10UW:
8774 + case BFD_RELOC_AVR32_10SW:
8775 + case BFD_RELOC_AVR32_STHH_W:
8776 + case BFD_RELOC_AVR32_14UW:
8777 + case BFD_RELOC_AVR32_16S:
8778 + case BFD_RELOC_AVR32_16U:
8779 + case BFD_RELOC_AVR32_21S:
8780 + case BFD_RELOC_AVR32_SUB5:
8781 + case BFD_RELOC_AVR32_CPCALL:
8782 + case BFD_RELOC_AVR32_16_CP:
8783 + case BFD_RELOC_AVR32_9W_CP:
8784 + case BFD_RELOC_AVR32_15S:
8785 + ifield = fixP->tc_fix_data.ifield;
8786 + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8787 + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8788 + fixP->tc_fix_data.align);
8789 + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8790 + as_bad_where(fixP->fx_file, fixP->fx_line,
8791 + _("operand out of range (%ld not between %ld and %ld)"),
8792 + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8793 + if (value & ((1 << fixP->tc_fix_data.align) - 1))
8794 + as_bad_where(fixP->fx_file, fixP->fx_line,
8795 + _("misaligned operand (required alignment: %d)"),
8796 + 1 << fixP->tc_fix_data.align);
8797 + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8799 + case BFD_RELOC_AVR32_ALIGN:
8800 + /* Nothing to do */
8801 + fixP->fx_done = FALSE;
8804 + as_fatal("reloc type %s not handled\n",
8805 + bfd_get_reloc_code_name(fixP->fx_r_type));
8809 + fixP->fx_addsy = fx_addsy;
8810 + fixP->fx_subsy = fx_subsy;
8811 + fixP->fx_offset = fx_offset;
8813 + if (!fixP->fx_done)
8815 + if (!fixP->fx_addsy)
8816 + fixP->fx_addsy = abs_section_sym;
8818 + symbol_mark_used_in_reloc(fixP->fx_addsy);
8819 + if (fixP->fx_subsy)
8826 +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
8828 + const struct avr32_ifield *ifield;
8829 + offsetT value = *valP;
8830 + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8831 + bfd_boolean apply;
8833 + pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n",
8834 + fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP,
8837 + if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8839 + as_bad_where(fixP->fx_file, fixP->fx_line,
8840 + _("Bad relocation type %d\n"), fixP->fx_r_type);
8844 + if (!fixP->fx_addsy && !fixP->fx_subsy)
8845 + fixP->fx_done = 1;
8847 + if (fixP->fx_pcrel)
8849 + if (fixP->fx_addsy != NULL
8850 + && S_IS_DEFINED(fixP->fx_addsy)
8851 + && S_GET_SEGMENT(fixP->fx_addsy) != seg)
8852 + value += md_pcrel_from_section(fixP, seg);
8854 + switch (fixP->fx_r_type)
8856 + case BFD_RELOC_32:
8857 + fixP->fx_r_type = BFD_RELOC_32_PCREL;
8859 + case BFD_RELOC_16:
8861 + as_bad_where (fixP->fx_file, fixP->fx_line,
8862 + _("8- and 16-bit PC-relative relocations not supported"));
8864 + case BFD_RELOC_AVR32_SUB5:
8865 + fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5;
8867 + case BFD_RELOC_AVR32_16S:
8868 + fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL;
8871 + /* Should have been taken care of already */
8876 + if (fixP->fx_r_type == BFD_RELOC_32
8877 + && fixP->fx_subsy)
8879 + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8881 + /* Offsets are only allowed if it's a result of adjusting a
8882 + local symbol into a section-relative offset.
8883 + tc_fix_adjustable() should prevent any adjustment if there
8884 + was an offset involved before. */
8885 + if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy))
8886 + as_bad_where(fixP->fx_file, fixP->fx_line,
8887 + _("cannot represent symbol difference with an offset"));
8889 + value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset
8890 + - S_GET_VALUE(fixP->fx_subsy));
8892 + /* The difference before any relaxing takes place is written
8893 + out, and the DIFF32 reloc identifies the address of the first
8894 + symbol (i.e. the on that's subtracted.) */
8896 + fixP->fx_offset -= value;
8897 + fixP->fx_subsy = NULL;
8899 + md_number_to_chars(buf, value, fixP->fx_size);
8902 + if (fixP->fx_done)
8904 + switch (fixP->fx_r_type)
8907 + case BFD_RELOC_16:
8908 + case BFD_RELOC_32:
8909 + md_number_to_chars(buf, value, fixP->fx_size);
8911 + case BFD_RELOC_HI16:
8913 + case BFD_RELOC_LO16:
8916 + md_number_to_chars(buf + 2, value, 2);
8918 + case BFD_RELOC_AVR32_PCREL_SUB5:
8920 + /* fall through */
8921 + case BFD_RELOC_AVR32_9_PCREL:
8922 + case BFD_RELOC_AVR32_11_PCREL:
8923 + case BFD_RELOC_AVR32_16_PCREL:
8924 + case BFD_RELOC_AVR32_18_PCREL:
8925 + case BFD_RELOC_AVR32_22_PCREL:
8926 + case BFD_RELOC_AVR32_3U:
8927 + case BFD_RELOC_AVR32_4UH:
8928 + case BFD_RELOC_AVR32_6UW:
8929 + case BFD_RELOC_AVR32_6S:
8930 + case BFD_RELOC_AVR32_7UW:
8931 + case BFD_RELOC_AVR32_8S:
8932 + case BFD_RELOC_AVR32_10UW:
8933 + case BFD_RELOC_AVR32_10SW:
8934 + case BFD_RELOC_AVR32_14UW:
8935 + case BFD_RELOC_AVR32_16S:
8936 + case BFD_RELOC_AVR32_16U:
8937 + case BFD_RELOC_AVR32_21S:
8938 + case BFD_RELOC_AVR32_BRC1:
8939 + case BFD_RELOC_AVR32_SUB5:
8940 + case BFD_RELOC_AVR32_CPCALL:
8941 + case BFD_RELOC_AVR32_16_CP:
8942 + case BFD_RELOC_AVR32_9_CP:
8943 + case BFD_RELOC_AVR32_15S:
8944 + ifield = fixP->tc_fix_data.ifield;
8945 + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8946 + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8947 + fixP->tc_fix_data.align);
8948 + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8949 + as_bad_where(fixP->fx_file, fixP->fx_line,
8950 + _("operand out of range (%ld not between %ld and %ld)"),
8951 + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8952 + if (value & ((1 << fixP->tc_fix_data.align) - 1))
8953 + as_bad_where(fixP->fx_file, fixP->fx_line,
8954 + _("misaligned operand (required alignment: %d)"),
8955 + 1 << fixP->tc_fix_data.align);
8956 + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8958 + case BFD_RELOC_AVR32_ALIGN:
8959 + /* Nothing to do */
8960 + fixP->fx_done = FALSE;
8963 + as_fatal("reloc type %s not handled\n",
8964 + bfd_get_reloc_code_name(fixP->fx_r_type));
8971 +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
8975 + bfd_reloc_code_real_type code;
8977 + reloc = xmalloc (sizeof (arelent));
8979 + reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
8980 + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8981 + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
8982 + reloc->addend = fixp->fx_offset;
8983 + code = fixp->fx_r_type;
8985 + reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
8987 + if (reloc->howto == NULL)
8989 + as_bad_where (fixp->fx_file, fixp->fx_line,
8990 + _("cannot represent relocation %s in this object file format"),
8991 + bfd_get_reloc_code_name (code));
8999 +avr32_force_reloc(fixS *fixP)
9001 + if (linkrelax && fixP->fx_addsy
9002 + && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING)
9003 + && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section)
9005 + pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n",
9006 + fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name);
9010 + return generic_force_reloc(fixP);
9014 +avr32_fix_adjustable(fixS *fixP)
9016 + switch (fixP->fx_r_type)
9018 + /* GOT relocations can't have addends since BFD treats all
9019 + references to a given symbol the same. This means that we
9020 + must avoid section-relative references to local symbols when
9021 + dealing with these kinds of relocs */
9022 + case BFD_RELOC_AVR32_GOT32:
9023 + case BFD_RELOC_AVR32_GOT16:
9024 + case BFD_RELOC_AVR32_GOT8:
9025 + case BFD_RELOC_AVR32_GOT21S:
9026 + case BFD_RELOC_AVR32_GOT18SW:
9027 + case BFD_RELOC_AVR32_GOT16S:
9028 + case BFD_RELOC_AVR32_LDA_GOT:
9029 + case BFD_RELOC_AVR32_GOTCALL:
9030 + pr_debug("fix not adjustable\n");
9040 +/* When we want the linker to be able to relax the code, we need to
9041 + output a reloc for every .align directive requesting an alignment
9042 + to a four byte boundary or larger. If we don't do this, the linker
9043 + can't guarantee that the alignment is actually maintained in the
9046 + TODO: Might as well insert proper NOPs while we're at it... */
9048 +avr32_handle_align(fragS *frag)
9051 + && frag->fr_type == rs_align_code
9052 + && frag->fr_address + frag->fr_fix > 0
9053 + && frag->fr_offset > 0)
9055 + /* The alignment order (fr_offset) is stored in the addend. */
9056 + fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset,
9057 + FALSE, BFD_RELOC_AVR32_ALIGN);
9061 +/* Relax_align. Advance location counter to next address that has 'alignment'
9062 + lowest order bits all 0s, return size of adjustment made. */
9064 +avr32_relax_align(segT segment ATTRIBUTE_UNUSED,
9066 + relax_addressT address)
9068 + relax_addressT mask;
9069 + relax_addressT new_address;
9072 + alignment = fragP->fr_offset;
9073 + mask = ~((~0) << alignment);
9074 + new_address = (address + mask) & (~mask);
9076 + return new_address - address;
9079 +/* Turn a string in input_line_pointer into a floating point constant
9080 + of type type, and store the appropriate bytes in *litP. The number
9081 + of LITTLENUMS emitted is stored in *sizeP . An error message is
9082 + returned, or NULL on OK. */
9084 +/* Equal to MAX_PRECISION in atof-ieee.c */
9085 +#define MAX_LITTLENUMS 6
9088 +md_atof (type, litP, sizeP)
9095 + LITTLENUM_TYPE words [MAX_LITTLENUMS];
9114 + /* FIXME: Some targets allow other format chars for bigger sizes here. */
9118 + return _("Bad call to md_atof()");
9121 + t = atof_ieee (input_line_pointer, type, words);
9123 + input_line_pointer = t;
9124 + * sizeP = prec * sizeof (LITTLENUM_TYPE);
9126 + for (i = 0; i < prec; i++)
9128 + md_number_to_chars (litP, (valueT) words[i],
9129 + sizeof (LITTLENUM_TYPE));
9130 + litP += sizeof (LITTLENUM_TYPE);
9136 +static char *avr32_end_of_match(char *cont, char *what)
9138 + int len = strlen (what);
9140 + if (! is_part_of_name (cont[len])
9141 + && strncasecmp (cont, what, len) == 0)
9142 + return cont + len;
9148 +avr32_parse_name (char const *name, expressionS *exp, char *nextchar)
9150 + char *next = input_line_pointer;
9153 + pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar);
9155 + if (*nextchar == '(')
9157 + if (strcasecmp(name, "hi") == 0)
9159 + *next = *nextchar;
9163 + if (exp->X_op == O_constant)
9165 + pr_debug(" -> constant hi(0x%08lx) -> 0x%04lx\n",
9166 + exp->X_add_number, exp->X_add_number >> 16);
9167 + exp->X_add_number = (exp->X_add_number >> 16) & 0xffff;
9171 + exp->X_md = exp->X_op;
9177 + else if (strcasecmp(name, "lo") == 0)
9179 + *next = *nextchar;
9183 + if (exp->X_op == O_constant)
9184 + exp->X_add_number &= 0xffff;
9187 + exp->X_md = exp->X_op;
9194 + else if (*nextchar == '@')
9196 + exp->X_md = exp->X_op;
9198 + if ((next_end = avr32_end_of_match (next + 1, "got")))
9199 + exp->X_op = O_got;
9200 + else if ((next_end = avr32_end_of_match (next + 1, "tlsgd")))
9201 + exp->X_op = O_tlsgd;
9202 + /* Add more as needed */
9206 + input_line_pointer++;
9207 + c = get_symbol_end();
9208 + as_bad (_("unknown relocation override `%s'"), next + 1);
9209 + *input_line_pointer = c;
9210 + input_line_pointer = next;
9214 + exp->X_op_symbol = NULL;
9215 + exp->X_add_symbol = symbol_find_or_make (name);
9216 + exp->X_add_number = 0;
9218 + *input_line_pointer = *nextchar;
9219 + input_line_pointer = next_end;
9220 + *nextchar = *input_line_pointer;
9221 + *input_line_pointer = '\0';
9224 + else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
9227 + GOT_symbol = symbol_find_or_make(name);
9229 + exp->X_add_symbol = GOT_symbol;
9230 + exp->X_op = O_symbol;
9231 + exp->X_add_number = 0;
9239 +s_rseg (int value ATTRIBUTE_UNUSED)
9241 + /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)]
9243 + * - type: undocumented ("typically CODE or DATA")
9245 + * - align: 1 for code, 0 for others
9247 + * TODO: NOROOT is ignored. If gas supports discardable segments, it should
9251 + int length, type, attr;
9254 + SKIP_WHITESPACE();
9256 + end = input_line_pointer;
9257 + while (0 == strchr ("\n\t;:( ", *end))
9259 + if (end == input_line_pointer)
9261 + as_warn (_("missing name"));
9262 + ignore_rest_of_line();
9266 + name = xmalloc (end - input_line_pointer + 1);
9267 + memcpy (name, input_line_pointer, end - input_line_pointer);
9268 + name[end - input_line_pointer] = '\0';
9269 + input_line_pointer = end;
9271 + SKIP_WHITESPACE();
9276 + if (*input_line_pointer == ':')
9278 + /* Skip the colon */
9279 + ++input_line_pointer;
9280 + SKIP_WHITESPACE();
9282 + /* Possible options at this point:
9283 + * - flag (ROOT or NOROOT)
9284 + * - a segment type
9286 + end = input_line_pointer;
9287 + while (0 == strchr ("\n\t;:( ", *end))
9289 + length = end - input_line_pointer;
9290 + if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) ||
9291 + ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9293 + /* Ignore ROOT/NOROOT */
9294 + input_line_pointer = end;
9298 + /* Must be a segment type */
9299 + switch (*input_line_pointer)
9303 + if ((length == 4) &&
9304 + (0 == strncasecmp (input_line_pointer, "CODE", 4)))
9306 + attr |= SHF_ALLOC | SHF_EXECINSTR;
9307 + type = SHT_PROGBITS;
9311 + if ((length == 5) &&
9312 + (0 == strncasecmp (input_line_pointer, "CONST", 5)))
9314 + attr |= SHF_ALLOC;
9315 + type = SHT_PROGBITS;
9322 + if ((length == 4) &&
9323 + (0 == strncasecmp (input_line_pointer, "DATA", 4)))
9325 + attr |= SHF_ALLOC | SHF_WRITE;
9326 + type = SHT_PROGBITS;
9331 + /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */
9335 + if ((length == 7) &&
9336 + (0 == strncasecmp (input_line_pointer, "UNTYPED", 7)))
9340 + /* TODO: Add XDATA and ZPAGE if necessary */
9344 + as_warn (_("unrecognized segment type"));
9347 + input_line_pointer = end;
9348 + SKIP_WHITESPACE();
9350 + if (*input_line_pointer == ':')
9353 + ++input_line_pointer;
9354 + SKIP_WHITESPACE();
9356 + end = input_line_pointer;
9357 + while (0 == strchr ("\n\t;:( ", *end))
9359 + length = end - input_line_pointer;
9360 + if (! ((length == 4) &&
9361 + (0 == strncasecmp( input_line_pointer, "ROOT", 4))) &&
9362 + ! ((length == 6) &&
9363 + (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9365 + as_warn (_("unrecognized segment flag"));
9368 + input_line_pointer = end;
9369 + SKIP_WHITESPACE();
9374 + if (*input_line_pointer == '(')
9376 + align = get_absolute_expression ();
9379 + demand_empty_rest_of_line();
9381 + obj_elf_change_section (name, type, attr, 0, NULL, 0, 0);
9383 + fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n",
9384 + name, type, attr );
9385 + fprintf( stderr, "RSEG: Aligning to 2**%d\n", align );
9391 + as_warn (_("alignment too large: %u assumed"), align);
9394 + /* Hope not, that is */
9395 + assert (now_seg != absolute_section);
9397 + /* Only make a frag if we HAVE to... */
9398 + if (align != 0 && !need_pass_2)
9400 + if (subseg_text_p (now_seg))
9401 + frag_align_code (align, 0);
9403 + frag_align (align, 0, 0);
9406 + record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER);
9409 +/* vim: syntax=c sw=2
9412 +++ b/gas/config/tc-avr32.h
9414 +/* Assembler definitions for AVR32.
9415 + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
9417 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
9419 + This file is part of GAS, the GNU Assembler.
9421 + GAS is free software; you can redistribute it and/or modify it
9422 + under the terms of the GNU General Public License as published by
9423 + the Free Software Foundation; either version 2, or (at your option)
9424 + any later version.
9426 + GAS is distributed in the hope that it will be useful, but WITHOUT
9427 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9428 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
9429 + License for more details.
9431 + You should have received a copy of the GNU General Public License
9432 + along with GAS; see the file COPYING. If not, write to the Free
9433 + Software Foundation, 59 Temple Place - Suite 330, Boston, MA
9434 + 02111-1307, USA. */
9445 +/* Are we trying to be compatible with the IAR assembler? (--iar) */
9446 +extern int avr32_iarcompat;
9448 +/* By convention, you should define this macro in the `.h' file. For
9449 + example, `tc-m68k.h' defines `TC_M68K'. You might have to use this
9450 + if it is necessary to add CPU specific code to the object format
9454 +/* This macro is the BFD target name to use when creating the output
9455 + file. This will normally depend upon the `OBJ_FMT' macro. */
9456 +#define TARGET_FORMAT "elf32-avr32"
9458 +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'. */
9459 +#define TARGET_ARCH bfd_arch_avr32
9461 +/* This macro is the BFD machine number to pass to
9462 + `bfd_set_arch_mach'. If it is not defined, GAS will use 0. */
9463 +#define TARGET_MACH 0
9465 +/* UNDOCUMENTED: Allow //-style comments */
9466 +#define DOUBLESLASH_LINE_COMMENTS
9468 +/* You should define this macro to be non-zero if the target is big
9469 + endian, and zero if the target is little endian. */
9470 +#define TARGET_BYTES_BIG_ENDIAN 1
9472 +/* FIXME: It seems that GAS only expects a one-byte opcode...
9473 + #define NOP_OPCODE 0xd703 */
9475 +/* If you define this macro, GAS will warn about the use of
9476 + nonstandard escape sequences in a string. */
9477 +#undef ONLY_STANDARD_ESCAPES
9479 +#define DWARF2_FORMAT(SEC) dwarf2_format_32bit
9481 +/* Instructions are either 2 or 4 bytes long */
9482 +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */
9484 +/* GAS will call this function for any expression that can not be
9485 + recognized. When the function is called, `input_line_pointer'
9486 + will point to the start of the expression. */
9487 +#define md_operand(x)
9489 +#define md_parse_name(name, expr, mode, c) avr32_parse_name(name, expr, c)
9490 +extern int avr32_parse_name(const char *, struct expressionS *, char *);
9492 +/* You may define this macro to generate a fixup for a data
9493 + allocation pseudo-op. */
9494 +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
9495 + avr32_cons_fix_new(FRAG, OFF, LEN, EXP)
9496 +void avr32_cons_fix_new (fragS *, int, int, expressionS *);
9498 +/* `extsym - .' expressions can be emitted using PC-relative relocs */
9499 +#define DIFF_EXPR_OK
9501 +/* This is used to construct expressions out of @gotoff, etc. The
9502 + relocation type is stored in X_md */
9503 +#define O_got O_md1
9506 +#define O_tlsgd O_md4
9508 +/* You may define this macro to parse an expression used in a data
9509 + allocation pseudo-op such as `.word'. You can use this to
9510 + recognize relocation directives that may appear in such directives. */
9511 +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
9512 + void avr_parse_cons_expression (expressionS *exp, int nbytes); */
9514 +/* This should just call either `number_to_chars_bigendian' or
9515 + `number_to_chars_littleendian', whichever is appropriate. On
9516 + targets like the MIPS which support options to change the
9517 + endianness, which function to call is a runtime decision. On
9518 + other targets, `md_number_to_chars' can be a simple macro. */
9519 +#define md_number_to_chars number_to_chars_bigendian
9521 +/* `md_short_jump_size'
9522 + `md_long_jump_size'
9523 + `md_create_short_jump'
9524 + `md_create_long_jump'
9525 + If `WORKING_DOT_WORD' is defined, GAS will not do broken word
9526 + processing (*note Broken words::.). Otherwise, you should set
9527 + `md_short_jump_size' to the size of a short jump (a jump that is
9528 + just long enough to jump around a long jmp) and
9529 + `md_long_jump_size' to the size of a long jump (a jump that can go
9530 + anywhere in the function), You should define
9531 + `md_create_short_jump' to create a short jump around a long jump,
9532 + and define `md_create_long_jump' to create a long jump. */
9533 +#define WORKING_DOT_WORD
9535 +/* If you define this macro, it means that `tc_gen_reloc' may return
9536 + multiple relocation entries for a single fixup. In this case, the
9537 + return value of `tc_gen_reloc' is a pointer to a null terminated
9539 +#undef RELOC_EXPANSION_POSSIBLE
9541 +/* If you define this macro, GAS will not require pseudo-ops to start with a .
9543 +#define NO_PSEUDO_DOT (avr32_iarcompat)
9545 +/* The IAR assembler uses $ as the location counter. Unfortunately, we
9546 + can't make this dependent on avr32_iarcompat... */
9549 +/* Values passed to md_apply_fix3 don't include the symbol value. */
9550 +#define MD_APPLY_SYM_VALUE(FIX) 0
9552 +/* The number of bytes to put into a word in a listing. This affects
9553 + the way the bytes are clumped together in the listing. For
9554 + example, a value of 2 might print `1234 5678' where a value of 1
9555 + would print `12 34 56 78'. The default value is 4. */
9556 +#define LISTING_WORD_SIZE 4
9558 +/* extern const struct relax_type md_relax_table[];
9559 +#define TC_GENERIC_RELAX_TABLE md_relax_table */
9562 + An `.lcomm' directive with no explicit alignment parameter will use
9563 + this macro to set P2VAR to the alignment that a request for SIZE
9564 + bytes will have. The alignment is expressed as a power of two. If
9565 + no alignment should take place, the macro definition should do
9566 + nothing. Some targets define a `.bss' directive that is also
9567 + affected by this macro. The default definition will set P2VAR to
9568 + the truncated power of two of sizes up to eight bytes.
9570 + We want doublewords to be word-aligned, so we're going to modify the
9571 + default definition a tiny bit.
9573 +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) \
9576 + if ((SIZE) >= 4) \
9578 + else if ((SIZE) >= 2) \
9585 +/* When relaxing, we need to generate relocations for alignment
9587 +#define HANDLE_ALIGN(frag) avr32_handle_align(frag)
9588 +extern void avr32_handle_align(fragS *);
9590 +/* See internals doc for explanation. Oh wait...
9591 + Now, can you guess where "alignment" comes from? ;-) */
9592 +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1)
9594 +/* We need to stop gas from reducing certain expressions (e.g. GOT
9596 +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix)
9597 +extern bfd_boolean avr32_fix_adjustable(struct fix *);
9599 +/* The linker needs to be passed a little more information when relaxing. */
9600 +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix)
9601 +extern bfd_boolean avr32_force_reloc(struct fix *);
9603 +/* I'm tired of working around all the madness in fixup_segment().
9604 + This hook will do basically the same things as the generic code,
9605 + and then it will "goto" right past it. */
9606 +#define TC_VALIDATE_FIX(FIX, SEG, SKIP) \
9609 + avr32_process_fixup(FIX, SEG); \
9610 + if (!(FIX)->fx_done) \
9611 + ++seg_reloc_count; \
9615 +extern void avr32_process_fixup(struct fix *fixP, segT this_segment);
9617 +/* Positive values of TC_FX_SIZE_SLACK allow a target to define
9618 + fixups that far past the end of a frag. Having such fixups
9619 + is of course most most likely a bug in setting fx_size correctly.
9620 + A negative value disables the fixup check entirely, which is
9621 + appropriate for something like the Renesas / SuperH SH_COUNT
9623 +/* This target is buggy, and sets fix size too large. */
9624 +#define TC_FX_SIZE_SLACK(FIX) -1
9626 +/* We don't want the gas core to make any assumptions about our way of
9627 + doing linkrelaxing. */
9628 +#define TC_LINKRELAX_FIXUP(SEG) 0
9630 +/* ... but we do want it to insert lots of padding. */
9631 +#define LINKER_RELAXING_SHRINKS_ONLY
9633 +/* Better do it ourselves, really... */
9634 +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR) avr32_relax_align(SEG, FRAG, ADDR)
9635 +extern relax_addressT
9636 +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address);
9638 +/* Use line number format that is amenable to linker relaxation. */
9639 +#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
9641 +/* This is called by write_object_file() just before symbols are
9642 + attempted converted into section symbols. */
9643 +#define tc_frob_file_before_adjust() avr32_frob_file()
9644 +extern void avr32_frob_file(void);
9646 +/* If you define this macro, GAS will call it at the end of each input
9648 +#define md_cleanup() avr32_cleanup()
9649 +extern void avr32_cleanup(void);
9651 +/* There's an AVR32-specific hack in operand() which creates O_md
9652 + expressions when encountering HWRD or LWRD. We need to generate
9653 + proper relocs for them */
9654 +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */
9656 +/* I needed to add an extra hook in gas_cgen_finish_insn() for
9657 + conversion of O_md* operands because md_cgen_record_fixup_exp()
9658 + isn't called for relaxable insns */
9659 +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo)
9660 + int avr32_cgen_convert_expr(expressionS *, int); */
9662 +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
9664 +/* If you define this macro, it should return the position from which
9665 + the PC relative adjustment for a PC relative fixup should be
9666 + made. On many processors, the base of a PC relative instruction is
9667 + the next instruction, so this macro would return the length of an
9668 + instruction, plus the address of the PC relative fixup. The latter
9669 + can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */
9670 +extern long md_pcrel_from_section (struct fix *, segT);
9671 +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
9673 +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
9674 +#define LOCAL_LABELS_FB 1
9676 +struct avr32_relaxer
9678 + int (*estimate_size)(fragS *, segT);
9679 + long (*relax_frag)(segT, fragS *, long);
9680 + void (*convert_frag)(bfd *, segT, fragS *);
9683 +/* AVR32 has quite complex instruction coding, which means we need
9684 + * lots of information in order to do the right thing during relaxing
9685 + * (basically, we need to be able to reconstruct a whole new opcode if
9687 +#define TC_FRAG_TYPE struct avr32_frag_data
9691 +struct avr32_frag_data
9693 + /* TODO: Maybe add an expression object here so that we can use
9694 + fix_new_exp() in md_convert_frag? We may have to decide
9695 + pcrel-ness in md_estimate_size_before_relax() as well...or we
9696 + might do it when parsing. Doing it while parsing may fail
9697 + because the sub_symbol is undefined then... */
9699 + int force_extended;
9701 + struct avr32_relaxer *relaxer;
9704 + /* Points to associated constant pool, for use by LDA and CALL in
9705 + non-pic mode, and when relaxing the .cpool directive */
9706 + struct cpool *pool;
9707 + unsigned int pool_entry;
9710 +/* We will have to initialize the fields explicitly when needed */
9711 +#define TC_FRAG_INIT(fragP)
9713 +#define md_estimate_size_before_relax(fragP, segT) \
9714 + ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT))
9715 +#define md_relax_frag(segment, fragP, stretch) \
9716 + ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch))
9717 +#define md_convert_frag(abfd, segment, fragP) \
9718 + ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP))
9720 +#define TC_FIX_TYPE struct avr32_fix_data
9722 +struct avr32_fix_data
9724 + const struct avr32_ifield *ifield;
9725 + unsigned int align;
9730 +#define TC_INIT_FIX_DATA(fixP) \
9733 + (fixP)->tc_fix_data.ifield = NULL; \
9734 + (fixP)->tc_fix_data.align = 0; \
9735 + (fixP)->tc_fix_data.min = 0; \
9736 + (fixP)->tc_fix_data.max = 0; \
9739 --- a/gas/configure.tgt
9740 +++ b/gas/configure.tgt
9741 @@ -33,6 +33,7 @@ case ${cpu} in
9742 am33_2.0) cpu_type=mn10300 endian=little ;;
9743 arm*be|arm*b) cpu_type=arm endian=big ;;
9744 arm*) cpu_type=arm endian=little ;;
9745 + avr32*) cpu_type=avr32 endian=big ;;
9746 bfin*) cpu_type=bfin endian=little ;;
9747 c4x*) cpu_type=tic4x ;;
9748 cr16*) cpu_type=cr16 endian=little ;;
9749 @@ -136,6 +137,9 @@ case ${generic_target} in
9751 cr16-*-elf*) fmt=elf ;;
9753 + avr32-*-linux*) fmt=elf em=linux bfd_gas=yes ;;
9754 + avr32*) fmt=elf bfd_gas=yes ;;
9756 cris-*-linux-* | crisv32-*-linux-*)
9757 fmt=multi em=linux ;;
9758 cris-*-* | crisv32-*-*) fmt=multi ;;
9759 --- a/gas/doc/all.texi
9760 +++ b/gas/doc/all.texi
9769 --- a/gas/doc/asconfig.texi
9770 +++ b/gas/doc/asconfig.texi
9779 --- a/gas/doc/as.texinfo
9780 +++ b/gas/doc/as.texinfo
9781 @@ -6865,6 +6865,9 @@ subject, see the hardware manufacturer's
9783 * AVR-Dependent:: AVR Dependent Features
9786 +* AVR32-Dependent:: AVR32 Dependent Features
9789 * Blackfin-Dependent:: Blackfin Dependent Features
9791 @@ -7006,6 +7009,10 @@ subject, see the hardware manufacturer's
9796 +@include c-avr32.texi
9800 @include c-bfin.texi
9803 +++ b/gas/doc/c-avr32.texi
9805 +@c Copyright 2005, 2006, 2007, 2008, 2009
9806 +@c Atmel Corporation
9807 +@c This is part of the GAS manual.
9808 +@c For copying conditions, see the file as.texinfo.
9812 +@node AVR32-Dependent
9813 +@chapter AVR32 Dependent Features
9817 +@node Machine Dependencies
9818 +@chapter AVR32 Dependent Features
9821 +@cindex AVR32 support
9823 +* AVR32 Options:: Options
9824 +* AVR32 Syntax:: Syntax
9825 +* AVR32 Directives:: Directives
9826 +* AVR32 Opcodes:: Opcodes
9829 +@node AVR32 Options
9831 +@cindex AVR32 options
9832 +@cindex options for AVR32
9836 +@cindex @code{--pic} command line option, AVR32
9837 +@cindex PIC code generation for AVR32
9839 +This option specifies that the output of the assembler should be marked
9840 +as position-independent code (PIC). It will also ensure that
9841 +pseudo-instructions that deal with address calculation are output as
9842 +PIC, and that all absolute address references in the code are marked as
9845 +@cindex @code{--linkrelax} command line option, AVR32
9847 +This option specifies that the output of the assembler should be marked
9848 +as linker-relaxable. It will also ensure that all PC-relative operands
9849 +that may change during linker relaxation get appropriate relocations.
9857 +* AVR32-Chars:: Special Characters
9858 +* AVR32-Symrefs:: Symbol references
9862 +@subsection Special Characters
9864 +@cindex line comment character, AVR32
9865 +@cindex AVR32 line comment character
9866 +The presence of a @samp{//} on a line indicates the start of a comment
9867 +that extends to the end of the current line. If a @samp{#} appears as
9868 +the first character of a line, the whole line is treated as a comment.
9870 +@cindex line separator, AVR32
9871 +@cindex statement separator, AVR32
9872 +@cindex AVR32 line separator
9873 +The @samp{;} character can be used instead of a newline to separate
9876 +@node AVR32-Symrefs
9877 +@subsection Symbol references
9879 +The absolute value of a symbol can be obtained by simply naming the
9880 +symbol. However, as AVR32 symbols have 32-bit values, most symbols have
9881 +values that are outside the range of any instructions.
9883 +Instructions that take a PC-relative offset, e.g. @code{lddpc} or
9884 +@code{rcall}, can also reference a symbol by simply naming the symbol
9885 +(no explicit calculations necessary). In this case, the assembler or
9886 +linker subtracts the address of the instruction from the symbol's value
9887 +and inserts the result into the instruction. Note that even though an
9888 +overflow is less likely to happen for a relative reference than for an
9889 +absolute reference, the assembler or linker will generate an error if
9890 +the referenced symbol is too far away from the current location.
9892 +Relative references can be used for data as well. For example:
9899 +2: .int @var{some_symbol} - 1b
9902 +Here, r0 will end up with the run-time address of @var{some_symbol} even
9903 +if the program was loaded at a different address than it was linked
9904 +(position-independent code).
9906 +@subsubsection Symbol modifiers
9910 +@item @code{hi(@var{symbol})}
9911 +Evaluates to the value of the symbol shifted right 16 bits. This will
9912 +work even if @var{symbol} is defined in a different module.
9914 +@item @code{lo(@var{symbol})}
9915 +Evaluates to the low 16 bits of the symbol's value. This will work even
9916 +if @var{symbol} is defined in a different module.
9918 +@item @code{@var{symbol}@@got}
9919 +Create a GOT entry for @var{symbol} and return the offset of that entry
9920 +relative to the GOT base.
9925 +@node AVR32 Directives
9926 +@section Directives
9927 +@cindex machine directives, AVR32
9928 +@cindex AVR32 directives
9932 +@cindex @code{.cpool} directive, AVR32
9934 +This directive causes the current contents of the constant pool to be
9935 +dumped into the current section at the current location (aligned to a
9936 +word boundary). @code{GAS} maintains a separate constant pool for each
9937 +section and each sub-section. The @code{.cpool} directive will only
9938 +affect the constant pool of the current section and sub-section. At the
9939 +end of assembly, all remaining, non-empty constant pools will
9940 +automatically be dumped.
9945 +@node AVR32 Opcodes
9947 +@cindex AVR32 opcodes
9948 +@cindex opcodes for AVR32
9950 +@code{@value{AS}} implements all the standard AVR32 opcodes. It also
9951 +implements several pseudo-opcodes, which are recommended to use wherever
9952 +possible because they give the tool chain better freedom to generate
9957 +@cindex @code{LDA.W reg, symbol} pseudo op, AVR32
9960 + lda.w @var{reg}, @var{symbol}
9963 +This instruction will load the address of @var{symbol} into
9964 +@var{reg}. The instruction will evaluate to one of the following,
9965 +depending on the relative distance to the symbol, the relative distance
9966 +to the constant pool and whether the @code{--pic} option has been
9967 +specified. If the @code{--pic} option has not been specified, the
9968 +alternatives are as follows:
9970 + /* @var{symbol} evaluates to a small enough value */
9971 + mov @var{reg}, @var{symbol}
9973 + /* (. - @var{symbol}) evaluates to a small enough value */
9974 + sub @var{reg}, pc, . - @var{symbol}
9976 + /* Constant pool is close enough */
9977 + lddpc @var{reg}, @var{cpent}
9980 + .long @var{symbol}
9982 + /* Otherwise (not implemented yet, probably not necessary) */
9983 + mov @var{reg}, lo(@var{symbol})
9984 + orh @var{reg}, hi(@var{symbol})
9987 +If the @code{--pic} option has been specified, the alternatives are as
9990 + /* (. - @var{symbol}) evaluates to a small enough value */
9991 + sub @var{reg}, pc, . - @var{symbol}
9993 + /* If @code{--linkrelax} not specified */
9994 + ld.w @var{reg}, r6[@var{symbol}@@got]
9997 + mov @var{reg}, @var{symbol}@@got / 4
9998 + ld.w @var{reg}, r6[@var{reg} << 2]
10001 +If @var{symbol} is not defined in the same file and section as the
10002 +@code{LDA.W} instruction, the most pessimistic alternative of the
10003 +above is selected. The linker may convert it back into the most
10004 +optimal alternative when the final value of all symbols is known.
10006 +@cindex @code{CALL symbol} pseudo op, AVR32
10009 + call @var{symbol}
10012 +This instruction will insert code to call the subroutine identified by
10013 +@var{symbol}. It will evaluate to one of the following, depending on
10014 +the relative distance to the symbol as well as the @code{--linkrelax}
10015 +and @code{--pic} command-line options.
10017 +If @var{symbol} is defined in the same section and input file, and the
10018 +distance is small enough, an @code{rcall} instruction is inserted:
10020 + rcall @var{symbol}
10023 +Otherwise, if the @code{--pic} option has not been specified:
10025 + mcall @var{cpent}
10028 + .long @var{symbol}
10031 +Finally, if nothing else fits and the @code{--pic} option has been
10032 +specified, the assembler will indirect the call through the Global
10035 + /* If @code{--linkrelax} not specified */
10036 + mcall r6[@var{symbol}@@got]
10038 + /* If @code{--linkrelax} specified */
10039 + mov lr, @var{symbol}@@got / 4
10040 + ld.w lr, r6[lr << 2]
10044 +The linker, after determining the final value of @var{symbol}, may
10045 +convert any of these into more optimal alternatives. This includes
10046 +deleting any superfluous constant pool- and GOT-entries.
10049 --- a/gas/doc/Makefile.am
10050 +++ b/gas/doc/Makefile.am
10051 @@ -33,6 +33,7 @@ CPU_DOCS = \
10059 --- a/gas/Makefile.am
10060 +++ b/gas/Makefile.am
10061 @@ -111,6 +111,7 @@ TARGET_CPU_CFILES = \
10065 + config/tc-avr32.c \
10069 @@ -175,6 +176,7 @@ TARGET_CPU_HFILES = \
10073 + config/tc-avr32.h \
10077 --- a/gas/Makefile.in
10078 +++ b/gas/Makefile.in
10079 @@ -378,6 +378,7 @@ TARGET_CPU_CFILES = \
10083 + config/tc-avr32.c \
10087 @@ -442,6 +443,7 @@ TARGET_CPU_HFILES = \
10091 + config/tc-avr32.h \
10095 @@ -785,6 +787,7 @@ distclean-compile:
10096 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
10097 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
10098 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr.Po@am__quote@
10099 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr32.Po@am__quote@
10100 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-bfin.Po@am__quote@
10101 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cr16.Po@am__quote@
10102 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cris.Po@am__quote@
10103 @@ -923,6 +926,20 @@ tc-avr.obj: config/tc-avr.c
10104 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10105 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr.obj `if test -f 'config/tc-avr.c'; then $(CYGPATH_W) 'config/tc-avr.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr.c'; fi`
10107 +tc-avr32.o: config/tc-avr32.c
10108 +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.o -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
10109 +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
10110 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-avr32.c' object='tc-avr32.o' libtool=no @AMDEPBACKSLASH@
10111 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10112 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
10114 +tc-avr32.obj: config/tc-avr32.c
10115 +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.obj -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
10116 +@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
10117 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-avr32.c' object='tc-avr32.obj' libtool=no @AMDEPBACKSLASH@
10118 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10119 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
10121 tc-bfin.o: config/tc-bfin.c
10122 @am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-bfin.o -MD -MP -MF $(DEPDIR)/tc-bfin.Tpo -c -o tc-bfin.o `test -f 'config/tc-bfin.c' || echo '$(srcdir)/'`config/tc-bfin.c
10123 @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-bfin.Tpo $(DEPDIR)/tc-bfin.Po
10125 +++ b/gas/testsuite/gas/avr32/aliases.d
10131 +.*: +file format .*
10133 +Disassembly of section \.text:
10135 +00000000 <ld_nodisp>:
10136 + 0: 19 80 [ \t]+ld\.ub r0,r12\[0x0\]
10137 + 2: f9 20 00 00[ \t]+ld\.sb r0,r12\[0\]
10138 + 6: 98 80 [ \t]+ld\.uh r0,r12\[0x0\]
10139 + 8: 98 00 [ \t]+ld\.sh r0,r12\[0x0\]
10140 + a: 78 00 [ \t]+ld\.w r0,r12\[0x0\]
10142 +0000000c <st_nodisp>:
10143 + c: b8 80 [ \t]+st\.b r12\[0x0\],r0
10144 + e: b8 00 [ \t]+st\.h r12\[0x0\],r0
10145 + 10: 99 00 [ \t]+st\.w r12\[0x0\],r0
10147 +++ b/gas/testsuite/gas/avr32/aliases.s
10150 + .global ld_nodisp
10158 + .global st_nodisp
10164 +++ b/gas/testsuite/gas/avr32/allinsn.d
10170 +.*: +file format .*
10172 +Disassembly of section \.text:
10174 +[0-9a-f]* <ld_d5>:
10175 + *[0-9a-f]*: fe 0f 02 3e ld\.d lr,pc\[pc<<0x3\]
10176 + *[0-9a-f]*: e0 00 02 00 ld\.d r0,r0\[r0\]
10177 + *[0-9a-f]*: ea 05 02 26 ld\.d r6,r5\[r5<<0x2\]
10178 + *[0-9a-f]*: e8 04 02 14 ld\.d r4,r4\[r4<<0x1\]
10179 + *[0-9a-f]*: fc 0e 02 1e ld\.d lr,lr\[lr<<0x1\]
10180 + *[0-9a-f]*: e6 0d 02 2a ld\.d r10,r3\[sp<<0x2\]
10181 + *[0-9a-f]*: f4 06 02 28 ld\.d r8,r10\[r6<<0x2\]
10182 + *[0-9a-f]*: ee 09 02 02 ld\.d r2,r7\[r9\]
10184 +[0-9a-f]* <ld_w5>:
10185 + *[0-9a-f]*: fe 0f 03 0f ld\.w pc,pc\[pc\]
10186 + *[0-9a-f]*: f8 0c 03 3c ld\.w r12,r12\[r12<<0x3\]
10187 + *[0-9a-f]*: ea 05 03 25 ld\.w r5,r5\[r5<<0x2\]
10188 + *[0-9a-f]*: e8 04 03 14 ld\.w r4,r4\[r4<<0x1\]
10189 + *[0-9a-f]*: fc 0e 03 1e ld\.w lr,lr\[lr<<0x1\]
10190 + *[0-9a-f]*: f2 09 03 02 ld\.w r2,r9\[r9\]
10191 + *[0-9a-f]*: e4 06 03 0b ld\.w r11,r2\[r6\]
10192 + *[0-9a-f]*: e4 0d 03 30 ld\.w r0,r2\[sp<<0x3\]
10194 +[0-9a-f]* <ld_sh5>:
10195 + *[0-9a-f]*: fe 0f 04 0f ld\.sh pc,pc\[pc\]
10196 + *[0-9a-f]*: f8 0c 04 3c ld\.sh r12,r12\[r12<<0x3\]
10197 + *[0-9a-f]*: ea 05 04 25 ld\.sh r5,r5\[r5<<0x2\]
10198 + *[0-9a-f]*: e8 04 04 14 ld\.sh r4,r4\[r4<<0x1\]
10199 + *[0-9a-f]*: fc 0e 04 1e ld\.sh lr,lr\[lr<<0x1\]
10200 + *[0-9a-f]*: e0 0f 04 2b ld\.sh r11,r0\[pc<<0x2\]
10201 + *[0-9a-f]*: fa 06 04 2a ld\.sh r10,sp\[r6<<0x2\]
10202 + *[0-9a-f]*: e4 02 04 0c ld\.sh r12,r2\[r2\]
10204 +[0-9a-f]* <ld_uh5>:
10205 + *[0-9a-f]*: fe 0f 05 0f ld\.uh pc,pc\[pc\]
10206 + *[0-9a-f]*: f8 0c 05 3c ld\.uh r12,r12\[r12<<0x3\]
10207 + *[0-9a-f]*: ea 05 05 25 ld\.uh r5,r5\[r5<<0x2\]
10208 + *[0-9a-f]*: e8 04 05 14 ld\.uh r4,r4\[r4<<0x1\]
10209 + *[0-9a-f]*: fc 0e 05 1e ld\.uh lr,lr\[lr<<0x1\]
10210 + *[0-9a-f]*: fe 0e 05 38 ld\.uh r8,pc\[lr<<0x3\]
10211 + *[0-9a-f]*: e2 0f 05 16 ld\.uh r6,r1\[pc<<0x1\]
10212 + *[0-9a-f]*: fc 0d 05 16 ld\.uh r6,lr\[sp<<0x1\]
10214 +[0-9a-f]* <ld_sb2>:
10215 + *[0-9a-f]*: fe 0f 06 0f ld\.sb pc,pc\[pc\]
10216 + *[0-9a-f]*: f8 0c 06 3c ld\.sb r12,r12\[r12<<0x3\]
10217 + *[0-9a-f]*: ea 05 06 25 ld\.sb r5,r5\[r5<<0x2\]
10218 + *[0-9a-f]*: e8 04 06 14 ld\.sb r4,r4\[r4<<0x1\]
10219 + *[0-9a-f]*: fc 0e 06 1e ld\.sb lr,lr\[lr<<0x1\]
10220 + *[0-9a-f]*: e2 0f 06 39 ld\.sb r9,r1\[pc<<0x3\]
10221 + *[0-9a-f]*: e6 0b 06 10 ld\.sb r0,r3\[r11<<0x1\]
10222 + *[0-9a-f]*: ea 05 06 1a ld\.sb r10,r5\[r5<<0x1\]
10224 +[0-9a-f]* <ld_ub5>:
10225 + *[0-9a-f]*: fe 0f 07 0f ld\.ub pc,pc\[pc\]
10226 + *[0-9a-f]*: f8 0c 07 3c ld\.ub r12,r12\[r12<<0x3\]
10227 + *[0-9a-f]*: ea 05 07 25 ld\.ub r5,r5\[r5<<0x2\]
10228 + *[0-9a-f]*: e8 04 07 14 ld\.ub r4,r4\[r4<<0x1\]
10229 + *[0-9a-f]*: fc 0e 07 1e ld\.ub lr,lr\[lr<<0x1\]
10230 + *[0-9a-f]*: f8 07 07 36 ld\.ub r6,r12\[r7<<0x3\]
10231 + *[0-9a-f]*: ec 0c 07 02 ld\.ub r2,r6\[r12\]
10232 + *[0-9a-f]*: ee 0b 07 10 ld\.ub r0,r7\[r11<<0x1\]
10234 +[0-9a-f]* <st_d5>:
10235 + *[0-9a-f]*: fe 0f 08 0e st\.d pc\[pc\],lr
10236 + *[0-9a-f]*: f8 0c 08 3c st\.d r12\[r12<<0x3\],r12
10237 + *[0-9a-f]*: ea 05 08 26 st\.d r5\[r5<<0x2\],r6
10238 + *[0-9a-f]*: e8 04 08 14 st\.d r4\[r4<<0x1\],r4
10239 + *[0-9a-f]*: fc 0e 08 1e st\.d lr\[lr<<0x1\],lr
10240 + *[0-9a-f]*: e2 09 08 14 st\.d r1\[r9<<0x1\],r4
10241 + *[0-9a-f]*: f4 02 08 14 st\.d r10\[r2<<0x1\],r4
10242 + *[0-9a-f]*: f8 06 08 0e st\.d r12\[r6\],lr
10244 +[0-9a-f]* <st_w5>:
10245 + *[0-9a-f]*: fe 0f 09 0f st\.w pc\[pc\],pc
10246 + *[0-9a-f]*: f8 0c 09 3c st\.w r12\[r12<<0x3\],r12
10247 + *[0-9a-f]*: ea 05 09 25 st\.w r5\[r5<<0x2\],r5
10248 + *[0-9a-f]*: e8 04 09 14 st\.w r4\[r4<<0x1\],r4
10249 + *[0-9a-f]*: fc 0e 09 1e st\.w lr\[lr<<0x1\],lr
10250 + *[0-9a-f]*: e2 0a 09 03 st\.w r1\[r10\],r3
10251 + *[0-9a-f]*: e0 0a 09 19 st\.w r0\[r10<<0x1\],r9
10252 + *[0-9a-f]*: e8 05 09 3f st\.w r4\[r5<<0x3\],pc
10254 +[0-9a-f]* <st_h5>:
10255 + *[0-9a-f]*: fe 0f 0a 0f st\.h pc\[pc\],pc
10256 + *[0-9a-f]*: f8 0c 0a 3c st\.h r12\[r12<<0x3\],r12
10257 + *[0-9a-f]*: ea 05 0a 25 st\.h r5\[r5<<0x2\],r5
10258 + *[0-9a-f]*: e8 04 0a 14 st\.h r4\[r4<<0x1\],r4
10259 + *[0-9a-f]*: fc 0e 0a 1e st\.h lr\[lr<<0x1\],lr
10260 + *[0-9a-f]*: e4 09 0a 0b st\.h r2\[r9\],r11
10261 + *[0-9a-f]*: ea 01 0a 2c st\.h r5\[r1<<0x2\],r12
10262 + *[0-9a-f]*: fe 08 0a 23 st\.h pc\[r8<<0x2\],r3
10264 +[0-9a-f]* <st_b5>:
10265 + *[0-9a-f]*: fe 0f 0b 0f st\.b pc\[pc\],pc
10266 + *[0-9a-f]*: f8 0c 0b 3c st\.b r12\[r12<<0x3\],r12
10267 + *[0-9a-f]*: ea 05 0b 25 st\.b r5\[r5<<0x2\],r5
10268 + *[0-9a-f]*: e8 04 0b 14 st\.b r4\[r4<<0x1\],r4
10269 + *[0-9a-f]*: fc 0e 0b 1e st\.b lr\[lr<<0x1\],lr
10270 + *[0-9a-f]*: e2 08 0b 16 st\.b r1\[r8<<0x1\],r6
10271 + *[0-9a-f]*: fc 0e 0b 31 st\.b lr\[lr<<0x3\],r1
10272 + *[0-9a-f]*: ea 00 0b 2f st\.b r5\[r0<<0x2\],pc
10275 + *[0-9a-f]*: fe 0f 0c 0f divs pc,pc,pc
10276 + *[0-9a-f]*: f8 0c 0c 0c divs r12,r12,r12
10277 + *[0-9a-f]*: ea 05 0c 05 divs r5,r5,r5
10278 + *[0-9a-f]*: e8 04 0c 04 divs r4,r4,r4
10279 + *[0-9a-f]*: fc 0e 0c 0e divs lr,lr,lr
10280 + *[0-9a-f]*: fe 0f 0c 03 divs r3,pc,pc
10281 + *[0-9a-f]*: f8 02 0c 09 divs r9,r12,r2
10282 + *[0-9a-f]*: e8 01 0c 07 divs r7,r4,r1
10285 + *[0-9a-f]*: 1e 0f add pc,pc
10286 + *[0-9a-f]*: 18 0c add r12,r12
10287 + *[0-9a-f]*: 0a 05 add r5,r5
10288 + *[0-9a-f]*: 08 04 add r4,r4
10289 + *[0-9a-f]*: 1c 0e add lr,lr
10290 + *[0-9a-f]*: 12 0c add r12,r9
10291 + *[0-9a-f]*: 06 06 add r6,r3
10292 + *[0-9a-f]*: 18 0a add r10,r12
10295 + *[0-9a-f]*: 1e 1f sub pc,pc
10296 + *[0-9a-f]*: 18 1c sub r12,r12
10297 + *[0-9a-f]*: 0a 15 sub r5,r5
10298 + *[0-9a-f]*: 08 14 sub r4,r4
10299 + *[0-9a-f]*: 1c 1e sub lr,lr
10300 + *[0-9a-f]*: 0c 1e sub lr,r6
10301 + *[0-9a-f]*: 1a 10 sub r0,sp
10302 + *[0-9a-f]*: 18 16 sub r6,r12
10304 +[0-9a-f]* <rsub1>:
10305 + *[0-9a-f]*: 1e 2f rsub pc,pc
10306 + *[0-9a-f]*: 18 2c rsub r12,r12
10307 + *[0-9a-f]*: 0a 25 rsub r5,r5
10308 + *[0-9a-f]*: 08 24 rsub r4,r4
10309 + *[0-9a-f]*: 1c 2e rsub lr,lr
10310 + *[0-9a-f]*: 1a 2b rsub r11,sp
10311 + *[0-9a-f]*: 08 27 rsub r7,r4
10312 + *[0-9a-f]*: 02 29 rsub r9,r1
10315 + *[0-9a-f]*: 1e 3f cp\.w pc,pc
10316 + *[0-9a-f]*: 18 3c cp\.w r12,r12
10317 + *[0-9a-f]*: 0a 35 cp\.w r5,r5
10318 + *[0-9a-f]*: 08 34 cp\.w r4,r4
10319 + *[0-9a-f]*: 1c 3e cp\.w lr,lr
10320 + *[0-9a-f]*: 04 36 cp\.w r6,r2
10321 + *[0-9a-f]*: 12 30 cp\.w r0,r9
10322 + *[0-9a-f]*: 1a 33 cp\.w r3,sp
10325 + *[0-9a-f]*: 1e 4f or pc,pc
10326 + *[0-9a-f]*: 18 4c or r12,r12
10327 + *[0-9a-f]*: 0a 45 or r5,r5
10328 + *[0-9a-f]*: 08 44 or r4,r4
10329 + *[0-9a-f]*: 1c 4e or lr,lr
10330 + *[0-9a-f]*: 12 44 or r4,r9
10331 + *[0-9a-f]*: 08 4b or r11,r4
10332 + *[0-9a-f]*: 00 44 or r4,r0
10335 + *[0-9a-f]*: 1e 5f eor pc,pc
10336 + *[0-9a-f]*: 18 5c eor r12,r12
10337 + *[0-9a-f]*: 0a 55 eor r5,r5
10338 + *[0-9a-f]*: 08 54 eor r4,r4
10339 + *[0-9a-f]*: 1c 5e eor lr,lr
10340 + *[0-9a-f]*: 16 5c eor r12,r11
10341 + *[0-9a-f]*: 02 50 eor r0,r1
10342 + *[0-9a-f]*: 1e 55 eor r5,pc
10345 + *[0-9a-f]*: 1e 6f and pc,pc
10346 + *[0-9a-f]*: 18 6c and r12,r12
10347 + *[0-9a-f]*: 0a 65 and r5,r5
10348 + *[0-9a-f]*: 08 64 and r4,r4
10349 + *[0-9a-f]*: 1c 6e and lr,lr
10350 + *[0-9a-f]*: 02 68 and r8,r1
10351 + *[0-9a-f]*: 1a 60 and r0,sp
10352 + *[0-9a-f]*: 0a 6a and r10,r5
10355 + *[0-9a-f]*: 1e 7f tst pc,pc
10356 + *[0-9a-f]*: 18 7c tst r12,r12
10357 + *[0-9a-f]*: 0a 75 tst r5,r5
10358 + *[0-9a-f]*: 08 74 tst r4,r4
10359 + *[0-9a-f]*: 1c 7e tst lr,lr
10360 + *[0-9a-f]*: 18 70 tst r0,r12
10361 + *[0-9a-f]*: 0c 7a tst r10,r6
10362 + *[0-9a-f]*: 08 7d tst sp,r4
10365 + *[0-9a-f]*: 1e 8f andn pc,pc
10366 + *[0-9a-f]*: 18 8c andn r12,r12
10367 + *[0-9a-f]*: 0a 85 andn r5,r5
10368 + *[0-9a-f]*: 08 84 andn r4,r4
10369 + *[0-9a-f]*: 1c 8e andn lr,lr
10370 + *[0-9a-f]*: 18 89 andn r9,r12
10371 + *[0-9a-f]*: 1a 8b andn r11,sp
10372 + *[0-9a-f]*: 0a 8c andn r12,r5
10375 + *[0-9a-f]*: 1e 9f mov pc,pc
10376 + *[0-9a-f]*: 18 9c mov r12,r12
10377 + *[0-9a-f]*: 0a 95 mov r5,r5
10378 + *[0-9a-f]*: 08 94 mov r4,r4
10379 + *[0-9a-f]*: 1c 9e mov lr,lr
10380 + *[0-9a-f]*: 12 95 mov r5,r9
10381 + *[0-9a-f]*: 16 9b mov r11,r11
10382 + *[0-9a-f]*: 1c 92 mov r2,lr
10384 +[0-9a-f]* <st_w1>:
10385 + *[0-9a-f]*: 1e af st\.w pc\+\+,pc
10386 + *[0-9a-f]*: 18 ac st\.w r12\+\+,r12
10387 + *[0-9a-f]*: 0a a5 st\.w r5\+\+,r5
10388 + *[0-9a-f]*: 08 a4 st\.w r4\+\+,r4
10389 + *[0-9a-f]*: 1c ae st\.w lr\+\+,lr
10390 + *[0-9a-f]*: 02 ab st\.w r1\+\+,r11
10391 + *[0-9a-f]*: 1a a0 st\.w sp\+\+,r0
10392 + *[0-9a-f]*: 1a a1 st\.w sp\+\+,r1
10394 +[0-9a-f]* <st_h1>:
10395 + *[0-9a-f]*: 1e bf st\.h pc\+\+,pc
10396 + *[0-9a-f]*: 18 bc st\.h r12\+\+,r12
10397 + *[0-9a-f]*: 0a b5 st\.h r5\+\+,r5
10398 + *[0-9a-f]*: 08 b4 st\.h r4\+\+,r4
10399 + *[0-9a-f]*: 1c be st\.h lr\+\+,lr
10400 + *[0-9a-f]*: 18 bd st\.h r12\+\+,sp
10401 + *[0-9a-f]*: 0e be st\.h r7\+\+,lr
10402 + *[0-9a-f]*: 0e b4 st\.h r7\+\+,r4
10404 +[0-9a-f]* <st_b1>:
10405 + *[0-9a-f]*: 1e cf st\.b pc\+\+,pc
10406 + *[0-9a-f]*: 18 cc st\.b r12\+\+,r12
10407 + *[0-9a-f]*: 0a c5 st\.b r5\+\+,r5
10408 + *[0-9a-f]*: 08 c4 st\.b r4\+\+,r4
10409 + *[0-9a-f]*: 1c ce st\.b lr\+\+,lr
10410 + *[0-9a-f]*: 12 cd st\.b r9\+\+,sp
10411 + *[0-9a-f]*: 02 cd st\.b r1\+\+,sp
10412 + *[0-9a-f]*: 00 c4 st\.b r0\+\+,r4
10414 +[0-9a-f]* <st_w2>:
10415 + *[0-9a-f]*: 1e df st\.w --pc,pc
10416 + *[0-9a-f]*: 18 dc st\.w --r12,r12
10417 + *[0-9a-f]*: 0a d5 st\.w --r5,r5
10418 + *[0-9a-f]*: 08 d4 st\.w --r4,r4
10419 + *[0-9a-f]*: 1c de st\.w --lr,lr
10420 + *[0-9a-f]*: 02 d7 st\.w --r1,r7
10421 + *[0-9a-f]*: 06 d9 st\.w --r3,r9
10422 + *[0-9a-f]*: 0a d5 st\.w --r5,r5
10424 +[0-9a-f]* <st_h2>:
10425 + *[0-9a-f]*: 1e ef st\.h --pc,pc
10426 + *[0-9a-f]*: 18 ec st\.h --r12,r12
10427 + *[0-9a-f]*: 0a e5 st\.h --r5,r5
10428 + *[0-9a-f]*: 08 e4 st\.h --r4,r4
10429 + *[0-9a-f]*: 1c ee st\.h --lr,lr
10430 + *[0-9a-f]*: 0a e7 st\.h --r5,r7
10431 + *[0-9a-f]*: 10 e8 st\.h --r8,r8
10432 + *[0-9a-f]*: 0e e2 st\.h --r7,r2
10434 +[0-9a-f]* <st_b2>:
10435 + *[0-9a-f]*: 1e ff st\.b --pc,pc
10436 + *[0-9a-f]*: 18 fc st\.b --r12,r12
10437 + *[0-9a-f]*: 0a f5 st\.b --r5,r5
10438 + *[0-9a-f]*: 08 f4 st\.b --r4,r4
10439 + *[0-9a-f]*: 1c fe st\.b --lr,lr
10440 + *[0-9a-f]*: 1a fd st\.b --sp,sp
10441 + *[0-9a-f]*: 1a fb st\.b --sp,r11
10442 + *[0-9a-f]*: 08 f5 st\.b --r4,r5
10444 +[0-9a-f]* <ld_w1>:
10445 + *[0-9a-f]*: 1f 0f ld\.w pc,pc\+\+
10446 + *[0-9a-f]*: 19 0c ld\.w r12,r12\+\+
10447 + *[0-9a-f]*: 0b 05 ld\.w r5,r5\+\+
10448 + *[0-9a-f]*: 09 04 ld\.w r4,r4\+\+
10449 + *[0-9a-f]*: 1d 0e ld\.w lr,lr\+\+
10450 + *[0-9a-f]*: 0f 03 ld\.w r3,r7\+\+
10451 + *[0-9a-f]*: 1d 03 ld\.w r3,lr\+\+
10452 + *[0-9a-f]*: 0b 0c ld\.w r12,r5\+\+
10454 +[0-9a-f]* <ld_sh1>:
10455 + *[0-9a-f]*: 1f 1f ld\.sh pc,pc\+\+
10456 + *[0-9a-f]*: 19 1c ld\.sh r12,r12\+\+
10457 + *[0-9a-f]*: 0b 15 ld\.sh r5,r5\+\+
10458 + *[0-9a-f]*: 09 14 ld\.sh r4,r4\+\+
10459 + *[0-9a-f]*: 1d 1e ld\.sh lr,lr\+\+
10460 + *[0-9a-f]*: 05 1b ld\.sh r11,r2\+\+
10461 + *[0-9a-f]*: 11 12 ld\.sh r2,r8\+\+
10462 + *[0-9a-f]*: 0d 17 ld\.sh r7,r6\+\+
10464 +[0-9a-f]* <ld_uh1>:
10465 + *[0-9a-f]*: 1f 2f ld\.uh pc,pc\+\+
10466 + *[0-9a-f]*: 19 2c ld\.uh r12,r12\+\+
10467 + *[0-9a-f]*: 0b 25 ld\.uh r5,r5\+\+
10468 + *[0-9a-f]*: 09 24 ld\.uh r4,r4\+\+
10469 + *[0-9a-f]*: 1d 2e ld\.uh lr,lr\+\+
10470 + *[0-9a-f]*: 0f 26 ld\.uh r6,r7\+\+
10471 + *[0-9a-f]*: 17 2a ld\.uh r10,r11\+\+
10472 + *[0-9a-f]*: 09 2e ld\.uh lr,r4\+\+
10474 +[0-9a-f]* <ld_ub1>:
10475 + *[0-9a-f]*: 1f 3f ld\.ub pc,pc\+\+
10476 + *[0-9a-f]*: 19 3c ld\.ub r12,r12\+\+
10477 + *[0-9a-f]*: 0b 35 ld\.ub r5,r5\+\+
10478 + *[0-9a-f]*: 09 34 ld\.ub r4,r4\+\+
10479 + *[0-9a-f]*: 1d 3e ld\.ub lr,lr\+\+
10480 + *[0-9a-f]*: 1d 38 ld\.ub r8,lr\+\+
10481 + *[0-9a-f]*: 19 3c ld\.ub r12,r12\+\+
10482 + *[0-9a-f]*: 15 3b ld\.ub r11,r10\+\+
10484 +[0-9a-f]* <ld_w2>:
10485 + *[0-9a-f]*: 1f 4f ld\.w pc,--pc
10486 + *[0-9a-f]*: 19 4c ld\.w r12,--r12
10487 + *[0-9a-f]*: 0b 45 ld\.w r5,--r5
10488 + *[0-9a-f]*: 09 44 ld\.w r4,--r4
10489 + *[0-9a-f]*: 1d 4e ld\.w lr,--lr
10490 + *[0-9a-f]*: 1d 4a ld\.w r10,--lr
10491 + *[0-9a-f]*: 13 4c ld\.w r12,--r9
10492 + *[0-9a-f]*: 0b 46 ld\.w r6,--r5
10494 +[0-9a-f]* <ld_sh2>:
10495 + *[0-9a-f]*: 1f 5f ld\.sh pc,--pc
10496 + *[0-9a-f]*: 19 5c ld\.sh r12,--r12
10497 + *[0-9a-f]*: 0b 55 ld\.sh r5,--r5
10498 + *[0-9a-f]*: 09 54 ld\.sh r4,--r4
10499 + *[0-9a-f]*: 1d 5e ld\.sh lr,--lr
10500 + *[0-9a-f]*: 15 5f ld\.sh pc,--r10
10501 + *[0-9a-f]*: 07 56 ld\.sh r6,--r3
10502 + *[0-9a-f]*: 0d 54 ld\.sh r4,--r6
10504 +[0-9a-f]* <ld_uh2>:
10505 + *[0-9a-f]*: 1f 6f ld\.uh pc,--pc
10506 + *[0-9a-f]*: 19 6c ld\.uh r12,--r12
10507 + *[0-9a-f]*: 0b 65 ld\.uh r5,--r5
10508 + *[0-9a-f]*: 09 64 ld\.uh r4,--r4
10509 + *[0-9a-f]*: 1d 6e ld\.uh lr,--lr
10510 + *[0-9a-f]*: 05 63 ld\.uh r3,--r2
10511 + *[0-9a-f]*: 01 61 ld\.uh r1,--r0
10512 + *[0-9a-f]*: 13 62 ld\.uh r2,--r9
10514 +[0-9a-f]* <ld_ub2>:
10515 + *[0-9a-f]*: 1f 7f ld\.ub pc,--pc
10516 + *[0-9a-f]*: 19 7c ld\.ub r12,--r12
10517 + *[0-9a-f]*: 0b 75 ld\.ub r5,--r5
10518 + *[0-9a-f]*: 09 74 ld\.ub r4,--r4
10519 + *[0-9a-f]*: 1d 7e ld\.ub lr,--lr
10520 + *[0-9a-f]*: 03 71 ld\.ub r1,--r1
10521 + *[0-9a-f]*: 0d 70 ld\.ub r0,--r6
10522 + *[0-9a-f]*: 0f 72 ld\.ub r2,--r7
10524 +[0-9a-f]* <ld_ub3>:
10525 + *[0-9a-f]*: 1f 8f ld\.ub pc,pc\[0x0\]
10526 + *[0-9a-f]*: 19 fc ld\.ub r12,r12\[0x7\]
10527 + *[0-9a-f]*: 0b c5 ld\.ub r5,r5\[0x4\]
10528 + *[0-9a-f]*: 09 b4 ld\.ub r4,r4\[0x3\]
10529 + *[0-9a-f]*: 1d 9e ld\.ub lr,lr\[0x1\]
10530 + *[0-9a-f]*: 13 e6 ld\.ub r6,r9\[0x6\]
10531 + *[0-9a-f]*: 1d c2 ld\.ub r2,lr\[0x4\]
10532 + *[0-9a-f]*: 11 81 ld\.ub r1,r8\[0x0\]
10534 +[0-9a-f]* <sub3_sp>:
10535 + *[0-9a-f]*: 20 0d sub sp,0
10536 + *[0-9a-f]*: 2f fd sub sp,-4
10537 + *[0-9a-f]*: 28 0d sub sp,-512
10538 + *[0-9a-f]*: 27 fd sub sp,508
10539 + *[0-9a-f]*: 20 1d sub sp,4
10540 + *[0-9a-f]*: 20 bd sub sp,44
10541 + *[0-9a-f]*: 20 2d sub sp,8
10542 + *[0-9a-f]*: 25 7d sub sp,348
10545 + *[0-9a-f]*: 20 0f sub pc,0
10546 + *[0-9a-f]*: 2f fc sub r12,-1
10547 + *[0-9a-f]*: 28 05 sub r5,-128
10548 + *[0-9a-f]*: 27 f4 sub r4,127
10549 + *[0-9a-f]*: 20 1e sub lr,1
10550 + *[0-9a-f]*: 2d 76 sub r6,-41
10551 + *[0-9a-f]*: 22 54 sub r4,37
10552 + *[0-9a-f]*: 23 8c sub r12,56
10555 + *[0-9a-f]*: 30 0f mov pc,0
10556 + *[0-9a-f]*: 3f fc mov r12,-1
10557 + *[0-9a-f]*: 38 05 mov r5,-128
10558 + *[0-9a-f]*: 37 f4 mov r4,127
10559 + *[0-9a-f]*: 30 1e mov lr,1
10560 + *[0-9a-f]*: 30 ef mov pc,14
10561 + *[0-9a-f]*: 39 c6 mov r6,-100
10562 + *[0-9a-f]*: 38 6e mov lr,-122
10564 +[0-9a-f]* <lddsp>:
10565 + *[0-9a-f]*: 40 0f lddsp pc,sp\[0x0\]
10566 + *[0-9a-f]*: 47 fc lddsp r12,sp\[0x1fc\]
10567 + *[0-9a-f]*: 44 05 lddsp r5,sp\[0x100\]
10568 + *[0-9a-f]*: 43 f4 lddsp r4,sp\[0xfc\]
10569 + *[0-9a-f]*: 40 1e lddsp lr,sp\[0x4\]
10570 + *[0-9a-f]*: 44 0e lddsp lr,sp\[0x100\]
10571 + *[0-9a-f]*: 40 5c lddsp r12,sp\[0x14\]
10572 + *[0-9a-f]*: 47 69 lddsp r9,sp\[0x1d8\]
10574 +[0-9a-f]* <lddpc>:
10575 + *[0-9a-f]*: 48 0f lddpc pc,[0-9a-f]* <.*>
10576 + *[0-9a-f]*: 4f f0 lddpc r0,[0-9a-f]* <.*>
10577 + *[0-9a-f]*: 4c 08 lddpc r8,[0-9a-f]* <.*>
10578 + *[0-9a-f]*: 4b f7 lddpc r7,[0-9a-f]* <.*>
10579 + *[0-9a-f]*: 48 1e lddpc lr,[0-9a-f]* <.*>
10580 + *[0-9a-f]*: 4f 6d lddpc sp,[0-9a-f]* <.*>
10581 + *[0-9a-f]*: 49 e6 lddpc r6,[0-9a-f]* <.*>
10582 + *[0-9a-f]*: 48 7b lddpc r11,[0-9a-f]* <.*>
10584 +[0-9a-f]* <stdsp>:
10585 + *[0-9a-f]*: 50 0f stdsp sp\[0x0\],pc
10586 + *[0-9a-f]*: 57 fc stdsp sp\[0x1fc\],r12
10587 + *[0-9a-f]*: 54 05 stdsp sp\[0x100\],r5
10588 + *[0-9a-f]*: 53 f4 stdsp sp\[0xfc\],r4
10589 + *[0-9a-f]*: 50 1e stdsp sp\[0x4\],lr
10590 + *[0-9a-f]*: 54 cf stdsp sp\[0x130\],pc
10591 + *[0-9a-f]*: 54 00 stdsp sp\[0x100\],r0
10592 + *[0-9a-f]*: 55 45 stdsp sp\[0x150\],r5
10595 + *[0-9a-f]*: 58 0f cp.w pc,0
10596 + *[0-9a-f]*: 5b fc cp.w r12,-1
10597 + *[0-9a-f]*: 5a 05 cp.w r5,-32
10598 + *[0-9a-f]*: 59 f4 cp.w r4,31
10599 + *[0-9a-f]*: 58 1e cp.w lr,1
10600 + *[0-9a-f]*: 58 38 cp.w r8,3
10601 + *[0-9a-f]*: 59 0e cp.w lr,16
10602 + *[0-9a-f]*: 5a 67 cp.w r7,-26
10605 + *[0-9a-f]*: 5c 0f acr pc
10606 + *[0-9a-f]*: 5c 0c acr r12
10607 + *[0-9a-f]*: 5c 05 acr r5
10608 + *[0-9a-f]*: 5c 04 acr r4
10609 + *[0-9a-f]*: 5c 0e acr lr
10610 + *[0-9a-f]*: 5c 02 acr r2
10611 + *[0-9a-f]*: 5c 0c acr r12
10612 + *[0-9a-f]*: 5c 0f acr pc
10615 + *[0-9a-f]*: 5c 1f scr pc
10616 + *[0-9a-f]*: 5c 1c scr r12
10617 + *[0-9a-f]*: 5c 15 scr r5
10618 + *[0-9a-f]*: 5c 14 scr r4
10619 + *[0-9a-f]*: 5c 1e scr lr
10620 + *[0-9a-f]*: 5c 1f scr pc
10621 + *[0-9a-f]*: 5c 16 scr r6
10622 + *[0-9a-f]*: 5c 11 scr r1
10625 + *[0-9a-f]*: 5c 2f cpc pc
10626 + *[0-9a-f]*: 5c 2c cpc r12
10627 + *[0-9a-f]*: 5c 25 cpc r5
10628 + *[0-9a-f]*: 5c 24 cpc r4
10629 + *[0-9a-f]*: 5c 2e cpc lr
10630 + *[0-9a-f]*: 5c 2f cpc pc
10631 + *[0-9a-f]*: 5c 24 cpc r4
10632 + *[0-9a-f]*: 5c 29 cpc r9
10635 + *[0-9a-f]*: 5c 3f neg pc
10636 + *[0-9a-f]*: 5c 3c neg r12
10637 + *[0-9a-f]*: 5c 35 neg r5
10638 + *[0-9a-f]*: 5c 34 neg r4
10639 + *[0-9a-f]*: 5c 3e neg lr
10640 + *[0-9a-f]*: 5c 37 neg r7
10641 + *[0-9a-f]*: 5c 31 neg r1
10642 + *[0-9a-f]*: 5c 39 neg r9
10645 + *[0-9a-f]*: 5c 4f abs pc
10646 + *[0-9a-f]*: 5c 4c abs r12
10647 + *[0-9a-f]*: 5c 45 abs r5
10648 + *[0-9a-f]*: 5c 44 abs r4
10649 + *[0-9a-f]*: 5c 4e abs lr
10650 + *[0-9a-f]*: 5c 46 abs r6
10651 + *[0-9a-f]*: 5c 46 abs r6
10652 + *[0-9a-f]*: 5c 44 abs r4
10654 +[0-9a-f]* <castu_b>:
10655 + *[0-9a-f]*: 5c 5f castu\.b pc
10656 + *[0-9a-f]*: 5c 5c castu\.b r12
10657 + *[0-9a-f]*: 5c 55 castu\.b r5
10658 + *[0-9a-f]*: 5c 54 castu\.b r4
10659 + *[0-9a-f]*: 5c 5e castu\.b lr
10660 + *[0-9a-f]*: 5c 57 castu\.b r7
10661 + *[0-9a-f]*: 5c 5d castu\.b sp
10662 + *[0-9a-f]*: 5c 59 castu\.b r9
10664 +[0-9a-f]* <casts_b>:
10665 + *[0-9a-f]*: 5c 6f casts\.b pc
10666 + *[0-9a-f]*: 5c 6c casts\.b r12
10667 + *[0-9a-f]*: 5c 65 casts\.b r5
10668 + *[0-9a-f]*: 5c 64 casts\.b r4
10669 + *[0-9a-f]*: 5c 6e casts\.b lr
10670 + *[0-9a-f]*: 5c 6b casts\.b r11
10671 + *[0-9a-f]*: 5c 61 casts\.b r1
10672 + *[0-9a-f]*: 5c 6a casts\.b r10
10674 +[0-9a-f]* <castu_h>:
10675 + *[0-9a-f]*: 5c 7f castu\.h pc
10676 + *[0-9a-f]*: 5c 7c castu\.h r12
10677 + *[0-9a-f]*: 5c 75 castu\.h r5
10678 + *[0-9a-f]*: 5c 74 castu\.h r4
10679 + *[0-9a-f]*: 5c 7e castu\.h lr
10680 + *[0-9a-f]*: 5c 7a castu\.h r10
10681 + *[0-9a-f]*: 5c 7b castu\.h r11
10682 + *[0-9a-f]*: 5c 71 castu\.h r1
10684 +[0-9a-f]* <casts_h>:
10685 + *[0-9a-f]*: 5c 8f casts\.h pc
10686 + *[0-9a-f]*: 5c 8c casts\.h r12
10687 + *[0-9a-f]*: 5c 85 casts\.h r5
10688 + *[0-9a-f]*: 5c 84 casts\.h r4
10689 + *[0-9a-f]*: 5c 8e casts\.h lr
10690 + *[0-9a-f]*: 5c 80 casts\.h r0
10691 + *[0-9a-f]*: 5c 85 casts\.h r5
10692 + *[0-9a-f]*: 5c 89 casts\.h r9
10695 + *[0-9a-f]*: 5c 9f brev pc
10696 + *[0-9a-f]*: 5c 9c brev r12
10697 + *[0-9a-f]*: 5c 95 brev r5
10698 + *[0-9a-f]*: 5c 94 brev r4
10699 + *[0-9a-f]*: 5c 9e brev lr
10700 + *[0-9a-f]*: 5c 95 brev r5
10701 + *[0-9a-f]*: 5c 9a brev r10
10702 + *[0-9a-f]*: 5c 98 brev r8
10704 +[0-9a-f]* <swap_h>:
10705 + *[0-9a-f]*: 5c af swap\.h pc
10706 + *[0-9a-f]*: 5c ac swap\.h r12
10707 + *[0-9a-f]*: 5c a5 swap\.h r5
10708 + *[0-9a-f]*: 5c a4 swap\.h r4
10709 + *[0-9a-f]*: 5c ae swap\.h lr
10710 + *[0-9a-f]*: 5c a7 swap\.h r7
10711 + *[0-9a-f]*: 5c a0 swap\.h r0
10712 + *[0-9a-f]*: 5c a8 swap\.h r8
10714 +[0-9a-f]* <swap_b>:
10715 + *[0-9a-f]*: 5c bf swap\.b pc
10716 + *[0-9a-f]*: 5c bc swap\.b r12
10717 + *[0-9a-f]*: 5c b5 swap\.b r5
10718 + *[0-9a-f]*: 5c b4 swap\.b r4
10719 + *[0-9a-f]*: 5c be swap\.b lr
10720 + *[0-9a-f]*: 5c ba swap\.b r10
10721 + *[0-9a-f]*: 5c bc swap\.b r12
10722 + *[0-9a-f]*: 5c b1 swap\.b r1
10724 +[0-9a-f]* <swap_bh>:
10725 + *[0-9a-f]*: 5c cf swap\.bh pc
10726 + *[0-9a-f]*: 5c cc swap\.bh r12
10727 + *[0-9a-f]*: 5c c5 swap\.bh r5
10728 + *[0-9a-f]*: 5c c4 swap\.bh r4
10729 + *[0-9a-f]*: 5c ce swap\.bh lr
10730 + *[0-9a-f]*: 5c c9 swap\.bh r9
10731 + *[0-9a-f]*: 5c c4 swap\.bh r4
10732 + *[0-9a-f]*: 5c c1 swap\.bh r1
10734 +[0-9a-f]* <One_s_compliment>:
10735 + *[0-9a-f]*: 5c df com pc
10736 + *[0-9a-f]*: 5c dc com r12
10737 + *[0-9a-f]*: 5c d5 com r5
10738 + *[0-9a-f]*: 5c d4 com r4
10739 + *[0-9a-f]*: 5c de com lr
10740 + *[0-9a-f]*: 5c d2 com r2
10741 + *[0-9a-f]*: 5c d2 com r2
10742 + *[0-9a-f]*: 5c d7 com r7
10745 + *[0-9a-f]*: 5c ef tnbz pc
10746 + *[0-9a-f]*: 5c ec tnbz r12
10747 + *[0-9a-f]*: 5c e5 tnbz r5
10748 + *[0-9a-f]*: 5c e4 tnbz r4
10749 + *[0-9a-f]*: 5c ee tnbz lr
10750 + *[0-9a-f]*: 5c e8 tnbz r8
10751 + *[0-9a-f]*: 5c ec tnbz r12
10752 + *[0-9a-f]*: 5c ef tnbz pc
10755 + *[0-9a-f]*: 5c ff rol pc
10756 + *[0-9a-f]*: 5c fc rol r12
10757 + *[0-9a-f]*: 5c f5 rol r5
10758 + *[0-9a-f]*: 5c f4 rol r4
10759 + *[0-9a-f]*: 5c fe rol lr
10760 + *[0-9a-f]*: 5c fa rol r10
10761 + *[0-9a-f]*: 5c f9 rol r9
10762 + *[0-9a-f]*: 5c f5 rol r5
10765 + *[0-9a-f]*: 5d 0f ror pc
10766 + *[0-9a-f]*: 5d 0c ror r12
10767 + *[0-9a-f]*: 5d 05 ror r5
10768 + *[0-9a-f]*: 5d 04 ror r4
10769 + *[0-9a-f]*: 5d 0e ror lr
10770 + *[0-9a-f]*: 5d 08 ror r8
10771 + *[0-9a-f]*: 5d 04 ror r4
10772 + *[0-9a-f]*: 5d 07 ror r7
10774 +[0-9a-f]* <icall>:
10775 + *[0-9a-f]*: 5d 1f icall pc
10776 + *[0-9a-f]*: 5d 1c icall r12
10777 + *[0-9a-f]*: 5d 15 icall r5
10778 + *[0-9a-f]*: 5d 14 icall r4
10779 + *[0-9a-f]*: 5d 1e icall lr
10780 + *[0-9a-f]*: 5d 13 icall r3
10781 + *[0-9a-f]*: 5d 11 icall r1
10782 + *[0-9a-f]*: 5d 13 icall r3
10784 +[0-9a-f]* <mustr>:
10785 + *[0-9a-f]*: 5d 2f mustr pc
10786 + *[0-9a-f]*: 5d 2c mustr r12
10787 + *[0-9a-f]*: 5d 25 mustr r5
10788 + *[0-9a-f]*: 5d 24 mustr r4
10789 + *[0-9a-f]*: 5d 2e mustr lr
10790 + *[0-9a-f]*: 5d 21 mustr r1
10791 + *[0-9a-f]*: 5d 24 mustr r4
10792 + *[0-9a-f]*: 5d 2c mustr r12
10794 +[0-9a-f]* <musfr>:
10795 + *[0-9a-f]*: 5d 3f musfr pc
10796 + *[0-9a-f]*: 5d 3c musfr r12
10797 + *[0-9a-f]*: 5d 35 musfr r5
10798 + *[0-9a-f]*: 5d 34 musfr r4
10799 + *[0-9a-f]*: 5d 3e musfr lr
10800 + *[0-9a-f]*: 5d 3b musfr r11
10801 + *[0-9a-f]*: 5d 3c musfr r12
10802 + *[0-9a-f]*: 5d 32 musfr r2
10804 +[0-9a-f]* <ret_cond>:
10805 + *[0-9a-f]*: 5e 0f reteq 1
10806 + *[0-9a-f]*: 5e fc retal r12
10807 + *[0-9a-f]*: 5e 85 retls r5
10808 + *[0-9a-f]*: 5e 74 retpl r4
10809 + *[0-9a-f]*: 5e 1e retne -1
10810 + *[0-9a-f]*: 5e 90 retgt r0
10811 + *[0-9a-f]*: 5e 9c retgt r12
10812 + *[0-9a-f]*: 5e 4a retge r10
10814 +[0-9a-f]* <sr_cond>:
10815 + *[0-9a-f]*: 5f 0f sreq pc
10816 + *[0-9a-f]*: 5f fc sral r12
10817 + *[0-9a-f]*: 5f 85 srls r5
10818 + *[0-9a-f]*: 5f 74 srpl r4
10819 + *[0-9a-f]*: 5f 1e srne lr
10820 + *[0-9a-f]*: 5f 50 srlt r0
10821 + *[0-9a-f]*: 5f fd sral sp
10822 + *[0-9a-f]*: 5f 49 srge r9
10824 +[0-9a-f]* <ld_w3>:
10825 + *[0-9a-f]*: 7e 0f ld\.w pc,pc\[0x0\]
10826 + *[0-9a-f]*: 79 fc ld\.w r12,r12\[0x7c\]
10827 + *[0-9a-f]*: 6b 05 ld\.w r5,r5\[0x40\]
10828 + *[0-9a-f]*: 68 f4 ld\.w r4,r4\[0x3c\]
10829 + *[0-9a-f]*: 7c 1e ld\.w lr,lr\[0x4\]
10830 + *[0-9a-f]*: 64 dd ld\.w sp,r2\[0x34\]
10831 + *[0-9a-f]*: 62 29 ld\.w r9,r1\[0x8\]
10832 + *[0-9a-f]*: 7a f5 ld\.w r5,sp\[0x3c\]
10834 +[0-9a-f]* <ld_sh3>:
10835 + *[0-9a-f]*: 9e 0f ld\.sh pc,pc\[0x0\]
10836 + *[0-9a-f]*: 98 7c ld\.sh r12,r12\[0xe\]
10837 + *[0-9a-f]*: 8a 45 ld\.sh r5,r5\[0x8\]
10838 + *[0-9a-f]*: 88 34 ld\.sh r4,r4\[0x6\]
10839 + *[0-9a-f]*: 9c 1e ld\.sh lr,lr\[0x2\]
10840 + *[0-9a-f]*: 84 44 ld\.sh r4,r2\[0x8\]
10841 + *[0-9a-f]*: 9c 5d ld\.sh sp,lr\[0xa\]
10842 + *[0-9a-f]*: 96 12 ld\.sh r2,r11\[0x2\]
10844 +[0-9a-f]* <ld_uh3>:
10845 + *[0-9a-f]*: 9e 8f ld\.uh pc,pc\[0x0\]
10846 + *[0-9a-f]*: 98 fc ld\.uh r12,r12\[0xe\]
10847 + *[0-9a-f]*: 8a c5 ld\.uh r5,r5\[0x8\]
10848 + *[0-9a-f]*: 88 b4 ld\.uh r4,r4\[0x6\]
10849 + *[0-9a-f]*: 9c 9e ld\.uh lr,lr\[0x2\]
10850 + *[0-9a-f]*: 80 da ld\.uh r10,r0\[0xa\]
10851 + *[0-9a-f]*: 96 c8 ld\.uh r8,r11\[0x8\]
10852 + *[0-9a-f]*: 84 ea ld\.uh r10,r2\[0xc\]
10854 +[0-9a-f]* <st_w3>:
10855 + *[0-9a-f]*: 9f 0f st\.w pc\[0x0\],pc
10856 + *[0-9a-f]*: 99 fc st\.w r12\[0x3c\],r12
10857 + *[0-9a-f]*: 8b 85 st\.w r5\[0x20\],r5
10858 + *[0-9a-f]*: 89 74 st\.w r4\[0x1c\],r4
10859 + *[0-9a-f]*: 9d 1e st\.w lr\[0x4\],lr
10860 + *[0-9a-f]*: 8f bb st\.w r7\[0x2c\],r11
10861 + *[0-9a-f]*: 85 66 st\.w r2\[0x18\],r6
10862 + *[0-9a-f]*: 89 39 st\.w r4\[0xc\],r9
10864 +[0-9a-f]* <st_h3>:
10865 + *[0-9a-f]*: be 0f st\.h pc\[0x0\],pc
10866 + *[0-9a-f]*: b8 7c st\.h r12\[0xe\],r12
10867 + *[0-9a-f]*: aa 45 st\.h r5\[0x8\],r5
10868 + *[0-9a-f]*: a8 34 st\.h r4\[0x6\],r4
10869 + *[0-9a-f]*: bc 1e st\.h lr\[0x2\],lr
10870 + *[0-9a-f]*: bc 5c st\.h lr\[0xa\],r12
10871 + *[0-9a-f]*: ac 20 st\.h r6\[0x4\],r0
10872 + *[0-9a-f]*: aa 6d st\.h r5\[0xc\],sp
10874 +[0-9a-f]* <st_b3>:
10875 + *[0-9a-f]*: be 8f st\.b pc\[0x0\],pc
10876 + *[0-9a-f]*: b8 fc st\.b r12\[0x7\],r12
10877 + *[0-9a-f]*: aa c5 st\.b r5\[0x4\],r5
10878 + *[0-9a-f]*: a8 b4 st\.b r4\[0x3\],r4
10879 + *[0-9a-f]*: bc 9e st\.b lr\[0x1\],lr
10880 + *[0-9a-f]*: b8 e9 st\.b r12\[0x6\],r9
10881 + *[0-9a-f]*: a4 be st\.b r2\[0x3\],lr
10882 + *[0-9a-f]*: a2 bb st\.b r1\[0x3\],r11
10885 + *[0-9a-f]*: bf 00 ld\.d r0,pc
10886 + *[0-9a-f]*: b9 0e ld\.d lr,r12
10887 + *[0-9a-f]*: ab 08 ld\.d r8,r5
10888 + *[0-9a-f]*: a9 06 ld\.d r6,r4
10889 + *[0-9a-f]*: bd 02 ld\.d r2,lr
10890 + *[0-9a-f]*: af 0e ld\.d lr,r7
10891 + *[0-9a-f]*: a9 04 ld\.d r4,r4
10892 + *[0-9a-f]*: bf 0e ld\.d lr,pc
10894 +[0-9a-f]* <ldd_postinc>:
10895 + *[0-9a-f]*: bf 01 ld\.d r0,pc\+\+
10896 + *[0-9a-f]*: b9 0f ld\.d lr,r12\+\+
10897 + *[0-9a-f]*: ab 09 ld\.d r8,r5\+\+
10898 + *[0-9a-f]*: a9 07 ld\.d r6,r4\+\+
10899 + *[0-9a-f]*: bd 03 ld\.d r2,lr\+\+
10900 + *[0-9a-f]*: ab 0f ld\.d lr,r5\+\+
10901 + *[0-9a-f]*: b7 0d ld\.d r12,r11\+\+
10902 + *[0-9a-f]*: b9 03 ld\.d r2,r12\+\+
10904 +[0-9a-f]* <ldd_predec>:
10905 + *[0-9a-f]*: bf 10 ld\.d r0,--pc
10906 + *[0-9a-f]*: b9 1e ld\.d lr,--r12
10907 + *[0-9a-f]*: ab 18 ld\.d r8,--r5
10908 + *[0-9a-f]*: a9 16 ld\.d r6,--r4
10909 + *[0-9a-f]*: bd 12 ld\.d r2,--lr
10910 + *[0-9a-f]*: a1 18 ld\.d r8,--r0
10911 + *[0-9a-f]*: bf 1a ld\.d r10,--pc
10912 + *[0-9a-f]*: a9 12 ld\.d r2,--r4
10915 + *[0-9a-f]*: bf 11 st\.d pc,r0
10916 + *[0-9a-f]*: b9 1f st\.d r12,lr
10917 + *[0-9a-f]*: ab 19 st\.d r5,r8
10918 + *[0-9a-f]*: a9 17 st\.d r4,r6
10919 + *[0-9a-f]*: bd 13 st\.d lr,r2
10920 + *[0-9a-f]*: a1 1d st\.d r0,r12
10921 + *[0-9a-f]*: bb 15 st\.d sp,r4
10922 + *[0-9a-f]*: b9 1d st\.d r12,r12
10924 +[0-9a-f]* <std_postinc>:
10925 + *[0-9a-f]*: bf 20 st\.d pc\+\+,r0
10926 + *[0-9a-f]*: b9 2e st\.d r12\+\+,lr
10927 + *[0-9a-f]*: ab 28 st\.d r5\+\+,r8
10928 + *[0-9a-f]*: a9 26 st\.d r4\+\+,r6
10929 + *[0-9a-f]*: bd 22 st\.d lr\+\+,r2
10930 + *[0-9a-f]*: bb 26 st\.d sp\+\+,r6
10931 + *[0-9a-f]*: b5 26 st\.d r10\+\+,r6
10932 + *[0-9a-f]*: af 22 st\.d r7\+\+,r2
10934 +[0-9a-f]* <std_predec>:
10935 + *[0-9a-f]*: bf 21 st\.d --pc,r0
10936 + *[0-9a-f]*: b9 2f st\.d --r12,lr
10937 + *[0-9a-f]*: ab 29 st\.d --r5,r8
10938 + *[0-9a-f]*: a9 27 st\.d --r4,r6
10939 + *[0-9a-f]*: bd 23 st\.d --lr,r2
10940 + *[0-9a-f]*: a7 27 st\.d --r3,r6
10941 + *[0-9a-f]*: bd 23 st\.d --lr,r2
10942 + *[0-9a-f]*: a1 25 st\.d --r0,r4
10945 + *[0-9a-f]*: bf 3f mul pc,pc
10946 + *[0-9a-f]*: b9 3c mul r12,r12
10947 + *[0-9a-f]*: ab 35 mul r5,r5
10948 + *[0-9a-f]*: a9 34 mul r4,r4
10949 + *[0-9a-f]*: bd 3e mul lr,lr
10950 + *[0-9a-f]*: bd 3a mul r10,lr
10951 + *[0-9a-f]*: b1 30 mul r0,r8
10952 + *[0-9a-f]*: ab 38 mul r8,r5
10954 +[0-9a-f]* <asr_imm5>:
10955 + *[0-9a-f]*: a1 4f asr pc,0x0
10956 + *[0-9a-f]*: bf 5c asr r12,0x1f
10957 + *[0-9a-f]*: b1 45 asr r5,0x10
10958 + *[0-9a-f]*: af 54 asr r4,0xf
10959 + *[0-9a-f]*: a1 5e asr lr,0x1
10960 + *[0-9a-f]*: b7 56 asr r6,0x17
10961 + *[0-9a-f]*: b3 46 asr r6,0x12
10962 + *[0-9a-f]*: a9 45 asr r5,0x8
10964 +[0-9a-f]* <lsl_imm5>:
10965 + *[0-9a-f]*: a1 6f lsl pc,0x0
10966 + *[0-9a-f]*: bf 7c lsl r12,0x1f
10967 + *[0-9a-f]*: b1 65 lsl r5,0x10
10968 + *[0-9a-f]*: af 74 lsl r4,0xf
10969 + *[0-9a-f]*: a1 7e lsl lr,0x1
10970 + *[0-9a-f]*: ad 7c lsl r12,0xd
10971 + *[0-9a-f]*: b1 66 lsl r6,0x10
10972 + *[0-9a-f]*: b9 71 lsl r1,0x19
10974 +[0-9a-f]* <lsr_imm5>:
10975 + *[0-9a-f]*: a1 8f lsr pc,0x0
10976 + *[0-9a-f]*: bf 9c lsr r12,0x1f
10977 + *[0-9a-f]*: b1 85 lsr r5,0x10
10978 + *[0-9a-f]*: af 94 lsr r4,0xf
10979 + *[0-9a-f]*: a1 9e lsr lr,0x1
10980 + *[0-9a-f]*: a1 90 lsr r0,0x1
10981 + *[0-9a-f]*: ab 88 lsr r8,0xa
10982 + *[0-9a-f]*: bb 87 lsr r7,0x1a
10985 + *[0-9a-f]*: a1 af sbr pc,0x0
10986 + *[0-9a-f]*: bf bc sbr r12,0x1f
10987 + *[0-9a-f]*: b1 a5 sbr r5,0x10
10988 + *[0-9a-f]*: af b4 sbr r4,0xf
10989 + *[0-9a-f]*: a1 be sbr lr,0x1
10990 + *[0-9a-f]*: bf b8 sbr r8,0x1f
10991 + *[0-9a-f]*: b7 a6 sbr r6,0x16
10992 + *[0-9a-f]*: b7 b1 sbr r1,0x17
10995 + *[0-9a-f]*: a1 cf cbr pc,0x0
10996 + *[0-9a-f]*: bf dc cbr r12,0x1f
10997 + *[0-9a-f]*: b1 c5 cbr r5,0x10
10998 + *[0-9a-f]*: af d4 cbr r4,0xf
10999 + *[0-9a-f]*: a1 de cbr lr,0x1
11000 + *[0-9a-f]*: ab cc cbr r12,0xa
11001 + *[0-9a-f]*: b7 c7 cbr r7,0x16
11002 + *[0-9a-f]*: a9 d8 cbr r8,0x9
11005 + *[0-9a-f]*: c0 00 breq [0-9a-f]* <.*>
11006 + *[0-9a-f]*: cf f7 brpl [0-9a-f]* <.*>
11007 + *[0-9a-f]*: c8 04 brge [0-9a-f]* <.*>
11008 + *[0-9a-f]*: c7 f3 brcs [0-9a-f]* <.*>
11009 + *[0-9a-f]*: c0 11 brne [0-9a-f]* <.*>
11010 + *[0-9a-f]*: c7 33 brcs [0-9a-f]* <.*>
11011 + *[0-9a-f]*: cf 70 breq [0-9a-f]* <.*>
11012 + *[0-9a-f]*: c0 60 breq [0-9a-f]* <.*>
11015 + *[0-9a-f]*: c0 08 rjmp [0-9a-f]* <.*>
11016 + *[0-9a-f]*: cf fb rjmp [0-9a-f]* <.*>
11017 + *[0-9a-f]*: c0 0a rjmp [0-9a-f]* <.*>
11018 + *[0-9a-f]*: cf f9 rjmp [0-9a-f]* <.*>
11019 + *[0-9a-f]*: c0 18 rjmp [0-9a-f]* <.*>
11020 + *[0-9a-f]*: c1 fa rjmp [0-9a-f]* <.*>
11021 + *[0-9a-f]*: c0 78 rjmp [0-9a-f]* <.*>
11022 + *[0-9a-f]*: cf ea rjmp [0-9a-f]* <.*>
11024 +[0-9a-f]* <rcall1>:
11025 + *[0-9a-f]*: c0 0c rcall [0-9a-f]* <.*>
11026 + *[0-9a-f]*: cf ff rcall [0-9a-f]* <.*>
11027 + *[0-9a-f]*: c0 0e rcall [0-9a-f]* <.*>
11028 + *[0-9a-f]*: cf fd rcall [0-9a-f]* <.*>
11029 + *[0-9a-f]*: c0 1c rcall [0-9a-f]* <.*>
11030 + *[0-9a-f]*: c6 cc rcall [0-9a-f]* <.*>
11031 + *[0-9a-f]*: cf 7e rcall [0-9a-f]* <.*>
11032 + *[0-9a-f]*: c1 ae rcall [0-9a-f]* <.*>
11034 +[0-9a-f]* <acall>:
11035 + *[0-9a-f]*: d0 00 acall 0x0
11036 + *[0-9a-f]*: df f0 acall 0x3fc
11037 + *[0-9a-f]*: d8 00 acall 0x200
11038 + *[0-9a-f]*: d7 f0 acall 0x1fc
11039 + *[0-9a-f]*: d0 10 acall 0x4
11040 + *[0-9a-f]*: d5 90 acall 0x164
11041 + *[0-9a-f]*: d4 c0 acall 0x130
11042 + *[0-9a-f]*: d2 b0 acall 0xac
11044 +[0-9a-f]* <scall>:
11045 + *[0-9a-f]*: d7 33 scall
11046 + *[0-9a-f]*: d7 33 scall
11047 + *[0-9a-f]*: d7 33 scall
11048 + *[0-9a-f]*: d7 33 scall
11049 + *[0-9a-f]*: d7 33 scall
11050 + *[0-9a-f]*: d7 33 scall
11051 + *[0-9a-f]*: d7 33 scall
11052 + *[0-9a-f]*: d7 33 scall
11055 + *[0-9a-f]*: d8 02 popm pc
11056 + *[0-9a-f]*: dd fa popm r0-r11,pc,r12=-1
11057 + *[0-9a-f]*: d4 02 popm lr
11058 + *[0-9a-f]*: db fa popm r0-r11,pc,r12=1
11059 + *[0-9a-f]*: d0 12 popm r0-r3
11060 + *[0-9a-f]*: d8 e2 popm r4-r10,pc
11061 + *[0-9a-f]*: d9 1a popm r0-r3,r11,pc,r12=0
11062 + *[0-9a-f]*: d7 b2 popm r0-r7,r10-r12,lr
11064 +[0-9a-f]* <pushm>:
11065 + *[0-9a-f]*: d8 01 pushm pc
11066 + *[0-9a-f]*: df f1 pushm r0-r12,lr-pc
11067 + *[0-9a-f]*: d8 01 pushm pc
11068 + *[0-9a-f]*: d7 f1 pushm r0-r12,lr
11069 + *[0-9a-f]*: d0 11 pushm r0-r3
11070 + *[0-9a-f]*: dc c1 pushm r8-r10,lr-pc
11071 + *[0-9a-f]*: d0 91 pushm r0-r3,r10
11072 + *[0-9a-f]*: d2 41 pushm r8-r9,r12
11074 +[0-9a-f]* <popm_n>:
11084 +[0-9a-f]* <pushm_n>:
11094 +[0-9a-f]* <csrfcz>:
11095 + *[0-9a-f]*: d0 03 csrfcz 0x0
11096 + *[0-9a-f]*: d1 f3 csrfcz 0x1f
11097 + *[0-9a-f]*: d1 03 csrfcz 0x10
11098 + *[0-9a-f]*: d0 f3 csrfcz 0xf
11099 + *[0-9a-f]*: d0 13 csrfcz 0x1
11100 + *[0-9a-f]*: d0 53 csrfcz 0x5
11101 + *[0-9a-f]*: d0 d3 csrfcz 0xd
11102 + *[0-9a-f]*: d1 73 csrfcz 0x17
11105 + *[0-9a-f]*: d2 03 ssrf 0x0
11106 + *[0-9a-f]*: d3 f3 ssrf 0x1f
11107 + *[0-9a-f]*: d3 03 ssrf 0x10
11108 + *[0-9a-f]*: d2 f3 ssrf 0xf
11109 + *[0-9a-f]*: d2 13 ssrf 0x1
11110 + *[0-9a-f]*: d3 d3 ssrf 0x1d
11111 + *[0-9a-f]*: d2 d3 ssrf 0xd
11112 + *[0-9a-f]*: d2 d3 ssrf 0xd
11115 + *[0-9a-f]*: d4 03 csrf 0x0
11116 + *[0-9a-f]*: d5 f3 csrf 0x1f
11117 + *[0-9a-f]*: d5 03 csrf 0x10
11118 + *[0-9a-f]*: d4 f3 csrf 0xf
11119 + *[0-9a-f]*: d4 13 csrf 0x1
11120 + *[0-9a-f]*: d4 a3 csrf 0xa
11121 + *[0-9a-f]*: d4 f3 csrf 0xf
11122 + *[0-9a-f]*: d4 b3 csrf 0xb
11125 + *[0-9a-f]*: d6 03 rete
11128 + *[0-9a-f]*: d6 13 rets
11131 + *[0-9a-f]*: d6 23 retd
11134 + *[0-9a-f]*: d6 33 retj
11137 + *[0-9a-f]*: d6 43 tlbr
11140 + *[0-9a-f]*: d6 53 tlbs
11143 + *[0-9a-f]*: d6 63 tlbw
11145 +[0-9a-f]* <breakpoint>:
11146 + *[0-9a-f]*: d6 73 breakpoint
11148 +[0-9a-f]* <incjosp>:
11149 + *[0-9a-f]*: d6 83 incjosp 1
11150 + *[0-9a-f]*: d6 93 incjosp 2
11151 + *[0-9a-f]*: d6 a3 incjosp 3
11152 + *[0-9a-f]*: d6 b3 incjosp 4
11153 + *[0-9a-f]*: d6 c3 incjosp -4
11154 + *[0-9a-f]*: d6 d3 incjosp -3
11155 + *[0-9a-f]*: d6 e3 incjosp -2
11156 + *[0-9a-f]*: d6 f3 incjosp -1
11159 + *[0-9a-f]*: d7 03 nop
11161 +[0-9a-f]* <popjc>:
11162 + *[0-9a-f]*: d7 13 popjc
11164 +[0-9a-f]* <pushjc>:
11165 + *[0-9a-f]*: d7 23 pushjc
11168 + *[0-9a-f]*: fe 0f 00 0f add pc,pc,pc
11169 + *[0-9a-f]*: f8 0c 00 3c add r12,r12,r12<<0x3
11170 + *[0-9a-f]*: ea 05 00 25 add r5,r5,r5<<0x2
11171 + *[0-9a-f]*: e8 04 00 14 add r4,r4,r4<<0x1
11172 + *[0-9a-f]*: fc 0e 00 1e add lr,lr,lr<<0x1
11173 + *[0-9a-f]*: f8 00 00 10 add r0,r12,r0<<0x1
11174 + *[0-9a-f]*: f8 04 00 09 add r9,r12,r4
11175 + *[0-9a-f]*: f8 07 00 2c add r12,r12,r7<<0x2
11178 + *[0-9a-f]*: fe 0f 01 0f sub pc,pc,pc
11179 + *[0-9a-f]*: f8 0c 01 3c sub r12,r12,r12<<0x3
11180 + *[0-9a-f]*: ea 05 01 25 sub r5,r5,r5<<0x2
11181 + *[0-9a-f]*: e8 04 01 14 sub r4,r4,r4<<0x1
11182 + *[0-9a-f]*: fc 0e 01 1e sub lr,lr,lr<<0x1
11183 + *[0-9a-f]*: e6 04 01 0d sub sp,r3,r4
11184 + *[0-9a-f]*: ee 03 01 03 sub r3,r7,r3
11185 + *[0-9a-f]*: f4 0d 01 1d sub sp,r10,sp<<0x1
11188 + *[0-9a-f]*: fe 0f 0d 0f divu pc,pc,pc
11189 + *[0-9a-f]*: f8 0c 0d 0c divu r12,r12,r12
11190 + *[0-9a-f]*: ea 05 0d 05 divu r5,r5,r5
11191 + *[0-9a-f]*: e8 04 0d 04 divu r4,r4,r4
11192 + *[0-9a-f]*: fc 0e 0d 0e divu lr,lr,lr
11193 + *[0-9a-f]*: e8 0f 0d 0d divu sp,r4,pc
11194 + *[0-9a-f]*: ea 0d 0d 05 divu r5,r5,sp
11195 + *[0-9a-f]*: fa 00 0d 0a divu r10,sp,r0
11197 +[0-9a-f]* <addhh_w>:
11198 + *[0-9a-f]*: fe 0f 0e 0f addhh\.w pc,pc:b,pc:b
11199 + *[0-9a-f]*: f8 0c 0e 3c addhh\.w r12,r12:t,r12:t
11200 + *[0-9a-f]*: ea 05 0e 35 addhh\.w r5,r5:t,r5:t
11201 + *[0-9a-f]*: e8 04 0e 04 addhh\.w r4,r4:b,r4:b
11202 + *[0-9a-f]*: fc 0e 0e 3e addhh\.w lr,lr:t,lr:t
11203 + *[0-9a-f]*: e0 03 0e 00 addhh\.w r0,r0:b,r3:b
11204 + *[0-9a-f]*: f8 07 0e 2e addhh\.w lr,r12:t,r7:b
11205 + *[0-9a-f]*: f4 02 0e 23 addhh\.w r3,r10:t,r2:b
11207 +[0-9a-f]* <subhh_w>:
11208 + *[0-9a-f]*: fe 0f 0f 0f subhh\.w pc,pc:b,pc:b
11209 + *[0-9a-f]*: f8 0c 0f 3c subhh\.w r12,r12:t,r12:t
11210 + *[0-9a-f]*: ea 05 0f 35 subhh\.w r5,r5:t,r5:t
11211 + *[0-9a-f]*: e8 04 0f 04 subhh\.w r4,r4:b,r4:b
11212 + *[0-9a-f]*: fc 0e 0f 3e subhh\.w lr,lr:t,lr:t
11213 + *[0-9a-f]*: e2 07 0f 2a subhh\.w r10,r1:t,r7:b
11214 + *[0-9a-f]*: f4 0e 0f 3f subhh\.w pc,r10:t,lr:t
11215 + *[0-9a-f]*: e0 0c 0f 23 subhh\.w r3,r0:t,r12:b
11218 + *[0-9a-f]*: fe 0f 00 4f adc pc,pc,pc
11219 + *[0-9a-f]*: f8 0c 00 4c adc r12,r12,r12
11220 + *[0-9a-f]*: ea 05 00 45 adc r5,r5,r5
11221 + *[0-9a-f]*: e8 04 00 44 adc r4,r4,r4
11222 + *[0-9a-f]*: fc 0e 00 4e adc lr,lr,lr
11223 + *[0-9a-f]*: e0 07 00 44 adc r4,r0,r7
11224 + *[0-9a-f]*: e8 03 00 4d adc sp,r4,r3
11225 + *[0-9a-f]*: f8 00 00 42 adc r2,r12,r0
11228 + *[0-9a-f]*: fe 0f 01 4f sbc pc,pc,pc
11229 + *[0-9a-f]*: f8 0c 01 4c sbc r12,r12,r12
11230 + *[0-9a-f]*: ea 05 01 45 sbc r5,r5,r5
11231 + *[0-9a-f]*: e8 04 01 44 sbc r4,r4,r4
11232 + *[0-9a-f]*: fc 0e 01 4e sbc lr,lr,lr
11233 + *[0-9a-f]*: ee 09 01 46 sbc r6,r7,r9
11234 + *[0-9a-f]*: f0 05 01 40 sbc r0,r8,r5
11235 + *[0-9a-f]*: e0 04 01 41 sbc r1,r0,r4
11237 +[0-9a-f]* <mul_2>:
11238 + *[0-9a-f]*: fe 0f 02 4f mul pc,pc,pc
11239 + *[0-9a-f]*: f8 0c 02 4c mul r12,r12,r12
11240 + *[0-9a-f]*: ea 05 02 45 mul r5,r5,r5
11241 + *[0-9a-f]*: e8 04 02 44 mul r4,r4,r4
11242 + *[0-9a-f]*: fc 0e 02 4e mul lr,lr,lr
11243 + *[0-9a-f]*: e0 00 02 4f mul pc,r0,r0
11244 + *[0-9a-f]*: fe 0e 02 48 mul r8,pc,lr
11245 + *[0-9a-f]*: f8 0f 02 44 mul r4,r12,pc
11248 + *[0-9a-f]*: fe 0f 03 4f mac pc,pc,pc
11249 + *[0-9a-f]*: f8 0c 03 4c mac r12,r12,r12
11250 + *[0-9a-f]*: ea 05 03 45 mac r5,r5,r5
11251 + *[0-9a-f]*: e8 04 03 44 mac r4,r4,r4
11252 + *[0-9a-f]*: fc 0e 03 4e mac lr,lr,lr
11253 + *[0-9a-f]*: e8 00 03 4a mac r10,r4,r0
11254 + *[0-9a-f]*: fc 00 03 47 mac r7,lr,r0
11255 + *[0-9a-f]*: f2 0c 03 42 mac r2,r9,r12
11257 +[0-9a-f]* <mulsd>:
11258 + *[0-9a-f]*: fe 0f 04 4f muls\.d pc,pc,pc
11259 + *[0-9a-f]*: f8 0c 04 4c muls\.d r12,r12,r12
11260 + *[0-9a-f]*: ea 05 04 45 muls\.d r5,r5,r5
11261 + *[0-9a-f]*: e8 04 04 44 muls\.d r4,r4,r4
11262 + *[0-9a-f]*: fc 0e 04 4e muls\.d lr,lr,lr
11263 + *[0-9a-f]*: f0 0e 04 42 muls\.d r2,r8,lr
11264 + *[0-9a-f]*: e0 0b 04 44 muls\.d r4,r0,r11
11265 + *[0-9a-f]*: fc 06 04 45 muls\.d r5,lr,r6
11267 +[0-9a-f]* <macsd>:
11268 + *[0-9a-f]*: fe 0f 05 40 macs\.d r0,pc,pc
11269 + *[0-9a-f]*: f8 0c 05 4e macs\.d lr,r12,r12
11270 + *[0-9a-f]*: ea 05 05 48 macs\.d r8,r5,r5
11271 + *[0-9a-f]*: e8 04 05 46 macs\.d r6,r4,r4
11272 + *[0-9a-f]*: fc 0e 05 42 macs\.d r2,lr,lr
11273 + *[0-9a-f]*: e2 09 05 48 macs\.d r8,r1,r9
11274 + *[0-9a-f]*: f0 08 05 4e macs\.d lr,r8,r8
11275 + *[0-9a-f]*: e6 0c 05 44 macs\.d r4,r3,r12
11277 +[0-9a-f]* <mulud>:
11278 + *[0-9a-f]*: fe 0f 06 40 mulu\.d r0,pc,pc
11279 + *[0-9a-f]*: f8 0c 06 4e mulu\.d lr,r12,r12
11280 + *[0-9a-f]*: ea 05 06 48 mulu\.d r8,r5,r5
11281 + *[0-9a-f]*: e8 04 06 46 mulu\.d r6,r4,r4
11282 + *[0-9a-f]*: fc 0e 06 42 mulu\.d r2,lr,lr
11283 + *[0-9a-f]*: ea 00 06 46 mulu\.d r6,r5,r0
11284 + *[0-9a-f]*: ec 01 06 44 mulu\.d r4,r6,r1
11285 + *[0-9a-f]*: f0 02 06 48 mulu\.d r8,r8,r2
11287 +[0-9a-f]* <macud>:
11288 + *[0-9a-f]*: fe 0f 07 40 macu\.d r0,pc,pc
11289 + *[0-9a-f]*: f8 0c 07 4e macu\.d lr,r12,r12
11290 + *[0-9a-f]*: ea 05 07 48 macu\.d r8,r5,r5
11291 + *[0-9a-f]*: e8 04 07 46 macu\.d r6,r4,r4
11292 + *[0-9a-f]*: fc 0e 07 42 macu\.d r2,lr,lr
11293 + *[0-9a-f]*: fa 0b 07 46 macu\.d r6,sp,r11
11294 + *[0-9a-f]*: e8 08 07 42 macu\.d r2,r4,r8
11295 + *[0-9a-f]*: f4 09 07 46 macu\.d r6,r10,r9
11297 +[0-9a-f]* <asr_1>:
11298 + *[0-9a-f]*: fe 0f 08 4f asr pc,pc,pc
11299 + *[0-9a-f]*: f8 0c 08 4c asr r12,r12,r12
11300 + *[0-9a-f]*: ea 05 08 45 asr r5,r5,r5
11301 + *[0-9a-f]*: e8 04 08 44 asr r4,r4,r4
11302 + *[0-9a-f]*: fc 0e 08 4e asr lr,lr,lr
11303 + *[0-9a-f]*: ec 0f 08 4f asr pc,r6,pc
11304 + *[0-9a-f]*: ec 0c 08 40 asr r0,r6,r12
11305 + *[0-9a-f]*: fa 00 08 44 asr r4,sp,r0
11307 +[0-9a-f]* <lsl_1>:
11308 + *[0-9a-f]*: fe 0f 09 4f lsl pc,pc,pc
11309 + *[0-9a-f]*: f8 0c 09 4c lsl r12,r12,r12
11310 + *[0-9a-f]*: ea 05 09 45 lsl r5,r5,r5
11311 + *[0-9a-f]*: e8 04 09 44 lsl r4,r4,r4
11312 + *[0-9a-f]*: fc 0e 09 4e lsl lr,lr,lr
11313 + *[0-9a-f]*: ea 0e 09 4e lsl lr,r5,lr
11314 + *[0-9a-f]*: fe 03 09 45 lsl r5,pc,r3
11315 + *[0-9a-f]*: fe 09 09 41 lsl r1,pc,r9
11317 +[0-9a-f]* <lsr_1>:
11318 + *[0-9a-f]*: fe 0f 0a 4f lsr pc,pc,pc
11319 + *[0-9a-f]*: f8 0c 0a 4c lsr r12,r12,r12
11320 + *[0-9a-f]*: ea 05 0a 45 lsr r5,r5,r5
11321 + *[0-9a-f]*: e8 04 0a 44 lsr r4,r4,r4
11322 + *[0-9a-f]*: fc 0e 0a 4e lsr lr,lr,lr
11323 + *[0-9a-f]*: e8 01 0a 42 lsr r2,r4,r1
11324 + *[0-9a-f]*: e2 06 0a 45 lsr r5,r1,r6
11325 + *[0-9a-f]*: ec 07 0a 4d lsr sp,r6,r7
11328 + *[0-9a-f]*: fe 0f 0b 4f xchg pc,pc,pc
11329 + *[0-9a-f]*: f8 0c 0b 4c xchg r12,r12,r12
11330 + *[0-9a-f]*: ea 05 0b 45 xchg r5,r5,r5
11331 + *[0-9a-f]*: e8 04 0b 44 xchg r4,r4,r4
11332 + *[0-9a-f]*: fc 0e 0b 4e xchg lr,lr,lr
11333 + *[0-9a-f]*: e8 0d 0b 4e xchg lr,r4,sp
11334 + *[0-9a-f]*: ea 0c 0b 41 xchg r1,r5,r12
11335 + *[0-9a-f]*: f8 00 0b 4e xchg lr,r12,r0
11338 + *[0-9a-f]*: fe 0f 0c 4f max pc,pc,pc
11339 + *[0-9a-f]*: f8 0c 0c 4c max r12,r12,r12
11340 + *[0-9a-f]*: ea 05 0c 45 max r5,r5,r5
11341 + *[0-9a-f]*: e8 04 0c 44 max r4,r4,r4
11342 + *[0-9a-f]*: fc 0e 0c 4e max lr,lr,lr
11343 + *[0-9a-f]*: e4 0d 0c 4e max lr,r2,sp
11344 + *[0-9a-f]*: f4 09 0c 44 max r4,r10,r9
11345 + *[0-9a-f]*: f2 0e 0c 4e max lr,r9,lr
11348 + *[0-9a-f]*: fe 0f 0d 4f min pc,pc,pc
11349 + *[0-9a-f]*: f8 0c 0d 4c min r12,r12,r12
11350 + *[0-9a-f]*: ea 05 0d 45 min r5,r5,r5
11351 + *[0-9a-f]*: e8 04 0d 44 min r4,r4,r4
11352 + *[0-9a-f]*: fc 0e 0d 4e min lr,lr,lr
11353 + *[0-9a-f]*: ee 08 0d 49 min r9,r7,r8
11354 + *[0-9a-f]*: ea 05 0d 4d min sp,r5,r5
11355 + *[0-9a-f]*: e2 04 0d 44 min r4,r1,r4
11357 +[0-9a-f]* <addabs>:
11358 + *[0-9a-f]*: fe 0f 0e 4f addabs pc,pc,pc
11359 + *[0-9a-f]*: f8 0c 0e 4c addabs r12,r12,r12
11360 + *[0-9a-f]*: ea 05 0e 45 addabs r5,r5,r5
11361 + *[0-9a-f]*: e8 04 0e 44 addabs r4,r4,r4
11362 + *[0-9a-f]*: fc 0e 0e 4e addabs lr,lr,lr
11363 + *[0-9a-f]*: f4 00 0e 47 addabs r7,r10,r0
11364 + *[0-9a-f]*: f2 07 0e 49 addabs r9,r9,r7
11365 + *[0-9a-f]*: f0 0c 0e 42 addabs r2,r8,r12
11367 +[0-9a-f]* <mulnhh_w>:
11368 + *[0-9a-f]*: fe 0f 01 8f mulnhh\.w pc,pc:b,pc:b
11369 + *[0-9a-f]*: f8 0c 01 bc mulnhh\.w r12,r12:t,r12:t
11370 + *[0-9a-f]*: ea 05 01 b5 mulnhh\.w r5,r5:t,r5:t
11371 + *[0-9a-f]*: e8 04 01 84 mulnhh\.w r4,r4:b,r4:b
11372 + *[0-9a-f]*: fc 0e 01 be mulnhh\.w lr,lr:t,lr:t
11373 + *[0-9a-f]*: fa 09 01 ab mulnhh\.w r11,sp:t,r9:b
11374 + *[0-9a-f]*: e8 0e 01 9d mulnhh\.w sp,r4:b,lr:t
11375 + *[0-9a-f]*: e4 0b 01 ac mulnhh\.w r12,r2:t,r11:b
11377 +[0-9a-f]* <mulnwh_d>:
11378 + *[0-9a-f]*: fe 0f 02 80 mulnwh\.d r0,pc,pc:b
11379 + *[0-9a-f]*: f8 0c 02 9e mulnwh\.d lr,r12,r12:t
11380 + *[0-9a-f]*: ea 05 02 98 mulnwh\.d r8,r5,r5:t
11381 + *[0-9a-f]*: e8 04 02 86 mulnwh\.d r6,r4,r4:b
11382 + *[0-9a-f]*: fc 0e 02 92 mulnwh\.d r2,lr,lr:t
11383 + *[0-9a-f]*: e6 02 02 9e mulnwh\.d lr,r3,r2:t
11384 + *[0-9a-f]*: ea 09 02 84 mulnwh\.d r4,r5,r9:b
11385 + *[0-9a-f]*: e8 04 02 9c mulnwh\.d r12,r4,r4:t
11387 +[0-9a-f]* <machh_w>:
11388 + *[0-9a-f]*: fe 0f 04 8f machh\.w pc,pc:b,pc:b
11389 + *[0-9a-f]*: f8 0c 04 bc machh\.w r12,r12:t,r12:t
11390 + *[0-9a-f]*: ea 05 04 b5 machh\.w r5,r5:t,r5:t
11391 + *[0-9a-f]*: e8 04 04 84 machh\.w r4,r4:b,r4:b
11392 + *[0-9a-f]*: fc 0e 04 be machh\.w lr,lr:t,lr:t
11393 + *[0-9a-f]*: ea 01 04 9e machh\.w lr,r5:b,r1:t
11394 + *[0-9a-f]*: ec 07 04 89 machh\.w r9,r6:b,r7:b
11395 + *[0-9a-f]*: fc 0c 04 a5 machh\.w r5,lr:t,r12:b
11397 +[0-9a-f]* <machh_d>:
11398 + *[0-9a-f]*: fe 0f 05 80 machh\.d r0,pc:b,pc:b
11399 + *[0-9a-f]*: f8 0c 05 be machh\.d lr,r12:t,r12:t
11400 + *[0-9a-f]*: ea 05 05 b8 machh\.d r8,r5:t,r5:t
11401 + *[0-9a-f]*: e8 04 05 86 machh\.d r6,r4:b,r4:b
11402 + *[0-9a-f]*: fc 0e 05 b2 machh\.d r2,lr:t,lr:t
11403 + *[0-9a-f]*: e0 08 05 8a machh\.d r10,r0:b,r8:b
11404 + *[0-9a-f]*: e8 05 05 9e machh\.d lr,r4:b,r5:t
11405 + *[0-9a-f]*: e0 04 05 98 machh\.d r8,r0:b,r4:t
11407 +[0-9a-f]* <macsathh_w>:
11408 + *[0-9a-f]*: fe 0f 06 8f macsathh\.w pc,pc:b,pc:b
11409 + *[0-9a-f]*: f8 0c 06 bc macsathh\.w r12,r12:t,r12:t
11410 + *[0-9a-f]*: ea 05 06 b5 macsathh\.w r5,r5:t,r5:t
11411 + *[0-9a-f]*: e8 04 06 84 macsathh\.w r4,r4:b,r4:b
11412 + *[0-9a-f]*: fc 0e 06 be macsathh\.w lr,lr:t,lr:t
11413 + *[0-9a-f]*: ee 0f 06 b7 macsathh\.w r7,r7:t,pc:t
11414 + *[0-9a-f]*: e4 04 06 a4 macsathh\.w r4,r2:t,r4:b
11415 + *[0-9a-f]*: f0 03 06 b4 macsathh\.w r4,r8:t,r3:t
11417 +[0-9a-f]* <mulhh_w>:
11418 + *[0-9a-f]*: fe 0f 07 8f mulhh\.w pc,pc:b,pc:b
11419 + *[0-9a-f]*: f8 0c 07 bc mulhh\.w r12,r12:t,r12:t
11420 + *[0-9a-f]*: ea 05 07 b5 mulhh\.w r5,r5:t,r5:t
11421 + *[0-9a-f]*: e8 04 07 84 mulhh\.w r4,r4:b,r4:b
11422 + *[0-9a-f]*: fc 0e 07 be mulhh\.w lr,lr:t,lr:t
11423 + *[0-9a-f]*: e8 09 07 a7 mulhh\.w r7,r4:t,r9:b
11424 + *[0-9a-f]*: e6 07 07 bf mulhh\.w pc,r3:t,r7:t
11425 + *[0-9a-f]*: e8 09 07 9f mulhh\.w pc,r4:b,r9:t
11427 +[0-9a-f]* <mulsathh_h>:
11428 + *[0-9a-f]*: fe 0f 08 8f mulsathh\.h pc,pc:b,pc:b
11429 + *[0-9a-f]*: f8 0c 08 bc mulsathh\.h r12,r12:t,r12:t
11430 + *[0-9a-f]*: ea 05 08 b5 mulsathh\.h r5,r5:t,r5:t
11431 + *[0-9a-f]*: e8 04 08 84 mulsathh\.h r4,r4:b,r4:b
11432 + *[0-9a-f]*: fc 0e 08 be mulsathh\.h lr,lr:t,lr:t
11433 + *[0-9a-f]*: e2 0d 08 83 mulsathh\.h r3,r1:b,sp:b
11434 + *[0-9a-f]*: fc 0b 08 ab mulsathh\.h r11,lr:t,r11:b
11435 + *[0-9a-f]*: f0 0b 08 98 mulsathh\.h r8,r8:b,r11:t
11437 +[0-9a-f]* <mulsathh_w>:
11438 + *[0-9a-f]*: fe 0f 09 8f mulsathh\.w pc,pc:b,pc:b
11439 + *[0-9a-f]*: f8 0c 09 bc mulsathh\.w r12,r12:t,r12:t
11440 + *[0-9a-f]*: ea 05 09 b5 mulsathh\.w r5,r5:t,r5:t
11441 + *[0-9a-f]*: e8 04 09 84 mulsathh\.w r4,r4:b,r4:b
11442 + *[0-9a-f]*: fc 0e 09 be mulsathh\.w lr,lr:t,lr:t
11443 + *[0-9a-f]*: f6 06 09 ae mulsathh\.w lr,r11:t,r6:b
11444 + *[0-9a-f]*: ec 07 09 96 mulsathh\.w r6,r6:b,r7:t
11445 + *[0-9a-f]*: e4 03 09 8a mulsathh\.w r10,r2:b,r3:b
11447 +[0-9a-f]* <mulsatrndhh_h>:
11448 + *[0-9a-f]*: fe 0f 0a 8f mulsatrndhh\.h pc,pc:b,pc:b
11449 + *[0-9a-f]*: f8 0c 0a bc mulsatrndhh\.h r12,r12:t,r12:t
11450 + *[0-9a-f]*: ea 05 0a b5 mulsatrndhh\.h r5,r5:t,r5:t
11451 + *[0-9a-f]*: e8 04 0a 84 mulsatrndhh\.h r4,r4:b,r4:b
11452 + *[0-9a-f]*: fc 0e 0a be mulsatrndhh\.h lr,lr:t,lr:t
11453 + *[0-9a-f]*: ec 09 0a 8b mulsatrndhh\.h r11,r6:b,r9:b
11454 + *[0-9a-f]*: e6 08 0a 9b mulsatrndhh\.h r11,r3:b,r8:t
11455 + *[0-9a-f]*: fa 07 0a b5 mulsatrndhh\.h r5,sp:t,r7:t
11457 +[0-9a-f]* <mulsatrndwh_w>:
11458 + *[0-9a-f]*: fe 0f 0b 8f mulsatrndwh\.w pc,pc,pc:b
11459 + *[0-9a-f]*: f8 0c 0b 9c mulsatrndwh\.w r12,r12,r12:t
11460 + *[0-9a-f]*: ea 05 0b 95 mulsatrndwh\.w r5,r5,r5:t
11461 + *[0-9a-f]*: e8 04 0b 84 mulsatrndwh\.w r4,r4,r4:b
11462 + *[0-9a-f]*: fc 0e 0b 9e mulsatrndwh\.w lr,lr,lr:t
11463 + *[0-9a-f]*: f8 00 0b 85 mulsatrndwh\.w r5,r12,r0:b
11464 + *[0-9a-f]*: f4 0f 0b 87 mulsatrndwh\.w r7,r10,pc:b
11465 + *[0-9a-f]*: f0 05 0b 9a mulsatrndwh\.w r10,r8,r5:t
11467 +[0-9a-f]* <macwh_d>:
11468 + *[0-9a-f]*: fe 0f 0c 80 macwh\.d r0,pc,pc:b
11469 + *[0-9a-f]*: f8 0c 0c 9e macwh\.d lr,r12,r12:t
11470 + *[0-9a-f]*: ea 05 0c 98 macwh\.d r8,r5,r5:t
11471 + *[0-9a-f]*: e8 04 0c 86 macwh\.d r6,r4,r4:b
11472 + *[0-9a-f]*: fc 0e 0c 92 macwh\.d r2,lr,lr:t
11473 + *[0-9a-f]*: f4 0c 0c 94 macwh\.d r4,r10,r12:t
11474 + *[0-9a-f]*: ee 0d 0c 84 macwh\.d r4,r7,sp:b
11475 + *[0-9a-f]*: f2 0b 0c 8e macwh\.d lr,r9,r11:b
11477 +[0-9a-f]* <mulwh_d>:
11478 + *[0-9a-f]*: fe 0f 0d 80 mulwh\.d r0,pc,pc:b
11479 + *[0-9a-f]*: f8 0c 0d 9e mulwh\.d lr,r12,r12:t
11480 + *[0-9a-f]*: ea 05 0d 98 mulwh\.d r8,r5,r5:t
11481 + *[0-9a-f]*: e8 04 0d 86 mulwh\.d r6,r4,r4:b
11482 + *[0-9a-f]*: fc 0e 0d 92 mulwh\.d r2,lr,lr:t
11483 + *[0-9a-f]*: ea 01 0d 8c mulwh\.d r12,r5,r1:b
11484 + *[0-9a-f]*: e2 03 0d 90 mulwh\.d r0,r1,r3:t
11485 + *[0-9a-f]*: f2 02 0d 80 mulwh\.d r0,r9,r2:b
11487 +[0-9a-f]* <mulsatwh_w>:
11488 + *[0-9a-f]*: fe 0f 0e 8f mulsatwh\.w pc,pc,pc:b
11489 + *[0-9a-f]*: f8 0c 0e 9c mulsatwh\.w r12,r12,r12:t
11490 + *[0-9a-f]*: ea 05 0e 95 mulsatwh\.w r5,r5,r5:t
11491 + *[0-9a-f]*: e8 04 0e 84 mulsatwh\.w r4,r4,r4:b
11492 + *[0-9a-f]*: fc 0e 0e 9e mulsatwh\.w lr,lr,lr:t
11493 + *[0-9a-f]*: fe 0a 0e 9b mulsatwh\.w r11,pc,r10:t
11494 + *[0-9a-f]*: f8 09 0e 9d mulsatwh\.w sp,r12,r9:t
11495 + *[0-9a-f]*: e6 02 0e 90 mulsatwh\.w r0,r3,r2:t
11498 + *[0-9a-f]*: fe 0f 0f 8f ld\.w pc,pc\[pc:b<<2\]
11499 + *[0-9a-f]*: f8 0c 0f bc ld\.w r12,r12\[r12:t<<2\]
11500 + *[0-9a-f]*: ea 05 0f a5 ld\.w r5,r5\[r5:u<<2\]
11501 + *[0-9a-f]*: e8 04 0f 94 ld\.w r4,r4\[r4:l<<2\]
11502 + *[0-9a-f]*: fc 0e 0f 9e ld\.w lr,lr\[lr:l<<2\]
11503 + *[0-9a-f]*: f4 06 0f 99 ld\.w r9,r10\[r6:l<<2\]
11504 + *[0-9a-f]*: f4 0a 0f 82 ld\.w r2,r10\[r10:b<<2\]
11505 + *[0-9a-f]*: ea 0f 0f 8b ld\.w r11,r5\[pc:b<<2\]
11507 +[0-9a-f]* <satadd_w>:
11508 + *[0-9a-f]*: fe 0f 00 cf satadd\.w pc,pc,pc
11509 + *[0-9a-f]*: f8 0c 00 cc satadd\.w r12,r12,r12
11510 + *[0-9a-f]*: ea 05 00 c5 satadd\.w r5,r5,r5
11511 + *[0-9a-f]*: e8 04 00 c4 satadd\.w r4,r4,r4
11512 + *[0-9a-f]*: fc 0e 00 ce satadd\.w lr,lr,lr
11513 + *[0-9a-f]*: f0 0b 00 c4 satadd\.w r4,r8,r11
11514 + *[0-9a-f]*: f8 06 00 c3 satadd\.w r3,r12,r6
11515 + *[0-9a-f]*: fc 09 00 c3 satadd\.w r3,lr,r9
11517 +[0-9a-f]* <satsub_w1>:
11518 + *[0-9a-f]*: fe 0f 01 cf satsub\.w pc,pc,pc
11519 + *[0-9a-f]*: f8 0c 01 cc satsub\.w r12,r12,r12
11520 + *[0-9a-f]*: ea 05 01 c5 satsub\.w r5,r5,r5
11521 + *[0-9a-f]*: e8 04 01 c4 satsub\.w r4,r4,r4
11522 + *[0-9a-f]*: fc 0e 01 ce satsub\.w lr,lr,lr
11523 + *[0-9a-f]*: fa 00 01 c8 satsub\.w r8,sp,r0
11524 + *[0-9a-f]*: f0 04 01 c9 satsub\.w r9,r8,r4
11525 + *[0-9a-f]*: fc 02 01 cf satsub\.w pc,lr,r2
11527 +[0-9a-f]* <satadd_h>:
11528 + *[0-9a-f]*: fe 0f 02 cf satadd\.h pc,pc,pc
11529 + *[0-9a-f]*: f8 0c 02 cc satadd\.h r12,r12,r12
11530 + *[0-9a-f]*: ea 05 02 c5 satadd\.h r5,r5,r5
11531 + *[0-9a-f]*: e8 04 02 c4 satadd\.h r4,r4,r4
11532 + *[0-9a-f]*: fc 0e 02 ce satadd\.h lr,lr,lr
11533 + *[0-9a-f]*: e6 09 02 c7 satadd\.h r7,r3,r9
11534 + *[0-9a-f]*: e0 02 02 c1 satadd\.h r1,r0,r2
11535 + *[0-9a-f]*: e8 0e 02 c1 satadd\.h r1,r4,lr
11537 +[0-9a-f]* <satsub_h>:
11538 + *[0-9a-f]*: fe 0f 03 cf satsub\.h pc,pc,pc
11539 + *[0-9a-f]*: f8 0c 03 cc satsub\.h r12,r12,r12
11540 + *[0-9a-f]*: ea 05 03 c5 satsub\.h r5,r5,r5
11541 + *[0-9a-f]*: e8 04 03 c4 satsub\.h r4,r4,r4
11542 + *[0-9a-f]*: fc 0e 03 ce satsub\.h lr,lr,lr
11543 + *[0-9a-f]*: fc 03 03 ce satsub\.h lr,lr,r3
11544 + *[0-9a-f]*: ec 05 03 cb satsub\.h r11,r6,r5
11545 + *[0-9a-f]*: fa 00 03 c3 satsub\.h r3,sp,r0
11548 + *[0-9a-f]*: fe 0f 10 00 mul pc,pc,0
11549 + *[0-9a-f]*: f8 0c 10 ff mul r12,r12,-1
11550 + *[0-9a-f]*: ea 05 10 80 mul r5,r5,-128
11551 + *[0-9a-f]*: e8 04 10 7f mul r4,r4,127
11552 + *[0-9a-f]*: fc 0e 10 01 mul lr,lr,1
11553 + *[0-9a-f]*: e4 0c 10 f9 mul r12,r2,-7
11554 + *[0-9a-f]*: fe 01 10 5f mul r1,pc,95
11555 + *[0-9a-f]*: ec 04 10 13 mul r4,r6,19
11557 +[0-9a-f]* <rsub2>:
11558 + *[0-9a-f]*: fe 0f 11 00 rsub pc,pc,0
11559 + *[0-9a-f]*: f8 0c 11 ff rsub r12,r12,-1
11560 + *[0-9a-f]*: ea 05 11 80 rsub r5,r5,-128
11561 + *[0-9a-f]*: e8 04 11 7f rsub r4,r4,127
11562 + *[0-9a-f]*: fc 0e 11 01 rsub lr,lr,1
11563 + *[0-9a-f]*: fc 09 11 60 rsub r9,lr,96
11564 + *[0-9a-f]*: e2 0b 11 38 rsub r11,r1,56
11565 + *[0-9a-f]*: ee 00 11 a9 rsub r0,r7,-87
11568 + *[0-9a-f]*: fe 0f 12 00 clz pc,pc
11569 + *[0-9a-f]*: f8 0c 12 00 clz r12,r12
11570 + *[0-9a-f]*: ea 05 12 00 clz r5,r5
11571 + *[0-9a-f]*: e8 04 12 00 clz r4,r4
11572 + *[0-9a-f]*: fc 0e 12 00 clz lr,lr
11573 + *[0-9a-f]*: e6 02 12 00 clz r2,r3
11574 + *[0-9a-f]*: f6 05 12 00 clz r5,r11
11575 + *[0-9a-f]*: e6 0f 12 00 clz pc,r3
11578 + *[0-9a-f]*: fe 0f 13 00 cpc pc,pc
11579 + *[0-9a-f]*: f8 0c 13 00 cpc r12,r12
11580 + *[0-9a-f]*: ea 05 13 00 cpc r5,r5
11581 + *[0-9a-f]*: e8 04 13 00 cpc r4,r4
11582 + *[0-9a-f]*: fc 0e 13 00 cpc lr,lr
11583 + *[0-9a-f]*: e8 0f 13 00 cpc pc,r4
11584 + *[0-9a-f]*: f2 05 13 00 cpc r5,r9
11585 + *[0-9a-f]*: ee 06 13 00 cpc r6,r7
11588 + *[0-9a-f]*: fe 0f 14 00 asr pc,pc,0x0
11589 + *[0-9a-f]*: f8 0c 14 1f asr r12,r12,0x1f
11590 + *[0-9a-f]*: ea 05 14 10 asr r5,r5,0x10
11591 + *[0-9a-f]*: e8 04 14 0f asr r4,r4,0xf
11592 + *[0-9a-f]*: fc 0e 14 01 asr lr,lr,0x1
11593 + *[0-9a-f]*: f6 04 14 13 asr r4,r11,0x13
11594 + *[0-9a-f]*: fe 0d 14 1a asr sp,pc,0x1a
11595 + *[0-9a-f]*: fa 0b 14 08 asr r11,sp,0x8
11598 + *[0-9a-f]*: fe 0f 15 00 lsl pc,pc,0x0
11599 + *[0-9a-f]*: f8 0c 15 1f lsl r12,r12,0x1f
11600 + *[0-9a-f]*: ea 05 15 10 lsl r5,r5,0x10
11601 + *[0-9a-f]*: e8 04 15 0f lsl r4,r4,0xf
11602 + *[0-9a-f]*: fc 0e 15 01 lsl lr,lr,0x1
11603 + *[0-9a-f]*: f4 08 15 11 lsl r8,r10,0x11
11604 + *[0-9a-f]*: fc 02 15 03 lsl r2,lr,0x3
11605 + *[0-9a-f]*: f6 0e 15 0e lsl lr,r11,0xe
11608 + *[0-9a-f]*: fe 0f 16 00 lsr pc,pc,0x0
11609 + *[0-9a-f]*: f8 0c 16 1f lsr r12,r12,0x1f
11610 + *[0-9a-f]*: ea 05 16 10 lsr r5,r5,0x10
11611 + *[0-9a-f]*: e8 04 16 0f lsr r4,r4,0xf
11612 + *[0-9a-f]*: fc 0e 16 01 lsr lr,lr,0x1
11613 + *[0-9a-f]*: e6 04 16 1f lsr r4,r3,0x1f
11614 + *[0-9a-f]*: f2 0f 16 0e lsr pc,r9,0xe
11615 + *[0-9a-f]*: e0 03 16 06 lsr r3,r0,0x6
11617 +[0-9a-f]* <movc1>:
11618 + *[0-9a-f]*: fe 0f 17 00 moveq pc,pc
11619 + *[0-9a-f]*: f8 0c 17 f0 moval r12,r12
11620 + *[0-9a-f]*: ea 05 17 80 movls r5,r5
11621 + *[0-9a-f]*: e8 04 17 70 movpl r4,r4
11622 + *[0-9a-f]*: fc 0e 17 10 movne lr,lr
11623 + *[0-9a-f]*: f6 0f 17 10 movne pc,r11
11624 + *[0-9a-f]*: e4 0a 17 60 movmi r10,r2
11625 + *[0-9a-f]*: f8 08 17 80 movls r8,r12
11627 +[0-9a-f]* <padd_h>:
11628 + *[0-9a-f]*: fe 0f 20 0f padd\.h pc,pc,pc
11629 + *[0-9a-f]*: f8 0c 20 0c padd\.h r12,r12,r12
11630 + *[0-9a-f]*: ea 05 20 05 padd\.h r5,r5,r5
11631 + *[0-9a-f]*: e8 04 20 04 padd\.h r4,r4,r4
11632 + *[0-9a-f]*: fc 0e 20 0e padd\.h lr,lr,lr
11633 + *[0-9a-f]*: e4 07 20 08 padd\.h r8,r2,r7
11634 + *[0-9a-f]*: e0 03 20 00 padd\.h r0,r0,r3
11635 + *[0-9a-f]*: f6 06 20 0d padd\.h sp,r11,r6
11637 +[0-9a-f]* <psub_h>:
11638 + *[0-9a-f]*: fe 0f 20 1f psub\.h pc,pc,pc
11639 + *[0-9a-f]*: f8 0c 20 1c psub\.h r12,r12,r12
11640 + *[0-9a-f]*: ea 05 20 15 psub\.h r5,r5,r5
11641 + *[0-9a-f]*: e8 04 20 14 psub\.h r4,r4,r4
11642 + *[0-9a-f]*: fc 0e 20 1e psub\.h lr,lr,lr
11643 + *[0-9a-f]*: ec 08 20 1e psub\.h lr,r6,r8
11644 + *[0-9a-f]*: e2 0d 20 10 psub\.h r0,r1,sp
11645 + *[0-9a-f]*: fe 0d 20 1f psub\.h pc,pc,sp
11647 +[0-9a-f]* <paddx_h>:
11648 + *[0-9a-f]*: fe 0f 20 2f paddx\.h pc,pc,pc
11649 + *[0-9a-f]*: f8 0c 20 2c paddx\.h r12,r12,r12
11650 + *[0-9a-f]*: ea 05 20 25 paddx\.h r5,r5,r5
11651 + *[0-9a-f]*: e8 04 20 24 paddx\.h r4,r4,r4
11652 + *[0-9a-f]*: fc 0e 20 2e paddx\.h lr,lr,lr
11653 + *[0-9a-f]*: fe 01 20 2f paddx\.h pc,pc,r1
11654 + *[0-9a-f]*: e8 05 20 2a paddx\.h r10,r4,r5
11655 + *[0-9a-f]*: fe 02 20 25 paddx\.h r5,pc,r2
11657 +[0-9a-f]* <psubx_h>:
11658 + *[0-9a-f]*: fe 0f 20 3f psubx\.h pc,pc,pc
11659 + *[0-9a-f]*: f8 0c 20 3c psubx\.h r12,r12,r12
11660 + *[0-9a-f]*: ea 05 20 35 psubx\.h r5,r5,r5
11661 + *[0-9a-f]*: e8 04 20 34 psubx\.h r4,r4,r4
11662 + *[0-9a-f]*: fc 0e 20 3e psubx\.h lr,lr,lr
11663 + *[0-9a-f]*: f8 05 20 35 psubx\.h r5,r12,r5
11664 + *[0-9a-f]*: f0 03 20 33 psubx\.h r3,r8,r3
11665 + *[0-9a-f]*: e4 03 20 35 psubx\.h r5,r2,r3
11667 +[0-9a-f]* <padds_sh>:
11668 + *[0-9a-f]*: fe 0f 20 4f padds\.sh pc,pc,pc
11669 + *[0-9a-f]*: f8 0c 20 4c padds\.sh r12,r12,r12
11670 + *[0-9a-f]*: ea 05 20 45 padds\.sh r5,r5,r5
11671 + *[0-9a-f]*: e8 04 20 44 padds\.sh r4,r4,r4
11672 + *[0-9a-f]*: fc 0e 20 4e padds\.sh lr,lr,lr
11673 + *[0-9a-f]*: fc 02 20 49 padds\.sh r9,lr,r2
11674 + *[0-9a-f]*: f0 01 20 46 padds\.sh r6,r8,r1
11675 + *[0-9a-f]*: e8 0a 20 46 padds\.sh r6,r4,r10
11677 +[0-9a-f]* <psubs_sh>:
11678 + *[0-9a-f]*: fe 0f 20 5f psubs\.sh pc,pc,pc
11679 + *[0-9a-f]*: f8 0c 20 5c psubs\.sh r12,r12,r12
11680 + *[0-9a-f]*: ea 05 20 55 psubs\.sh r5,r5,r5
11681 + *[0-9a-f]*: e8 04 20 54 psubs\.sh r4,r4,r4
11682 + *[0-9a-f]*: fc 0e 20 5e psubs\.sh lr,lr,lr
11683 + *[0-9a-f]*: fc 0b 20 56 psubs\.sh r6,lr,r11
11684 + *[0-9a-f]*: f8 04 20 52 psubs\.sh r2,r12,r4
11685 + *[0-9a-f]*: f2 00 20 50 psubs\.sh r0,r9,r0
11687 +[0-9a-f]* <paddxs_sh>:
11688 + *[0-9a-f]*: fe 0f 20 6f paddxs\.sh pc,pc,pc
11689 + *[0-9a-f]*: f8 0c 20 6c paddxs\.sh r12,r12,r12
11690 + *[0-9a-f]*: ea 05 20 65 paddxs\.sh r5,r5,r5
11691 + *[0-9a-f]*: e8 04 20 64 paddxs\.sh r4,r4,r4
11692 + *[0-9a-f]*: fc 0e 20 6e paddxs\.sh lr,lr,lr
11693 + *[0-9a-f]*: e6 09 20 60 paddxs\.sh r0,r3,r9
11694 + *[0-9a-f]*: f4 0b 20 6f paddxs\.sh pc,r10,r11
11695 + *[0-9a-f]*: f4 0f 20 6f paddxs\.sh pc,r10,pc
11697 +[0-9a-f]* <psubxs_sh>:
11698 + *[0-9a-f]*: fe 0f 20 7f psubxs\.sh pc,pc,pc
11699 + *[0-9a-f]*: f8 0c 20 7c psubxs\.sh r12,r12,r12
11700 + *[0-9a-f]*: ea 05 20 75 psubxs\.sh r5,r5,r5
11701 + *[0-9a-f]*: e8 04 20 74 psubxs\.sh r4,r4,r4
11702 + *[0-9a-f]*: fc 0e 20 7e psubxs\.sh lr,lr,lr
11703 + *[0-9a-f]*: e8 04 20 77 psubxs\.sh r7,r4,r4
11704 + *[0-9a-f]*: f0 03 20 77 psubxs\.sh r7,r8,r3
11705 + *[0-9a-f]*: ec 05 20 7f psubxs\.sh pc,r6,r5
11707 +[0-9a-f]* <padds_uh>:
11708 + *[0-9a-f]*: fe 0f 20 8f padds\.uh pc,pc,pc
11709 + *[0-9a-f]*: f8 0c 20 8c padds\.uh r12,r12,r12
11710 + *[0-9a-f]*: ea 05 20 85 padds\.uh r5,r5,r5
11711 + *[0-9a-f]*: e8 04 20 84 padds\.uh r4,r4,r4
11712 + *[0-9a-f]*: fc 0e 20 8e padds\.uh lr,lr,lr
11713 + *[0-9a-f]*: f6 07 20 8c padds\.uh r12,r11,r7
11714 + *[0-9a-f]*: f0 0e 20 87 padds\.uh r7,r8,lr
11715 + *[0-9a-f]*: f2 07 20 86 padds\.uh r6,r9,r7
11717 +[0-9a-f]* <psubs_uh>:
11718 + *[0-9a-f]*: fe 0f 20 9f psubs\.uh pc,pc,pc
11719 + *[0-9a-f]*: f8 0c 20 9c psubs\.uh r12,r12,r12
11720 + *[0-9a-f]*: ea 05 20 95 psubs\.uh r5,r5,r5
11721 + *[0-9a-f]*: e8 04 20 94 psubs\.uh r4,r4,r4
11722 + *[0-9a-f]*: fc 0e 20 9e psubs\.uh lr,lr,lr
11723 + *[0-9a-f]*: f4 06 20 9e psubs\.uh lr,r10,r6
11724 + *[0-9a-f]*: e4 0f 20 9d psubs\.uh sp,r2,pc
11725 + *[0-9a-f]*: f2 02 20 92 psubs\.uh r2,r9,r2
11727 +[0-9a-f]* <paddxs_uh>:
11728 + *[0-9a-f]*: fe 0f 20 af paddxs\.uh pc,pc,pc
11729 + *[0-9a-f]*: f8 0c 20 ac paddxs\.uh r12,r12,r12
11730 + *[0-9a-f]*: ea 05 20 a5 paddxs\.uh r5,r5,r5
11731 + *[0-9a-f]*: e8 04 20 a4 paddxs\.uh r4,r4,r4
11732 + *[0-9a-f]*: fc 0e 20 ae paddxs\.uh lr,lr,lr
11733 + *[0-9a-f]*: f2 05 20 a7 paddxs\.uh r7,r9,r5
11734 + *[0-9a-f]*: e2 04 20 a9 paddxs\.uh r9,r1,r4
11735 + *[0-9a-f]*: e4 03 20 a5 paddxs\.uh r5,r2,r3
11737 +[0-9a-f]* <psubxs_uh>:
11738 + *[0-9a-f]*: fe 0f 20 bf psubxs\.uh pc,pc,pc
11739 + *[0-9a-f]*: f8 0c 20 bc psubxs\.uh r12,r12,r12
11740 + *[0-9a-f]*: ea 05 20 b5 psubxs\.uh r5,r5,r5
11741 + *[0-9a-f]*: e8 04 20 b4 psubxs\.uh r4,r4,r4
11742 + *[0-9a-f]*: fc 0e 20 be psubxs\.uh lr,lr,lr
11743 + *[0-9a-f]*: ea 0d 20 bd psubxs\.uh sp,r5,sp
11744 + *[0-9a-f]*: ec 06 20 bd psubxs\.uh sp,r6,r6
11745 + *[0-9a-f]*: f6 08 20 b3 psubxs\.uh r3,r11,r8
11747 +[0-9a-f]* <paddh_sh>:
11748 + *[0-9a-f]*: fe 0f 20 cf paddh\.sh pc,pc,pc
11749 + *[0-9a-f]*: f8 0c 20 cc paddh\.sh r12,r12,r12
11750 + *[0-9a-f]*: ea 05 20 c5 paddh\.sh r5,r5,r5
11751 + *[0-9a-f]*: e8 04 20 c4 paddh\.sh r4,r4,r4
11752 + *[0-9a-f]*: fc 0e 20 ce paddh\.sh lr,lr,lr
11753 + *[0-9a-f]*: fa 03 20 cc paddh\.sh r12,sp,r3
11754 + *[0-9a-f]*: ea 03 20 cf paddh\.sh pc,r5,r3
11755 + *[0-9a-f]*: f0 0d 20 c8 paddh\.sh r8,r8,sp
11757 +[0-9a-f]* <psubh_sh>:
11758 + *[0-9a-f]*: fe 0f 20 df psubh\.sh pc,pc,pc
11759 + *[0-9a-f]*: f8 0c 20 dc psubh\.sh r12,r12,r12
11760 + *[0-9a-f]*: ea 05 20 d5 psubh\.sh r5,r5,r5
11761 + *[0-9a-f]*: e8 04 20 d4 psubh\.sh r4,r4,r4
11762 + *[0-9a-f]*: fc 0e 20 de psubh\.sh lr,lr,lr
11763 + *[0-9a-f]*: ea 08 20 d1 psubh\.sh r1,r5,r8
11764 + *[0-9a-f]*: e6 06 20 d7 psubh\.sh r7,r3,r6
11765 + *[0-9a-f]*: e6 03 20 d4 psubh\.sh r4,r3,r3
11767 +[0-9a-f]* <paddxh_sh>:
11768 + *[0-9a-f]*: fe 0f 20 ef paddxh\.sh pc,pc,pc
11769 + *[0-9a-f]*: f8 0c 20 ec paddxh\.sh r12,r12,r12
11770 + *[0-9a-f]*: ea 05 20 e5 paddxh\.sh r5,r5,r5
11771 + *[0-9a-f]*: e8 04 20 e4 paddxh\.sh r4,r4,r4
11772 + *[0-9a-f]*: fc 0e 20 ee paddxh\.sh lr,lr,lr
11773 + *[0-9a-f]*: e0 04 20 e6 paddxh\.sh r6,r0,r4
11774 + *[0-9a-f]*: f0 09 20 e9 paddxh\.sh r9,r8,r9
11775 + *[0-9a-f]*: e0 0d 20 e3 paddxh\.sh r3,r0,sp
11777 +[0-9a-f]* <psubxh_sh>:
11778 + *[0-9a-f]*: fe 0f 20 ff psubxh\.sh pc,pc,pc
11779 + *[0-9a-f]*: f8 0c 20 fc psubxh\.sh r12,r12,r12
11780 + *[0-9a-f]*: ea 05 20 f5 psubxh\.sh r5,r5,r5
11781 + *[0-9a-f]*: e8 04 20 f4 psubxh\.sh r4,r4,r4
11782 + *[0-9a-f]*: fc 0e 20 fe psubxh\.sh lr,lr,lr
11783 + *[0-9a-f]*: fe 0c 20 f4 psubxh\.sh r4,pc,r12
11784 + *[0-9a-f]*: e8 06 20 f8 psubxh\.sh r8,r4,r6
11785 + *[0-9a-f]*: f2 04 20 fc psubxh\.sh r12,r9,r4
11787 +[0-9a-f]* <paddsub_h>:
11788 + *[0-9a-f]*: fe 0f 21 0f paddsub\.h pc,pc:b,pc:b
11789 + *[0-9a-f]*: f8 0c 21 3c paddsub\.h r12,r12:t,r12:t
11790 + *[0-9a-f]*: ea 05 21 35 paddsub\.h r5,r5:t,r5:t
11791 + *[0-9a-f]*: e8 04 21 04 paddsub\.h r4,r4:b,r4:b
11792 + *[0-9a-f]*: fc 0e 21 3e paddsub\.h lr,lr:t,lr:t
11793 + *[0-9a-f]*: e4 0e 21 25 paddsub\.h r5,r2:t,lr:b
11794 + *[0-9a-f]*: e2 08 21 07 paddsub\.h r7,r1:b,r8:b
11795 + *[0-9a-f]*: f4 05 21 36 paddsub\.h r6,r10:t,r5:t
11797 +[0-9a-f]* <psubadd_h>:
11798 + *[0-9a-f]*: fe 0f 21 4f psubadd\.h pc,pc:b,pc:b
11799 + *[0-9a-f]*: f8 0c 21 7c psubadd\.h r12,r12:t,r12:t
11800 + *[0-9a-f]*: ea 05 21 75 psubadd\.h r5,r5:t,r5:t
11801 + *[0-9a-f]*: e8 04 21 44 psubadd\.h r4,r4:b,r4:b
11802 + *[0-9a-f]*: fc 0e 21 7e psubadd\.h lr,lr:t,lr:t
11803 + *[0-9a-f]*: f6 08 21 79 psubadd\.h r9,r11:t,r8:t
11804 + *[0-9a-f]*: ee 0e 21 7a psubadd\.h r10,r7:t,lr:t
11805 + *[0-9a-f]*: fe 0f 21 66 psubadd\.h r6,pc:t,pc:b
11807 +[0-9a-f]* <paddsubs_sh>:
11808 + *[0-9a-f]*: fe 0f 21 8f paddsubs\.sh pc,pc:b,pc:b
11809 + *[0-9a-f]*: f8 0c 21 bc paddsubs\.sh r12,r12:t,r12:t
11810 + *[0-9a-f]*: ea 05 21 b5 paddsubs\.sh r5,r5:t,r5:t
11811 + *[0-9a-f]*: e8 04 21 84 paddsubs\.sh r4,r4:b,r4:b
11812 + *[0-9a-f]*: fc 0e 21 be paddsubs\.sh lr,lr:t,lr:t
11813 + *[0-9a-f]*: fc 00 21 a0 paddsubs\.sh r0,lr:t,r0:b
11814 + *[0-9a-f]*: e4 04 21 b9 paddsubs\.sh r9,r2:t,r4:t
11815 + *[0-9a-f]*: f2 0d 21 bc paddsubs\.sh r12,r9:t,sp:t
11817 +[0-9a-f]* <psubadds_sh>:
11818 + *[0-9a-f]*: fe 0f 21 cf psubadds\.sh pc,pc:b,pc:b
11819 + *[0-9a-f]*: f8 0c 21 fc psubadds\.sh r12,r12:t,r12:t
11820 + *[0-9a-f]*: ea 05 21 f5 psubadds\.sh r5,r5:t,r5:t
11821 + *[0-9a-f]*: e8 04 21 c4 psubadds\.sh r4,r4:b,r4:b
11822 + *[0-9a-f]*: fc 0e 21 fe psubadds\.sh lr,lr:t,lr:t
11823 + *[0-9a-f]*: fc 01 21 df psubadds\.sh pc,lr:b,r1:t
11824 + *[0-9a-f]*: e6 0c 21 cb psubadds\.sh r11,r3:b,r12:b
11825 + *[0-9a-f]*: e4 08 21 fa psubadds\.sh r10,r2:t,r8:t
11827 +[0-9a-f]* <paddsubs_uh>:
11828 + *[0-9a-f]*: fe 0f 22 0f paddsubs\.uh pc,pc:b,pc:b
11829 + *[0-9a-f]*: f8 0c 22 3c paddsubs\.uh r12,r12:t,r12:t
11830 + *[0-9a-f]*: ea 05 22 35 paddsubs\.uh r5,r5:t,r5:t
11831 + *[0-9a-f]*: e8 04 22 04 paddsubs\.uh r4,r4:b,r4:b
11832 + *[0-9a-f]*: fc 0e 22 3e paddsubs\.uh lr,lr:t,lr:t
11833 + *[0-9a-f]*: e4 03 22 09 paddsubs\.uh r9,r2:b,r3:b
11834 + *[0-9a-f]*: fa 07 22 1d paddsubs\.uh sp,sp:b,r7:t
11835 + *[0-9a-f]*: e0 0a 22 1e paddsubs\.uh lr,r0:b,r10:t
11837 +[0-9a-f]* <psubadds_uh>:
11838 + *[0-9a-f]*: fe 0f 22 4f psubadds\.uh pc,pc:b,pc:b
11839 + *[0-9a-f]*: f8 0c 22 7c psubadds\.uh r12,r12:t,r12:t
11840 + *[0-9a-f]*: ea 05 22 75 psubadds\.uh r5,r5:t,r5:t
11841 + *[0-9a-f]*: e8 04 22 44 psubadds\.uh r4,r4:b,r4:b
11842 + *[0-9a-f]*: fc 0e 22 7e psubadds\.uh lr,lr:t,lr:t
11843 + *[0-9a-f]*: f2 0f 22 7c psubadds\.uh r12,r9:t,pc:t
11844 + *[0-9a-f]*: ec 08 22 48 psubadds\.uh r8,r6:b,r8:b
11845 + *[0-9a-f]*: f0 04 22 48 psubadds\.uh r8,r8:b,r4:b
11847 +[0-9a-f]* <paddsubh_sh>:
11848 + *[0-9a-f]*: fe 0f 22 8f paddsubh\.sh pc,pc:b,pc:b
11849 + *[0-9a-f]*: f8 0c 22 bc paddsubh\.sh r12,r12:t,r12:t
11850 + *[0-9a-f]*: ea 05 22 b5 paddsubh\.sh r5,r5:t,r5:t
11851 + *[0-9a-f]*: e8 04 22 84 paddsubh\.sh r4,r4:b,r4:b
11852 + *[0-9a-f]*: fc 0e 22 be paddsubh\.sh lr,lr:t,lr:t
11853 + *[0-9a-f]*: f2 09 22 a8 paddsubh\.sh r8,r9:t,r9:b
11854 + *[0-9a-f]*: fa 01 22 b0 paddsubh\.sh r0,sp:t,r1:t
11855 + *[0-9a-f]*: e2 00 22 93 paddsubh\.sh r3,r1:b,r0:t
11857 +[0-9a-f]* <psubaddh_sh>:
11858 + *[0-9a-f]*: fe 0f 22 cf psubaddh\.sh pc,pc:b,pc:b
11859 + *[0-9a-f]*: f8 0c 22 fc psubaddh\.sh r12,r12:t,r12:t
11860 + *[0-9a-f]*: ea 05 22 f5 psubaddh\.sh r5,r5:t,r5:t
11861 + *[0-9a-f]*: e8 04 22 c4 psubaddh\.sh r4,r4:b,r4:b
11862 + *[0-9a-f]*: fc 0e 22 fe psubaddh\.sh lr,lr:t,lr:t
11863 + *[0-9a-f]*: e6 0a 22 e7 psubaddh\.sh r7,r3:t,r10:b
11864 + *[0-9a-f]*: e4 01 22 f7 psubaddh\.sh r7,r2:t,r1:t
11865 + *[0-9a-f]*: e6 06 22 cb psubaddh\.sh r11,r3:b,r6:b
11867 +[0-9a-f]* <padd_b>:
11868 + *[0-9a-f]*: fe 0f 23 0f padd\.b pc,pc,pc
11869 + *[0-9a-f]*: f8 0c 23 0c padd\.b r12,r12,r12
11870 + *[0-9a-f]*: ea 05 23 05 padd\.b r5,r5,r5
11871 + *[0-9a-f]*: e8 04 23 04 padd\.b r4,r4,r4
11872 + *[0-9a-f]*: fc 0e 23 0e padd\.b lr,lr,lr
11873 + *[0-9a-f]*: ec 0f 23 02 padd\.b r2,r6,pc
11874 + *[0-9a-f]*: f2 0c 23 08 padd\.b r8,r9,r12
11875 + *[0-9a-f]*: f8 03 23 05 padd\.b r5,r12,r3
11877 +[0-9a-f]* <psub_b>:
11878 + *[0-9a-f]*: fe 0f 23 1f psub\.b pc,pc,pc
11879 + *[0-9a-f]*: f8 0c 23 1c psub\.b r12,r12,r12
11880 + *[0-9a-f]*: ea 05 23 15 psub\.b r5,r5,r5
11881 + *[0-9a-f]*: e8 04 23 14 psub\.b r4,r4,r4
11882 + *[0-9a-f]*: fc 0e 23 1e psub\.b lr,lr,lr
11883 + *[0-9a-f]*: f8 0f 23 10 psub\.b r0,r12,pc
11884 + *[0-9a-f]*: fa 0a 23 17 psub\.b r7,sp,r10
11885 + *[0-9a-f]*: fa 0c 23 15 psub\.b r5,sp,r12
11887 +[0-9a-f]* <padds_sb>:
11888 + *[0-9a-f]*: fe 0f 23 2f padds\.sb pc,pc,pc
11889 + *[0-9a-f]*: f8 0c 23 2c padds\.sb r12,r12,r12
11890 + *[0-9a-f]*: ea 05 23 25 padds\.sb r5,r5,r5
11891 + *[0-9a-f]*: e8 04 23 24 padds\.sb r4,r4,r4
11892 + *[0-9a-f]*: fc 0e 23 2e padds\.sb lr,lr,lr
11893 + *[0-9a-f]*: f6 04 23 2d padds\.sb sp,r11,r4
11894 + *[0-9a-f]*: f4 0b 23 2b padds\.sb r11,r10,r11
11895 + *[0-9a-f]*: f8 06 23 25 padds\.sb r5,r12,r6
11897 +[0-9a-f]* <psubs_sb>:
11898 + *[0-9a-f]*: fe 0f 23 3f psubs\.sb pc,pc,pc
11899 + *[0-9a-f]*: f8 0c 23 3c psubs\.sb r12,r12,r12
11900 + *[0-9a-f]*: ea 05 23 35 psubs\.sb r5,r5,r5
11901 + *[0-9a-f]*: e8 04 23 34 psubs\.sb r4,r4,r4
11902 + *[0-9a-f]*: fc 0e 23 3e psubs\.sb lr,lr,lr
11903 + *[0-9a-f]*: ec 08 23 37 psubs\.sb r7,r6,r8
11904 + *[0-9a-f]*: f4 09 23 3c psubs\.sb r12,r10,r9
11905 + *[0-9a-f]*: f6 00 23 3f psubs\.sb pc,r11,r0
11907 +[0-9a-f]* <padds_ub>:
11908 + *[0-9a-f]*: fe 0f 23 4f padds\.ub pc,pc,pc
11909 + *[0-9a-f]*: f8 0c 23 4c padds\.ub r12,r12,r12
11910 + *[0-9a-f]*: ea 05 23 45 padds\.ub r5,r5,r5
11911 + *[0-9a-f]*: e8 04 23 44 padds\.ub r4,r4,r4
11912 + *[0-9a-f]*: fc 0e 23 4e padds\.ub lr,lr,lr
11913 + *[0-9a-f]*: e4 0b 23 43 padds\.ub r3,r2,r11
11914 + *[0-9a-f]*: f0 01 23 4a padds\.ub r10,r8,r1
11915 + *[0-9a-f]*: f0 0a 23 4b padds\.ub r11,r8,r10
11917 +[0-9a-f]* <psubs_ub>:
11918 + *[0-9a-f]*: fe 0f 23 5f psubs\.ub pc,pc,pc
11919 + *[0-9a-f]*: f8 0c 23 5c psubs\.ub r12,r12,r12
11920 + *[0-9a-f]*: ea 05 23 55 psubs\.ub r5,r5,r5
11921 + *[0-9a-f]*: e8 04 23 54 psubs\.ub r4,r4,r4
11922 + *[0-9a-f]*: fc 0e 23 5e psubs\.ub lr,lr,lr
11923 + *[0-9a-f]*: e4 07 23 50 psubs\.ub r0,r2,r7
11924 + *[0-9a-f]*: ea 03 23 5e psubs\.ub lr,r5,r3
11925 + *[0-9a-f]*: ee 09 23 56 psubs\.ub r6,r7,r9
11927 +[0-9a-f]* <paddh_ub>:
11928 + *[0-9a-f]*: fe 0f 23 6f paddh\.ub pc,pc,pc
11929 + *[0-9a-f]*: f8 0c 23 6c paddh\.ub r12,r12,r12
11930 + *[0-9a-f]*: ea 05 23 65 paddh\.ub r5,r5,r5
11931 + *[0-9a-f]*: e8 04 23 64 paddh\.ub r4,r4,r4
11932 + *[0-9a-f]*: fc 0e 23 6e paddh\.ub lr,lr,lr
11933 + *[0-9a-f]*: e2 00 23 6e paddh\.ub lr,r1,r0
11934 + *[0-9a-f]*: ee 07 23 62 paddh\.ub r2,r7,r7
11935 + *[0-9a-f]*: e2 02 23 62 paddh\.ub r2,r1,r2
11937 +[0-9a-f]* <psubh_ub>:
11938 + *[0-9a-f]*: fe 0f 23 7f psubh\.ub pc,pc,pc
11939 + *[0-9a-f]*: f8 0c 23 7c psubh\.ub r12,r12,r12
11940 + *[0-9a-f]*: ea 05 23 75 psubh\.ub r5,r5,r5
11941 + *[0-9a-f]*: e8 04 23 74 psubh\.ub r4,r4,r4
11942 + *[0-9a-f]*: fc 0e 23 7e psubh\.ub lr,lr,lr
11943 + *[0-9a-f]*: e2 06 23 70 psubh\.ub r0,r1,r6
11944 + *[0-9a-f]*: fc 0a 23 74 psubh\.ub r4,lr,r10
11945 + *[0-9a-f]*: f0 01 23 79 psubh\.ub r9,r8,r1
11947 +[0-9a-f]* <pmax_ub>:
11948 + *[0-9a-f]*: fe 0f 23 8f pmax\.ub pc,pc,pc
11949 + *[0-9a-f]*: f8 0c 23 8c pmax\.ub r12,r12,r12
11950 + *[0-9a-f]*: ea 05 23 85 pmax\.ub r5,r5,r5
11951 + *[0-9a-f]*: e8 04 23 84 pmax\.ub r4,r4,r4
11952 + *[0-9a-f]*: fc 0e 23 8e pmax\.ub lr,lr,lr
11953 + *[0-9a-f]*: e4 0b 23 8f pmax\.ub pc,r2,r11
11954 + *[0-9a-f]*: e2 01 23 8c pmax\.ub r12,r1,r1
11955 + *[0-9a-f]*: e4 00 23 85 pmax\.ub r5,r2,r0
11957 +[0-9a-f]* <pmax_sh>:
11958 + *[0-9a-f]*: fe 0f 23 9f pmax\.sh pc,pc,pc
11959 + *[0-9a-f]*: f8 0c 23 9c pmax\.sh r12,r12,r12
11960 + *[0-9a-f]*: ea 05 23 95 pmax\.sh r5,r5,r5
11961 + *[0-9a-f]*: e8 04 23 94 pmax\.sh r4,r4,r4
11962 + *[0-9a-f]*: fc 0e 23 9e pmax\.sh lr,lr,lr
11963 + *[0-9a-f]*: ec 0c 23 9e pmax\.sh lr,r6,r12
11964 + *[0-9a-f]*: fe 05 23 92 pmax\.sh r2,pc,r5
11965 + *[0-9a-f]*: e4 07 23 9f pmax\.sh pc,r2,r7
11967 +[0-9a-f]* <pmin_ub>:
11968 + *[0-9a-f]*: fe 0f 23 af pmin\.ub pc,pc,pc
11969 + *[0-9a-f]*: f8 0c 23 ac pmin\.ub r12,r12,r12
11970 + *[0-9a-f]*: ea 05 23 a5 pmin\.ub r5,r5,r5
11971 + *[0-9a-f]*: e8 04 23 a4 pmin\.ub r4,r4,r4
11972 + *[0-9a-f]*: fc 0e 23 ae pmin\.ub lr,lr,lr
11973 + *[0-9a-f]*: e2 05 23 a8 pmin\.ub r8,r1,r5
11974 + *[0-9a-f]*: f0 03 23 a1 pmin\.ub r1,r8,r3
11975 + *[0-9a-f]*: e4 07 23 a0 pmin\.ub r0,r2,r7
11977 +[0-9a-f]* <pmin_sh>:
11978 + *[0-9a-f]*: fe 0f 23 bf pmin\.sh pc,pc,pc
11979 + *[0-9a-f]*: f8 0c 23 bc pmin\.sh r12,r12,r12
11980 + *[0-9a-f]*: ea 05 23 b5 pmin\.sh r5,r5,r5
11981 + *[0-9a-f]*: e8 04 23 b4 pmin\.sh r4,r4,r4
11982 + *[0-9a-f]*: fc 0e 23 be pmin\.sh lr,lr,lr
11983 + *[0-9a-f]*: e8 0a 23 b8 pmin\.sh r8,r4,r10
11984 + *[0-9a-f]*: f4 0c 23 be pmin\.sh lr,r10,r12
11985 + *[0-9a-f]*: ec 02 23 b2 pmin\.sh r2,r6,r2
11987 +[0-9a-f]* <pavg_ub>:
11988 + *[0-9a-f]*: fe 0f 23 cf pavg\.ub pc,pc,pc
11989 + *[0-9a-f]*: f8 0c 23 cc pavg\.ub r12,r12,r12
11990 + *[0-9a-f]*: ea 05 23 c5 pavg\.ub r5,r5,r5
11991 + *[0-9a-f]*: e8 04 23 c4 pavg\.ub r4,r4,r4
11992 + *[0-9a-f]*: fc 0e 23 ce pavg\.ub lr,lr,lr
11993 + *[0-9a-f]*: e2 06 23 c0 pavg\.ub r0,r1,r6
11994 + *[0-9a-f]*: e6 06 23 c8 pavg\.ub r8,r3,r6
11995 + *[0-9a-f]*: f8 0a 23 cf pavg\.ub pc,r12,r10
11997 +[0-9a-f]* <pavg_sh>:
11998 + *[0-9a-f]*: fe 0f 23 df pavg\.sh pc,pc,pc
11999 + *[0-9a-f]*: f8 0c 23 dc pavg\.sh r12,r12,r12
12000 + *[0-9a-f]*: ea 05 23 d5 pavg\.sh r5,r5,r5
12001 + *[0-9a-f]*: e8 04 23 d4 pavg\.sh r4,r4,r4
12002 + *[0-9a-f]*: fc 0e 23 de pavg\.sh lr,lr,lr
12003 + *[0-9a-f]*: fe 0d 23 d9 pavg\.sh r9,pc,sp
12004 + *[0-9a-f]*: fa 03 23 df pavg\.sh pc,sp,r3
12005 + *[0-9a-f]*: e2 09 23 d6 pavg\.sh r6,r1,r9
12007 +[0-9a-f]* <pabs_sb>:
12008 + *[0-9a-f]*: e0 0f 23 ef pabs\.sb pc,pc
12009 + *[0-9a-f]*: e0 0c 23 ec pabs\.sb r12,r12
12010 + *[0-9a-f]*: e0 05 23 e5 pabs\.sb r5,r5
12011 + *[0-9a-f]*: e0 04 23 e4 pabs\.sb r4,r4
12012 + *[0-9a-f]*: e0 0e 23 ee pabs\.sb lr,lr
12013 + *[0-9a-f]*: e0 06 23 eb pabs\.sb r11,r6
12014 + *[0-9a-f]*: e0 09 23 ee pabs\.sb lr,r9
12015 + *[0-9a-f]*: e0 07 23 ed pabs\.sb sp,r7
12017 +[0-9a-f]* <pabs_sh>:
12018 + *[0-9a-f]*: e0 0f 23 ff pabs\.sh pc,pc
12019 + *[0-9a-f]*: e0 0c 23 fc pabs\.sh r12,r12
12020 + *[0-9a-f]*: e0 05 23 f5 pabs\.sh r5,r5
12021 + *[0-9a-f]*: e0 04 23 f4 pabs\.sh r4,r4
12022 + *[0-9a-f]*: e0 0e 23 fe pabs\.sh lr,lr
12023 + *[0-9a-f]*: e0 03 23 ff pabs\.sh pc,r3
12024 + *[0-9a-f]*: e0 07 23 f5 pabs\.sh r5,r7
12025 + *[0-9a-f]*: e0 00 23 f4 pabs\.sh r4,r0
12028 + *[0-9a-f]*: fe 0f 24 0f psad pc,pc,pc
12029 + *[0-9a-f]*: f8 0c 24 0c psad r12,r12,r12
12030 + *[0-9a-f]*: ea 05 24 05 psad r5,r5,r5
12031 + *[0-9a-f]*: e8 04 24 04 psad r4,r4,r4
12032 + *[0-9a-f]*: fc 0e 24 0e psad lr,lr,lr
12033 + *[0-9a-f]*: f6 0b 24 09 psad r9,r11,r11
12034 + *[0-9a-f]*: e8 0d 24 0e psad lr,r4,sp
12035 + *[0-9a-f]*: e8 05 24 0e psad lr,r4,r5
12037 +[0-9a-f]* <pasr_b>:
12038 + *[0-9a-f]*: fe 00 24 1f pasr\.b pc,pc,0x0
12039 + *[0-9a-f]*: f8 07 24 1c pasr\.b r12,r12,0x7
12040 + *[0-9a-f]*: ea 04 24 15 pasr\.b r5,r5,0x4
12041 + *[0-9a-f]*: e8 03 24 14 pasr\.b r4,r4,0x3
12042 + *[0-9a-f]*: fc 01 24 1e pasr\.b lr,lr,0x1
12043 + *[0-9a-f]*: ee 01 24 1f pasr\.b pc,r7,0x1
12044 + *[0-9a-f]*: fc 06 24 1d pasr\.b sp,lr,0x6
12045 + *[0-9a-f]*: e6 02 24 1d pasr\.b sp,r3,0x2
12047 +[0-9a-f]* <plsl_b>:
12048 + *[0-9a-f]*: fe 00 24 2f plsl\.b pc,pc,0x0
12049 + *[0-9a-f]*: f8 07 24 2c plsl\.b r12,r12,0x7
12050 + *[0-9a-f]*: ea 04 24 25 plsl\.b r5,r5,0x4
12051 + *[0-9a-f]*: e8 03 24 24 plsl\.b r4,r4,0x3
12052 + *[0-9a-f]*: fc 01 24 2e plsl\.b lr,lr,0x1
12053 + *[0-9a-f]*: f6 04 24 22 plsl\.b r2,r11,0x4
12054 + *[0-9a-f]*: ea 07 24 28 plsl\.b r8,r5,0x7
12055 + *[0-9a-f]*: e0 02 24 2f plsl\.b pc,r0,0x2
12057 +[0-9a-f]* <plsr_b>:
12058 + *[0-9a-f]*: fe 00 24 3f plsr\.b pc,pc,0x0
12059 + *[0-9a-f]*: f8 07 24 3c plsr\.b r12,r12,0x7
12060 + *[0-9a-f]*: ea 04 24 35 plsr\.b r5,r5,0x4
12061 + *[0-9a-f]*: e8 03 24 34 plsr\.b r4,r4,0x3
12062 + *[0-9a-f]*: fc 01 24 3e plsr\.b lr,lr,0x1
12063 + *[0-9a-f]*: e2 02 24 3c plsr\.b r12,r1,0x2
12064 + *[0-9a-f]*: fe 07 24 36 plsr\.b r6,pc,0x7
12065 + *[0-9a-f]*: f6 02 24 3c plsr\.b r12,r11,0x2
12067 +[0-9a-f]* <pasr_h>:
12068 + *[0-9a-f]*: fe 00 24 4f pasr\.h pc,pc,0x0
12069 + *[0-9a-f]*: f8 0f 24 4c pasr\.h r12,r12,0xf
12070 + *[0-9a-f]*: ea 08 24 45 pasr\.h r5,r5,0x8
12071 + *[0-9a-f]*: e8 07 24 44 pasr\.h r4,r4,0x7
12072 + *[0-9a-f]*: fc 01 24 4e pasr\.h lr,lr,0x1
12073 + *[0-9a-f]*: f6 0a 24 40 pasr\.h r0,r11,0xa
12074 + *[0-9a-f]*: ec 08 24 44 pasr\.h r4,r6,0x8
12075 + *[0-9a-f]*: e4 04 24 46 pasr\.h r6,r2,0x4
12077 +[0-9a-f]* <plsl_h>:
12078 + *[0-9a-f]*: fe 00 24 5f plsl\.h pc,pc,0x0
12079 + *[0-9a-f]*: f8 0f 24 5c plsl\.h r12,r12,0xf
12080 + *[0-9a-f]*: ea 08 24 55 plsl\.h r5,r5,0x8
12081 + *[0-9a-f]*: e8 07 24 54 plsl\.h r4,r4,0x7
12082 + *[0-9a-f]*: fc 01 24 5e plsl\.h lr,lr,0x1
12083 + *[0-9a-f]*: f4 09 24 55 plsl\.h r5,r10,0x9
12084 + *[0-9a-f]*: fc 08 24 5d plsl\.h sp,lr,0x8
12085 + *[0-9a-f]*: fc 07 24 50 plsl\.h r0,lr,0x7
12087 +[0-9a-f]* <plsr_h>:
12088 + *[0-9a-f]*: fe 00 24 6f plsr\.h pc,pc,0x0
12089 + *[0-9a-f]*: f8 0f 24 6c plsr\.h r12,r12,0xf
12090 + *[0-9a-f]*: ea 08 24 65 plsr\.h r5,r5,0x8
12091 + *[0-9a-f]*: e8 07 24 64 plsr\.h r4,r4,0x7
12092 + *[0-9a-f]*: fc 01 24 6e plsr\.h lr,lr,0x1
12093 + *[0-9a-f]*: e0 0f 24 6b plsr\.h r11,r0,0xf
12094 + *[0-9a-f]*: e6 03 24 6e plsr\.h lr,r3,0x3
12095 + *[0-9a-f]*: fc 0a 24 68 plsr\.h r8,lr,0xa
12097 +[0-9a-f]* <packw_sh>:
12098 + *[0-9a-f]*: fe 0f 24 7f packw\.sh pc,pc,pc
12099 + *[0-9a-f]*: f8 0c 24 7c packw\.sh r12,r12,r12
12100 + *[0-9a-f]*: ea 05 24 75 packw\.sh r5,r5,r5
12101 + *[0-9a-f]*: e8 04 24 74 packw\.sh r4,r4,r4
12102 + *[0-9a-f]*: fc 0e 24 7e packw\.sh lr,lr,lr
12103 + *[0-9a-f]*: f6 0a 24 7d packw\.sh sp,r11,r10
12104 + *[0-9a-f]*: e4 0c 24 78 packw\.sh r8,r2,r12
12105 + *[0-9a-f]*: e2 05 24 78 packw\.sh r8,r1,r5
12107 +[0-9a-f]* <punpckub_h>:
12108 + *[0-9a-f]*: fe 00 24 8f punpckub\.h pc,pc:b
12109 + *[0-9a-f]*: f8 00 24 9c punpckub\.h r12,r12:t
12110 + *[0-9a-f]*: ea 00 24 95 punpckub\.h r5,r5:t
12111 + *[0-9a-f]*: e8 00 24 84 punpckub\.h r4,r4:b
12112 + *[0-9a-f]*: fc 00 24 9e punpckub\.h lr,lr:t
12113 + *[0-9a-f]*: e2 00 24 96 punpckub\.h r6,r1:t
12114 + *[0-9a-f]*: ea 00 24 8e punpckub\.h lr,r5:b
12115 + *[0-9a-f]*: e4 00 24 9e punpckub\.h lr,r2:t
12117 +[0-9a-f]* <punpcksb_h>:
12118 + *[0-9a-f]*: fe 00 24 af punpcksb\.h pc,pc:b
12119 + *[0-9a-f]*: f8 00 24 bc punpcksb\.h r12,r12:t
12120 + *[0-9a-f]*: ea 00 24 b5 punpcksb\.h r5,r5:t
12121 + *[0-9a-f]*: e8 00 24 a4 punpcksb\.h r4,r4:b
12122 + *[0-9a-f]*: fc 00 24 be punpcksb\.h lr,lr:t
12123 + *[0-9a-f]*: ee 00 24 b4 punpcksb\.h r4,r7:t
12124 + *[0-9a-f]*: fc 00 24 a6 punpcksb\.h r6,lr:b
12125 + *[0-9a-f]*: f8 00 24 bc punpcksb\.h r12,r12:t
12127 +[0-9a-f]* <packsh_ub>:
12128 + *[0-9a-f]*: fe 0f 24 cf packsh\.ub pc,pc,pc
12129 + *[0-9a-f]*: f8 0c 24 cc packsh\.ub r12,r12,r12
12130 + *[0-9a-f]*: ea 05 24 c5 packsh\.ub r5,r5,r5
12131 + *[0-9a-f]*: e8 04 24 c4 packsh\.ub r4,r4,r4
12132 + *[0-9a-f]*: fc 0e 24 ce packsh\.ub lr,lr,lr
12133 + *[0-9a-f]*: ec 03 24 c3 packsh\.ub r3,r6,r3
12134 + *[0-9a-f]*: e0 03 24 c8 packsh\.ub r8,r0,r3
12135 + *[0-9a-f]*: e6 0e 24 c9 packsh\.ub r9,r3,lr
12137 +[0-9a-f]* <packsh_sb>:
12138 + *[0-9a-f]*: fe 0f 24 df packsh\.sb pc,pc,pc
12139 + *[0-9a-f]*: f8 0c 24 dc packsh\.sb r12,r12,r12
12140 + *[0-9a-f]*: ea 05 24 d5 packsh\.sb r5,r5,r5
12141 + *[0-9a-f]*: e8 04 24 d4 packsh\.sb r4,r4,r4
12142 + *[0-9a-f]*: fc 0e 24 de packsh\.sb lr,lr,lr
12143 + *[0-9a-f]*: f0 01 24 d6 packsh\.sb r6,r8,r1
12144 + *[0-9a-f]*: f2 08 24 de packsh\.sb lr,r9,r8
12145 + *[0-9a-f]*: ec 06 24 dd packsh\.sb sp,r6,r6
12148 + *[0-9a-f]*: e0 1f 00 00 andl pc,0x0
12149 + *[0-9a-f]*: e0 1c ff ff andl r12,0xffff
12150 + *[0-9a-f]*: e0 15 80 00 andl r5,0x8000
12151 + *[0-9a-f]*: e0 14 7f ff andl r4,0x7fff
12152 + *[0-9a-f]*: e0 1e 00 01 andl lr,0x1
12153 + *[0-9a-f]*: e0 1f 5a 58 andl pc,0x5a58
12154 + *[0-9a-f]*: e0 18 b8 9e andl r8,0xb89e
12155 + *[0-9a-f]*: e0 17 35 97 andl r7,0x3597
12157 +[0-9a-f]* <andl_coh>:
12158 + *[0-9a-f]*: e2 1f 00 00 andl pc,0x0,COH
12159 + *[0-9a-f]*: e2 1c ff ff andl r12,0xffff,COH
12160 + *[0-9a-f]*: e2 15 80 00 andl r5,0x8000,COH
12161 + *[0-9a-f]*: e2 14 7f ff andl r4,0x7fff,COH
12162 + *[0-9a-f]*: e2 1e 00 01 andl lr,0x1,COH
12163 + *[0-9a-f]*: e2 16 58 e1 andl r6,0x58e1,COH
12164 + *[0-9a-f]*: e2 10 9e cd andl r0,0x9ecd,COH
12165 + *[0-9a-f]*: e2 14 bd c4 andl r4,0xbdc4,COH
12168 + *[0-9a-f]*: e4 1f 00 00 andh pc,0x0
12169 + *[0-9a-f]*: e4 1c ff ff andh r12,0xffff
12170 + *[0-9a-f]*: e4 15 80 00 andh r5,0x8000
12171 + *[0-9a-f]*: e4 14 7f ff andh r4,0x7fff
12172 + *[0-9a-f]*: e4 1e 00 01 andh lr,0x1
12173 + *[0-9a-f]*: e4 1c cc 58 andh r12,0xcc58
12174 + *[0-9a-f]*: e4 13 21 e3 andh r3,0x21e3
12175 + *[0-9a-f]*: e4 12 a7 eb andh r2,0xa7eb
12177 +[0-9a-f]* <andh_coh>:
12178 + *[0-9a-f]*: e6 1f 00 00 andh pc,0x0,COH
12179 + *[0-9a-f]*: e6 1c ff ff andh r12,0xffff,COH
12180 + *[0-9a-f]*: e6 15 80 00 andh r5,0x8000,COH
12181 + *[0-9a-f]*: e6 14 7f ff andh r4,0x7fff,COH
12182 + *[0-9a-f]*: e6 1e 00 01 andh lr,0x1,COH
12183 + *[0-9a-f]*: e6 1b 86 0d andh r11,0x860d,COH
12184 + *[0-9a-f]*: e6 18 ce f6 andh r8,0xcef6,COH
12185 + *[0-9a-f]*: e6 1a 5c 83 andh r10,0x5c83,COH
12188 + *[0-9a-f]*: e8 1f 00 00 orl pc,0x0
12189 + *[0-9a-f]*: e8 1c ff ff orl r12,0xffff
12190 + *[0-9a-f]*: e8 15 80 00 orl r5,0x8000
12191 + *[0-9a-f]*: e8 14 7f ff orl r4,0x7fff
12192 + *[0-9a-f]*: e8 1e 00 01 orl lr,0x1
12193 + *[0-9a-f]*: e8 1d 41 7e orl sp,0x417e
12194 + *[0-9a-f]*: e8 10 52 bd orl r0,0x52bd
12195 + *[0-9a-f]*: e8 1f ac 47 orl pc,0xac47
12198 + *[0-9a-f]*: ea 1f 00 00 orh pc,0x0
12199 + *[0-9a-f]*: ea 1c ff ff orh r12,0xffff
12200 + *[0-9a-f]*: ea 15 80 00 orh r5,0x8000
12201 + *[0-9a-f]*: ea 14 7f ff orh r4,0x7fff
12202 + *[0-9a-f]*: ea 1e 00 01 orh lr,0x1
12203 + *[0-9a-f]*: ea 18 6e 7d orh r8,0x6e7d
12204 + *[0-9a-f]*: ea 1c 77 1c orh r12,0x771c
12205 + *[0-9a-f]*: ea 11 ea 1a orh r1,0xea1a
12208 + *[0-9a-f]*: ec 1f 00 00 eorl pc,0x0
12209 + *[0-9a-f]*: ec 1c ff ff eorl r12,0xffff
12210 + *[0-9a-f]*: ec 15 80 00 eorl r5,0x8000
12211 + *[0-9a-f]*: ec 14 7f ff eorl r4,0x7fff
12212 + *[0-9a-f]*: ec 1e 00 01 eorl lr,0x1
12213 + *[0-9a-f]*: ec 14 c7 b9 eorl r4,0xc7b9
12214 + *[0-9a-f]*: ec 16 fb dd eorl r6,0xfbdd
12215 + *[0-9a-f]*: ec 11 51 b1 eorl r1,0x51b1
12218 + *[0-9a-f]*: ee 1f 00 00 eorh pc,0x0
12219 + *[0-9a-f]*: ee 1c ff ff eorh r12,0xffff
12220 + *[0-9a-f]*: ee 15 80 00 eorh r5,0x8000
12221 + *[0-9a-f]*: ee 14 7f ff eorh r4,0x7fff
12222 + *[0-9a-f]*: ee 1e 00 01 eorh lr,0x1
12223 + *[0-9a-f]*: ee 10 2d d4 eorh r0,0x2dd4
12224 + *[0-9a-f]*: ee 1a 94 b5 eorh r10,0x94b5
12225 + *[0-9a-f]*: ee 19 df 2a eorh r9,0xdf2a
12227 +[0-9a-f]* <mcall>:
12228 + *[0-9a-f]*: f0 1f 00 00 mcall [0-9a-f]* <.*>
12229 + *[0-9a-f]*: f0 1c ff ff mcall r12\[-4\]
12230 + *[0-9a-f]*: f0 15 80 00 mcall r5\[-131072\]
12231 + *[0-9a-f]*: f0 14 7f ff mcall r4\[131068\]
12232 + *[0-9a-f]*: f0 1e 00 01 mcall lr\[4\]
12233 + *[0-9a-f]*: f0 1d 3b bf mcall sp\[61180\]
12234 + *[0-9a-f]*: f0 14 dd d2 mcall r4\[-35000\]
12235 + *[0-9a-f]*: f0 10 09 b1 mcall r0\[9924\]
12238 + *[0-9a-f]*: f2 1f 00 00 pref pc\[0\]
12239 + *[0-9a-f]*: f2 1c ff ff pref r12\[-1\]
12240 + *[0-9a-f]*: f2 15 80 00 pref r5\[-32768\]
12241 + *[0-9a-f]*: f2 14 7f ff pref r4\[32767\]
12242 + *[0-9a-f]*: f2 1e 00 01 pref lr\[1\]
12243 + *[0-9a-f]*: f2 17 1e 44 pref r7\[7748\]
12244 + *[0-9a-f]*: f2 17 e1 ed pref r7\[-7699\]
12245 + *[0-9a-f]*: f2 12 9a dc pref r2\[-25892\]
12247 +[0-9a-f]* <cache>:
12248 + *[0-9a-f]*: f4 1f 00 00 cache pc\[0\],0x0
12249 + *[0-9a-f]*: f4 1c ff ff cache r12\[-1\],0x1f
12250 + *[0-9a-f]*: f4 15 84 00 cache r5\[-1024\],0x10
12251 + *[0-9a-f]*: f4 14 7b ff cache r4\[1023\],0xf
12252 + *[0-9a-f]*: f4 1e 08 01 cache lr\[1\],0x1
12253 + *[0-9a-f]*: f4 13 8c 3c cache r3\[-964\],0x11
12254 + *[0-9a-f]*: f4 14 b6 89 cache r4\[-375\],0x16
12255 + *[0-9a-f]*: f4 13 8c 88 cache r3\[-888\],0x11
12258 + *[0-9a-f]*: 20 0f sub pc,0
12259 + *[0-9a-f]*: 2f fc sub r12,-1
12260 + *[0-9a-f]*: f0 25 00 00 sub r5,-1048576
12261 + *[0-9a-f]*: ee 34 ff ff sub r4,1048575
12262 + *[0-9a-f]*: 20 1e sub lr,1
12263 + *[0-9a-f]*: f6 22 8d 6c sub r2,-619156
12264 + *[0-9a-f]*: e6 3e 0a cd sub lr,461517
12265 + *[0-9a-f]*: fc 38 2d 25 sub r8,-185051
12268 + *[0-9a-f]*: 58 0f cp.w pc,0
12269 + *[0-9a-f]*: 5b fc cp.w r12,-1
12270 + *[0-9a-f]*: f0 45 00 00 cp.w r5,-1048576
12271 + *[0-9a-f]*: ee 54 ff ff cp.w r4,1048575
12272 + *[0-9a-f]*: 58 1e cp.w lr,1
12273 + *[0-9a-f]*: e0 51 e4 ae cp.w r1,124078
12274 + *[0-9a-f]*: fa 40 37 e3 cp.w r0,-378909
12275 + *[0-9a-f]*: fc 44 4a 14 cp.w r4,-243180
12278 + *[0-9a-f]*: 30 0f mov pc,0
12279 + *[0-9a-f]*: 3f fc mov r12,-1
12280 + *[0-9a-f]*: f0 65 00 00 mov r5,-1048576
12281 + *[0-9a-f]*: ee 74 ff ff mov r4,1048575
12282 + *[0-9a-f]*: 30 1e mov lr,1
12283 + *[0-9a-f]*: fa 75 29 a3 mov r5,-317021
12284 + *[0-9a-f]*: f4 6d 91 94 mov sp,-749164
12285 + *[0-9a-f]*: ee 65 58 93 mov r5,940179
12288 + *[0-9a-f]*: c0 00 breq [0-9a-f]* <.*>
12289 + *[0-9a-f]*: fe 9f ff ff bral [0-9a-f]* <.*>
12290 + *[0-9a-f]*: f0 88 00 00 brls [0-9a-f]* <.*>
12291 + *[0-9a-f]*: ee 97 ff ff brpl [0-9a-f]* <.*>
12292 + *[0-9a-f]*: c0 11 brne [0-9a-f]* <.*>
12293 + *[0-9a-f]*: f2 8b 4a 4d brhi [0-9a-f]* <.*>
12294 + *[0-9a-f]*: ea 8e 14 cc brqs [0-9a-f]* <.*>
12295 + *[0-9a-f]*: fa 98 98 33 brls [0-9a-f]* <.*>
12297 +[0-9a-f]* <rcall2>:
12298 + *[0-9a-f]*: c0 0c rcall [0-9a-f]* <.*>
12299 + *[0-9a-f]*: cf ff rcall [0-9a-f]* <.*>
12300 + *[0-9a-f]*: f0 a0 00 00 rcall [0-9a-f]* <.*>
12301 + *[0-9a-f]*: ee b0 ff ff rcall [0-9a-f]* <.*>
12302 + *[0-9a-f]*: c0 1c rcall [0-9a-f]* <.*>
12303 + *[0-9a-f]*: e2 b0 ca 5a rcall [0-9a-f]* <.*>
12304 + *[0-9a-f]*: e8 a0 47 52 rcall [0-9a-f]* <.*>
12305 + *[0-9a-f]*: fe b0 fd ef rcall [0-9a-f]* <.*>
12308 + *[0-9a-f]*: fe cf 00 00 sub pc,pc,0
12309 + *[0-9a-f]*: f8 cc ff ff sub r12,r12,-1
12310 + *[0-9a-f]*: ea c5 80 00 sub r5,r5,-32768
12311 + *[0-9a-f]*: e8 c4 7f ff sub r4,r4,32767
12312 + *[0-9a-f]*: fc ce 00 01 sub lr,lr,1
12313 + *[0-9a-f]*: fe cf ce 38 sub pc,pc,-12744
12314 + *[0-9a-f]*: ee c7 95 1b sub r7,r7,-27365
12315 + *[0-9a-f]*: f2 c2 bc 32 sub r2,r9,-17358
12317 +[0-9a-f]* <satsub_w2>:
12318 + *[0-9a-f]*: fe df 00 00 satsub\.w pc,pc,0
12319 + *[0-9a-f]*: f8 dc ff ff satsub\.w r12,r12,-1
12320 + *[0-9a-f]*: ea d5 80 00 satsub\.w r5,r5,-32768
12321 + *[0-9a-f]*: e8 d4 7f ff satsub\.w r4,r4,32767
12322 + *[0-9a-f]*: fc de 00 01 satsub\.w lr,lr,1
12323 + *[0-9a-f]*: fc d2 f8 29 satsub\.w r2,lr,-2007
12324 + *[0-9a-f]*: f8 d7 fc f0 satsub\.w r7,r12,-784
12325 + *[0-9a-f]*: ee d4 5a 8c satsub\.w r4,r7,23180
12327 +[0-9a-f]* <ld_d4>:
12328 + *[0-9a-f]*: fe e0 00 00 ld\.d r0,pc\[0\]
12329 + *[0-9a-f]*: f8 ee ff ff ld\.d lr,r12\[-1\]
12330 + *[0-9a-f]*: ea e8 80 00 ld\.d r8,r5\[-32768\]
12331 + *[0-9a-f]*: e8 e6 7f ff ld\.d r6,r4\[32767\]
12332 + *[0-9a-f]*: fc e2 00 01 ld\.d r2,lr\[1\]
12333 + *[0-9a-f]*: f6 ee 39 c0 ld\.d lr,r11\[14784\]
12334 + *[0-9a-f]*: f2 e6 b6 27 ld\.d r6,r9\[-18905\]
12335 + *[0-9a-f]*: e6 e2 e7 2d ld\.d r2,r3\[-6355\]
12337 +[0-9a-f]* <ld_w4>:
12338 + *[0-9a-f]*: 7e 0f ld\.w pc,pc\[0x0\]
12339 + *[0-9a-f]*: f8 fc ff ff ld\.w r12,r12\[-1\]
12340 + *[0-9a-f]*: ea f5 80 00 ld\.w r5,r5\[-32768\]
12341 + *[0-9a-f]*: e8 f4 7f ff ld\.w r4,r4\[32767\]
12342 + *[0-9a-f]*: fc fe 00 01 ld\.w lr,lr\[1\]
12343 + *[0-9a-f]*: f8 f0 a9 8b ld\.w r0,r12\[-22133\]
12344 + *[0-9a-f]*: fe fd af d7 ld\.w sp,pc\[-20521\]
12345 + *[0-9a-f]*: d7 03 nop
12347 +[0-9a-f]* <ld_sh4>:
12348 + *[0-9a-f]*: 9e 0f ld\.sh pc,pc\[0x0\]
12349 + *[0-9a-f]*: f9 0c ff ff ld\.sh r12,r12\[-1\]
12350 + *[0-9a-f]*: eb 05 80 00 ld\.sh r5,r5\[-32768\]
12351 + *[0-9a-f]*: e9 04 7f ff ld\.sh r4,r4\[32767\]
12352 + *[0-9a-f]*: fd 0e 00 01 ld\.sh lr,lr\[1\]
12353 + *[0-9a-f]*: f5 06 78 d2 ld\.sh r6,r10\[30930\]
12354 + *[0-9a-f]*: f5 06 55 d5 ld\.sh r6,r10\[21973\]
12355 + *[0-9a-f]*: d7 03 nop
12357 +[0-9a-f]* <ld_uh4>:
12358 + *[0-9a-f]*: 9e 8f ld\.uh pc,pc\[0x0\]
12359 + *[0-9a-f]*: f9 1c ff ff ld\.uh r12,r12\[-1\]
12360 + *[0-9a-f]*: eb 15 80 00 ld\.uh r5,r5\[-32768\]
12361 + *[0-9a-f]*: e9 14 7f ff ld\.uh r4,r4\[32767\]
12362 + *[0-9a-f]*: fd 1e 00 01 ld\.uh lr,lr\[1\]
12363 + *[0-9a-f]*: f3 11 cb d6 ld\.uh r1,r9\[-13354\]
12364 + *[0-9a-f]*: f7 1e 53 59 ld\.uh lr,r11\[21337\]
12365 + *[0-9a-f]*: d7 03 nop
12367 +[0-9a-f]* <ld_sb1>:
12368 + *[0-9a-f]*: ff 2f 00 00 ld\.sb pc,pc\[0\]
12369 + *[0-9a-f]*: f9 2c ff ff ld\.sb r12,r12\[-1\]
12370 + *[0-9a-f]*: eb 25 80 00 ld\.sb r5,r5\[-32768\]
12371 + *[0-9a-f]*: e9 24 7f ff ld\.sb r4,r4\[32767\]
12372 + *[0-9a-f]*: fd 2e 00 01 ld\.sb lr,lr\[1\]
12373 + *[0-9a-f]*: fb 27 90 09 ld\.sb r7,sp\[-28663\]
12374 + *[0-9a-f]*: e3 22 e9 09 ld\.sb r2,r1\[-5879\]
12375 + *[0-9a-f]*: e7 2c 49 2e ld\.sb r12,r3\[18734\]
12377 +[0-9a-f]* <ld_ub4>:
12378 + *[0-9a-f]*: 1f 8f ld\.ub pc,pc\[0x0\]
12379 + *[0-9a-f]*: f9 3c ff ff ld\.ub r12,r12\[-1\]
12380 + *[0-9a-f]*: eb 35 80 00 ld\.ub r5,r5\[-32768\]
12381 + *[0-9a-f]*: e9 34 7f ff ld\.ub r4,r4\[32767\]
12382 + *[0-9a-f]*: 1d 9e ld\.ub lr,lr\[0x1\]
12383 + *[0-9a-f]*: e9 3f 20 55 ld\.ub pc,r4\[8277\]
12384 + *[0-9a-f]*: f9 35 4a e4 ld\.ub r5,r12\[19172\]
12385 + *[0-9a-f]*: fd 3a 66 eb ld\.ub r10,lr\[26347\]
12387 +[0-9a-f]* <st_d4>:
12388 + *[0-9a-f]*: fe e1 00 00 st\.d pc\[0\],r0
12389 + *[0-9a-f]*: f8 ef ff ff st\.d r12\[-1\],lr
12390 + *[0-9a-f]*: ea e9 80 00 st\.d r5\[-32768\],r8
12391 + *[0-9a-f]*: e8 e7 7f ff st\.d r4\[32767\],r6
12392 + *[0-9a-f]*: fc e3 00 01 st\.d lr\[1\],r2
12393 + *[0-9a-f]*: ea eb 33 90 st\.d r5\[13200\],r10
12394 + *[0-9a-f]*: ea eb 24 88 st\.d r5\[9352\],r10
12395 + *[0-9a-f]*: ea e5 7e 75 st\.d r5\[32373\],r4
12397 +[0-9a-f]* <st_w4>:
12398 + *[0-9a-f]*: 9f 0f st\.w pc\[0x0\],pc
12399 + *[0-9a-f]*: f9 4c ff ff st\.w r12\[-1\],r12
12400 + *[0-9a-f]*: eb 45 80 00 st\.w r5\[-32768\],r5
12401 + *[0-9a-f]*: e9 44 7f ff st\.w r4\[32767\],r4
12402 + *[0-9a-f]*: fd 4e 00 01 st\.w lr\[1\],lr
12403 + *[0-9a-f]*: fb 47 17 f8 st\.w sp\[6136\],r7
12404 + *[0-9a-f]*: ed 4c 69 cf st\.w r6\[27087\],r12
12405 + *[0-9a-f]*: d7 03 nop
12407 +[0-9a-f]* <st_h4>:
12408 + *[0-9a-f]*: be 0f st\.h pc\[0x0\],pc
12409 + *[0-9a-f]*: f9 5c ff ff st\.h r12\[-1\],r12
12410 + *[0-9a-f]*: eb 55 80 00 st\.h r5\[-32768\],r5
12411 + *[0-9a-f]*: e9 54 7f ff st\.h r4\[32767\],r4
12412 + *[0-9a-f]*: fd 5e 00 01 st\.h lr\[1\],lr
12413 + *[0-9a-f]*: e9 57 d9 16 st\.h r4\[-9962\],r7
12414 + *[0-9a-f]*: f3 53 c0 86 st\.h r9\[-16250\],r3
12415 + *[0-9a-f]*: d7 03 nop
12417 +[0-9a-f]* <st_b4>:
12418 + *[0-9a-f]*: be 8f st\.b pc\[0x0\],pc
12419 + *[0-9a-f]*: f9 6c ff ff st\.b r12\[-1\],r12
12420 + *[0-9a-f]*: eb 65 80 00 st\.b r5\[-32768\],r5
12421 + *[0-9a-f]*: e9 64 7f ff st\.b r4\[32767\],r4
12422 + *[0-9a-f]*: bc 9e st\.b lr\[0x1\],lr
12423 + *[0-9a-f]*: f9 66 75 96 st\.b r12\[30102\],r6
12424 + *[0-9a-f]*: eb 61 71 31 st\.b r5\[28977\],r1
12425 + *[0-9a-f]*: e1 61 15 5e st\.b r0\[5470\],r1
12428 + *[0-9a-f]*: e1 bf 00 00 mfsr pc,0x0
12429 + *[0-9a-f]*: e1 bc 00 ff mfsr r12,0x3fc
12430 + *[0-9a-f]*: e1 b5 00 80 mfsr r5,0x200
12431 + *[0-9a-f]*: e1 b4 00 7f mfsr r4,0x1fc
12432 + *[0-9a-f]*: e1 be 00 01 mfsr lr,0x4
12433 + *[0-9a-f]*: e1 b2 00 ae mfsr r2,0x2b8
12434 + *[0-9a-f]*: e1 b4 00 41 mfsr r4,0x104
12435 + *[0-9a-f]*: e1 ba 00 fe mfsr r10,0x3f8
12438 + *[0-9a-f]*: e3 bf 00 00 mtsr 0x0,pc
12439 + *[0-9a-f]*: e3 bc 00 ff mtsr 0x3fc,r12
12440 + *[0-9a-f]*: e3 b5 00 80 mtsr 0x200,r5
12441 + *[0-9a-f]*: e3 b4 00 7f mtsr 0x1fc,r4
12442 + *[0-9a-f]*: e3 be 00 01 mtsr 0x4,lr
12443 + *[0-9a-f]*: e3 ba 00 38 mtsr 0xe0,r10
12444 + *[0-9a-f]*: e3 bc 00 d1 mtsr 0x344,r12
12445 + *[0-9a-f]*: e3 b9 00 4c mtsr 0x130,r9
12448 + *[0-9a-f]*: e5 bf 00 00 mfdr pc,0x0
12449 + *[0-9a-f]*: e5 bc 00 ff mfdr r12,0x3fc
12450 + *[0-9a-f]*: e5 b5 00 80 mfdr r5,0x200
12451 + *[0-9a-f]*: e5 b4 00 7f mfdr r4,0x1fc
12452 + *[0-9a-f]*: e5 be 00 01 mfdr lr,0x4
12453 + *[0-9a-f]*: e5 b6 00 e9 mfdr r6,0x3a4
12454 + *[0-9a-f]*: e5 b5 00 09 mfdr r5,0x24
12455 + *[0-9a-f]*: e5 b9 00 4b mfdr r9,0x12c
12458 + *[0-9a-f]*: e7 bf 00 00 mtdr 0x0,pc
12459 + *[0-9a-f]*: e7 bc 00 ff mtdr 0x3fc,r12
12460 + *[0-9a-f]*: e7 b5 00 80 mtdr 0x200,r5
12461 + *[0-9a-f]*: e7 b4 00 7f mtdr 0x1fc,r4
12462 + *[0-9a-f]*: e7 be 00 01 mtdr 0x4,lr
12463 + *[0-9a-f]*: e7 b8 00 2d mtdr 0xb4,r8
12464 + *[0-9a-f]*: e7 ba 00 b4 mtdr 0x2d0,r10
12465 + *[0-9a-f]*: e7 be 00 66 mtdr 0x198,lr
12467 +[0-9a-f]* <sleep>:
12468 + *[0-9a-f]*: e9 b0 00 00 sleep 0x0
12469 + *[0-9a-f]*: e9 b0 00 ff sleep 0xff
12470 + *[0-9a-f]*: e9 b0 00 80 sleep 0x80
12471 + *[0-9a-f]*: e9 b0 00 7f sleep 0x7f
12472 + *[0-9a-f]*: e9 b0 00 01 sleep 0x1
12473 + *[0-9a-f]*: e9 b0 00 fe sleep 0xfe
12474 + *[0-9a-f]*: e9 b0 00 0f sleep 0xf
12475 + *[0-9a-f]*: e9 b0 00 2b sleep 0x2b
12478 + *[0-9a-f]*: eb b0 00 00 sync 0x0
12479 + *[0-9a-f]*: eb b0 00 ff sync 0xff
12480 + *[0-9a-f]*: eb b0 00 80 sync 0x80
12481 + *[0-9a-f]*: eb b0 00 7f sync 0x7f
12482 + *[0-9a-f]*: eb b0 00 01 sync 0x1
12483 + *[0-9a-f]*: eb b0 00 a6 sync 0xa6
12484 + *[0-9a-f]*: eb b0 00 e6 sync 0xe6
12485 + *[0-9a-f]*: eb b0 00 b4 sync 0xb4
12488 + *[0-9a-f]*: ed bf 00 00 bld pc,0x0
12489 + *[0-9a-f]*: ed bc 00 1f bld r12,0x1f
12490 + *[0-9a-f]*: ed b5 00 10 bld r5,0x10
12491 + *[0-9a-f]*: ed b4 00 0f bld r4,0xf
12492 + *[0-9a-f]*: ed be 00 01 bld lr,0x1
12493 + *[0-9a-f]*: ed b9 00 0f bld r9,0xf
12494 + *[0-9a-f]*: ed b0 00 04 bld r0,0x4
12495 + *[0-9a-f]*: ed be 00 1a bld lr,0x1a
12498 + *[0-9a-f]*: ef bf 00 00 bst pc,0x0
12499 + *[0-9a-f]*: ef bc 00 1f bst r12,0x1f
12500 + *[0-9a-f]*: ef b5 00 10 bst r5,0x10
12501 + *[0-9a-f]*: ef b4 00 0f bst r4,0xf
12502 + *[0-9a-f]*: ef be 00 01 bst lr,0x1
12503 + *[0-9a-f]*: ef ba 00 1c bst r10,0x1c
12504 + *[0-9a-f]*: ef b0 00 03 bst r0,0x3
12505 + *[0-9a-f]*: ef bd 00 02 bst sp,0x2
12508 + *[0-9a-f]*: f1 bf 00 00 sats pc,0x0
12509 + *[0-9a-f]*: f1 bc 03 ff sats r12>>0x1f,0x1f
12510 + *[0-9a-f]*: f1 b5 02 10 sats r5>>0x10,0x10
12511 + *[0-9a-f]*: f1 b4 01 ef sats r4>>0xf,0xf
12512 + *[0-9a-f]*: f1 be 00 21 sats lr>>0x1,0x1
12513 + *[0-9a-f]*: f1 ba 02 63 sats r10>>0x3,0x13
12514 + *[0-9a-f]*: f1 ba 03 42 sats r10>>0x2,0x1a
12515 + *[0-9a-f]*: f1 b1 00 34 sats r1>>0x14,0x1
12518 + *[0-9a-f]*: f1 bf 04 00 satu pc,0x0
12519 + *[0-9a-f]*: f1 bc 07 ff satu r12>>0x1f,0x1f
12520 + *[0-9a-f]*: f1 b5 06 10 satu r5>>0x10,0x10
12521 + *[0-9a-f]*: f1 b4 05 ef satu r4>>0xf,0xf
12522 + *[0-9a-f]*: f1 be 04 21 satu lr>>0x1,0x1
12523 + *[0-9a-f]*: f1 bf 04 e5 satu pc>>0x5,0x7
12524 + *[0-9a-f]*: f1 b7 04 a5 satu r7>>0x5,0x5
12525 + *[0-9a-f]*: f1 b2 06 7a satu r2>>0x1a,0x13
12527 +[0-9a-f]* <satrnds>:
12528 + *[0-9a-f]*: f3 bf 00 00 satrnds pc,0x0
12529 + *[0-9a-f]*: f3 bc 03 ff satrnds r12>>0x1f,0x1f
12530 + *[0-9a-f]*: f3 b5 02 10 satrnds r5>>0x10,0x10
12531 + *[0-9a-f]*: f3 b4 01 ef satrnds r4>>0xf,0xf
12532 + *[0-9a-f]*: f3 be 00 21 satrnds lr>>0x1,0x1
12533 + *[0-9a-f]*: f3 b0 02 75 satrnds r0>>0x15,0x13
12534 + *[0-9a-f]*: f3 bd 00 40 satrnds sp,0x2
12535 + *[0-9a-f]*: f3 b7 03 a6 satrnds r7>>0x6,0x1d
12537 +[0-9a-f]* <satrndu>:
12538 + *[0-9a-f]*: f3 bf 04 00 satrndu pc,0x0
12539 + *[0-9a-f]*: f3 bc 07 ff satrndu r12>>0x1f,0x1f
12540 + *[0-9a-f]*: f3 b5 06 10 satrndu r5>>0x10,0x10
12541 + *[0-9a-f]*: f3 b4 05 ef satrndu r4>>0xf,0xf
12542 + *[0-9a-f]*: f3 be 04 21 satrndu lr>>0x1,0x1
12543 + *[0-9a-f]*: f3 bc 07 40 satrndu r12,0x1a
12544 + *[0-9a-f]*: f3 b4 04 75 satrndu r4>>0x15,0x3
12545 + *[0-9a-f]*: f3 ba 06 03 satrndu r10>>0x3,0x10
12547 +[0-9a-f]* <subfc>:
12548 + *[0-9a-f]*: f5 bf 00 00 subfeq pc,0
12549 + *[0-9a-f]*: f5 bc 0f ff subfal r12,-1
12550 + *[0-9a-f]*: f5 b5 08 80 subfls r5,-128
12551 + *[0-9a-f]*: f5 b4 07 7f subfpl r4,127
12552 + *[0-9a-f]*: f5 be 01 01 subfne lr,1
12553 + *[0-9a-f]*: f5 ba 08 08 subfls r10,8
12554 + *[0-9a-f]*: f5 bb 0d 63 subfvc r11,99
12555 + *[0-9a-f]*: f5 b2 0c 49 subfvs r2,73
12558 + *[0-9a-f]*: f7 bf 00 00 subeq pc,0
12559 + *[0-9a-f]*: f7 bc 0f ff subal r12,-1
12560 + *[0-9a-f]*: f7 b5 08 80 subls r5,-128
12561 + *[0-9a-f]*: f7 b4 07 7f subpl r4,127
12562 + *[0-9a-f]*: f7 be 01 01 subne lr,1
12563 + *[0-9a-f]*: f7 bc 08 76 subls r12,118
12564 + *[0-9a-f]*: f7 be 0d f4 subvc lr,-12
12565 + *[0-9a-f]*: f7 b4 06 f3 submi r4,-13
12567 +[0-9a-f]* <movc2>:
12568 + *[0-9a-f]*: f9 bf 00 00 moveq pc,0
12569 + *[0-9a-f]*: f9 bc 0f ff moval r12,-1
12570 + *[0-9a-f]*: f9 b5 08 80 movls r5,-128
12571 + *[0-9a-f]*: f9 b4 07 7f movpl r4,127
12572 + *[0-9a-f]*: f9 be 01 01 movne lr,1
12573 + *[0-9a-f]*: f9 b3 05 86 movlt r3,-122
12574 + *[0-9a-f]*: f9 b8 0d 02 movvc r8,2
12575 + *[0-9a-f]*: f9 b7 01 91 movne r7,-111
12578 + *[0-9a-f]*: e0 0f 18 00 cp\.b pc,r0
12579 + *[0-9a-f]*: fe 00 18 00 cp\.b r0,pc
12580 + *[0-9a-f]*: f0 07 18 00 cp\.b r7,r8
12581 + *[0-9a-f]*: ee 08 18 00 cp\.b r8,r7
12584 + *[0-9a-f]*: e0 0f 19 00 cp\.h pc,r0
12585 + *[0-9a-f]*: fe 00 19 00 cp\.h r0,pc
12586 + *[0-9a-f]*: f0 07 19 00 cp\.h r7,r8
12587 + *[0-9a-f]*: ee 08 19 00 cp\.h r8,r7
12590 + *[0-9a-f]*: e1 cf 00 7e ldm pc,r1-r6
12591 + *[0-9a-f]*: e1 cc ff ff ldm r12,r0-pc
12592 + *[0-9a-f]*: e1 c5 80 00 ldm r5,pc
12593 + *[0-9a-f]*: e1 c4 7f ff ldm r4,r0-lr
12594 + *[0-9a-f]*: e1 ce 00 01 ldm lr,r0
12595 + *[0-9a-f]*: e1 c9 40 22 ldm r9,r1,r5,lr
12596 + *[0-9a-f]*: e1 cb 81 ec ldm r11,r2-r3,r5-r8,pc
12597 + *[0-9a-f]*: e1 c6 a2 09 ldm r6,r0,r3,r9,sp,pc
12599 +[0-9a-f]* <ldm_pu>:
12600 + *[0-9a-f]*: e3 cf 03 c0 ldm pc\+\+,r6-r9
12601 + *[0-9a-f]*: e3 cc ff ff ldm r12\+\+,r0-pc
12602 + *[0-9a-f]*: e3 c5 80 00 ldm r5\+\+,pc
12603 + *[0-9a-f]*: e3 c4 7f ff ldm r4\+\+,r0-lr
12604 + *[0-9a-f]*: e3 ce 00 01 ldm lr\+\+,r0
12605 + *[0-9a-f]*: e3 cc d5 38 ldm r12\+\+,r3-r5,r8,r10,r12,lr-pc
12606 + *[0-9a-f]*: e3 ca c0 74 ldm r10\+\+,r2,r4-r6,lr-pc
12607 + *[0-9a-f]*: e3 c6 7e 1a ldm r6\+\+,r1,r3-r4,r9-lr
12609 +[0-9a-f]* <ldmts>:
12610 + *[0-9a-f]*: e5 cf 01 80 ldmts pc,r7-r8
12611 + *[0-9a-f]*: e5 cc ff ff ldmts r12,r0-pc
12612 + *[0-9a-f]*: e5 c5 80 00 ldmts r5,pc
12613 + *[0-9a-f]*: e5 c4 7f ff ldmts r4,r0-lr
12614 + *[0-9a-f]*: e5 ce 00 01 ldmts lr,r0
12615 + *[0-9a-f]*: e5 c0 18 06 ldmts r0,r1-r2,r11-r12
12616 + *[0-9a-f]*: e5 ce 61 97 ldmts lr,r0-r2,r4,r7-r8,sp-lr
12617 + *[0-9a-f]*: e5 cc c2 3b ldmts r12,r0-r1,r3-r5,r9,lr-pc
12619 +[0-9a-f]* <ldmts_pu>:
12620 + *[0-9a-f]*: e7 cf 02 00 ldmts pc\+\+,r9
12621 + *[0-9a-f]*: e7 cc ff ff ldmts r12\+\+,r0-pc
12622 + *[0-9a-f]*: e7 c5 80 00 ldmts r5\+\+,pc
12623 + *[0-9a-f]*: e7 c4 7f ff ldmts r4\+\+,r0-lr
12624 + *[0-9a-f]*: e7 ce 00 01 ldmts lr\+\+,r0
12625 + *[0-9a-f]*: e7 cd 0a bd ldmts sp\+\+,r0,r2-r5,r7,r9,r11
12626 + *[0-9a-f]*: e7 c5 0c 8e ldmts r5\+\+,r1-r3,r7,r10-r11
12627 + *[0-9a-f]*: e7 c8 a1 9c ldmts r8\+\+,r2-r4,r7-r8,sp,pc
12630 + *[0-9a-f]*: e9 cf 00 80 stm pc,r7
12631 + *[0-9a-f]*: e9 cc ff ff stm r12,r0-pc
12632 + *[0-9a-f]*: e9 c5 80 00 stm r5,pc
12633 + *[0-9a-f]*: e9 c4 7f ff stm r4,r0-lr
12634 + *[0-9a-f]*: e9 ce 00 01 stm lr,r0
12635 + *[0-9a-f]*: e9 cd 49 2c stm sp,r2-r3,r5,r8,r11,lr
12636 + *[0-9a-f]*: e9 c4 4c 5f stm r4,r0-r4,r6,r10-r11,lr
12637 + *[0-9a-f]*: e9 c9 f2 22 stm r9,r1,r5,r9,r12-pc
12639 +[0-9a-f]* <stm_pu>:
12640 + *[0-9a-f]*: eb cf 00 70 stm --pc,r4-r6
12641 + *[0-9a-f]*: eb cc ff ff stm --r12,r0-pc
12642 + *[0-9a-f]*: eb c5 80 00 stm --r5,pc
12643 + *[0-9a-f]*: eb c4 7f ff stm --r4,r0-lr
12644 + *[0-9a-f]*: eb ce 00 01 stm --lr,r0
12645 + *[0-9a-f]*: eb cb fb f1 stm --r11,r0,r4-r9,r11-pc
12646 + *[0-9a-f]*: eb cb 56 09 stm --r11,r0,r3,r9-r10,r12,lr
12647 + *[0-9a-f]*: eb c6 63 04 stm --r6,r2,r8-r9,sp-lr
12649 +[0-9a-f]* <stmts>:
12650 + *[0-9a-f]*: ed cf 01 00 stmts pc,r8
12651 + *[0-9a-f]*: ed cc ff ff stmts r12,r0-pc
12652 + *[0-9a-f]*: ed c5 80 00 stmts r5,pc
12653 + *[0-9a-f]*: ed c4 7f ff stmts r4,r0-lr
12654 + *[0-9a-f]*: ed ce 00 01 stmts lr,r0
12655 + *[0-9a-f]*: ed c1 c6 5b stmts r1,r0-r1,r3-r4,r6,r9-r10,lr-pc
12656 + *[0-9a-f]*: ed c3 1d c1 stmts r3,r0,r6-r8,r10-r12
12657 + *[0-9a-f]*: ed cb d6 d1 stmts r11,r0,r4,r6-r7,r9-r10,r12,lr-pc
12659 +[0-9a-f]* <stmts_pu>:
12660 + *[0-9a-f]*: ef cf 01 c0 stmts --pc,r6-r8
12661 + *[0-9a-f]*: ef cc ff ff stmts --r12,r0-pc
12662 + *[0-9a-f]*: ef c5 80 00 stmts --r5,pc
12663 + *[0-9a-f]*: ef c4 7f ff stmts --r4,r0-lr
12664 + *[0-9a-f]*: ef ce 00 01 stmts --lr,r0
12665 + *[0-9a-f]*: ef c2 36 19 stmts --r2,r0,r3-r4,r9-r10,r12-sp
12666 + *[0-9a-f]*: ef c3 c0 03 stmts --r3,r0-r1,lr-pc
12667 + *[0-9a-f]*: ef c0 44 7d stmts --r0,r0,r2-r6,r10,lr
12669 +[0-9a-f]* <ldins_h>:
12670 + *[0-9a-f]*: ff df 00 00 ldins\.h pc:b,pc\[0\]
12671 + *[0-9a-f]*: f9 dc 1f ff ldins\.h r12:t,r12\[-2\]
12672 + *[0-9a-f]*: eb d5 18 00 ldins\.h r5:t,r5\[-4096\]
12673 + *[0-9a-f]*: e9 d4 07 ff ldins\.h r4:b,r4\[4094\]
12674 + *[0-9a-f]*: fd de 10 01 ldins\.h lr:t,lr\[2\]
12675 + *[0-9a-f]*: fd d0 13 c5 ldins\.h r0:t,lr\[1930\]
12676 + *[0-9a-f]*: ef d3 0e f5 ldins\.h r3:b,r7\[-534\]
12677 + *[0-9a-f]*: f9 d2 0b 9a ldins\.h r2:b,r12\[-2252\]
12679 +[0-9a-f]* <ldins_b>:
12680 + *[0-9a-f]*: ff df 40 00 ldins\.b pc:b,pc\[0\]
12681 + *[0-9a-f]*: f9 dc 7f ff ldins\.b r12:t,r12\[-1\]
12682 + *[0-9a-f]*: eb d5 68 00 ldins\.b r5:u,r5\[-2048\]
12683 + *[0-9a-f]*: e9 d4 57 ff ldins\.b r4:l,r4\[2047\]
12684 + *[0-9a-f]*: fd de 50 01 ldins\.b lr:l,lr\[1\]
12685 + *[0-9a-f]*: e9 d6 7d 6a ldins\.b r6:t,r4\[-662\]
12686 + *[0-9a-f]*: e3 d5 4f 69 ldins\.b r5:b,r1\[-151\]
12687 + *[0-9a-f]*: f7 da 78 7d ldins\.b r10:t,r11\[-1923\]
12689 +[0-9a-f]* <ldswp_sh>:
12690 + *[0-9a-f]*: ff df 20 00 ldswp\.sh pc,pc\[0\]
12691 + *[0-9a-f]*: f9 dc 2f ff ldswp\.sh r12,r12\[-2\]
12692 + *[0-9a-f]*: eb d5 28 00 ldswp\.sh r5,r5\[-4096\]
12693 + *[0-9a-f]*: e9 d4 27 ff ldswp\.sh r4,r4\[4094\]
12694 + *[0-9a-f]*: fd de 20 01 ldswp\.sh lr,lr\[2\]
12695 + *[0-9a-f]*: f5 d9 27 84 ldswp\.sh r9,r10\[3848\]
12696 + *[0-9a-f]*: f9 d4 2c 04 ldswp\.sh r4,r12\[-2040\]
12697 + *[0-9a-f]*: e5 da 26 08 ldswp\.sh r10,r2\[3088\]
12699 +[0-9a-f]* <ldswp_uh>:
12700 + *[0-9a-f]*: ff df 30 00 ldswp\.uh pc,pc\[0\]
12701 + *[0-9a-f]*: f9 dc 3f ff ldswp\.uh r12,r12\[-2\]
12702 + *[0-9a-f]*: eb d5 38 00 ldswp\.uh r5,r5\[-4096\]
12703 + *[0-9a-f]*: e9 d4 37 ff ldswp\.uh r4,r4\[4094\]
12704 + *[0-9a-f]*: fd de 30 01 ldswp\.uh lr,lr\[2\]
12705 + *[0-9a-f]*: f3 d4 37 46 ldswp\.uh r4,r9\[3724\]
12706 + *[0-9a-f]*: fb de 3c bc ldswp\.uh lr,sp\[-1672\]
12707 + *[0-9a-f]*: f9 d8 38 7d ldswp\.uh r8,r12\[-3846\]
12709 +[0-9a-f]* <ldswp_w>:
12710 + *[0-9a-f]*: ff df 80 00 ldswp\.w pc,pc\[0\]
12711 + *[0-9a-f]*: f9 dc 8f ff ldswp\.w r12,r12\[-4\]
12712 + *[0-9a-f]*: eb d5 88 00 ldswp\.w r5,r5\[-8192\]
12713 + *[0-9a-f]*: e9 d4 87 ff ldswp\.w r4,r4\[8188\]
12714 + *[0-9a-f]*: fd de 80 01 ldswp\.w lr,lr\[4\]
12715 + *[0-9a-f]*: ef dd 81 d1 ldswp\.w sp,r7\[1860\]
12716 + *[0-9a-f]*: eb df 8c c1 ldswp\.w pc,r5\[-3324\]
12717 + *[0-9a-f]*: f5 dc 8c c8 ldswp\.w r12,r10\[-3296\]
12719 +[0-9a-f]* <stswp_h>:
12720 + *[0-9a-f]*: ff df 90 00 stswp\.h pc\[0\],pc
12721 + *[0-9a-f]*: f9 dc 9f ff stswp\.h r12\[-2\],r12
12722 + *[0-9a-f]*: eb d5 98 00 stswp\.h r5\[-4096\],r5
12723 + *[0-9a-f]*: e9 d4 97 ff stswp\.h r4\[4094\],r4
12724 + *[0-9a-f]*: fd de 90 01 stswp\.h lr\[2\],lr
12725 + *[0-9a-f]*: ef da 90 20 stswp\.h r7\[64\],r10
12726 + *[0-9a-f]*: f5 d2 95 e8 stswp\.h r10\[3024\],r2
12727 + *[0-9a-f]*: e1 da 9b 74 stswp\.h r0\[-2328\],r10
12729 +[0-9a-f]* <stswp_w>:
12730 + *[0-9a-f]*: ff df a0 00 stswp\.w pc\[0\],pc
12731 + *[0-9a-f]*: f9 dc af ff stswp\.w r12\[-4\],r12
12732 + *[0-9a-f]*: eb d5 a8 00 stswp\.w r5\[-8192\],r5
12733 + *[0-9a-f]*: e9 d4 a7 ff stswp\.w r4\[8188\],r4
12734 + *[0-9a-f]*: fd de a0 01 stswp\.w lr\[4\],lr
12735 + *[0-9a-f]*: ff d8 a1 21 stswp\.w pc\[1156\],r8
12736 + *[0-9a-f]*: fb da a7 ce stswp\.w sp\[7992\],r10
12737 + *[0-9a-f]*: f1 d5 ae db stswp\.w r8\[-1172\],r5
12740 + *[0-9a-f]*: ff ef 00 0f and pc,pc,pc
12741 + *[0-9a-f]*: f9 ec 01 fc and r12,r12,r12<<0x1f
12742 + *[0-9a-f]*: eb e5 01 05 and r5,r5,r5<<0x10
12743 + *[0-9a-f]*: e9 e4 00 f4 and r4,r4,r4<<0xf
12744 + *[0-9a-f]*: fd ee 00 1e and lr,lr,lr<<0x1
12745 + *[0-9a-f]*: e5 e1 00 1a and r10,r2,r1<<0x1
12746 + *[0-9a-f]*: f1 eb 01 bc and r12,r8,r11<<0x1b
12747 + *[0-9a-f]*: ef e0 00 3a and r10,r7,r0<<0x3
12750 + *[0-9a-f]*: ff ef 02 0f and pc,pc,pc
12751 + *[0-9a-f]*: f9 ec 03 fc and r12,r12,r12>>0x1f
12752 + *[0-9a-f]*: eb e5 03 05 and r5,r5,r5>>0x10
12753 + *[0-9a-f]*: e9 e4 02 f4 and r4,r4,r4>>0xf
12754 + *[0-9a-f]*: fd ee 02 1e and lr,lr,lr>>0x1
12755 + *[0-9a-f]*: f1 e7 03 1c and r12,r8,r7>>0x11
12756 + *[0-9a-f]*: e9 e9 03 4f and pc,r4,r9>>0x14
12757 + *[0-9a-f]*: f3 ea 02 ca and r10,r9,r10>>0xc
12760 + *[0-9a-f]*: ff ef 10 0f or pc,pc,pc
12761 + *[0-9a-f]*: f9 ec 11 fc or r12,r12,r12<<0x1f
12762 + *[0-9a-f]*: eb e5 11 05 or r5,r5,r5<<0x10
12763 + *[0-9a-f]*: e9 e4 10 f4 or r4,r4,r4<<0xf
12764 + *[0-9a-f]*: fd ee 10 1e or lr,lr,lr<<0x1
12765 + *[0-9a-f]*: fb eb 11 d8 or r8,sp,r11<<0x1d
12766 + *[0-9a-f]*: f3 e2 11 cf or pc,r9,r2<<0x1c
12767 + *[0-9a-f]*: e3 e2 10 35 or r5,r1,r2<<0x3
12770 + *[0-9a-f]*: ff ef 12 0f or pc,pc,pc
12771 + *[0-9a-f]*: f9 ec 13 fc or r12,r12,r12>>0x1f
12772 + *[0-9a-f]*: eb e5 13 05 or r5,r5,r5>>0x10
12773 + *[0-9a-f]*: e9 e4 12 f4 or r4,r4,r4>>0xf
12774 + *[0-9a-f]*: fd ee 12 1e or lr,lr,lr>>0x1
12775 + *[0-9a-f]*: fb ed 12 21 or r1,sp,sp>>0x2
12776 + *[0-9a-f]*: e3 e1 13 d0 or r0,r1,r1>>0x1d
12777 + *[0-9a-f]*: f9 e8 12 84 or r4,r12,r8>>0x8
12780 + *[0-9a-f]*: ff ef 20 0f eor pc,pc,pc
12781 + *[0-9a-f]*: f9 ec 21 fc eor r12,r12,r12<<0x1f
12782 + *[0-9a-f]*: eb e5 21 05 eor r5,r5,r5<<0x10
12783 + *[0-9a-f]*: e9 e4 20 f4 eor r4,r4,r4<<0xf
12784 + *[0-9a-f]*: fd ee 20 1e eor lr,lr,lr<<0x1
12785 + *[0-9a-f]*: f3 e4 20 ba eor r10,r9,r4<<0xb
12786 + *[0-9a-f]*: e1 e1 21 f4 eor r4,r0,r1<<0x1f
12787 + *[0-9a-f]*: e5 ec 20 d6 eor r6,r2,r12<<0xd
12790 + *[0-9a-f]*: ff ef 22 0f eor pc,pc,pc
12791 + *[0-9a-f]*: f9 ec 23 fc eor r12,r12,r12>>0x1f
12792 + *[0-9a-f]*: eb e5 23 05 eor r5,r5,r5>>0x10
12793 + *[0-9a-f]*: e9 e4 22 f4 eor r4,r4,r4>>0xf
12794 + *[0-9a-f]*: fd ee 22 1e eor lr,lr,lr>>0x1
12795 + *[0-9a-f]*: eb e5 23 65 eor r5,r5,r5>>0x16
12796 + *[0-9a-f]*: e3 ee 22 3a eor r10,r1,lr>>0x3
12797 + *[0-9a-f]*: fd ed 23 a7 eor r7,lr,sp>>0x1a
12799 +[0-9a-f]* <sthh_w2>:
12800 + *[0-9a-f]*: ff ef 8f 0f sthh\.w pc\[pc\],pc:b,pc:b
12801 + *[0-9a-f]*: f9 ec bc 3c sthh\.w r12\[r12<<0x3\],r12:t,r12:t
12802 + *[0-9a-f]*: eb e5 b5 25 sthh\.w r5\[r5<<0x2\],r5:t,r5:t
12803 + *[0-9a-f]*: e9 e4 84 14 sthh\.w r4\[r4<<0x1\],r4:b,r4:b
12804 + *[0-9a-f]*: fd ee be 1e sthh\.w lr\[lr<<0x1\],lr:t,lr:t
12805 + *[0-9a-f]*: e3 ec b6 3d sthh\.w sp\[r6<<0x3\],r1:t,r12:t
12806 + *[0-9a-f]*: f3 e9 b6 06 sthh\.w r6\[r6\],r9:t,r9:t
12807 + *[0-9a-f]*: e1 eb 93 0a sthh\.w r10\[r3\],r0:b,r11:t
12809 +[0-9a-f]* <sthh_w1>:
12810 + *[0-9a-f]*: ff ef c0 0f sthh\.w pc\[0x0\],pc:b,pc:b
12811 + *[0-9a-f]*: f9 ec ff fc sthh\.w r12\[0x3fc\],r12:t,r12:t
12812 + *[0-9a-f]*: eb e5 f8 05 sthh\.w r5\[0x200\],r5:t,r5:t
12813 + *[0-9a-f]*: e9 e4 c7 f4 sthh\.w r4\[0x1fc\],r4:b,r4:b
12814 + *[0-9a-f]*: fd ee f0 1e sthh\.w lr\[0x4\],lr:t,lr:t
12815 + *[0-9a-f]*: f3 e0 e6 54 sthh\.w r4\[0x194\],r9:t,r0:b
12816 + *[0-9a-f]*: e5 ea e5 78 sthh\.w r8\[0x15c\],r2:t,r10:b
12817 + *[0-9a-f]*: f3 e2 c2 bd sthh\.w sp\[0xac\],r9:b,r2:b
12820 + *[0-9a-f]*: e1 a0 00 00 cop cp0,cr0,cr0,cr0,0x0
12821 + *[0-9a-f]*: e7 af ff ff cop cp7,cr15,cr15,cr15,0x7f
12822 + *[0-9a-f]*: e3 a8 75 55 cop cp3,cr5,cr5,cr5,0x31
12823 + *[0-9a-f]*: e3 a8 44 44 cop cp2,cr4,cr4,cr4,0x30
12824 + *[0-9a-f]*: e5 ad a8 37 cop cp5,cr8,cr3,cr7,0x5a
12826 +[0-9a-f]* <ldc_w1>:
12827 + *[0-9a-f]*: e9 a0 00 00 ldc\.w cp0,cr0,r0\[0x0\]
12828 + *[0-9a-f]*: e9 af ef ff ldc\.w cp7,cr15,pc\[0x3fc\]
12829 + *[0-9a-f]*: e9 a5 65 80 ldc\.w cp3,cr5,r5\[0x200\]
12830 + *[0-9a-f]*: e9 a4 44 7f ldc\.w cp2,cr4,r4\[0x1fc\]
12831 + *[0-9a-f]*: e9 ad 89 24 ldc\.w cp4,cr9,sp\[0x90\]
12833 +[0-9a-f]* <ldc_w2>:
12834 + *[0-9a-f]*: ef a0 00 40 ldc\.w cp0,cr0,--r0
12835 + *[0-9a-f]*: ef af ef 40 ldc\.w cp7,cr15,--pc
12836 + *[0-9a-f]*: ef a5 65 40 ldc\.w cp3,cr5,--r5
12837 + *[0-9a-f]*: ef a4 44 40 ldc\.w cp2,cr4,--r4
12838 + *[0-9a-f]*: ef ad 89 40 ldc\.w cp4,cr9,--sp
12840 +[0-9a-f]* <ldc_w3>:
12841 + *[0-9a-f]*: ef a0 10 00 ldc\.w cp0,cr0,r0\[r0\]
12842 + *[0-9a-f]*: ef af ff 3f ldc\.w cp7,cr15,pc\[pc<<0x3\]
12843 + *[0-9a-f]*: ef a5 75 24 ldc\.w cp3,cr5,r5\[r4<<0x2\]
12844 + *[0-9a-f]*: ef a4 54 13 ldc\.w cp2,cr4,r4\[r3<<0x1\]
12845 + *[0-9a-f]*: ef ad 99 0c ldc\.w cp4,cr9,sp\[r12\]
12847 +[0-9a-f]* <ldc_d1>:
12848 + *[0-9a-f]*: e9 a0 10 00 ldc\.d cp0,cr0,r0\[0x0\]
12849 + *[0-9a-f]*: e9 af fe ff ldc\.d cp7,cr14,pc\[0x3fc\]
12850 + *[0-9a-f]*: e9 a5 76 80 ldc\.d cp3,cr6,r5\[0x200\]
12851 + *[0-9a-f]*: e9 a4 54 7f ldc\.d cp2,cr4,r4\[0x1fc\]
12852 + *[0-9a-f]*: e9 ad 98 24 ldc\.d cp4,cr8,sp\[0x90\]
12854 +[0-9a-f]* <ldc_d2>:
12855 + *[0-9a-f]*: ef a0 00 50 ldc\.d cp0,cr0,--r0
12856 + *[0-9a-f]*: ef af ee 50 ldc\.d cp7,cr14,--pc
12857 + *[0-9a-f]*: ef a5 66 50 ldc\.d cp3,cr6,--r5
12858 + *[0-9a-f]*: ef a4 44 50 ldc\.d cp2,cr4,--r4
12859 + *[0-9a-f]*: ef ad 88 50 ldc\.d cp4,cr8,--sp
12861 +[0-9a-f]* <ldc_d3>:
12862 + *[0-9a-f]*: ef a0 10 40 ldc\.d cp0,cr0,r0\[r0\]
12863 + *[0-9a-f]*: ef af fe 7f ldc\.d cp7,cr14,pc\[pc<<0x3\]
12864 + *[0-9a-f]*: ef a5 76 64 ldc\.d cp3,cr6,r5\[r4<<0x2\]
12865 + *[0-9a-f]*: ef a4 54 53 ldc\.d cp2,cr4,r4\[r3<<0x1\]
12866 + *[0-9a-f]*: ef ad 98 4c ldc\.d cp4,cr8,sp\[r12\]
12868 +[0-9a-f]* <stc_w1>:
12869 + *[0-9a-f]*: eb a0 00 00 stc\.w cp0,r0\[0x0\],cr0
12870 + *[0-9a-f]*: eb af ef ff stc\.w cp7,pc\[0x3fc\],cr15
12871 + *[0-9a-f]*: eb a5 65 80 stc\.w cp3,r5\[0x200\],cr5
12872 + *[0-9a-f]*: eb a4 44 7f stc\.w cp2,r4\[0x1fc\],cr4
12873 + *[0-9a-f]*: eb ad 89 24 stc\.w cp4,sp\[0x90\],cr9
12875 +[0-9a-f]* <stc_w2>:
12876 + *[0-9a-f]*: ef a0 00 60 stc\.w cp0,r0\+\+,cr0
12877 + *[0-9a-f]*: ef af ef 60 stc\.w cp7,pc\+\+,cr15
12878 + *[0-9a-f]*: ef a5 65 60 stc\.w cp3,r5\+\+,cr5
12879 + *[0-9a-f]*: ef a4 44 60 stc\.w cp2,r4\+\+,cr4
12880 + *[0-9a-f]*: ef ad 89 60 stc\.w cp4,sp\+\+,cr9
12882 +[0-9a-f]* <stc_w3>:
12883 + *[0-9a-f]*: ef a0 10 80 stc\.w cp0,r0\[r0\],cr0
12884 + *[0-9a-f]*: ef af ff bf stc\.w cp7,pc\[pc<<0x3\],cr15
12885 + *[0-9a-f]*: ef a5 75 a4 stc\.w cp3,r5\[r4<<0x2\],cr5
12886 + *[0-9a-f]*: ef a4 54 93 stc\.w cp2,r4\[r3<<0x1\],cr4
12887 + *[0-9a-f]*: ef ad 99 8c stc\.w cp4,sp\[r12\],cr9
12889 +[0-9a-f]* <stc_d1>:
12890 + *[0-9a-f]*: eb a0 10 00 stc\.d cp0,r0\[0x0\],cr0
12891 + *[0-9a-f]*: eb af fe ff stc\.d cp7,pc\[0x3fc\],cr14
12892 + *[0-9a-f]*: eb a5 76 80 stc\.d cp3,r5\[0x200\],cr6
12893 + *[0-9a-f]*: eb a4 54 7f stc\.d cp2,r4\[0x1fc\],cr4
12894 + *[0-9a-f]*: eb ad 98 24 stc\.d cp4,sp\[0x90\],cr8
12896 +[0-9a-f]* <stc_d2>:
12897 + *[0-9a-f]*: ef a0 00 70 stc\.d cp0,r0\+\+,cr0
12898 + *[0-9a-f]*: ef af ee 70 stc\.d cp7,pc\+\+,cr14
12899 + *[0-9a-f]*: ef a5 66 70 stc\.d cp3,r5\+\+,cr6
12900 + *[0-9a-f]*: ef a4 44 70 stc\.d cp2,r4\+\+,cr4
12901 + *[0-9a-f]*: ef ad 88 70 stc\.d cp4,sp\+\+,cr8
12903 +[0-9a-f]* <stc_d3>:
12904 + *[0-9a-f]*: ef a0 10 c0 stc\.d cp0,r0\[r0\],cr0
12905 + *[0-9a-f]*: ef af fe ff stc\.d cp7,pc\[pc<<0x3\],cr14
12906 + *[0-9a-f]*: ef a5 76 e4 stc\.d cp3,r5\[r4<<0x2\],cr6
12907 + *[0-9a-f]*: ef a4 54 d3 stc\.d cp2,r4\[r3<<0x1\],cr4
12908 + *[0-9a-f]*: ef ad 98 cc stc\.d cp4,sp\[r12\],cr8
12910 +[0-9a-f]* <ldc0_w>:
12911 + *[0-9a-f]*: f1 a0 00 00 ldc0\.w cr0,r0\[0x0\]
12912 + *[0-9a-f]*: f1 af ff ff ldc0\.w cr15,pc\[0x3ffc\]
12913 + *[0-9a-f]*: f1 a5 85 00 ldc0\.w cr5,r5\[0x2000\]
12914 + *[0-9a-f]*: f1 a4 74 ff ldc0\.w cr4,r4\[0x1ffc\]
12915 + *[0-9a-f]*: f1 ad 09 93 ldc0\.w cr9,sp\[0x24c\]
12917 +[0-9a-f]* <ldc0_d>:
12918 + *[0-9a-f]*: f3 a0 00 00 ldc0\.d cr0,r0\[0x0\]
12919 + *[0-9a-f]*: f3 af fe ff ldc0\.d cr14,pc\[0x3ffc\]
12920 + *[0-9a-f]*: f3 a5 86 00 ldc0\.d cr6,r5\[0x2000\]
12921 + *[0-9a-f]*: f3 a4 74 ff ldc0\.d cr4,r4\[0x1ffc\]
12922 + *[0-9a-f]*: f3 ad 08 93 ldc0\.d cr8,sp\[0x24c\]
12924 +[0-9a-f]* <stc0_w>:
12925 + *[0-9a-f]*: f5 a0 00 00 stc0\.w r0\[0x0\],cr0
12926 + *[0-9a-f]*: f5 af ff ff stc0\.w pc\[0x3ffc\],cr15
12927 + *[0-9a-f]*: f5 a5 85 00 stc0\.w r5\[0x2000\],cr5
12928 + *[0-9a-f]*: f5 a4 74 ff stc0\.w r4\[0x1ffc\],cr4
12929 + *[0-9a-f]*: f5 ad 09 93 stc0\.w sp\[0x24c\],cr9
12931 +[0-9a-f]* <stc0_d>:
12932 + *[0-9a-f]*: f7 a0 00 00 stc0\.d r0\[0x0\],cr0
12933 + *[0-9a-f]*: f7 af fe ff stc0\.d pc\[0x3ffc\],cr14
12934 + *[0-9a-f]*: f7 a5 86 00 stc0\.d r5\[0x2000\],cr6
12935 + *[0-9a-f]*: f7 a4 74 ff stc0\.d r4\[0x1ffc\],cr4
12936 + *[0-9a-f]*: f7 ad 08 93 stc0\.d sp\[0x24c\],cr8
12939 + *[0-9a-f]*: f6 10 00 00 memc 0,0x0
12940 + *[0-9a-f]*: f6 1f ff ff memc -4,0x1f
12941 + *[0-9a-f]*: f6 18 40 00 memc -65536,0x10
12942 + *[0-9a-f]*: f6 17 bf ff memc 65532,0xf
12945 + *[0-9a-f]*: f8 10 00 00 mems 0,0x0
12946 + *[0-9a-f]*: f8 1f ff ff mems -4,0x1f
12947 + *[0-9a-f]*: f8 18 40 00 mems -65536,0x10
12948 + *[0-9a-f]*: f8 17 bf ff mems 65532,0xf
12951 + *[0-9a-f]*: fa 10 00 00 memt 0,0x0
12952 + *[0-9a-f]*: fa 1f ff ff memt -4,0x1f
12953 + *[0-9a-f]*: fa 18 40 00 memt -65536,0x10
12954 + *[0-9a-f]*: fa 17 bf ff memt 65532,0xf
12956 +[0-9a-f]* <stcond>:
12957 + *[0-9a-f]*: e1 70 00 00 stcond r0\[0\],r0
12958 + *[0-9a-f]*: ff 7f ff ff stcond pc\[-1\],pc
12959 + *[0-9a-f]*: f1 77 80 00 stcond r8\[-32768\],r7
12960 + *[0-9a-f]*: ef 78 7f ff stcond r7\[32767\],r8
12961 + *[0-9a-f]*: eb 7a 12 34 stcond r5\[4660\],r10
12963 +[0-9a-f]* <ldcm_w>:
12964 + *[0-9a-f]*: ed af 00 ff ldcm\.w cp0,pc,cr0-cr7
12965 + *[0-9a-f]*: ed a0 e0 01 ldcm\.w cp7,r0,cr0
12966 + *[0-9a-f]*: ed a4 90 7f ldcm\.w cp4,r4\+\+,cr0-cr6
12967 + *[0-9a-f]*: ed a7 60 80 ldcm\.w cp3,r7,cr7
12968 + *[0-9a-f]*: ed ac 30 72 ldcm\.w cp1,r12\+\+,cr1,cr4-cr6
12969 + *[0-9a-f]*: ed af 01 ff ldcm\.w cp0,pc,cr8-cr15
12970 + *[0-9a-f]*: ed a0 e1 01 ldcm\.w cp7,r0,cr8
12971 + *[0-9a-f]*: ed a4 91 7f ldcm\.w cp4,r4\+\+,cr8-cr14
12972 + *[0-9a-f]*: ed a7 61 80 ldcm\.w cp3,r7,cr15
12973 + *[0-9a-f]*: ed ac 31 72 ldcm\.w cp1,r12\+\+,cr9,cr12-cr14
12975 +[0-9a-f]* <ldcm_d>:
12976 + *[0-9a-f]*: ed af 04 ff ldcm\.d cp0,pc,cr0-cr15
12977 + *[0-9a-f]*: ed a0 e4 01 ldcm\.d cp7,r0,cr0-cr1
12978 + *[0-9a-f]*: ed a4 94 7f ldcm\.d cp4,r4\+\+,cr0-cr13
12979 + *[0-9a-f]*: ed a7 64 80 ldcm\.d cp3,r7,cr14-cr15
12980 + *[0-9a-f]*: ed ac 54 93 ldcm\.d cp2,r12\+\+,cr0-cr3,cr8-cr9,cr14-cr15
12982 +[0-9a-f]* <stcm_w>:
12983 + *[0-9a-f]*: ed af 02 ff stcm\.w cp0,pc,cr0-cr7
12984 + *[0-9a-f]*: ed a0 e2 01 stcm\.w cp7,r0,cr0
12985 + *[0-9a-f]*: ed a4 92 7f stcm\.w cp4,--r4,cr0-cr6
12986 + *[0-9a-f]*: ed a7 62 80 stcm\.w cp3,r7,cr7
12987 + *[0-9a-f]*: ed ac 32 72 stcm\.w cp1,--r12,cr1,cr4-cr6
12988 + *[0-9a-f]*: ed af 03 ff stcm\.w cp0,pc,cr8-cr15
12989 + *[0-9a-f]*: ed a0 e3 01 stcm\.w cp7,r0,cr8
12990 + *[0-9a-f]*: ed a4 93 7f stcm\.w cp4,--r4,cr8-cr14
12991 + *[0-9a-f]*: ed a7 63 80 stcm\.w cp3,r7,cr15
12992 + *[0-9a-f]*: ed ac 33 72 stcm\.w cp1,--r12,cr9,cr12-cr14
12994 +[0-9a-f]* <stcm_d>:
12995 + *[0-9a-f]*: ed af 05 ff stcm\.d cp0,pc,cr0-cr15
12996 + *[0-9a-f]*: ed a0 e5 01 stcm\.d cp7,r0,cr0-cr1
12997 + *[0-9a-f]*: ed a4 95 7f stcm\.d cp4,--r4,cr0-cr13
12998 + *[0-9a-f]*: ed a7 65 80 stcm\.d cp3,r7,cr14-cr15
12999 + *[0-9a-f]*: ed ac 55 93 stcm\.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
13001 +[0-9a-f]* <mvcr_w>:
13002 + *[0-9a-f]*: ef af ef 00 mvcr\.w cp7,pc,cr15
13003 + *[0-9a-f]*: ef a0 00 00 mvcr\.w cp0,r0,cr0
13004 + *[0-9a-f]*: ef af 0f 00 mvcr\.w cp0,pc,cr15
13005 + *[0-9a-f]*: ef a0 ef 00 mvcr\.w cp7,r0,cr15
13006 + *[0-9a-f]*: ef af e0 00 mvcr\.w cp7,pc,cr0
13007 + *[0-9a-f]*: ef a7 88 00 mvcr\.w cp4,r7,cr8
13008 + *[0-9a-f]*: ef a8 67 00 mvcr\.w cp3,r8,cr7
13010 +[0-9a-f]* <mvcr_d>:
13011 + *[0-9a-f]*: ef ae ee 10 mvcr\.d cp7,lr,cr14
13012 + *[0-9a-f]*: ef a0 00 10 mvcr\.d cp0,r0,cr0
13013 + *[0-9a-f]*: ef ae 0e 10 mvcr\.d cp0,lr,cr14
13014 + *[0-9a-f]*: ef a0 ee 10 mvcr\.d cp7,r0,cr14
13015 + *[0-9a-f]*: ef ae e0 10 mvcr\.d cp7,lr,cr0
13016 + *[0-9a-f]*: ef a6 88 10 mvcr\.d cp4,r6,cr8
13017 + *[0-9a-f]*: ef a8 66 10 mvcr\.d cp3,r8,cr6
13019 +[0-9a-f]* <mvrc_w>:
13020 + *[0-9a-f]*: ef af ef 20 mvrc\.w cp7,cr15,pc
13021 + *[0-9a-f]*: ef a0 00 20 mvrc\.w cp0,cr0,r0
13022 + *[0-9a-f]*: ef af 0f 20 mvrc\.w cp0,cr15,pc
13023 + *[0-9a-f]*: ef a0 ef 20 mvrc\.w cp7,cr15,r0
13024 + *[0-9a-f]*: ef af e0 20 mvrc\.w cp7,cr0,pc
13025 + *[0-9a-f]*: ef a7 88 20 mvrc\.w cp4,cr8,r7
13026 + *[0-9a-f]*: ef a8 67 20 mvrc\.w cp3,cr7,r8
13028 +[0-9a-f]* <mvrc_d>:
13029 + *[0-9a-f]*: ef ae ee 30 mvrc\.d cp7,cr14,lr
13030 + *[0-9a-f]*: ef a0 00 30 mvrc\.d cp0,cr0,r0
13031 + *[0-9a-f]*: ef ae 0e 30 mvrc\.d cp0,cr14,lr
13032 + *[0-9a-f]*: ef a0 ee 30 mvrc\.d cp7,cr14,r0
13033 + *[0-9a-f]*: ef ae e0 30 mvrc\.d cp7,cr0,lr
13034 + *[0-9a-f]*: ef a6 88 30 mvrc\.d cp4,cr8,r6
13035 + *[0-9a-f]*: ef a8 66 30 mvrc\.d cp3,cr6,r8
13037 +[0-9a-f]* <bfexts>:
13038 + *[0-9a-f]*: ff df b3 ff bfexts pc,pc,0x1f,0x1f
13039 + *[0-9a-f]*: e1 d0 b0 00 bfexts r0,r0,0x0,0x0
13040 + *[0-9a-f]*: e1 df b3 ff bfexts r0,pc,0x1f,0x1f
13041 + *[0-9a-f]*: ff d0 b3 ff bfexts pc,r0,0x1f,0x1f
13042 + *[0-9a-f]*: ff df b0 1f bfexts pc,pc,0x0,0x1f
13043 + *[0-9a-f]*: ff df b3 e0 bfexts pc,pc,0x1f,0x0
13044 + *[0-9a-f]*: ef d8 b1 f0 bfexts r7,r8,0xf,0x10
13045 + *[0-9a-f]*: f1 d7 b2 0f bfexts r8,r7,0x10,0xf
13047 +[0-9a-f]* <bfextu>:
13048 + *[0-9a-f]*: ff df c3 ff bfextu pc,pc,0x1f,0x1f
13049 + *[0-9a-f]*: e1 d0 c0 00 bfextu r0,r0,0x0,0x0
13050 + *[0-9a-f]*: e1 df c3 ff bfextu r0,pc,0x1f,0x1f
13051 + *[0-9a-f]*: ff d0 c3 ff bfextu pc,r0,0x1f,0x1f
13052 + *[0-9a-f]*: ff df c0 1f bfextu pc,pc,0x0,0x1f
13053 + *[0-9a-f]*: ff df c3 e0 bfextu pc,pc,0x1f,0x0
13054 + *[0-9a-f]*: ef d8 c1 f0 bfextu r7,r8,0xf,0x10
13055 + *[0-9a-f]*: f1 d7 c2 0f bfextu r8,r7,0x10,0xf
13057 +[0-9a-f]* <bfins>:
13058 + *[0-9a-f]*: ff df d3 ff bfins pc,pc,0x1f,0x1f
13059 + *[0-9a-f]*: e1 d0 d0 00 bfins r0,r0,0x0,0x0
13060 + *[0-9a-f]*: e1 df d3 ff bfins r0,pc,0x1f,0x1f
13061 + *[0-9a-f]*: ff d0 d3 ff bfins pc,r0,0x1f,0x1f
13062 + *[0-9a-f]*: ff df d0 1f bfins pc,pc,0x0,0x1f
13063 + *[0-9a-f]*: ff df d3 e0 bfins pc,pc,0x1f,0x0
13064 + *[0-9a-f]*: ef d8 d1 f0 bfins r7,r8,0xf,0x10
13065 + *[0-9a-f]*: f1 d7 d2 0f bfins r8,r7,0x10,0xf
13067 +[0-9a-f]* <rsubc>:
13068 + *[0-9a-f]*: fb bf 00 00 rsubeq pc,0
13069 + *[0-9a-f]*: fb bc 0f ff rsubal r12,-1
13070 + *[0-9a-f]*: fb b5 08 80 rsubls r5,-128
13071 + *[0-9a-f]*: fb b4 07 7f rsubpl r4,127
13072 + *[0-9a-f]*: fb be 01 01 rsubne lr,1
13073 + *[0-9a-f]*: fb bc 08 76 rsubls r12,118
13074 + *[0-9a-f]*: fb be 0d f4 rsubvc lr,-12
13075 + *[0-9a-f]*: fb b4 06 f3 rsubmi r4,-13
13078 + *[0-9a-f]*: ff df e0 0f addeq pc,pc,pc
13079 + *[0-9a-f]*: f9 dc ef 0c addal r12,r12,r12
13080 + *[0-9a-f]*: eb d5 e8 05 addls r5,r5,r5
13081 + *[0-9a-f]*: e9 d4 e7 04 addpl r4,r4,r4
13082 + *[0-9a-f]*: fd de e1 0e addne lr,lr,lr
13083 + *[0-9a-f]*: e5 d1 e8 0a addls r10,r2,r1
13084 + *[0-9a-f]*: f1 db ed 0c addvc r12,r8,r11
13085 + *[0-9a-f]*: ef d0 e6 0a addmi r10,r7,r0
13087 +[0-9a-f]* <subc2>:
13088 + *[0-9a-f]*: ff df e0 1f subeq pc,pc,pc
13089 + *[0-9a-f]*: f9 dc ef 1c subal r12,r12,r12
13090 + *[0-9a-f]*: eb d5 e8 15 subls r5,r5,r5
13091 + *[0-9a-f]*: e9 d4 e7 14 subpl r4,r4,r4
13092 + *[0-9a-f]*: fd de e1 1e subne lr,lr,lr
13093 + *[0-9a-f]*: e5 d1 e8 1a subls r10,r2,r1
13094 + *[0-9a-f]*: f1 db ed 1c subvc r12,r8,r11
13095 + *[0-9a-f]*: ef d0 e6 1a submi r10,r7,r0
13098 + *[0-9a-f]*: ff df e0 2f andeq pc,pc,pc
13099 + *[0-9a-f]*: f9 dc ef 2c andal r12,r12,r12
13100 + *[0-9a-f]*: eb d5 e8 25 andls r5,r5,r5
13101 + *[0-9a-f]*: e9 d4 e7 24 andpl r4,r4,r4
13102 + *[0-9a-f]*: fd de e1 2e andne lr,lr,lr
13103 + *[0-9a-f]*: e5 d1 e8 2a andls r10,r2,r1
13104 + *[0-9a-f]*: f1 db ed 2c andvc r12,r8,r11
13105 + *[0-9a-f]*: ef d0 e6 2a andmi r10,r7,r0
13108 + *[0-9a-f]*: ff df e0 3f oreq pc,pc,pc
13109 + *[0-9a-f]*: f9 dc ef 3c oral r12,r12,r12
13110 + *[0-9a-f]*: eb d5 e8 35 orls r5,r5,r5
13111 + *[0-9a-f]*: e9 d4 e7 34 orpl r4,r4,r4
13112 + *[0-9a-f]*: fd de e1 3e orne lr,lr,lr
13113 + *[0-9a-f]*: e5 d1 e8 3a orls r10,r2,r1
13114 + *[0-9a-f]*: f1 db ed 3c orvc r12,r8,r11
13115 + *[0-9a-f]*: ef d0 e6 3a ormi r10,r7,r0
13118 + *[0-9a-f]*: ff df e0 4f eoreq pc,pc,pc
13119 + *[0-9a-f]*: f9 dc ef 4c eoral r12,r12,r12
13120 + *[0-9a-f]*: eb d5 e8 45 eorls r5,r5,r5
13121 + *[0-9a-f]*: e9 d4 e7 44 eorpl r4,r4,r4
13122 + *[0-9a-f]*: fd de e1 4e eorne lr,lr,lr
13123 + *[0-9a-f]*: e5 d1 e8 4a eorls r10,r2,r1
13124 + *[0-9a-f]*: f1 db ed 4c eorvc r12,r8,r11
13125 + *[0-9a-f]*: ef d0 e6 4a eormi r10,r7,r0
13127 +[0-9a-f]* <ldcond>:
13128 + *[0-9a-f]*: ff ff 01 ff ld.weq pc,pc[0x7fc]
13129 + *[0-9a-f]*: f9 fc f3 ff ld.shal r12,r12[0x3fe]
13130 + *[0-9a-f]*: eb f5 84 00 ld.shls r5,r5[0x0]
13131 + *[0-9a-f]*: e9 f4 79 ff ld.ubpl r4,r4[0x1ff]
13132 + *[0-9a-f]*: fd fe 16 00 ld.sbne lr,lr[0x0]
13133 + *[0-9a-f]*: e5 fa 80 00 ld.wls r10,r2[0x0]
13134 + *[0-9a-f]*: f1 fc d3 ff ld.shvc r12,r8[0x3fe]
13135 + *[0-9a-f]*: ef fa 68 01 ld.ubmi r10,r7[0x1]
13137 +[0-9a-f]* <stcond2>:
13138 + *[0-9a-f]*: ff ff 0b ff st.weq pc[0x7fc],pc
13139 + *[0-9a-f]*: f9 fc fd ff st.hal r12[0x3fe],r12
13140 + *[0-9a-f]*: eb f5 8c 00 st.hls r5[0x0],r5
13141 + *[0-9a-f]*: e9 f4 7f ff st.bpl r4[0x1ff],r4
13142 + *[0-9a-f]*: fd fe 1e 00 st.bne lr[0x0],lr
13143 + *[0-9a-f]*: e5 fa 8a 00 st.wls r2[0x0],r10
13144 + *[0-9a-f]*: f1 fc dd ff st.hvc r8[0x3fe],r12
13145 + *[0-9a-f]*: ef fa 6e 01 st.bmi r7[0x1],r10
13148 + *[0-9a-f]*: fc 1f ff ff movh pc,0xffff
13149 + *[0-9a-f]*: fc 10 00 00 movh r0,0x0
13150 + *[0-9a-f]*: fc 15 00 01 movh r5,0x1
13151 + *[0-9a-f]*: fc 1c 7f ff movh r12,0x7fff
13154 +++ b/gas/testsuite/gas/avr32/allinsn.exp
13156 +# AVR32 assembler testsuite. -*- Tcl -*-
13158 +if [istarget avr32-*-*] {
13159 + run_dump_test "allinsn"
13162 +++ b/gas/testsuite/gas/avr32/allinsn.s
13171 + ld.d lr,pc[pc<<3]
13172 + ld.d r0,r0[r0<<0]
13173 + ld.d r6,r5[r5<<2]
13174 + ld.d r4,r4[r4<<1]
13175 + ld.d lr,lr[lr<<1]
13176 + ld.d r10,r3[sp<<2]
13177 + ld.d r8,r10[r6<<2]
13178 + ld.d r2,r7[r9<<0]
13182 + ld.w pc,pc[pc<<0]
13183 + ld.w r12,r12[r12<<3]
13184 + ld.w r5,r5[r5<<2]
13185 + ld.w r4,r4[r4<<1]
13186 + ld.w lr,lr[lr<<1]
13187 + ld.w r2,r9[r9<<0]
13188 + ld.w r11,r2[r6<<0]
13189 + ld.w r0,r2[sp<<3]
13193 + ld.sh pc,pc[pc<<0]
13194 + ld.sh r12,r12[r12<<3]
13195 + ld.sh r5,r5[r5<<2]
13196 + ld.sh r4,r4[r4<<1]
13197 + ld.sh lr,lr[lr<<1]
13198 + ld.sh r11,r0[pc<<2]
13199 + ld.sh r10,sp[r6<<2]
13200 + ld.sh r12,r2[r2<<0]
13204 + ld.uh pc,pc[pc<<0]
13205 + ld.uh r12,r12[r12<<3]
13206 + ld.uh r5,r5[r5<<2]
13207 + ld.uh r4,r4[r4<<1]
13208 + ld.uh lr,lr[lr<<1]
13209 + ld.uh r8,pc[lr<<3]
13210 + ld.uh r6,r1[pc<<1]
13211 + ld.uh r6,lr[sp<<1]
13215 + ld.sb pc,pc[pc<<0]
13216 + ld.sb r12,r12[r12<<3]
13217 + ld.sb r5,r5[r5<<2]
13218 + ld.sb r4,r4[r4<<1]
13219 + ld.sb lr,lr[lr<<1]
13220 + ld.sb r9,r1[pc<<3]
13221 + ld.sb r0,r3[r11<<1]
13222 + ld.sb r10,r5[r5<<1]
13226 + ld.ub pc,pc[pc<<0]
13227 + ld.ub r12,r12[r12<<3]
13228 + ld.ub r5,r5[r5<<2]
13229 + ld.ub r4,r4[r4<<1]
13230 + ld.ub lr,lr[lr<<1]
13231 + ld.ub r6,r12[r7<<3]
13232 + ld.ub r2,r6[r12<<0]
13233 + ld.ub r0,r7[r11<<1]
13237 + st.d pc[pc<<0],r14
13238 + st.d r12[r12<<3],r12
13239 + st.d r5[r5<<2],r6
13240 + st.d r4[r4<<1],r4
13241 + st.d lr[lr<<1],lr
13242 + st.d r1[r9<<1],r4
13243 + st.d r10[r2<<1],r4
13244 + st.d r12[r6<<0],lr
13248 + st.w pc[pc<<0],pc
13249 + st.w r12[r12<<3],r12
13250 + st.w r5[r5<<2],r5
13251 + st.w r4[r4<<1],r4
13252 + st.w lr[lr<<1],lr
13253 + st.w r1[r10<<0],r3
13254 + st.w r0[r10<<1],r9
13255 + st.w r4[r5<<3],pc
13259 + st.h pc[pc<<0],pc
13260 + st.h r12[r12<<3],r12
13261 + st.h r5[r5<<2],r5
13262 + st.h r4[r4<<1],r4
13263 + st.h lr[lr<<1],lr
13264 + st.h r2[r9<<0],r11
13265 + st.h r5[r1<<2],r12
13266 + st.h pc[r8<<2],r3
13270 + st.b pc[pc<<0],pc
13271 + st.b r12[r12<<3],r12
13272 + st.b r5[r5<<2],r5
13273 + st.b r4[r4<<1],r4
13274 + st.b lr[lr<<1],lr
13275 + st.b r1[r8<<1],r6
13276 + st.b lr[lr<<3],r1
13277 + st.b r5[r0<<2],pc
13601 + lddsp r12,sp[508]
13623 + stdsp sp[508],r12
13785 + .global One_s_compliment
13887 + ld.w r12,r12[124]
13898 + ld.sh r12,r12[14]
13909 + ld.uh r12,r12[14]
13961 + .global ldd_postinc
13972 + .global ldd_predec
13994 + .global std_postinc
14005 + .global std_predec
14139 + /* popm with no argument fails currently */
14141 + popm r0-r11,pc,r12=-1
14143 + popm r0-r11,pc,r12=1
14146 + popm r0-r3,r11,pc,r12=0
14147 + popm r0-r7,r10-r12,lr
14152 + pushm r0-r12,lr,pc
14156 + pushm r8-r10,lr,pc
14163 + popm r0-r11,pc,r12=-1
14165 + popm r0-r11,pc,r12=1
14168 + popm r0-r3,r11,pc,r12=0
14169 + popm r0-r7,r10-r12,lr
14174 + pushm r0-r12,lr,pc
14178 + pushm r8-r10,lr,pc
14243 + .global breakpoint
14273 + add r12,r12,r12<<3
14279 + add r12,r12,r7<<2
14284 + sub r12,r12,r12<<3
14305 + addhh.w pc,pc:b,pc:b
14306 + addhh.w r12,r12:t,r12:t
14307 + addhh.w r5,r5:t,r5:t
14308 + addhh.w r4,r4:b,r4:b
14309 + addhh.w lr,lr:t,lr:t
14310 + addhh.w r0,r0:b,r3:b
14311 + addhh.w lr,r12:t,r7:b
14312 + addhh.w r3,r10:t,r2:b
14316 + subhh.w pc,pc:b,pc:b
14317 + subhh.w r12,r12:t,r12:t
14318 + subhh.w r5,r5:t,r5:t
14319 + subhh.w r4,r4:b,r4:b
14320 + subhh.w lr,lr:t,lr:t
14321 + subhh.w r10,r1:t,r7:b
14322 + subhh.w pc,r10:t,lr:t
14323 + subhh.w r3,r0:t,r12:b
14372 + muls.d r12,r12,r12
14383 + macs.d r14,r12,r12
14394 + mulu.d r14,r12,r12
14405 + macu.d r14,r12,r12
14482 + addabs r12,r12,r12
14492 + mulnhh.w pc,pc:b,pc:b
14493 + mulnhh.w r12,r12:t,r12:t
14494 + mulnhh.w r5,r5:t,r5:t
14495 + mulnhh.w r4,r4:b,r4:b
14496 + mulnhh.w lr,lr:t,lr:t
14497 + mulnhh.w r11,sp:t,r9:b
14498 + mulnhh.w sp,r4:b,lr:t
14499 + mulnhh.w r12,r2:t,r11:b
14503 + mulnwh.d r0,pc,pc:b
14504 + mulnwh.d r14,r12,r12:t
14505 + mulnwh.d r8,r5,r5:t
14506 + mulnwh.d r6,r4,r4:b
14507 + mulnwh.d r2,lr,lr:t
14508 + mulnwh.d r14,r3,r2:t
14509 + mulnwh.d r4,r5,r9:b
14510 + mulnwh.d r12,r4,r4:t
14514 + machh.w pc,pc:b,pc:b
14515 + machh.w r12,r12:t,r12:t
14516 + machh.w r5,r5:t,r5:t
14517 + machh.w r4,r4:b,r4:b
14518 + machh.w lr,lr:t,lr:t
14519 + machh.w lr,r5:b,r1:t
14520 + machh.w r9,r6:b,r7:b
14521 + machh.w r5,lr:t,r12:b
14525 + machh.d r0,pc:b,pc:b
14526 + machh.d r14,r12:t,r12:t
14527 + machh.d r8,r5:t,r5:t
14528 + machh.d r6,r4:b,r4:b
14529 + machh.d r2,lr:t,lr:t
14530 + machh.d r10,r0:b,r8:b
14531 + machh.d r14,r4:b,r5:t
14532 + machh.d r8,r0:b,r4:t
14534 + .global macsathh_w
14536 + macsathh.w pc,pc:b,pc:b
14537 + macsathh.w r12,r12:t,r12:t
14538 + macsathh.w r5,r5:t,r5:t
14539 + macsathh.w r4,r4:b,r4:b
14540 + macsathh.w lr,lr:t,lr:t
14541 + macsathh.w r7,r7:t,pc:t
14542 + macsathh.w r4,r2:t,r4:b
14543 + macsathh.w r4,r8:t,r3:t
14547 + mulhh.w pc,pc:b,pc:b
14548 + mulhh.w r12,r12:t,r12:t
14549 + mulhh.w r5,r5:t,r5:t
14550 + mulhh.w r4,r4:b,r4:b
14551 + mulhh.w lr,lr:t,lr:t
14552 + mulhh.w r7,r4:t,r9:b
14553 + mulhh.w pc,r3:t,r7:t
14554 + mulhh.w pc,r4:b,r9:t
14556 + .global mulsathh_h
14558 + mulsathh.h pc,pc:b,pc:b
14559 + mulsathh.h r12,r12:t,r12:t
14560 + mulsathh.h r5,r5:t,r5:t
14561 + mulsathh.h r4,r4:b,r4:b
14562 + mulsathh.h lr,lr:t,lr:t
14563 + mulsathh.h r3,r1:b,sp:b
14564 + mulsathh.h r11,lr:t,r11:b
14565 + mulsathh.h r8,r8:b,r11:t
14567 + .global mulsathh_w
14569 + mulsathh.w pc,pc:b,pc:b
14570 + mulsathh.w r12,r12:t,r12:t
14571 + mulsathh.w r5,r5:t,r5:t
14572 + mulsathh.w r4,r4:b,r4:b
14573 + mulsathh.w lr,lr:t,lr:t
14574 + mulsathh.w lr,r11:t,r6:b
14575 + mulsathh.w r6,r6:b,r7:t
14576 + mulsathh.w r10,r2:b,r3:b
14578 + .global mulsatrndhh_h
14580 + mulsatrndhh.h pc,pc:b,pc:b
14581 + mulsatrndhh.h r12,r12:t,r12:t
14582 + mulsatrndhh.h r5,r5:t,r5:t
14583 + mulsatrndhh.h r4,r4:b,r4:b
14584 + mulsatrndhh.h lr,lr:t,lr:t
14585 + mulsatrndhh.h r11,r6:b,r9:b
14586 + mulsatrndhh.h r11,r3:b,r8:t
14587 + mulsatrndhh.h r5,sp:t,r7:t
14589 + .global mulsatrndwh_w
14591 + mulsatrndwh.w pc,pc,pc:b
14592 + mulsatrndwh.w r12,r12,r12:t
14593 + mulsatrndwh.w r5,r5,r5:t
14594 + mulsatrndwh.w r4,r4,r4:b
14595 + mulsatrndwh.w lr,lr,lr:t
14596 + mulsatrndwh.w r5,r12,r0:b
14597 + mulsatrndwh.w r7,r10,pc:b
14598 + mulsatrndwh.w r10,r8,r5:t
14602 + macwh.d r0,pc,pc:b
14603 + macwh.d r14,r12,r12:t
14604 + macwh.d r8,r5,r5:t
14605 + macwh.d r6,r4,r4:b
14606 + macwh.d r2,lr,lr:t
14607 + macwh.d r4,r10,r12:t
14608 + macwh.d r4,r7,sp:b
14609 + macwh.d r14,r9,r11:b
14613 + mulwh.d r0,pc,pc:b
14614 + mulwh.d r14,r12,r12:t
14615 + mulwh.d r8,r5,r5:t
14616 + mulwh.d r6,r4,r4:b
14617 + mulwh.d r2,lr,lr:t
14618 + mulwh.d r12,r5,r1:b
14619 + mulwh.d r0,r1,r3:t
14620 + mulwh.d r0,r9,r2:b
14622 + .global mulsatwh_w
14624 + mulsatwh.w pc,pc,pc:b
14625 + mulsatwh.w r12,r12,r12:t
14626 + mulsatwh.w r5,r5,r5:t
14627 + mulsatwh.w r4,r4,r4:b
14628 + mulsatwh.w lr,lr,lr:t
14629 + mulsatwh.w r11,pc,r10:t
14630 + mulsatwh.w sp,r12,r9:t
14631 + mulsatwh.w r0,r3,r2:t
14635 + ld.w pc,pc[pc:b<<2]
14636 + ld.w r12,r12[r12:t<<2]
14637 + ld.w r5,r5[r5:u<<2]
14638 + ld.w r4,r4[r4:l<<2]
14639 + ld.w lr,lr[lr:l<<2]
14640 + ld.w r9,r10[r6:l<<2]
14641 + ld.w r2,r10[r10:b<<2]
14642 + ld.w r11,r5[pc:b<<2]
14646 + satadd.w pc,pc,pc
14647 + satadd.w r12,r12,r12
14648 + satadd.w r5,r5,r5
14649 + satadd.w r4,r4,r4
14650 + satadd.w lr,lr,lr
14651 + satadd.w r4,r8,r11
14652 + satadd.w r3,r12,r6
14653 + satadd.w r3,lr,r9
14655 + .global satsub_w1
14657 + satsub.w pc,pc,pc
14658 + satsub.w r12,r12,r12
14659 + satsub.w r5,r5,r5
14660 + satsub.w r4,r4,r4
14661 + satsub.w lr,lr,lr
14662 + satsub.w r8,sp,r0
14663 + satsub.w r9,r8,r4
14664 + satsub.w pc,lr,r2
14668 + satadd.h pc,pc,pc
14669 + satadd.h r12,r12,r12
14670 + satadd.h r5,r5,r5
14671 + satadd.h r4,r4,r4
14672 + satadd.h lr,lr,lr
14673 + satadd.h r7,r3,r9
14674 + satadd.h r1,r0,r2
14675 + satadd.h r1,r4,lr
14679 + satsub.h pc,pc,pc
14680 + satsub.h r12,r12,r12
14681 + satsub.h r5,r5,r5
14682 + satsub.h r4,r4,r4
14683 + satsub.h lr,lr,lr
14684 + satsub.h lr,lr,r3
14685 + satsub.h r11,r6,r5
14686 + satsub.h r3,sp,r0
14765 + .global extract_b
14767 + extract.b pc,pc:b
14768 + extract.b r12,r12:t
14769 + extract.b r5,r5:u
14770 + extract.b r4,r4:l
14771 + extract.b lr,lr:l
14772 + extract.b r2,r5:l
14773 + extract.b r12,r3:l
14774 + extract.b sp,r3:l
14779 + insert.b r12:t,r12
14783 + insert.b r12:u,r3
14784 + insert.b r10:l,lr
14785 + insert.b r11:l,r12
14787 + .global extract_h
14789 + extract.h pc,pc:b
14790 + extract.h r12,r12:t
14791 + extract.h r5,r5:t
14792 + extract.h r4,r4:b
14793 + extract.h lr,lr:t
14794 + extract.h r11,lr:b
14795 + extract.h r10,r0:b
14796 + extract.h r11,r12:b
14801 + insert.h r12:t,r12
14805 + insert.h r12:t,r11
14807 + insert.h r1:t,r11 */
14823 + padd.h r12,r12,r12
14834 + psub.h r12,r12,r12
14845 + paddx.h r12,r12,r12
14850 + paddx.h r10,r4,r5
14856 + psubx.h r12,r12,r12
14860 + psubx.h r5,r12,r5
14866 + padds.sh pc,pc,pc
14867 + padds.sh r12,r12,r12
14868 + padds.sh r5,r5,r5
14869 + padds.sh r4,r4,r4
14870 + padds.sh lr,lr,lr
14871 + padds.sh r9,lr,r2
14872 + padds.sh r6,r8,r1
14873 + padds.sh r6,r4,r10
14877 + psubs.sh pc,pc,pc
14878 + psubs.sh r12,r12,r12
14879 + psubs.sh r5,r5,r5
14880 + psubs.sh r4,r4,r4
14881 + psubs.sh lr,lr,lr
14882 + psubs.sh r6,lr,r11
14883 + psubs.sh r2,r12,r4
14884 + psubs.sh r0,r9,r0
14886 + .global paddxs_sh
14888 + paddxs.sh pc,pc,pc
14889 + paddxs.sh r12,r12,r12
14890 + paddxs.sh r5,r5,r5
14891 + paddxs.sh r4,r4,r4
14892 + paddxs.sh lr,lr,lr
14893 + paddxs.sh r0,r3,r9
14894 + paddxs.sh pc,r10,r11
14895 + paddxs.sh pc,r10,pc
14897 + .global psubxs_sh
14899 + psubxs.sh pc,pc,pc
14900 + psubxs.sh r12,r12,r12
14901 + psubxs.sh r5,r5,r5
14902 + psubxs.sh r4,r4,r4
14903 + psubxs.sh lr,lr,lr
14904 + psubxs.sh r7,r4,r4
14905 + psubxs.sh r7,r8,r3
14906 + psubxs.sh pc,r6,r5
14910 + padds.uh pc,pc,pc
14911 + padds.uh r12,r12,r12
14912 + padds.uh r5,r5,r5
14913 + padds.uh r4,r4,r4
14914 + padds.uh lr,lr,lr
14915 + padds.uh r12,r11,r7
14916 + padds.uh r7,r8,lr
14917 + padds.uh r6,r9,r7
14921 + psubs.uh pc,pc,pc
14922 + psubs.uh r12,r12,r12
14923 + psubs.uh r5,r5,r5
14924 + psubs.uh r4,r4,r4
14925 + psubs.uh lr,lr,lr
14926 + psubs.uh lr,r10,r6
14927 + psubs.uh sp,r2,pc
14928 + psubs.uh r2,r9,r2
14930 + .global paddxs_uh
14932 + paddxs.uh pc,pc,pc
14933 + paddxs.uh r12,r12,r12
14934 + paddxs.uh r5,r5,r5
14935 + paddxs.uh r4,r4,r4
14936 + paddxs.uh lr,lr,lr
14937 + paddxs.uh r7,r9,r5
14938 + paddxs.uh r9,r1,r4
14939 + paddxs.uh r5,r2,r3
14941 + .global psubxs_uh
14943 + psubxs.uh pc,pc,pc
14944 + psubxs.uh r12,r12,r12
14945 + psubxs.uh r5,r5,r5
14946 + psubxs.uh r4,r4,r4
14947 + psubxs.uh lr,lr,lr
14948 + psubxs.uh sp,r5,sp
14949 + psubxs.uh sp,r6,r6
14950 + psubxs.uh r3,r11,r8
14954 + paddh.sh pc,pc,pc
14955 + paddh.sh r12,r12,r12
14956 + paddh.sh r5,r5,r5
14957 + paddh.sh r4,r4,r4
14958 + paddh.sh lr,lr,lr
14959 + paddh.sh r12,sp,r3
14960 + paddh.sh pc,r5,r3
14961 + paddh.sh r8,r8,sp
14965 + psubh.sh pc,pc,pc
14966 + psubh.sh r12,r12,r12
14967 + psubh.sh r5,r5,r5
14968 + psubh.sh r4,r4,r4
14969 + psubh.sh lr,lr,lr
14970 + psubh.sh r1,r5,r8
14971 + psubh.sh r7,r3,r6
14972 + psubh.sh r4,r3,r3
14974 + .global paddxh_sh
14976 + paddxh.sh pc,pc,pc
14977 + paddxh.sh r12,r12,r12
14978 + paddxh.sh r5,r5,r5
14979 + paddxh.sh r4,r4,r4
14980 + paddxh.sh lr,lr,lr
14981 + paddxh.sh r6,r0,r4
14982 + paddxh.sh r9,r8,r9
14983 + paddxh.sh r3,r0,sp
14985 + .global psubxh_sh
14987 + psubxh.sh pc,pc,pc
14988 + psubxh.sh r12,r12,r12
14989 + psubxh.sh r5,r5,r5
14990 + psubxh.sh r4,r4,r4
14991 + psubxh.sh lr,lr,lr
14992 + psubxh.sh r4,pc,r12
14993 + psubxh.sh r8,r4,r6
14994 + psubxh.sh r12,r9,r4
14996 + .global paddsub_h
14998 + paddsub.h pc,pc:b,pc:b
14999 + paddsub.h r12,r12:t,r12:t
15000 + paddsub.h r5,r5:t,r5:t
15001 + paddsub.h r4,r4:b,r4:b
15002 + paddsub.h lr,lr:t,lr:t
15003 + paddsub.h r5,r2:t,lr:b
15004 + paddsub.h r7,r1:b,r8:b
15005 + paddsub.h r6,r10:t,r5:t
15007 + .global psubadd_h
15009 + psubadd.h pc,pc:b,pc:b
15010 + psubadd.h r12,r12:t,r12:t
15011 + psubadd.h r5,r5:t,r5:t
15012 + psubadd.h r4,r4:b,r4:b
15013 + psubadd.h lr,lr:t,lr:t
15014 + psubadd.h r9,r11:t,r8:t
15015 + psubadd.h r10,r7:t,lr:t
15016 + psubadd.h r6,pc:t,pc:b
15018 + .global paddsubs_sh
15020 + paddsubs.sh pc,pc:b,pc:b
15021 + paddsubs.sh r12,r12:t,r12:t
15022 + paddsubs.sh r5,r5:t,r5:t
15023 + paddsubs.sh r4,r4:b,r4:b
15024 + paddsubs.sh lr,lr:t,lr:t
15025 + paddsubs.sh r0,lr:t,r0:b
15026 + paddsubs.sh r9,r2:t,r4:t
15027 + paddsubs.sh r12,r9:t,sp:t
15029 + .global psubadds_sh
15031 + psubadds.sh pc,pc:b,pc:b
15032 + psubadds.sh r12,r12:t,r12:t
15033 + psubadds.sh r5,r5:t,r5:t
15034 + psubadds.sh r4,r4:b,r4:b
15035 + psubadds.sh lr,lr:t,lr:t
15036 + psubadds.sh pc,lr:b,r1:t
15037 + psubadds.sh r11,r3:b,r12:b
15038 + psubadds.sh r10,r2:t,r8:t
15040 + .global paddsubs_uh
15042 + paddsubs.uh pc,pc:b,pc:b
15043 + paddsubs.uh r12,r12:t,r12:t
15044 + paddsubs.uh r5,r5:t,r5:t
15045 + paddsubs.uh r4,r4:b,r4:b
15046 + paddsubs.uh lr,lr:t,lr:t
15047 + paddsubs.uh r9,r2:b,r3:b
15048 + paddsubs.uh sp,sp:b,r7:t
15049 + paddsubs.uh lr,r0:b,r10:t
15051 + .global psubadds_uh
15053 + psubadds.uh pc,pc:b,pc:b
15054 + psubadds.uh r12,r12:t,r12:t
15055 + psubadds.uh r5,r5:t,r5:t
15056 + psubadds.uh r4,r4:b,r4:b
15057 + psubadds.uh lr,lr:t,lr:t
15058 + psubadds.uh r12,r9:t,pc:t
15059 + psubadds.uh r8,r6:b,r8:b
15060 + psubadds.uh r8,r8:b,r4:b
15062 + .global paddsubh_sh
15064 + paddsubh.sh pc,pc:b,pc:b
15065 + paddsubh.sh r12,r12:t,r12:t
15066 + paddsubh.sh r5,r5:t,r5:t
15067 + paddsubh.sh r4,r4:b,r4:b
15068 + paddsubh.sh lr,lr:t,lr:t
15069 + paddsubh.sh r8,r9:t,r9:b
15070 + paddsubh.sh r0,sp:t,r1:t
15071 + paddsubh.sh r3,r1:b,r0:t
15073 + .global psubaddh_sh
15075 + psubaddh.sh pc,pc:b,pc:b
15076 + psubaddh.sh r12,r12:t,r12:t
15077 + psubaddh.sh r5,r5:t,r5:t
15078 + psubaddh.sh r4,r4:b,r4:b
15079 + psubaddh.sh lr,lr:t,lr:t
15080 + psubaddh.sh r7,r3:t,r10:b
15081 + psubaddh.sh r7,r2:t,r1:t
15082 + psubaddh.sh r11,r3:b,r6:b
15087 + padd.b r12,r12,r12
15098 + psub.b r12,r12,r12
15108 + padds.sb pc,pc,pc
15109 + padds.sb r12,r12,r12
15110 + padds.sb r5,r5,r5
15111 + padds.sb r4,r4,r4
15112 + padds.sb lr,lr,lr
15113 + padds.sb sp,r11,r4
15114 + padds.sb r11,r10,r11
15115 + padds.sb r5,r12,r6
15119 + psubs.sb pc,pc,pc
15120 + psubs.sb r12,r12,r12
15121 + psubs.sb r5,r5,r5
15122 + psubs.sb r4,r4,r4
15123 + psubs.sb lr,lr,lr
15124 + psubs.sb r7,r6,r8
15125 + psubs.sb r12,r10,r9
15126 + psubs.sb pc,r11,r0
15130 + padds.ub pc,pc,pc
15131 + padds.ub r12,r12,r12
15132 + padds.ub r5,r5,r5
15133 + padds.ub r4,r4,r4
15134 + padds.ub lr,lr,lr
15135 + padds.ub r3,r2,r11
15136 + padds.ub r10,r8,r1
15137 + padds.ub r11,r8,r10
15141 + psubs.ub pc,pc,pc
15142 + psubs.ub r12,r12,r12
15143 + psubs.ub r5,r5,r5
15144 + psubs.ub r4,r4,r4
15145 + psubs.ub lr,lr,lr
15146 + psubs.ub r0,r2,r7
15147 + psubs.ub lr,r5,r3
15148 + psubs.ub r6,r7,r9
15152 + paddh.ub pc,pc,pc
15153 + paddh.ub r12,r12,r12
15154 + paddh.ub r5,r5,r5
15155 + paddh.ub r4,r4,r4
15156 + paddh.ub lr,lr,lr
15157 + paddh.ub lr,r1,r0
15158 + paddh.ub r2,r7,r7
15159 + paddh.ub r2,r1,r2
15163 + psubh.ub pc,pc,pc
15164 + psubh.ub r12,r12,r12
15165 + psubh.ub r5,r5,r5
15166 + psubh.ub r4,r4,r4
15167 + psubh.ub lr,lr,lr
15168 + psubh.ub r0,r1,r6
15169 + psubh.ub r4,lr,r10
15170 + psubh.ub r9,r8,r1
15175 + pmax.ub r12,r12,r12
15179 + pmax.ub pc,r2,r11
15180 + pmax.ub r12,r1,r1
15186 + pmax.sh r12,r12,r12
15190 + pmax.sh lr,r6,r12
15197 + pmin.ub r12,r12,r12
15208 + pmin.sh r12,r12,r12
15212 + pmin.sh r8,r4,r10
15213 + pmin.sh lr,r10,r12
15219 + pavg.ub r12,r12,r12
15225 + pavg.ub pc,r12,r10
15230 + pavg.sh r12,r12,r12
15307 + pasr.h r12,r12,15
15318 + plsl.h r12,r12,15
15329 + plsr.h r12,r12,15
15339 + packw.sh pc,pc,pc
15340 + packw.sh r12,r12,r12
15341 + packw.sh r5,r5,r5
15342 + packw.sh r4,r4,r4
15343 + packw.sh lr,lr,lr
15344 + packw.sh sp,r11,r10
15345 + packw.sh r8,r2,r12
15346 + packw.sh r8,r1,r5
15348 + .global punpckub_h
15350 + punpckub.h pc,pc:b
15351 + punpckub.h r12,r12:t
15352 + punpckub.h r5,r5:t
15353 + punpckub.h r4,r4:b
15354 + punpckub.h lr,lr:t
15355 + punpckub.h r6,r1:t
15356 + punpckub.h lr,r5:b
15357 + punpckub.h lr,r2:t
15359 + .global punpcksb_h
15361 + punpcksb.h pc,pc:b
15362 + punpcksb.h r12,r12:t
15363 + punpcksb.h r5,r5:t
15364 + punpcksb.h r4,r4:b
15365 + punpcksb.h lr,lr:t
15366 + punpcksb.h r4,r7:t
15367 + punpcksb.h r6,lr:b
15368 + punpcksb.h r12,r12:t
15370 + .global packsh_ub
15372 + packsh.ub pc,pc,pc
15373 + packsh.ub r12,r12,r12
15374 + packsh.ub r5,r5,r5
15375 + packsh.ub r4,r4,r4
15376 + packsh.ub lr,lr,lr
15377 + packsh.ub r3,r6,r3
15378 + packsh.ub r8,r0,r3
15379 + packsh.ub r9,r3,lr
15381 + .global packsh_sb
15383 + packsh.sb pc,pc,pc
15384 + packsh.sb r12,r12,r12
15385 + packsh.sb r5,r5,r5
15386 + packsh.sb r4,r4,r4
15387 + packsh.sb lr,lr,lr
15388 + packsh.sb r6,r8,r1
15389 + packsh.sb lr,r9,r8
15390 + packsh.sb sp,r6,r6
15406 + andl r12,65535,COH
15407 + andl r5,32768,COH
15408 + andl r4,32767,COH
15410 + andl r6,22753,COH
15411 + andl r0,40653,COH
15412 + andl r4,48580,COH
15428 + andh r12,65535,COH
15429 + andh r5,32768,COH
15430 + andh r4,32767,COH
15432 + andh r11,34317,COH
15433 + andh r8,52982,COH
15434 + andh r10,23683,COH
15484 + mcall r5[-131072]
15506 + cache r5[-1024],16
15507 + cache r4[1023],15
15509 + cache r3[-964],17
15510 + cache r4[-375],22
15511 + cache r3[-888],17
15579 + .global satsub_w2
15582 + satsub.w r12,r12,-1
15583 + satsub.w r5,r5,-32768
15584 + satsub.w r4,r4,32767
15586 + satsub.w r2,lr,-2007
15587 + satsub.w r7,r12,-784
15588 + satsub.w r4,r7,23180
15594 + ld.d r8,r5[-32768]
15595 + ld.d r6,r4[32767]
15597 + ld.d r14,r11[14784]
15598 + ld.d r6,r9[-18905]
15599 + ld.d r2,r3[-6355]
15605 + ld.w r5,r5[-32768]
15606 + ld.w r4,r4[32767]
15608 + ld.w r0,r12[-22133]
15609 + ld.w sp,pc[-20521]
15610 + /* ld.w r3,r5[29035] */
15616 + ld.sh r12,r12[-1]
15617 + ld.sh r5,r5[-32768]
15618 + ld.sh r4,r4[32767]
15620 + ld.sh r6,r10[30930]
15621 + ld.sh r6,r10[21973]
15622 + /* ld.sh r11,r10[-2058] */
15628 + ld.uh r12,r12[-1]
15629 + ld.uh r5,r5[-32768]
15630 + ld.uh r4,r4[32767]
15632 + ld.uh r1,r9[-13354]
15633 + ld.uh lr,r11[21337]
15634 + /* ld.uh r2,lr[-25370] */
15640 + ld.sb r12,r12[-1]
15641 + ld.sb r5,r5[-32768]
15642 + ld.sb r4,r4[32767]
15644 + ld.sb r7,sp[-28663]
15645 + ld.sb r2,r1[-5879]
15646 + ld.sb r12,r3[18734]
15651 + ld.ub r12,r12[-1]
15652 + ld.ub r5,r5[-32768]
15653 + ld.ub r4,r4[32767]
15655 + ld.ub pc,r4[8277]
15656 + ld.ub r5,r12[19172]
15657 + ld.ub r10,lr[26347]
15663 + st.d r5[-32768],r8
15664 + st.d r4[32767],r6
15666 + st.d r5[13200],r10
15667 + st.d r5[9352],r10
15668 + st.d r5[32373],r4
15674 + st.w r5[-32768],r5
15675 + st.w r4[32767],r4
15678 + st.w r6[27087],r12
15679 + /* st.w r3[20143],r7 */
15686 + st.h r5[-32768],r5
15687 + st.h r4[32767],r4
15689 + st.h r4[-9962],r7
15690 + st.h r9[-16250],r3
15691 + /* st.h r8[-28810],r7 */
15698 + st.b r5[-32768],r5
15699 + st.b r4[32767],r4
15701 + st.b r12[30102],r6
15702 + st.b r5[28977],r1
15818 + satrnds r12>>31,31
15819 + satrnds r5>>16,16
15820 + satrnds r4>>15,15
15822 + satrnds r0>>21,19
15829 + satrndu r12>>31,31
15830 + satrndu r5>>16,16
15831 + satrndu r4>>15,15
15833 + satrndu r12>>0,26
15835 + satrndu r10>>3,16
15892 + ldm r11,r2-r3,r5-r8,r15
15893 + ldm r6,r0,r3,r9,r13,r15
15902 + ldm r12++,r3-r5,r8,r10,r12,r14-r15
15903 + ldm r10++,r2,r4-r6,r14-r15
15904 + ldm r6++,r1,r3-r4,r9-r14
15913 + ldmts r0,r1-r2,r11-r12
15914 + ldmts lr,r0-r2,r4,r7-r8,r13-r14
15915 + ldmts r12,r0-r1,r3-r5,r9,r14-r15
15920 + ldmts r12++,r0-r15
15922 + ldmts r4++,r0-r14
15924 + ldmts sp++,r0,r2-r5,r7,r9,r11
15925 + ldmts r5++,r1-r3,r7,r10-r11
15926 + ldmts r8++,r2-r4,r7-r8,r13,r15
15935 + stm sp,r2-r3,r5,r8,r11,r14
15936 + stm r4,r0-r4,r6,r10-r11,r14
15937 + stm r9,r1,r5,r9,r12-r15
15946 + stm --r11,r0,r4-r9,r11-r15
15947 + stm --r11,r0,r3,r9-r10,r12,r14
15948 + stm --r6,r2,r8-r9,r13-r14
15957 + stmts r1,r0-r1,r3-r4,r6,r9-r10,r14-r15
15958 + stmts r3,r0,r6-r8,r10-r12
15959 + stmts r11,r0,r4,r6-r7,r9-r10,r12,r14-r15
15964 + stmts --r12,r0-r15
15966 + stmts --r4,r0-r14
15968 + stmts --r2,r0,r3-r4,r9-r10,r12-r13
15969 + stmts --r3,r0-r1,r14-r15
15970 + stmts --r0,r0,r2-r6,r10,r14
15974 + ldins.h pc:b,pc[0]
15975 + ldins.h r12:t,r12[-2]
15976 + ldins.h r5:t,r5[-4096]
15977 + ldins.h r4:b,r4[4094]
15978 + ldins.h lr:t,lr[2]
15979 + ldins.h r0:t,lr[1930]
15980 + ldins.h r3:b,r7[-534]
15981 + ldins.h r2:b,r12[-2252]
15985 + ldins.b pc:b,pc[0]
15986 + ldins.b r12:t,r12[-1]
15987 + ldins.b r5:u,r5[-2048]
15988 + ldins.b r4:l,r4[2047]
15989 + ldins.b lr:l,lr[1]
15990 + ldins.b r6:t,r4[-662]
15991 + ldins.b r5:b,r1[-151]
15992 + ldins.b r10:t,r11[-1923]
15996 + ldswp.sh pc,pc[0]
15997 + ldswp.sh r12,r12[-2]
15998 + ldswp.sh r5,r5[-4096]
15999 + ldswp.sh r4,r4[4094]
16000 + ldswp.sh lr,lr[2]
16001 + ldswp.sh r9,r10[3848]
16002 + ldswp.sh r4,r12[-2040]
16003 + ldswp.sh r10,r2[3088]
16007 + ldswp.uh pc,pc[0]
16008 + ldswp.uh r12,r12[-2]
16009 + ldswp.uh r5,r5[-4096]
16010 + ldswp.uh r4,r4[4094]
16011 + ldswp.uh lr,lr[2]
16012 + ldswp.uh r4,r9[3724]
16013 + ldswp.uh lr,sp[-1672]
16014 + ldswp.uh r8,r12[-3846]
16019 + ldswp.w r12,r12[-4]
16020 + ldswp.w r5,r5[-8192]
16021 + ldswp.w r4,r4[8188]
16023 + ldswp.w sp,r7[1860]
16024 + ldswp.w pc,r5[-3324]
16025 + ldswp.w r12,r10[-3296]
16030 + stswp.h r12[-2],r12
16031 + stswp.h r5[-4096],r5
16032 + stswp.h r4[4094],r4
16034 + stswp.h r7[64],r10
16035 + stswp.h r10[3024],r2
16036 + stswp.h r0[-2328],r10
16041 + stswp.w r12[-4],r12
16042 + stswp.w r5[-8192],r5
16043 + stswp.w r4[8188],r4
16045 + stswp.w pc[1156],r8
16046 + stswp.w sp[7992],r10
16047 + stswp.w r8[-1172],r5
16052 + and r12,r12,r12<<31
16057 + and r12,r8,r11<<27
16063 + and r12,r12,r12>>31
16067 + and r12,r8,r7>>17
16069 + and r10,r9,r10>>12
16074 + or r12,r12,r12<<31
16085 + or r12,r12,r12>>31
16096 + eor r12,r12,r12<<31
16100 + eor r10,r9,r4<<11
16102 + eor r6,r2,r12<<13
16107 + eor r12,r12,r12>>31
16117 + sthh.w pc[pc<<0],pc:b,pc:b
16118 + sthh.w r12[r12<<3],r12:t,r12:t
16119 + sthh.w r5[r5<<2],r5:t,r5:t
16120 + sthh.w r4[r4<<1],r4:b,r4:b
16121 + sthh.w lr[lr<<1],lr:t,lr:t
16122 + sthh.w sp[r6<<3],r1:t,r12:t
16123 + sthh.w r6[r6<<0],r9:t,r9:t
16124 + sthh.w r10[r3<<0],r0:b,r11:t
16128 + sthh.w pc[0],pc:b,pc:b
16129 + sthh.w r12[1020],r12:t,r12:t
16130 + sthh.w r5[512],r5:t,r5:t
16131 + sthh.w r4[508],r4:b,r4:b
16132 + sthh.w lr[4],lr:t,lr:t
16133 + sthh.w r4[404],r9:t,r0:b
16134 + sthh.w r8[348],r2:t,r10:b
16135 + sthh.w sp[172],r9:b,r2:b
16139 + cop cp0,cr0,cr0,cr0,0
16140 + cop cp7,cr15,cr15,cr15,0x7f
16141 + cop cp3,cr5,cr5,cr5,0x31
16142 + cop cp2,cr4,cr4,cr4,0x30
16143 + cop cp5,cr8,cr3,cr7,0x5a
16147 + ldc.w cp0,cr0,r0[0]
16148 + ldc.w cp7,cr15,pc[255<<2]
16149 + ldc.w cp3,cr5,r5[128<<2]
16150 + ldc.w cp2,cr4,r4[127<<2]
16151 + ldc.w cp4,cr9,r13[36<<2]
16155 + ldc.w cp0,cr0,--r0
16156 + ldc.w cp7,cr15,--pc
16157 + ldc.w cp3,cr5,--r5
16158 + ldc.w cp2,cr4,--r4
16159 + ldc.w cp4,cr9,--r13
16163 + ldc.w cp0,cr0,r0[r0]
16164 + ldc.w cp7,cr15,pc[pc<<3]
16165 + ldc.w cp3,cr5,r5[r4<<2]
16166 + ldc.w cp2,cr4,r4[r3<<1]
16167 + ldc.w cp4,cr9,r13[r12<<0]
16171 + ldc.d cp0,cr0,r0[0]
16172 + ldc.d cp7,cr14,pc[255<<2]
16173 + ldc.d cp3,cr6,r5[128<<2]
16174 + ldc.d cp2,cr4,r4[127<<2]
16175 + ldc.d cp4,cr8,r13[36<<2]
16179 + ldc.d cp0,cr0,--r0
16180 + ldc.d cp7,cr14,--pc
16181 + ldc.d cp3,cr6,--r5
16182 + ldc.d cp2,cr4,--r4
16183 + ldc.d cp4,cr8,--r13
16187 + ldc.d cp0,cr0,r0[r0]
16188 + ldc.d cp7,cr14,pc[pc<<3]
16189 + ldc.d cp3,cr6,r5[r4<<2]
16190 + ldc.d cp2,cr4,r4[r3<<1]
16191 + ldc.d cp4,cr8,r13[r12<<0]
16195 + stc.w cp0,r0[0],cr0
16196 + stc.w cp7,pc[255<<2],cr15
16197 + stc.w cp3,r5[128<<2],cr5
16198 + stc.w cp2,r4[127<<2],cr4
16199 + stc.w cp4,r13[36<<2],cr9
16203 + stc.w cp0,r0++,cr0
16204 + stc.w cp7,pc++,cr15
16205 + stc.w cp3,r5++,cr5
16206 + stc.w cp2,r4++,cr4
16207 + stc.w cp4,r13++,cr9
16211 + stc.w cp0,r0[r0],cr0
16212 + stc.w cp7,pc[pc<<3],cr15
16213 + stc.w cp3,r5[r4<<2],cr5
16214 + stc.w cp2,r4[r3<<1],cr4
16215 + stc.w cp4,r13[r12<<0],cr9
16219 + stc.d cp0,r0[0],cr0
16220 + stc.d cp7,pc[255<<2],cr14
16221 + stc.d cp3,r5[128<<2],cr6
16222 + stc.d cp2,r4[127<<2],cr4
16223 + stc.d cp4,r13[36<<2],cr8
16227 + stc.d cp0,r0++,cr0
16228 + stc.d cp7,pc++,cr14
16229 + stc.d cp3,r5++,cr6
16230 + stc.d cp2,r4++,cr4
16231 + stc.d cp4,r13++,cr8
16235 + stc.d cp0,r0[r0],cr0
16236 + stc.d cp7,pc[pc<<3],cr14
16237 + stc.d cp3,r5[r4<<2],cr6
16238 + stc.d cp2,r4[r3<<1],cr4
16239 + stc.d cp4,r13[r12<<0],cr8
16244 + ldc0.w cr15,pc[4095<<2]
16245 + ldc0.w cr5,r5[2048<<2]
16246 + ldc0.w cr4,r4[2047<<2]
16247 + ldc0.w cr9,r13[147<<2]
16252 + ldc0.d cr14,pc[4095<<2]
16253 + ldc0.d cr6,r5[2048<<2]
16254 + ldc0.d cr4,r4[2047<<2]
16255 + ldc0.d cr8,r13[147<<2]
16260 + stc0.w pc[4095<<2],cr15
16261 + stc0.w r5[2048<<2],cr5
16262 + stc0.w r4[2047<<2],cr4
16263 + stc0.w r13[147<<2],cr9
16268 + stc0.d pc[4095<<2],cr14
16269 + stc0.d r5[2048<<2],cr6
16270 + stc0.d r4[2047<<2],cr4
16271 + stc0.d r13[147<<2],cr8
16298 + stcond pc[-1], pc
16299 + stcond r8[-32768], r7
16300 + stcond r7[32767], r8
16301 + stcond r5[0x1234], r10
16304 + ldcm.w cp0,pc,cr0-cr7
16305 + ldcm.w cp7,r0,cr0
16306 + ldcm.w cp4,r4++,cr0-cr6
16307 + ldcm.w cp3,r7,cr7
16308 + ldcm.w cp1,r12++,cr1,cr4-cr6
16309 + ldcm.w cp0,pc,cr8-cr15
16310 + ldcm.w cp7,r0,cr8
16311 + ldcm.w cp4,r4++,cr8-cr14
16312 + ldcm.w cp3,r7,cr15
16313 + ldcm.w cp1,r12++,cr9,cr12-cr14
16316 + ldcm.d cp0,pc,cr0-cr15
16317 + ldcm.d cp7,r0,cr0,cr1
16318 + ldcm.d cp4,r4++,cr0-cr13
16319 + ldcm.d cp3,r7,cr14-cr15
16320 + ldcm.d cp2,r12++,cr0-cr3,cr8-cr9,cr14-cr15
16323 + stcm.w cp0,pc,cr0-cr7
16324 + stcm.w cp7,r0,cr0
16325 + stcm.w cp4,--r4,cr0-cr6
16326 + stcm.w cp3,r7,cr7
16327 + stcm.w cp1,--r12,cr1,cr4-cr6
16328 + stcm.w cp0,pc,cr8-cr15
16329 + stcm.w cp7,r0,cr8
16330 + stcm.w cp4,--r4,cr8-cr14
16331 + stcm.w cp3,r7,cr15
16332 + stcm.w cp1,--r12,cr9,cr12-cr14
16335 + stcm.d cp0,pc,cr0-cr15
16336 + stcm.d cp7,r0,cr0,cr1
16337 + stcm.d cp4,--r4,cr0-cr13
16338 + stcm.d cp3,r7,cr14-cr15
16339 + stcm.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
16342 + mvcr.w cp7,pc,cr15
16343 + mvcr.w cp0,r0,cr0
16344 + mvcr.w cp0,pc,cr15
16345 + mvcr.w cp7,r0,cr15
16346 + mvcr.w cp7,pc,cr0
16347 + mvcr.w cp4,r7,cr8
16348 + mvcr.w cp3,r8,cr7
16351 + mvcr.d cp7,lr,cr14
16352 + mvcr.d cp0,r0,cr0
16353 + mvcr.d cp0,lr,cr14
16354 + mvcr.d cp7,r0,cr14
16355 + mvcr.d cp7,lr,cr0
16356 + mvcr.d cp4,r6,cr8
16357 + mvcr.d cp3,r8,cr6
16360 + mvrc.w cp7,cr15,pc
16361 + mvrc.w cp0,cr0,r0
16362 + mvrc.w cp0,cr15,pc
16363 + mvrc.w cp7,cr15,r0
16364 + mvrc.w cp7,cr0,pc
16365 + mvrc.w cp4,cr8,r7
16366 + mvrc.w cp3,cr7,r8
16369 + mvrc.d cp7,cr14,lr
16370 + mvrc.d cp0,cr0,r0
16371 + mvrc.d cp0,cr14,lr
16372 + mvrc.d cp7,cr14,r0
16373 + mvrc.d cp7,cr0,lr
16374 + mvrc.d cp4,cr8,r6
16375 + mvrc.d cp3,cr6,r8
16378 + bfexts pc,pc,31,31
16380 + bfexts r0,pc,31,31
16381 + bfexts pc,r0,31,31
16382 + bfexts pc,pc,0,31
16383 + bfexts pc,pc,31,0
16384 + bfexts r7,r8,15,16
16385 + bfexts r8,r7,16,15
16388 + bfextu pc,pc,31,31
16390 + bfextu r0,pc,31,31
16391 + bfextu pc,r0,31,31
16392 + bfextu pc,pc,0,31
16393 + bfextu pc,pc,31,0
16394 + bfextu r7,r8,15,16
16395 + bfextu r8,r7,16,15
16398 + bfins pc,pc,31,31
16400 + bfins r0,pc,31,31
16401 + bfins pc,r0,31,31
16404 + bfins r7,r8,15,16
16405 + bfins r8,r7,16,15
16419 + addal r12,r12,r12
16429 + subal r12,r12,r12
16439 + andal r12,r12,r12
16459 + eoral r12,r12,r12
16468 + ld.weq pc,pc[2044]
16469 + ld.shal r12,r12[1022]
16471 + ld.ubpl r4,r4[511]
16474 + ld.shvc r12,r8[0x3fe]
16475 + ld.ubmi r10,r7[1]
16478 + st.weq pc[2044],pc
16479 + st.hal r12[1022],r12
16481 + st.bpl r4[511],r4
16484 + st.hvc r8[0x3fe],r12
16495 +++ b/gas/testsuite/gas/avr32/avr32.exp
16497 +# AVR32 assembler testsuite. -*- Tcl -*-
16499 +if [istarget avr32-*-*] {
16500 + run_dump_test "hwrd-lwrd"
16501 + run_dump_test "pcrel"
16502 + run_dump_test "aliases"
16503 + run_dump_test "dwarf2"
16504 + run_dump_test "pic_reloc"
16505 + run_dump_test "fpinsn"
16506 + run_dump_test "pico"
16507 + run_dump_test "lda_pic"
16508 + run_dump_test "lda_pic_linkrelax"
16509 + run_dump_test "lda_nopic"
16510 + run_dump_test "lda_nopic_linkrelax"
16511 + run_dump_test "call_pic"
16512 + run_dump_test "call_pic_linkrelax"
16513 + run_dump_test "call_nopic"
16514 + run_dump_test "call_nopic_linkrelax"
16515 + run_dump_test "jmptable"
16516 + run_dump_test "jmptable_linkrelax"
16517 + run_dump_test "symdiff"
16518 + run_dump_test "symdiff_linkrelax"
16521 +++ b/gas/testsuite/gas/avr32/call_nopic.d
16528 +.*: +file format .*
16530 +Disassembly of section \.text:
16532 +00000000 <call_test>:
16535 +00000002 <toofar_negative>:
16537 + 1ffffe: 00 00 add r0,r0
16538 + 200000: f0 a0 00 00 rcall 0 <call_test>
16539 + 200004: f0 1f 00 0c mcall 200034 <toofar_negative\+0x200032>
16540 + 200008: f0 1f 00 0c mcall 200038 <toofar_negative\+0x200036>
16541 + 20000c: f0 1f 00 0c mcall 20003c <toofar_negative\+0x20003a>
16542 + 200010: f0 1f 00 0c mcall 200040 <toofar_negative\+0x20003e>
16544 + 200030: ee b0 ff ff rcall 40002e <far_positive>
16546 + 200034: R_AVR32_32_CPENT \.text\+0x2
16547 + 200038: R_AVR32_32_CPENT \.text\.init
16548 + 20003c: R_AVR32_32_CPENT undefined
16549 + 200040: R_AVR32_32_CPENT \.text\+0x40002c
16551 +0040002c <toofar_positive>:
16552 + 40002c: d7 03 nop
16553 +0040002e <far_positive>:
16554 + 40002e: d7 03 nop
16555 +Disassembly of section \.text\.init:
16557 +00000000 <different_section>:
16558 + 0: e2 c0 00 00 sub r0,r1,0
16560 +++ b/gas/testsuite/gas/avr32/call_nopic_linkrelax.d
16565 +#name: call_nopic_linkrelax
16567 +.*: +file format .*
16569 +Disassembly of section \.text:
16571 +00000000 <call_test>:
16574 +00000002 <toofar_negative>:
16576 + 1ffffe: 00 00 add r0,r0
16577 + 200000: e0 a0 00 00 rcall 200000 <toofar_negative\+0x1ffffe>
16578 + 200000: R_AVR32_22H_PCREL \.text
16579 + 200004: f0 1f 00 00 mcall 200004 <toofar_negative\+0x200002>
16580 + 200004: R_AVR32_CPCALL \.text\+0x200034
16581 + 200008: f0 1f 00 00 mcall 200008 <toofar_negative\+0x200006>
16582 + 200008: R_AVR32_CPCALL \.text\+0x200038
16583 + 20000c: f0 1f 00 00 mcall 20000c <toofar_negative\+0x20000a>
16584 + 20000c: R_AVR32_CPCALL \.text\+0x20003c
16585 + 200010: f0 1f 00 00 mcall 200010 <toofar_negative\+0x20000e>
16586 + 200010: R_AVR32_CPCALL \.text\+0x200040
16588 + 200030: e0 a0 00 00 rcall 200030 <toofar_negative\+0x20002e>
16589 + 200030: R_AVR32_22H_PCREL \.text\+0x40002e
16591 + 200034: R_AVR32_ALIGN \*ABS\*\+0x2
16592 + 200034: R_AVR32_32_CPENT \.text\+0x2
16593 + 200038: R_AVR32_32_CPENT \.text\.init
16594 + 20003c: R_AVR32_32_CPENT undefined
16595 + 200040: R_AVR32_32_CPENT \.text\+0x40002c
16597 +0040002c <toofar_positive>:
16598 + 40002c: d7 03 nop
16599 +0040002e <far_positive>:
16600 + 40002e: d7 03 nop
16601 +Disassembly of section \.text\.init:
16603 +00000000 <different_section>:
16604 + 0: e2 c0 00 00 sub r0,r1,0
16606 +++ b/gas/testsuite/gas/avr32/call_pic.d
16613 +.*: +file format .*
16615 +Disassembly of section \.text:
16617 +00000000 <call_test>:
16620 +00000002 <toofar_negative>:
16622 + 1ffffe: 00 00 add r0,r0
16623 + 200000: f0 a0 00 00 rcall 0 <call_test>
16624 + 200004: f0 16 00 00 mcall r6\[0\]
16625 + 200004: R_AVR32_GOT18SW toofar_negative
16626 + 200008: f0 16 00 00 mcall r6\[0\]
16627 + 200008: R_AVR32_GOT18SW different_section
16628 + 20000c: f0 16 00 00 mcall r6\[0\]
16629 + 20000c: R_AVR32_GOT18SW undefined
16630 + 200010: f0 16 00 00 mcall r6\[0\]
16631 + 200010: R_AVR32_GOT18SW toofar_positive
16633 + 200030: ee b0 ff ff rcall 40002e <far_positive>
16636 +0040002c <toofar_positive>:
16637 + 40002c: d7 03 nop
16638 +0040002e <far_positive>:
16639 + 40002e: d7 03 nop
16640 +Disassembly of section \.text\.init:
16642 +00000000 <different_section>:
16643 + 0: e2 c0 00 00 sub r0,r1,0
16645 +++ b/gas/testsuite/gas/avr32/call_pic_linkrelax.d
16648 +#as: --pic --linkrelax
16650 +#name: call_pic_linkrelax
16652 +.*: +file format .*
16654 +Disassembly of section \.text:
16656 +00000000 <call_test>:
16659 +00000002 <toofar_negative>:
16661 + 1ffffe: 00 00 add r0,r0
16662 + 200000: e0 a0 00 00 rcall 200000 <toofar_negative\+0x1ffffe>
16663 + 200000: R_AVR32_22H_PCREL \.text
16664 + 200004: e0 6e 00 00 mov lr,0
16665 + 200004: R_AVR32_GOTCALL toofar_negative
16666 + 200008: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
16667 + 20000c: 5d 1e icall lr
16668 + 20000e: e0 6e 00 00 mov lr,0
16669 + 20000e: R_AVR32_GOTCALL different_section
16670 + 200012: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
16671 + 200016: 5d 1e icall lr
16672 + 200018: e0 6e 00 00 mov lr,0
16673 + 200018: R_AVR32_GOTCALL undefined
16674 + 20001c: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
16675 + 200020: 5d 1e icall lr
16676 + 200022: e0 6e 00 00 mov lr,0
16677 + 200022: R_AVR32_GOTCALL toofar_positive
16678 + 200026: ec 0e 03 2e ld\.w lr,r6\[lr<<0x2\]
16679 + 20002a: 5d 1e icall lr
16680 + 20002c: 00 00 add r0,r0
16681 + 20002e: 00 00 add r0,r0
16682 + 200030: e0 a0 00 00 rcall 200030 <toofar_negative\+0x20002e>
16683 + 200030: R_AVR32_22H_PCREL \.text\+0x40002e
16686 +0040002c <toofar_positive>:
16687 + 40002c: d7 03 nop
16688 +0040002e <far_positive>:
16689 + 40002e: d7 03 nop
16690 +Disassembly of section \.text\.init:
16692 +00000000 <different_section>:
16693 + 0: e2 c0 00 00 sub r0,r1,0
16695 +++ b/gas/testsuite/gas/avr32/call.s
16699 + .global call_test
16707 + call far_negative
16708 + call toofar_negative
16709 + call different_section
16711 + call toofar_positive
16713 + call far_positive
16724 + .section .text.init,"ax",@progbits
16725 +different_section:
16728 +++ b/gas/testsuite/gas/avr32/dwarf2.d
16734 +Dump of debug contents of section \.debug_line:
16738 + Prologue Length: 26
16739 + Minimum Instruction Length: 1
16740 + Initial value of 'is_stmt': 1
16744 + \(Pointer size: 4\)
16747 + Opcode 1 has 0 args
16748 + Opcode 2 has 1 args
16749 + Opcode 3 has 1 args
16750 + Opcode 4 has 1 args
16751 + Opcode 5 has 1 args
16752 + Opcode 6 has 0 args
16753 + Opcode 7 has 0 args
16754 + Opcode 8 has 0 args
16755 + Opcode 9 has 1 args
16757 + The Directory Table is empty\.
16759 + The File Name Table:
16760 + Entry Dir Time Size Name
16763 + Line Number Statements:
16764 + Extended opcode 2: set Address to 0x0
16765 + Advance Line by 87 to 88
16767 + Advance Line by 23 to 111
16768 + Special opcode .*: advance Address by 4 to 0x4 and Line by 0 to 111
16769 + Special opcode .*: advance Address by 10 to 0xe and Line by 1 to 112
16770 + Advance PC by 530 to 220
16771 + Extended opcode 1: End of Sequence
16773 +++ b/gas/testsuite/gas/avr32/dwarf2.s
16775 +# Source file used to test DWARF2 information for AVR32.
16779 + .section .debug_abbrev,"",@progbits
16781 + .section .debug_info,"",@progbits
16783 + .section .debug_line,"",@progbits
16789 + .type main, @function
16815 + .size main, . - main
16819 + .section .debug_info
16820 + .int .Ledebug_info0 - .Ldebug_info0 // size
16821 + .short 2 // version
16822 + .int .Ldebug_abbrev0 // abbrev offset
16823 + .byte 4 // bytes per addr
16825 + .uleb128 1 // abbrev 1
16826 + .int .Ldebug_line0 // DW_AT_stmt_list
16827 + .int .Letext0 // DW_AT_high_pc
16828 + .int .Ltext0 // DW_AT_low_pc
16832 + .section .debug_abbrev
16834 + .uleb128 0x11 // DW_TAG_compile_unit
16835 + .byte 0 // DW_CHILDREN_no
16836 + .uleb128 0x10, 0x6 // DW_AT_stmt_list
16837 + .uleb128 0x12, 0x1 // DW_AT_high_pc
16838 + .uleb128 0x11, 0x1 // DW_AT_low_pc
16843 +++ b/gas/testsuite/gas/avr32/fpinsn.d
16849 +.*: +file format .*
16851 +Disassembly of section \.text:
16853 +[0-9a-f]* <fadd_s>:
16854 + *[0-9a-f]*: e1 a2 0f ff cop cp0,cr15,cr15,cr15,0x4
16855 + *[0-9a-f]*: e1 a2 00 00 cop cp0,cr0,cr0,cr0,0x4
16856 + *[0-9a-f]*: e1 a2 00 ff cop cp0,cr0,cr15,cr15,0x4
16857 + *[0-9a-f]*: e1 a2 0f 0f cop cp0,cr15,cr0,cr15,0x4
16858 + *[0-9a-f]*: e1 a2 0f f0 cop cp0,cr15,cr15,cr0,0x4
16859 + *[0-9a-f]*: e1 a2 07 88 cop cp0,cr7,cr8,cr8,0x4
16860 + *[0-9a-f]*: e1 a2 08 78 cop cp0,cr8,cr7,cr8,0x4
16861 + *[0-9a-f]*: e1 a2 08 87 cop cp0,cr8,cr8,cr7,0x4
16863 +[0-9a-f]* <fsub_s>:
16864 + *[0-9a-f]*: e1 a2 1f ff cop cp0,cr15,cr15,cr15,0x5
16865 + *[0-9a-f]*: e1 a2 10 00 cop cp0,cr0,cr0,cr0,0x5
16866 + *[0-9a-f]*: e1 a2 10 ff cop cp0,cr0,cr15,cr15,0x5
16867 + *[0-9a-f]*: e1 a2 1f 0f cop cp0,cr15,cr0,cr15,0x5
16868 + *[0-9a-f]*: e1 a2 1f f0 cop cp0,cr15,cr15,cr0,0x5
16869 + *[0-9a-f]*: e1 a2 17 88 cop cp0,cr7,cr8,cr8,0x5
16870 + *[0-9a-f]*: e1 a2 18 78 cop cp0,cr8,cr7,cr8,0x5
16871 + *[0-9a-f]*: e1 a2 18 87 cop cp0,cr8,cr8,cr7,0x5
16873 +[0-9a-f]* <fmac_s>:
16874 + *[0-9a-f]*: e1 a0 0f ff cop cp0,cr15,cr15,cr15,0x0
16875 + *[0-9a-f]*: e1 a0 00 00 cop cp0,cr0,cr0,cr0,0x0
16876 + *[0-9a-f]*: e1 a0 00 ff cop cp0,cr0,cr15,cr15,0x0
16877 + *[0-9a-f]*: e1 a0 0f 0f cop cp0,cr15,cr0,cr15,0x0
16878 + *[0-9a-f]*: e1 a0 0f f0 cop cp0,cr15,cr15,cr0,0x0
16879 + *[0-9a-f]*: e1 a0 07 88 cop cp0,cr7,cr8,cr8,0x0
16880 + *[0-9a-f]*: e1 a0 08 78 cop cp0,cr8,cr7,cr8,0x0
16881 + *[0-9a-f]*: e1 a0 08 87 cop cp0,cr8,cr8,cr7,0x0
16883 +[0-9a-f]* <fnmac_s>:
16884 + *[0-9a-f]*: e1 a0 1f ff cop cp0,cr15,cr15,cr15,0x1
16885 + *[0-9a-f]*: e1 a0 10 00 cop cp0,cr0,cr0,cr0,0x1
16886 + *[0-9a-f]*: e1 a0 10 ff cop cp0,cr0,cr15,cr15,0x1
16887 + *[0-9a-f]*: e1 a0 1f 0f cop cp0,cr15,cr0,cr15,0x1
16888 + *[0-9a-f]*: e1 a0 1f f0 cop cp0,cr15,cr15,cr0,0x1
16889 + *[0-9a-f]*: e1 a0 17 88 cop cp0,cr7,cr8,cr8,0x1
16890 + *[0-9a-f]*: e1 a0 18 78 cop cp0,cr8,cr7,cr8,0x1
16891 + *[0-9a-f]*: e1 a0 18 87 cop cp0,cr8,cr8,cr7,0x1
16893 +[0-9a-f]* <fmsc_s>:
16894 + *[0-9a-f]*: e1 a1 0f ff cop cp0,cr15,cr15,cr15,0x2
16895 + *[0-9a-f]*: e1 a1 00 00 cop cp0,cr0,cr0,cr0,0x2
16896 + *[0-9a-f]*: e1 a1 00 ff cop cp0,cr0,cr15,cr15,0x2
16897 + *[0-9a-f]*: e1 a1 0f 0f cop cp0,cr15,cr0,cr15,0x2
16898 + *[0-9a-f]*: e1 a1 0f f0 cop cp0,cr15,cr15,cr0,0x2
16899 + *[0-9a-f]*: e1 a1 07 88 cop cp0,cr7,cr8,cr8,0x2
16900 + *[0-9a-f]*: e1 a1 08 78 cop cp0,cr8,cr7,cr8,0x2
16901 + *[0-9a-f]*: e1 a1 08 87 cop cp0,cr8,cr8,cr7,0x2
16903 +[0-9a-f]* <fnmsc_s>:
16904 + *[0-9a-f]*: e1 a1 1f ff cop cp0,cr15,cr15,cr15,0x3
16905 + *[0-9a-f]*: e1 a1 10 00 cop cp0,cr0,cr0,cr0,0x3
16906 + *[0-9a-f]*: e1 a1 10 ff cop cp0,cr0,cr15,cr15,0x3
16907 + *[0-9a-f]*: e1 a1 1f 0f cop cp0,cr15,cr0,cr15,0x3
16908 + *[0-9a-f]*: e1 a1 1f f0 cop cp0,cr15,cr15,cr0,0x3
16909 + *[0-9a-f]*: e1 a1 17 88 cop cp0,cr7,cr8,cr8,0x3
16910 + *[0-9a-f]*: e1 a1 18 78 cop cp0,cr8,cr7,cr8,0x3
16911 + *[0-9a-f]*: e1 a1 18 87 cop cp0,cr8,cr8,cr7,0x3
16913 +[0-9a-f]* <fmul_s>:
16914 + *[0-9a-f]*: e1 a3 0f ff cop cp0,cr15,cr15,cr15,0x6
16915 + *[0-9a-f]*: e1 a3 00 00 cop cp0,cr0,cr0,cr0,0x6
16916 + *[0-9a-f]*: e1 a3 00 ff cop cp0,cr0,cr15,cr15,0x6
16917 + *[0-9a-f]*: e1 a3 0f 0f cop cp0,cr15,cr0,cr15,0x6
16918 + *[0-9a-f]*: e1 a3 0f f0 cop cp0,cr15,cr15,cr0,0x6
16919 + *[0-9a-f]*: e1 a3 07 88 cop cp0,cr7,cr8,cr8,0x6
16920 + *[0-9a-f]*: e1 a3 08 78 cop cp0,cr8,cr7,cr8,0x6
16921 + *[0-9a-f]*: e1 a3 08 87 cop cp0,cr8,cr8,cr7,0x6
16923 +[0-9a-f]* <fnmul_s>:
16924 + *[0-9a-f]*: e1 a3 1f ff cop cp0,cr15,cr15,cr15,0x7
16925 + *[0-9a-f]*: e1 a3 10 00 cop cp0,cr0,cr0,cr0,0x7
16926 + *[0-9a-f]*: e1 a3 10 ff cop cp0,cr0,cr15,cr15,0x7
16927 + *[0-9a-f]*: e1 a3 1f 0f cop cp0,cr15,cr0,cr15,0x7
16928 + *[0-9a-f]*: e1 a3 1f f0 cop cp0,cr15,cr15,cr0,0x7
16929 + *[0-9a-f]*: e1 a3 17 88 cop cp0,cr7,cr8,cr8,0x7
16930 + *[0-9a-f]*: e1 a3 18 78 cop cp0,cr8,cr7,cr8,0x7
16931 + *[0-9a-f]*: e1 a3 18 87 cop cp0,cr8,cr8,cr7,0x7
16933 +[0-9a-f]* <fneg_s>:
16934 + *[0-9a-f]*: e1 a4 0f f0 cop cp0,cr15,cr15,cr0,0x8
16935 + *[0-9a-f]*: e1 a4 00 00 cop cp0,cr0,cr0,cr0,0x8
16936 + *[0-9a-f]*: e1 a4 00 f0 cop cp0,cr0,cr15,cr0,0x8
16937 + *[0-9a-f]*: e1 a4 0f 00 cop cp0,cr15,cr0,cr0,0x8
16938 + *[0-9a-f]*: e1 a4 07 80 cop cp0,cr7,cr8,cr0,0x8
16939 + *[0-9a-f]*: e1 a4 08 70 cop cp0,cr8,cr7,cr0,0x8
16941 +[0-9a-f]* <fabs_s>:
16942 + *[0-9a-f]*: e1 a4 1f f0 cop cp0,cr15,cr15,cr0,0x9
16943 + *[0-9a-f]*: e1 a4 10 00 cop cp0,cr0,cr0,cr0,0x9
16944 + *[0-9a-f]*: e1 a4 10 f0 cop cp0,cr0,cr15,cr0,0x9
16945 + *[0-9a-f]*: e1 a4 1f 00 cop cp0,cr15,cr0,cr0,0x9
16946 + *[0-9a-f]*: e1 a4 17 80 cop cp0,cr7,cr8,cr0,0x9
16947 + *[0-9a-f]*: e1 a4 18 70 cop cp0,cr8,cr7,cr0,0x9
16949 +[0-9a-f]* <fcmp_s>:
16950 + *[0-9a-f]*: e1 a6 10 ff cop cp0,cr0,cr15,cr15,0xd
16951 + *[0-9a-f]*: e1 a6 10 00 cop cp0,cr0,cr0,cr0,0xd
16952 + *[0-9a-f]*: e1 a6 10 0f cop cp0,cr0,cr0,cr15,0xd
16953 + *[0-9a-f]*: e1 a6 10 f0 cop cp0,cr0,cr15,cr0,0xd
16954 + *[0-9a-f]*: e1 a6 10 78 cop cp0,cr0,cr7,cr8,0xd
16955 + *[0-9a-f]*: e1 a6 10 87 cop cp0,cr0,cr8,cr7,0xd
16957 +[0-9a-f]* <fadd_d>:
16958 + *[0-9a-f]*: e5 a2 0e ee cop cp0,cr14,cr14,cr14,0x44
16959 + *[0-9a-f]*: e5 a2 00 00 cop cp0,cr0,cr0,cr0,0x44
16960 + *[0-9a-f]*: e5 a2 00 ee cop cp0,cr0,cr14,cr14,0x44
16961 + *[0-9a-f]*: e5 a2 0e 0e cop cp0,cr14,cr0,cr14,0x44
16962 + *[0-9a-f]*: e5 a2 0e e0 cop cp0,cr14,cr14,cr0,0x44
16963 + *[0-9a-f]*: e5 a2 06 88 cop cp0,cr6,cr8,cr8,0x44
16964 + *[0-9a-f]*: e5 a2 08 68 cop cp0,cr8,cr6,cr8,0x44
16965 + *[0-9a-f]*: e5 a2 08 86 cop cp0,cr8,cr8,cr6,0x44
16967 +[0-9a-f]* <fsub_d>:
16968 + *[0-9a-f]*: e5 a2 1e ee cop cp0,cr14,cr14,cr14,0x45
16969 + *[0-9a-f]*: e5 a2 10 00 cop cp0,cr0,cr0,cr0,0x45
16970 + *[0-9a-f]*: e5 a2 10 ee cop cp0,cr0,cr14,cr14,0x45
16971 + *[0-9a-f]*: e5 a2 1e 0e cop cp0,cr14,cr0,cr14,0x45
16972 + *[0-9a-f]*: e5 a2 1e e0 cop cp0,cr14,cr14,cr0,0x45
16973 + *[0-9a-f]*: e5 a2 16 88 cop cp0,cr6,cr8,cr8,0x45
16974 + *[0-9a-f]*: e5 a2 18 68 cop cp0,cr8,cr6,cr8,0x45
16975 + *[0-9a-f]*: e5 a2 18 86 cop cp0,cr8,cr8,cr6,0x45
16977 +[0-9a-f]* <fmac_d>:
16978 + *[0-9a-f]*: e5 a0 0e ee cop cp0,cr14,cr14,cr14,0x40
16979 + *[0-9a-f]*: e5 a0 00 00 cop cp0,cr0,cr0,cr0,0x40
16980 + *[0-9a-f]*: e5 a0 00 ee cop cp0,cr0,cr14,cr14,0x40
16981 + *[0-9a-f]*: e5 a0 0e 0e cop cp0,cr14,cr0,cr14,0x40
16982 + *[0-9a-f]*: e5 a0 0e e0 cop cp0,cr14,cr14,cr0,0x40
16983 + *[0-9a-f]*: e5 a0 06 88 cop cp0,cr6,cr8,cr8,0x40
16984 + *[0-9a-f]*: e5 a0 08 68 cop cp0,cr8,cr6,cr8,0x40
16985 + *[0-9a-f]*: e5 a0 08 86 cop cp0,cr8,cr8,cr6,0x40
16987 +[0-9a-f]* <fnmac_d>:
16988 + *[0-9a-f]*: e5 a0 1e ee cop cp0,cr14,cr14,cr14,0x41
16989 + *[0-9a-f]*: e5 a0 10 00 cop cp0,cr0,cr0,cr0,0x41
16990 + *[0-9a-f]*: e5 a0 10 ee cop cp0,cr0,cr14,cr14,0x41
16991 + *[0-9a-f]*: e5 a0 1e 0e cop cp0,cr14,cr0,cr14,0x41
16992 + *[0-9a-f]*: e5 a0 1e e0 cop cp0,cr14,cr14,cr0,0x41
16993 + *[0-9a-f]*: e5 a0 16 88 cop cp0,cr6,cr8,cr8,0x41
16994 + *[0-9a-f]*: e5 a0 18 68 cop cp0,cr8,cr6,cr8,0x41
16995 + *[0-9a-f]*: e5 a0 18 86 cop cp0,cr8,cr8,cr6,0x41
16997 +[0-9a-f]* <fmsc_d>:
16998 + *[0-9a-f]*: e5 a1 0e ee cop cp0,cr14,cr14,cr14,0x42
16999 + *[0-9a-f]*: e5 a1 00 00 cop cp0,cr0,cr0,cr0,0x42
17000 + *[0-9a-f]*: e5 a1 00 ee cop cp0,cr0,cr14,cr14,0x42
17001 + *[0-9a-f]*: e5 a1 0e 0e cop cp0,cr14,cr0,cr14,0x42
17002 + *[0-9a-f]*: e5 a1 0e e0 cop cp0,cr14,cr14,cr0,0x42
17003 + *[0-9a-f]*: e5 a1 06 88 cop cp0,cr6,cr8,cr8,0x42
17004 + *[0-9a-f]*: e5 a1 08 68 cop cp0,cr8,cr6,cr8,0x42
17005 + *[0-9a-f]*: e5 a1 08 86 cop cp0,cr8,cr8,cr6,0x42
17007 +[0-9a-f]* <fnmsc_d>:
17008 + *[0-9a-f]*: e5 a1 1e ee cop cp0,cr14,cr14,cr14,0x43
17009 + *[0-9a-f]*: e5 a1 10 00 cop cp0,cr0,cr0,cr0,0x43
17010 + *[0-9a-f]*: e5 a1 10 ee cop cp0,cr0,cr14,cr14,0x43
17011 + *[0-9a-f]*: e5 a1 1e 0e cop cp0,cr14,cr0,cr14,0x43
17012 + *[0-9a-f]*: e5 a1 1e e0 cop cp0,cr14,cr14,cr0,0x43
17013 + *[0-9a-f]*: e5 a1 16 88 cop cp0,cr6,cr8,cr8,0x43
17014 + *[0-9a-f]*: e5 a1 18 68 cop cp0,cr8,cr6,cr8,0x43
17015 + *[0-9a-f]*: e5 a1 18 86 cop cp0,cr8,cr8,cr6,0x43
17017 +[0-9a-f]* <fmul_d>:
17018 + *[0-9a-f]*: e5 a3 0e ee cop cp0,cr14,cr14,cr14,0x46
17019 + *[0-9a-f]*: e5 a3 00 00 cop cp0,cr0,cr0,cr0,0x46
17020 + *[0-9a-f]*: e5 a3 00 ee cop cp0,cr0,cr14,cr14,0x46
17021 + *[0-9a-f]*: e5 a3 0e 0e cop cp0,cr14,cr0,cr14,0x46
17022 + *[0-9a-f]*: e5 a3 0e e0 cop cp0,cr14,cr14,cr0,0x46
17023 + *[0-9a-f]*: e5 a3 06 88 cop cp0,cr6,cr8,cr8,0x46
17024 + *[0-9a-f]*: e5 a3 08 68 cop cp0,cr8,cr6,cr8,0x46
17025 + *[0-9a-f]*: e5 a3 08 86 cop cp0,cr8,cr8,cr6,0x46
17027 +[0-9a-f]* <fnmul_d>:
17028 + *[0-9a-f]*: e5 a3 1e ee cop cp0,cr14,cr14,cr14,0x47
17029 + *[0-9a-f]*: e5 a3 10 00 cop cp0,cr0,cr0,cr0,0x47
17030 + *[0-9a-f]*: e5 a3 10 ee cop cp0,cr0,cr14,cr14,0x47
17031 + *[0-9a-f]*: e5 a3 1e 0e cop cp0,cr14,cr0,cr14,0x47
17032 + *[0-9a-f]*: e5 a3 1e e0 cop cp0,cr14,cr14,cr0,0x47
17033 + *[0-9a-f]*: e5 a3 16 88 cop cp0,cr6,cr8,cr8,0x47
17034 + *[0-9a-f]*: e5 a3 18 68 cop cp0,cr8,cr6,cr8,0x47
17035 + *[0-9a-f]*: e5 a3 18 86 cop cp0,cr8,cr8,cr6,0x47
17037 +[0-9a-f]* <fneg_d>:
17038 + *[0-9a-f]*: e5 a4 0e e0 cop cp0,cr14,cr14,cr0,0x48
17039 + *[0-9a-f]*: e5 a4 00 00 cop cp0,cr0,cr0,cr0,0x48
17040 + *[0-9a-f]*: e5 a4 00 e0 cop cp0,cr0,cr14,cr0,0x48
17041 + *[0-9a-f]*: e5 a4 0e 00 cop cp0,cr14,cr0,cr0,0x48
17042 + *[0-9a-f]*: e5 a4 06 80 cop cp0,cr6,cr8,cr0,0x48
17043 + *[0-9a-f]*: e5 a4 08 60 cop cp0,cr8,cr6,cr0,0x48
17045 +[0-9a-f]* <fabs_d>:
17046 + *[0-9a-f]*: e5 a4 1e e0 cop cp0,cr14,cr14,cr0,0x49
17047 + *[0-9a-f]*: e5 a4 10 00 cop cp0,cr0,cr0,cr0,0x49
17048 + *[0-9a-f]*: e5 a4 10 e0 cop cp0,cr0,cr14,cr0,0x49
17049 + *[0-9a-f]*: e5 a4 1e 00 cop cp0,cr14,cr0,cr0,0x49
17050 + *[0-9a-f]*: e5 a4 16 80 cop cp0,cr6,cr8,cr0,0x49
17051 + *[0-9a-f]*: e5 a4 18 60 cop cp0,cr8,cr6,cr0,0x49
17053 +[0-9a-f]* <fcmp_d>:
17054 + *[0-9a-f]*: e5 a6 10 ee cop cp0,cr0,cr14,cr14,0x4d
17055 + *[0-9a-f]*: e5 a6 10 00 cop cp0,cr0,cr0,cr0,0x4d
17056 + *[0-9a-f]*: e5 a6 10 0e cop cp0,cr0,cr0,cr14,0x4d
17057 + *[0-9a-f]*: e5 a6 10 e0 cop cp0,cr0,cr14,cr0,0x4d
17058 + *[0-9a-f]*: e5 a6 10 68 cop cp0,cr0,cr6,cr8,0x4d
17059 + *[0-9a-f]*: e5 a6 10 86 cop cp0,cr0,cr8,cr6,0x4d
17061 +[0-9a-f]* <fmov_s>:
17062 + *[0-9a-f]*: e1 a5 0f f0 cop cp0,cr15,cr15,cr0,0xa
17063 + *[0-9a-f]*: e1 a5 00 00 cop cp0,cr0,cr0,cr0,0xa
17064 + *[0-9a-f]*: e1 a5 0f 00 cop cp0,cr15,cr0,cr0,0xa
17065 + *[0-9a-f]*: e1 a5 00 f0 cop cp0,cr0,cr15,cr0,0xa
17066 + *[0-9a-f]*: e1 a5 08 70 cop cp0,cr8,cr7,cr0,0xa
17067 + *[0-9a-f]*: e1 a5 07 80 cop cp0,cr7,cr8,cr0,0xa
17068 + *[0-9a-f]*: ef af 0f 00 mvcr.w cp0,pc,cr15
17069 + *[0-9a-f]*: ef a0 00 00 mvcr.w cp0,r0,cr0
17070 + *[0-9a-f]*: ef af 00 00 mvcr.w cp0,pc,cr0
17071 + *[0-9a-f]*: ef a0 0f 00 mvcr.w cp0,r0,cr15
17072 + *[0-9a-f]*: ef a8 07 00 mvcr.w cp0,r8,cr7
17073 + *[0-9a-f]*: ef a7 08 00 mvcr.w cp0,r7,cr8
17074 + *[0-9a-f]*: ef af 0f 20 mvrc.w cp0,cr15,pc
17075 + *[0-9a-f]*: ef a0 00 20 mvrc.w cp0,cr0,r0
17076 + *[0-9a-f]*: ef a0 0f 20 mvrc.w cp0,cr15,r0
17077 + *[0-9a-f]*: ef af 00 20 mvrc.w cp0,cr0,pc
17078 + *[0-9a-f]*: ef a7 08 20 mvrc.w cp0,cr8,r7
17079 + *[0-9a-f]*: ef a8 07 20 mvrc.w cp0,cr7,r8
17081 +[0-9a-f]* <fmov_d>:
17082 + *[0-9a-f]*: e5 a5 0e e0 cop cp0,cr14,cr14,cr0,0x4a
17083 + *[0-9a-f]*: e5 a5 00 00 cop cp0,cr0,cr0,cr0,0x4a
17084 + *[0-9a-f]*: e5 a5 0e 00 cop cp0,cr14,cr0,cr0,0x4a
17085 + *[0-9a-f]*: e5 a5 00 e0 cop cp0,cr0,cr14,cr0,0x4a
17086 + *[0-9a-f]*: e5 a5 08 60 cop cp0,cr8,cr6,cr0,0x4a
17087 + *[0-9a-f]*: e5 a5 06 80 cop cp0,cr6,cr8,cr0,0x4a
17088 + *[0-9a-f]*: ef ae 0e 10 mvcr.d cp0,lr,cr14
17089 + *[0-9a-f]*: ef a0 00 10 mvcr.d cp0,r0,cr0
17090 + *[0-9a-f]*: ef ae 00 10 mvcr.d cp0,lr,cr0
17091 + *[0-9a-f]*: ef a0 0e 10 mvcr.d cp0,r0,cr14
17092 + *[0-9a-f]*: ef a8 06 10 mvcr.d cp0,r8,cr6
17093 + *[0-9a-f]*: ef a6 08 10 mvcr.d cp0,r6,cr8
17094 + *[0-9a-f]*: ef ae 0e 30 mvrc.d cp0,cr14,lr
17095 + *[0-9a-f]*: ef a0 00 30 mvrc.d cp0,cr0,r0
17096 + *[0-9a-f]*: ef a0 0e 30 mvrc.d cp0,cr14,r0
17097 + *[0-9a-f]*: ef ae 00 30 mvrc.d cp0,cr0,lr
17098 + *[0-9a-f]*: ef a6 08 30 mvrc.d cp0,cr8,r6
17099 + *[0-9a-f]*: ef a8 06 30 mvrc.d cp0,cr6,r8
17101 +[0-9a-f]* <fcasts_d>:
17102 + *[0-9a-f]*: e1 a7 1f e0 cop cp0,cr15,cr14,cr0,0xf
17103 + *[0-9a-f]*: e1 a7 10 00 cop cp0,cr0,cr0,cr0,0xf
17104 + *[0-9a-f]*: e1 a7 1f 00 cop cp0,cr15,cr0,cr0,0xf
17105 + *[0-9a-f]*: e1 a7 10 e0 cop cp0,cr0,cr14,cr0,0xf
17106 + *[0-9a-f]*: e1 a7 18 60 cop cp0,cr8,cr6,cr0,0xf
17107 + *[0-9a-f]*: e1 a7 17 80 cop cp0,cr7,cr8,cr0,0xf
17109 +[0-9a-f]* <fcastd_s>:
17110 + *[0-9a-f]*: e1 a8 0e f0 cop cp0,cr14,cr15,cr0,0x10
17111 + *[0-9a-f]*: e1 a8 00 00 cop cp0,cr0,cr0,cr0,0x10
17112 + *[0-9a-f]*: e1 a8 0e 00 cop cp0,cr14,cr0,cr0,0x10
17113 + *[0-9a-f]*: e1 a8 00 f0 cop cp0,cr0,cr15,cr0,0x10
17114 + *[0-9a-f]*: e1 a8 08 70 cop cp0,cr8,cr7,cr0,0x10
17115 + *[0-9a-f]*: e1 a8 06 80 cop cp0,cr6,cr8,cr0,0x10
17117 +++ b/gas/testsuite/gas/avr32/fpinsn.s
17123 + fadd.s fr15, fr15, fr15
17124 + fadd.s fr0, fr0, fr0
17125 + fadd.s fr0, fr15, fr15
17126 + fadd.s fr15, fr0, fr15
17127 + fadd.s fr15, fr15, fr0
17128 + fadd.s fr7, fr8, fr8
17129 + fadd.s fr8, fr7, fr8
17130 + fadd.s fr8, fr8, fr7
17133 + fsub.s fr15, fr15, fr15
17134 + fsub.s fr0, fr0, fr0
17135 + fsub.s fr0, fr15, fr15
17136 + fsub.s fr15, fr0, fr15
17137 + fsub.s fr15, fr15, fr0
17138 + fsub.s fr7, fr8, fr8
17139 + fsub.s fr8, fr7, fr8
17140 + fsub.s fr8, fr8, fr7
17143 + fmac.s fr15, fr15, fr15
17144 + fmac.s fr0, fr0, fr0
17145 + fmac.s fr0, fr15, fr15
17146 + fmac.s fr15, fr0, fr15
17147 + fmac.s fr15, fr15, fr0
17148 + fmac.s fr7, fr8, fr8
17149 + fmac.s fr8, fr7, fr8
17150 + fmac.s fr8, fr8, fr7
17153 + fnmac.s fr15, fr15, fr15
17154 + fnmac.s fr0, fr0, fr0
17155 + fnmac.s fr0, fr15, fr15
17156 + fnmac.s fr15, fr0, fr15
17157 + fnmac.s fr15, fr15, fr0
17158 + fnmac.s fr7, fr8, fr8
17159 + fnmac.s fr8, fr7, fr8
17160 + fnmac.s fr8, fr8, fr7
17163 + fmsc.s fr15, fr15, fr15
17164 + fmsc.s fr0, fr0, fr0
17165 + fmsc.s fr0, fr15, fr15
17166 + fmsc.s fr15, fr0, fr15
17167 + fmsc.s fr15, fr15, fr0
17168 + fmsc.s fr7, fr8, fr8
17169 + fmsc.s fr8, fr7, fr8
17170 + fmsc.s fr8, fr8, fr7
17173 + fnmsc.s fr15, fr15, fr15
17174 + fnmsc.s fr0, fr0, fr0
17175 + fnmsc.s fr0, fr15, fr15
17176 + fnmsc.s fr15, fr0, fr15
17177 + fnmsc.s fr15, fr15, fr0
17178 + fnmsc.s fr7, fr8, fr8
17179 + fnmsc.s fr8, fr7, fr8
17180 + fnmsc.s fr8, fr8, fr7
17183 + fmul.s fr15, fr15, fr15
17184 + fmul.s fr0, fr0, fr0
17185 + fmul.s fr0, fr15, fr15
17186 + fmul.s fr15, fr0, fr15
17187 + fmul.s fr15, fr15, fr0
17188 + fmul.s fr7, fr8, fr8
17189 + fmul.s fr8, fr7, fr8
17190 + fmul.s fr8, fr8, fr7
17193 + fnmul.s fr15, fr15, fr15
17194 + fnmul.s fr0, fr0, fr0
17195 + fnmul.s fr0, fr15, fr15
17196 + fnmul.s fr15, fr0, fr15
17197 + fnmul.s fr15, fr15, fr0
17198 + fnmul.s fr7, fr8, fr8
17199 + fnmul.s fr8, fr7, fr8
17200 + fnmul.s fr8, fr8, fr7
17203 + fneg.s fr15, fr15
17211 + fabs.s fr15, fr15
17219 + fcmp.s fr15, fr15
17227 + fadd.d fr14, fr14, fr14
17228 + fadd.d fr0, fr0, fr0
17229 + fadd.d fr0, fr14, fr14
17230 + fadd.d fr14, fr0, fr14
17231 + fadd.d fr14, fr14, fr0
17232 + fadd.d fr6, fr8, fr8
17233 + fadd.d fr8, fr6, fr8
17234 + fadd.d fr8, fr8, fr6
17237 + fsub.d fr14, fr14, fr14
17238 + fsub.d fr0, fr0, fr0
17239 + fsub.d fr0, fr14, fr14
17240 + fsub.d fr14, fr0, fr14
17241 + fsub.d fr14, fr14, fr0
17242 + fsub.d fr6, fr8, fr8
17243 + fsub.d fr8, fr6, fr8
17244 + fsub.d fr8, fr8, fr6
17247 + fmac.d fr14, fr14, fr14
17248 + fmac.d fr0, fr0, fr0
17249 + fmac.d fr0, fr14, fr14
17250 + fmac.d fr14, fr0, fr14
17251 + fmac.d fr14, fr14, fr0
17252 + fmac.d fr6, fr8, fr8
17253 + fmac.d fr8, fr6, fr8
17254 + fmac.d fr8, fr8, fr6
17257 + fnmac.d fr14, fr14, fr14
17258 + fnmac.d fr0, fr0, fr0
17259 + fnmac.d fr0, fr14, fr14
17260 + fnmac.d fr14, fr0, fr14
17261 + fnmac.d fr14, fr14, fr0
17262 + fnmac.d fr6, fr8, fr8
17263 + fnmac.d fr8, fr6, fr8
17264 + fnmac.d fr8, fr8, fr6
17267 + fmsc.d fr14, fr14, fr14
17268 + fmsc.d fr0, fr0, fr0
17269 + fmsc.d fr0, fr14, fr14
17270 + fmsc.d fr14, fr0, fr14
17271 + fmsc.d fr14, fr14, fr0
17272 + fmsc.d fr6, fr8, fr8
17273 + fmsc.d fr8, fr6, fr8
17274 + fmsc.d fr8, fr8, fr6
17277 + fnmsc.d fr14, fr14, fr14
17278 + fnmsc.d fr0, fr0, fr0
17279 + fnmsc.d fr0, fr14, fr14
17280 + fnmsc.d fr14, fr0, fr14
17281 + fnmsc.d fr14, fr14, fr0
17282 + fnmsc.d fr6, fr8, fr8
17283 + fnmsc.d fr8, fr6, fr8
17284 + fnmsc.d fr8, fr8, fr6
17287 + fmul.d fr14, fr14, fr14
17288 + fmul.d fr0, fr0, fr0
17289 + fmul.d fr0, fr14, fr14
17290 + fmul.d fr14, fr0, fr14
17291 + fmul.d fr14, fr14, fr0
17292 + fmul.d fr6, fr8, fr8
17293 + fmul.d fr8, fr6, fr8
17294 + fmul.d fr8, fr8, fr6
17297 + fnmul.d fr14, fr14, fr14
17298 + fnmul.d fr0, fr0, fr0
17299 + fnmul.d fr0, fr14, fr14
17300 + fnmul.d fr14, fr0, fr14
17301 + fnmul.d fr14, fr14, fr0
17302 + fnmul.d fr6, fr8, fr8
17303 + fnmul.d fr8, fr6, fr8
17304 + fnmul.d fr8, fr8, fr6
17307 + fneg.d fr14, fr14
17315 + fabs.d fr14, fr14
17323 + fcmp.d fr14, fr14
17331 + fmov.s fr15, fr15
17351 + fmov.d fr14, fr14
17371 + fcasts.d fr15, fr14
17372 + fcasts.d fr0, fr0
17373 + fcasts.d fr15, fr0
17374 + fcasts.d fr0, fr14
17375 + fcasts.d fr8, fr6
17376 + fcasts.d fr7, fr8
17379 + fcastd.s fr14, fr15
17380 + fcastd.s fr0, fr0
17381 + fcastd.s fr14, fr0
17382 + fcastd.s fr0, fr15
17383 + fcastd.s fr8, fr7
17384 + fcastd.s fr6, fr8
17386 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.d
17392 +.*: +file format .*
17394 +Disassembly of section \.text:
17396 +00000000 <test_hwrd>:
17397 + 0: e0 60 87 65 mov r0,34661
17398 + 4: e0 60 12 34 mov r0,4660
17399 + 8: e0 60 00 00 mov r0,0
17400 + 8: R_AVR32_HI16 \.text\+0x60
17401 + c: e0 60 00 00 mov r0,0
17402 + c: R_AVR32_HI16 extsym1
17403 + 10: ea 10 87 65 orh r0,0x8765
17404 + 14: ea 10 12 34 orh r0,0x1234
17405 + 18: ea 10 00 00 orh r0,0x0
17406 + 18: R_AVR32_HI16 \.text\+0x60
17407 + 1c: ea 10 00 00 orh r0,0x0
17408 + 1c: R_AVR32_HI16 extsym1
17409 + 20: e4 10 87 65 andh r0,0x8765
17410 + 24: e4 10 12 34 andh r0,0x1234
17411 + 28: e4 10 00 00 andh r0,0x0
17412 + 28: R_AVR32_HI16 \.text\+0x60
17413 + 2c: e4 10 00 00 andh r0,0x0
17414 + 2c: R_AVR32_HI16 extsym1
17416 +00000030 <test_lwrd>:
17417 + 30: e0 60 43 21 mov r0,17185
17418 + 34: e0 60 56 78 mov r0,22136
17419 + 38: e0 60 00 00 mov r0,0
17420 + 38: R_AVR32_LO16 \.text\+0x60
17421 + 3c: e0 60 00 00 mov r0,0
17422 + 3c: R_AVR32_LO16 extsym1
17423 + 40: e8 10 43 21 orl r0,0x4321
17424 + 44: e8 10 56 78 orl r0,0x5678
17425 + 48: e8 10 00 00 orl r0,0x0
17426 + 48: R_AVR32_LO16 \.text\+0x60
17427 + 4c: e8 10 00 00 orl r0,0x0
17428 + 4c: R_AVR32_LO16 extsym1
17429 + 50: e0 10 43 21 andl r0,0x4321
17430 + 54: e0 10 56 78 andl r0,0x5678
17431 + 58: e0 10 00 00 andl r0,0x0
17432 + 58: R_AVR32_LO16 \.text\+0x60
17433 + 5c: e0 10 00 00 andl r0,0x0
17434 + 5c: R_AVR32_LO16 extsym1
17436 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.s
17439 + .equ sym1, 0x12345678
17442 + .global test_hwrd
17444 + mov r0, hi(0x87654321)
17447 + mov r0, hi(extsym1)
17449 + orh r0, hi(0x87654321)
17452 + orh r0, hi(extsym1)
17454 + andh r0, hi(0x87654321)
17455 + andh r0, hi(sym1)
17456 + andh r0, hi(sym2)
17457 + andh r0, hi(extsym1)
17459 + .global test_lwrd
17461 + mov r0, lo(0x87654321)
17464 + mov r0, lo(extsym1)
17466 + orl r0, lo(0x87654321)
17469 + orl r0, lo(extsym1)
17471 + andl r0, lo(0x87654321)
17472 + andl r0, lo(sym1)
17473 + andl r0, lo(sym2)
17474 + andl r0, lo(extsym1)
17478 +++ b/gas/testsuite/gas/avr32/jmptable.d
17480 +#source: jmptable.s
17485 +.*: +file format .*
17487 +Disassembly of section \.text:
17489 +00000000 <jmptable_test>:
17490 + 0: fe c8 ff f4 sub r8,pc,-12
17491 + 4: f0 00 00 2f add pc,r8,r0<<0x2
17493 + a: 00 00 add r0,r0
17494 + c: c0 38 rjmp 12 <jmptable_test\+0x12>
17495 + e: c0 38 rjmp 14 <jmptable_test\+0x14>
17496 + 10: c0 38 rjmp 16 <jmptable_test\+0x16>
17501 +++ b/gas/testsuite/gas/avr32/jmptable_linkrelax.d
17503 +#source: jmptable.s
17506 +#name: jmptable_linkrelax
17508 +.*: +file format .*
17510 +Disassembly of section \.text:
17512 +00000000 <jmptable_test>:
17513 + 0: fe c8 00 00 sub r8,pc,0
17514 + 0: R_AVR32_16N_PCREL \.text\+0xc
17515 + 4: f0 00 00 2f add pc,r8,r0<<0x2
17517 + a: 00 00 add r0,r0
17518 + a: R_AVR32_ALIGN \*ABS\*\+0x2
17519 + c: c0 08 rjmp c <jmptable_test\+0xc>
17520 + c: R_AVR32_11H_PCREL \.text\+0x12
17521 + e: c0 08 rjmp e <jmptable_test\+0xe>
17522 + e: R_AVR32_11H_PCREL \.text\+0x14
17523 + 10: c0 08 rjmp 10 <jmptable_test\+0x10>
17524 + 10: R_AVR32_11H_PCREL \.text\+0x16
17529 +++ b/gas/testsuite/gas/avr32/jmptable.s
17533 + .global jmptable_test
17535 + sub r8, pc, -(.L1 - .)
17536 + add pc, r8, r0 << 2
17546 +++ b/gas/testsuite/gas/avr32/lda_nopic.d
17553 +.*: +file format .*
17555 +Disassembly of section \.text:
17557 +00000000 <lda_test>:
17558 + 0: f2 c8 00 00 sub r8,r9,0
17560 +00000004 <far_negative>:
17561 + 4: f6 ca 00 00 sub r10,r11,0
17563 + 8000: fe c0 7f fc sub r0,pc,32764
17564 + 8004: 48 31 lddpc r1,8010 <far_negative\+0x800c>
17565 + 8006: 48 42 lddpc r2,8014 <far_negative\+0x8010>
17566 + 8008: 48 43 lddpc r3,8018 <far_negative\+0x8014>
17567 + 800a: 48 54 lddpc r4,801c <far_negative\+0x8018>
17568 + 800c: fe c5 80 04 sub r5,pc,-32764
17570 + 8010: R_AVR32_32_CPENT \.text
17571 + 8014: R_AVR32_32_CPENT \.data
17572 + 8018: R_AVR32_32_CPENT undefined
17573 + 801c: R_AVR32_32_CPENT \.text\+0x1001c
17575 +00010008 <far_positive>:
17576 + 10008: fa cc 00 00 sub r12,sp,0
17578 +0001001c <toofar_positive>:
17579 + 1001c: fe ce 00 00 sub lr,pc,0
17581 +++ b/gas/testsuite/gas/avr32/lda_nopic_linkrelax.d
17586 +#name: lda_nopic_linkrelax
17588 +.*: +file format .*
17590 +Disassembly of section \.text:
17592 +00000000 <lda_test>:
17593 + 0: f2 c8 00 00 sub r8,r9,0
17595 +00000004 <far_negative>:
17596 + 4: f6 ca 00 00 sub r10,r11,0
17598 + 8000: 48 00 lddpc r0,8000 <far_negative\+0x7ffc>
17599 + 8000: R_AVR32_9W_CP \.text\+0x800c
17600 + 8002: 48 01 lddpc r1,8000 <far_negative\+0x7ffc>
17601 + 8002: R_AVR32_9W_CP \.text\+0x8010
17602 + 8004: 48 02 lddpc r2,8004 <far_negative\+0x8000>
17603 + 8004: R_AVR32_9W_CP \.text\+0x8014
17604 + 8006: 48 03 lddpc r3,8004 <far_negative\+0x8000>
17605 + 8006: R_AVR32_9W_CP \.text\+0x8018
17606 + 8008: 48 04 lddpc r4,8008 <far_negative\+0x8004>
17607 + 8008: R_AVR32_9W_CP \.text\+0x801c
17608 + 800a: 48 05 lddpc r5,8008 <far_negative\+0x8004>
17609 + 800a: R_AVR32_9W_CP \.text\+0x8020
17611 + 800c: R_AVR32_ALIGN \*ABS\*\+0x2
17612 + 800c: R_AVR32_32_CPENT \.text\+0x4
17613 + 8010: R_AVR32_32_CPENT \.text
17614 + 8014: R_AVR32_32_CPENT \.data
17615 + 8018: R_AVR32_32_CPENT undefined
17616 + 801c: R_AVR32_32_CPENT \.text\+0x10020
17617 + 8020: R_AVR32_32_CPENT \.text\+0x1000c
17619 +0001000c <far_positive>:
17620 + 1000c: fa cc 00 00 sub r12,sp,0
17622 +00010020 <toofar_positive>:
17623 + 10020: fe ce 00 00 sub lr,pc,0
17625 +++ b/gas/testsuite/gas/avr32/lda_pic.d
17632 +.*: +file format .*
17634 +Disassembly of section \.text:
17636 +00000000 <lda_test>:
17637 + 0: f2 c8 00 00 sub r8,r9,0
17639 +00000004 <far_negative>:
17640 + 4: f6 ca 00 00 sub r10,r11,0
17642 + 8000: fe c0 7f fc sub r0,pc,32764
17643 + 8004: ec f1 00 00 ld.w r1,r6\[0\]
17644 + 8004: R_AVR32_GOT16S toofar_negative
17645 + 8008: ec f2 00 00 ld.w r2,r6\[0\]
17646 + 8008: R_AVR32_GOT16S different_section
17647 + 800c: ec f3 00 00 ld.w r3,r6\[0\]
17648 + 800c: R_AVR32_GOT16S undefined
17649 + 8010: ec f4 00 00 ld.w r4,r6\[0\]
17650 + 8010: R_AVR32_GOT16S toofar_positive
17651 + 8014: fe c5 80 14 sub r5,pc,-32748
17654 +00010000 <far_positive>:
17655 + 10000: fa cc 00 00 sub r12,sp,0
17657 +00010014 <toofar_positive>:
17658 + 10014: fe ce 00 00 sub lr,pc,0
17660 +++ b/gas/testsuite/gas/avr32/lda_pic_linkrelax.d
17663 +#as: --pic --linkrelax
17665 +#name: lda_pic_linkrelax
17667 +.*: +file format .*
17669 +Disassembly of section \.text:
17671 +00000000 <lda_test>:
17672 + 0: f2 c8 00 00 sub r8,r9,0
17674 +00000004 <far_negative>:
17675 + 4: f6 ca 00 00 sub r10,r11,0
17677 + 8000: e0 60 00 00 mov r0,0
17678 + 8000: R_AVR32_LDA_GOT far_negative
17679 + 8004: ec 00 03 20 ld\.w r0,r6\[r0<<0x2\]
17680 + 8008: e0 61 00 00 mov r1,0
17681 + 8008: R_AVR32_LDA_GOT toofar_negative
17682 + 800c: ec 01 03 21 ld\.w r1,r6\[r1<<0x2\]
17683 + 8010: e0 62 00 00 mov r2,0
17684 + 8010: R_AVR32_LDA_GOT different_section
17685 + 8014: ec 02 03 22 ld\.w r2,r6\[r2<<0x2\]
17686 + 8018: e0 63 00 00 mov r3,0
17687 + 8018: R_AVR32_LDA_GOT undefined
17688 + 801c: ec 03 03 23 ld\.w r3,r6\[r3<<0x2\]
17689 + 8020: e0 64 00 00 mov r4,0
17690 + 8020: R_AVR32_LDA_GOT toofar_positive
17691 + 8024: ec 04 03 24 ld\.w r4,r6\[r4<<0x2\]
17692 + 8028: e0 65 00 00 mov r5,0
17693 + 8028: R_AVR32_LDA_GOT far_positive
17694 + 802c: ec 05 03 25 ld\.w r5,r6\[r5<<0x2\]
17697 +00010018 <far_positive>:
17698 + 10018: fa cc 00 00 sub r12,sp,0
17700 +0001002c <toofar_positive>:
17701 + 1002c: fe ce 00 00 sub lr,pc,0
17703 +++ b/gas/testsuite/gas/avr32/lda.s
17714 + .fill 32760, 1, 0x00
17716 + lda.w r0, far_negative
17717 + lda.w r1, toofar_negative
17718 + lda.w r2, different_section
17719 + lda.w r3, undefined
17720 + lda.w r4, toofar_positive
17721 + lda.w r5, far_positive
17725 + .fill 32744, 1, 0x00
17728 + .fill 16, 1, 0x00
17733 +different_section:
17736 +++ b/gas/testsuite/gas/avr32/pcrel.d
17742 +.*: +file format .*
17744 +Disassembly of section \.text:
17746 +00000000 <test_rjmp>:
17748 + 2: c0 28 rjmp 6 <test_rjmp\+0x6>
17750 + 6: e0 8f 00 00 bral 6 <test_rjmp\+0x6>
17751 + 6: R_AVR32_22H_PCREL extsym10
17753 +0000000a <test_rcall>:
17755 +0000000c <test_rcall2>:
17756 + c: c0 2c rcall 10 <test_rcall2\+0x4>
17758 + 10: e0 a0 00 00 rcall 10 <test_rcall2\+0x4>
17759 + 10: R_AVR32_22H_PCREL extsym21
17761 +00000014 <test_branch>:
17762 + 14: c0 31 brne 1a <test_branch\+0x6>
17763 + 16: e0 8f 00 00 bral 16 <test_branch\+0x2>
17764 + 16: R_AVR32_22H_PCREL test_branch
17765 + 1a: e0 80 00 00 breq 1a <test_branch\+0x6>
17766 + 1a: R_AVR32_22H_PCREL extsym21
17768 +0000001e <test_lddpc>:
17769 + 1e: 48 30 lddpc r0,28 <sym1>
17770 + 20: 48 20 lddpc r0,28 <sym1>
17771 + 22: fe f0 00 00 ld.w r0,pc\[0\]
17772 + 22: R_AVR32_16B_PCREL extsym16
17779 +0000002c <test_local>:
17780 + 2c: 48 20 lddpc r0,34 <test_local\+0x8>
17781 + 2e: 48 30 lddpc r0,38 <test_local\+0xc>
17782 + 30: 48 20 lddpc r0,38 <test_local\+0xc>
17783 + 32: 00 00 add r0,r0
17789 +Disassembly of section \.text\.init:
17791 +00000000 <test_inter_section>:
17792 + 0: e0 a0 .. .. rcall [0-9a-f]+ <.*>
17793 + 0: R_AVR32_22H_PCREL test_rcall
17795 + 6: e0 a0 .. .. rcall [0-9a-f]+ <.*>
17796 + 6: R_AVR32_22H_PCREL test_rcall
17797 + a: e0 a0 .. .. rcall [0-9a-z]+ <.*>
17798 + a: R_AVR32_22H_PCREL \.text\+0xc
17800 + 10: e0 a0 .. .. rcall [0-9a-f]+ <.*>
17801 + 10: R_AVR32_22H_PCREL \.text\+0xc
17803 +++ b/gas/testsuite/gas/avr32/pcrel.s
17807 + .global test_rjmp
17814 + .global test_rcall
17822 + .global test_branch
17825 + /* This will generate a reloc since test_branch is global */
17829 + .global test_lddpc
17833 + lddpc r0,extsym16
17839 + .global test_local
17843 + lddpc r0, .LC1 + 0x4
17853 + .section .text.init,"ax"
17854 + .global test_inter_section
17855 +test_inter_section:
17859 + rcall test_rcall2
17861 + rcall test_rcall2
17863 +++ b/gas/testsuite/gas/avr32/pico.d
17869 +.*: +file format .*
17871 +Disassembly of section \.text:
17873 +[0-9a-f]* <picosvmac>:
17874 + *[0-9a-f]*: e1 a6 20 00 cop cp1,cr0,cr0,cr0,0xc
17875 + *[0-9a-f]*: e1 a7 2b bb cop cp1,cr11,cr11,cr11,0xe
17876 + *[0-9a-f]*: e1 a6 3a 05 cop cp1,cr10,cr0,cr5,0xd
17877 + *[0-9a-f]*: e1 a7 36 90 cop cp1,cr6,cr9,cr0,0xf
17879 +[0-9a-f]* <picosvmul>:
17880 + *[0-9a-f]*: e1 a4 20 00 cop cp1,cr0,cr0,cr0,0x8
17881 + *[0-9a-f]*: e1 a5 2b bb cop cp1,cr11,cr11,cr11,0xa
17882 + *[0-9a-f]*: e1 a4 3a 05 cop cp1,cr10,cr0,cr5,0x9
17883 + *[0-9a-f]*: e1 a5 36 90 cop cp1,cr6,cr9,cr0,0xb
17885 +[0-9a-f]* <picovmac>:
17886 + *[0-9a-f]*: e1 a2 20 00 cop cp1,cr0,cr0,cr0,0x4
17887 + *[0-9a-f]*: e1 a3 2b bb cop cp1,cr11,cr11,cr11,0x6
17888 + *[0-9a-f]*: e1 a2 3a 05 cop cp1,cr10,cr0,cr5,0x5
17889 + *[0-9a-f]*: e1 a3 36 90 cop cp1,cr6,cr9,cr0,0x7
17891 +[0-9a-f]* <picovmul>:
17892 + *[0-9a-f]*: e1 a0 20 00 cop cp1,cr0,cr0,cr0,0x0
17893 + *[0-9a-f]*: e1 a1 2b bb cop cp1,cr11,cr11,cr11,0x2
17894 + *[0-9a-f]*: e1 a0 3a 05 cop cp1,cr10,cr0,cr5,0x1
17895 + *[0-9a-f]*: e1 a1 36 90 cop cp1,cr6,cr9,cr0,0x3
17897 +[0-9a-f]* <picold_d>:
17898 + *[0-9a-f]*: e9 af 3e ff ldc\.d cp1,cr14,pc\[0x3fc\]
17899 + *[0-9a-f]*: e9 a0 30 ff ldc\.d cp1,cr0,r0\[0x3fc\]
17900 + *[0-9a-f]*: e9 a0 30 00 ldc\.d cp1,cr0,r0\[0x0\]
17901 + *[0-9a-f]*: ef a8 26 50 ldc\.d cp1,cr6,--r8
17902 + *[0-9a-f]*: ef a7 28 50 ldc\.d cp1,cr8,--r7
17903 + *[0-9a-f]*: ef aa 32 65 ldc\.d cp1,cr2,r10\[r5<<0x2\]
17904 + *[0-9a-f]*: ef a3 3c 46 ldc\.d cp1,cr12,r3\[r6\]
17906 +[0-9a-f]* <picold_w>:
17907 + *[0-9a-f]*: e9 af 2f ff ldc\.w cp1,cr15,pc\[0x3fc\]
17908 + *[0-9a-f]*: e9 a0 20 ff ldc\.w cp1,cr0,r0\[0x3fc\]
17909 + *[0-9a-f]*: e9 a0 20 00 ldc\.w cp1,cr0,r0\[0x0\]
17910 + *[0-9a-f]*: ef a8 27 40 ldc\.w cp1,cr7,--r8
17911 + *[0-9a-f]*: ef a7 28 40 ldc\.w cp1,cr8,--r7
17912 + *[0-9a-f]*: ef aa 31 25 ldc\.w cp1,cr1,r10\[r5<<0x2\]
17913 + *[0-9a-f]*: ef a3 3d 06 ldc\.w cp1,cr13,r3\[r6\]
17915 +[0-9a-f]* <picoldm_d>:
17916 + *[0-9a-f]*: ed af 24 ff ldcm\.d cp1,pc,cr0-cr15
17917 + *[0-9a-f]*: ed a0 24 01 ldcm\.d cp1,r0,cr0-cr1
17918 + *[0-9a-f]*: ed a7 24 80 ldcm\.d cp1,r7,cr14-cr15
17919 + *[0-9a-f]*: ed a8 24 7f ldcm\.d cp1,r8,cr0-cr13
17921 +[0-9a-f]* <picoldm_d_pu>:
17922 + *[0-9a-f]*: ed af 34 ff ldcm\.d cp1,pc\+\+,cr0-cr15
17923 + *[0-9a-f]*: ed a0 34 01 ldcm\.d cp1,r0\+\+,cr0-cr1
17924 + *[0-9a-f]*: ed a7 34 80 ldcm\.d cp1,r7\+\+,cr14-cr15
17925 + *[0-9a-f]*: ed a8 34 7f ldcm\.d cp1,r8\+\+,cr0-cr13
17927 +[0-9a-f]* <picoldm_w>:
17928 + *[0-9a-f]*: ed af 20 ff ldcm\.w cp1,pc,cr0-cr7
17929 + *[0-9a-f]*: ed a0 20 01 ldcm\.w cp1,r0,cr0
17930 + *[0-9a-f]*: ed a7 20 80 ldcm\.w cp1,r7,cr7
17931 + *[0-9a-f]*: ed a8 20 7f ldcm\.w cp1,r8,cr0-cr6
17932 + *[0-9a-f]*: ed af 21 ff ldcm\.w cp1,pc,cr8-cr15
17933 + *[0-9a-f]*: ed a0 21 01 ldcm\.w cp1,r0,cr8
17934 + *[0-9a-f]*: ed a7 21 80 ldcm\.w cp1,r7,cr15
17935 + *[0-9a-f]*: ed a8 21 7f ldcm\.w cp1,r8,cr8-cr14
17937 +[0-9a-f]* <picoldm_w_pu>:
17938 + *[0-9a-f]*: ed af 30 ff ldcm\.w cp1,pc\+\+,cr0-cr7
17939 + *[0-9a-f]*: ed a0 30 01 ldcm\.w cp1,r0\+\+,cr0
17940 + *[0-9a-f]*: ed a7 30 80 ldcm\.w cp1,r7\+\+,cr7
17941 + *[0-9a-f]*: ed a8 30 7f ldcm\.w cp1,r8\+\+,cr0-cr6
17942 + *[0-9a-f]*: ed af 31 ff ldcm\.w cp1,pc\+\+,cr8-cr15
17943 + *[0-9a-f]*: ed a0 31 01 ldcm\.w cp1,r0\+\+,cr8
17944 + *[0-9a-f]*: ed a7 31 80 ldcm\.w cp1,r7\+\+,cr15
17945 + *[0-9a-f]*: ed a8 31 7f ldcm\.w cp1,r8\+\+,cr8-cr14
17947 +[0-9a-f]* <picomv_d>:
17948 + *[0-9a-f]*: ef ae 2e 30 mvrc\.d cp1,cr14,lr
17949 + *[0-9a-f]*: ef a0 20 30 mvrc\.d cp1,cr0,r0
17950 + *[0-9a-f]*: ef a8 26 30 mvrc\.d cp1,cr6,r8
17951 + *[0-9a-f]*: ef a6 28 30 mvrc\.d cp1,cr8,r6
17952 + *[0-9a-f]*: ef ae 2e 10 mvcr\.d cp1,lr,cr14
17953 + *[0-9a-f]*: ef a0 20 10 mvcr\.d cp1,r0,cr0
17954 + *[0-9a-f]*: ef a8 26 10 mvcr\.d cp1,r8,cr6
17955 + *[0-9a-f]*: ef a6 28 10 mvcr\.d cp1,r6,cr8
17957 +[0-9a-f]* <picomv_w>:
17958 + *[0-9a-f]*: ef af 2f 20 mvrc\.w cp1,cr15,pc
17959 + *[0-9a-f]*: ef a0 20 20 mvrc\.w cp1,cr0,r0
17960 + *[0-9a-f]*: ef a8 27 20 mvrc\.w cp1,cr7,r8
17961 + *[0-9a-f]*: ef a7 28 20 mvrc\.w cp1,cr8,r7
17962 + *[0-9a-f]*: ef af 2f 00 mvcr\.w cp1,pc,cr15
17963 + *[0-9a-f]*: ef a0 20 00 mvcr\.w cp1,r0,cr0
17964 + *[0-9a-f]*: ef a8 27 00 mvcr\.w cp1,r8,cr7
17965 + *[0-9a-f]*: ef a7 28 00 mvcr\.w cp1,r7,cr8
17967 +[0-9a-f]* <picost_d>:
17968 + *[0-9a-f]*: eb af 3e ff stc\.d cp1,pc\[0x3fc\],cr14
17969 + *[0-9a-f]*: eb a0 30 00 stc\.d cp1,r0\[0x0\],cr0
17970 + *[0-9a-f]*: ef a8 26 70 stc\.d cp1,r8\+\+,cr6
17971 + *[0-9a-f]*: ef a7 28 70 stc\.d cp1,r7\+\+,cr8
17972 + *[0-9a-f]*: ef aa 32 e5 stc\.d cp1,r10\[r5<<0x2\],cr2
17973 + *[0-9a-f]*: ef a3 3c c6 stc\.d cp1,r3\[r6\],cr12
17975 +[0-9a-f]* <picost_w>:
17976 + *[0-9a-f]*: eb af 2f ff stc\.w cp1,pc\[0x3fc\],cr15
17977 + *[0-9a-f]*: eb a0 20 00 stc\.w cp1,r0\[0x0\],cr0
17978 + *[0-9a-f]*: ef a8 27 60 stc\.w cp1,r8\+\+,cr7
17979 + *[0-9a-f]*: ef a7 28 60 stc\.w cp1,r7\+\+,cr8
17980 + *[0-9a-f]*: ef aa 31 a5 stc\.w cp1,r10\[r5<<0x2\],cr1
17981 + *[0-9a-f]*: ef a3 3d 86 stc\.w cp1,r3\[r6\],cr13
17983 +[0-9a-f]* <picostm_d>:
17984 + *[0-9a-f]*: ed af 25 ff stcm\.d cp1,pc,cr0-cr15
17985 + *[0-9a-f]*: ed a0 25 01 stcm\.d cp1,r0,cr0-cr1
17986 + *[0-9a-f]*: ed a7 25 80 stcm\.d cp1,r7,cr14-cr15
17987 + *[0-9a-f]*: ed a8 25 7f stcm\.d cp1,r8,cr0-cr13
17989 +[0-9a-f]* <picostm_d_pu>:
17990 + *[0-9a-f]*: ed af 35 ff stcm\.d cp1,--pc,cr0-cr15
17991 + *[0-9a-f]*: ed a0 35 01 stcm\.d cp1,--r0,cr0-cr1
17992 + *[0-9a-f]*: ed a7 35 80 stcm\.d cp1,--r7,cr14-cr15
17993 + *[0-9a-f]*: ed a8 35 7f stcm\.d cp1,--r8,cr0-cr13
17995 +[0-9a-f]* <picostm_w>:
17996 + *[0-9a-f]*: ed af 22 ff stcm\.w cp1,pc,cr0-cr7
17997 + *[0-9a-f]*: ed a0 22 01 stcm\.w cp1,r0,cr0
17998 + *[0-9a-f]*: ed a7 22 80 stcm\.w cp1,r7,cr7
17999 + *[0-9a-f]*: ed a8 22 7f stcm\.w cp1,r8,cr0-cr6
18000 + *[0-9a-f]*: ed af 23 ff stcm\.w cp1,pc,cr8-cr15
18001 + *[0-9a-f]*: ed a0 23 01 stcm\.w cp1,r0,cr8
18002 + *[0-9a-f]*: ed a7 23 80 stcm\.w cp1,r7,cr15
18003 + *[0-9a-f]*: ed a8 23 7f stcm\.w cp1,r8,cr8-cr14
18005 +[0-9a-f]* <picostm_w_pu>:
18006 + *[0-9a-f]*: ed af 32 ff stcm\.w cp1,--pc,cr0-cr7
18007 + *[0-9a-f]*: ed a0 32 01 stcm\.w cp1,--r0,cr0
18008 + *[0-9a-f]*: ed a7 32 80 stcm\.w cp1,--r7,cr7
18009 + *[0-9a-f]*: ed a8 32 7f stcm\.w cp1,--r8,cr0-cr6
18010 + *[0-9a-f]*: ed af 33 ff stcm\.w cp1,--pc,cr8-cr15
18011 + *[0-9a-f]*: ed a0 33 01 stcm\.w cp1,--r0,cr8
18012 + *[0-9a-f]*: ed a7 33 80 stcm\.w cp1,--r7,cr15
18013 + *[0-9a-f]*: ed a8 33 7f stcm\.w cp1,--r8,cr8-cr14
18015 +++ b/gas/testsuite/gas/avr32/pico.s
18019 + .global picosvmac
18021 + picosvmac out0, in0, in0, in0
18022 + picosvmac out2, in11, in11, in11
18023 + picosvmac out1, in10, in0, in5
18024 + picosvmac out3, in6, in9, in0
18025 + .global picosvmul
18027 + picosvmul out0, in0, in0, in0
18028 + picosvmul out2, in11, in11, in11
18029 + picosvmul out1, in10, in0, in5
18030 + picosvmul out3, in6, in9, in0
18033 + picovmac out0, in0, in0, in0
18034 + picovmac out2, in11, in11, in11
18035 + picovmac out1, in10, in0, in5
18036 + picovmac out3, in6, in9, in0
18039 + picovmul out0, in0, in0, in0
18040 + picovmul out2, in11, in11, in11
18041 + picovmul out1, in10, in0, in5
18042 + picovmul out3, in6, in9, in0
18045 + picold.d vmu2_out, pc[1020]
18046 + picold.d inpix2, r0[1020]
18047 + picold.d inpix2, r0[0]
18048 + picold.d coeff0_a, --r8
18049 + picold.d coeff1_a, --r7
18050 + picold.d inpix0, r10[r5 << 2]
18051 + picold.d vmu0_out, r3[r6 << 0]
18054 + picold.w config, pc[1020]
18055 + picold.w inpix2, r0[1020]
18056 + picold.w inpix2, r0[0]
18057 + picold.w coeff0_b, --r8
18058 + picold.w coeff1_a, --r7
18059 + picold.w inpix1, r10[r5 << 2]
18060 + picold.w vmu1_out, r3[r6 << 0]
18061 + .global picoldm_d
18063 + picoldm.d pc, inpix2-config
18064 + picoldm.d r0, inpix2, inpix1
18065 + picoldm.d r7, vmu2_out, config
18066 + picoldm.d r8, inpix2-vmu1_out
18067 + .global picoldm_d_pu
18069 + picoldm.d pc++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18070 + picoldm.d r0++, inpix2, inpix1
18071 + picoldm.d r7++, vmu2_out, config
18072 + picoldm.d r8++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18073 + .global picoldm_w
18075 + picoldm.w pc, inpix2-coeff0_b
18076 + picoldm.w r0, inpix2
18077 + picoldm.w r7, coeff0_b
18078 + picoldm.w r8, inpix2-coeff0_a
18079 + picoldm.w pc, coeff1_a-config
18080 + picoldm.w r0, coeff1_a
18081 + picoldm.w r7, config
18082 + picoldm.w r8, coeff1_a-vmu2_out
18083 + .global picoldm_w_pu
18085 + picoldm.w pc++, inpix2-coeff0_b
18086 + picoldm.w r0++, inpix2
18087 + picoldm.w r7++, coeff0_b
18088 + picoldm.w r8++, inpix2-coeff0_a
18089 + picoldm.w pc++, coeff1_a-config
18090 + picoldm.w r0++, coeff1_a
18091 + picoldm.w r7++, config
18092 + picoldm.w r8++, coeff1_a-vmu2_out
18095 + picomv.d vmu2_out, lr
18096 + picomv.d inpix2, r0
18097 + picomv.d coeff0_a, r8
18098 + picomv.d coeff1_a, r6
18099 + picomv.d pc, vmu2_out
18100 + picomv.d r0, inpix2
18101 + picomv.d r8, coeff0_a
18102 + picomv.d r6, coeff1_a
18105 + picomv.w config, pc
18106 + picomv.w inpix2, r0
18107 + picomv.w coeff0_b, r8
18108 + picomv.w coeff1_a, r7
18109 + picomv.w pc, config
18110 + picomv.w r0, inpix2
18111 + picomv.w r8, coeff0_b
18112 + picomv.w r7, coeff1_a
18115 + picost.d pc[1020], vmu2_out
18116 + picost.d r0[0], inpix2
18117 + picost.d r8++, coeff0_a
18118 + picost.d r7++, coeff1_a
18119 + picost.d r10[r5 << 2], inpix0
18120 + picost.d r3[r6 << 0], vmu0_out
18123 + picost.w pc[1020], config
18124 + picost.w r0[0], inpix2
18125 + picost.w r8++, coeff0_b
18126 + picost.w r7++, coeff1_a
18127 + picost.w r10[r5 << 2], inpix1
18128 + picost.w r3[r6 << 0], vmu1_out
18129 + .global picostm_d
18131 + picostm.d pc, inpix2-config
18132 + picostm.d r0, inpix2, inpix1
18133 + picostm.d r7, vmu2_out, config
18134 + picostm.d r8, inpix2-vmu1_out
18135 + .global picostm_d_pu
18137 + picostm.d --pc, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18138 + picostm.d --r0, inpix2, inpix1
18139 + picostm.d --r7, vmu2_out, config
18140 + picostm.d --r8, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18141 + .global picostm_w
18143 + picostm.w pc, inpix2-coeff0_b
18144 + picostm.w r0, inpix2
18145 + picostm.w r7, coeff0_b
18146 + picostm.w r8, inpix2-coeff0_a
18147 + picostm.w pc, coeff1_a-config
18148 + picostm.w r0, coeff1_a
18149 + picostm.w r7, config
18150 + picostm.w r8, coeff1_a-vmu2_out
18151 + .global picostm_w_pu
18153 + picostm.w --pc, inpix2-coeff0_b
18154 + picostm.w --r0, inpix2
18155 + picostm.w --r7, coeff0_b
18156 + picostm.w --r8, inpix2-coeff0_a
18157 + picostm.w --pc, coeff1_a-config
18158 + picostm.w --r0, coeff1_a
18159 + picostm.w --r7, config
18160 + picostm.w --r8, coeff1_a-vmu2_out
18162 +++ b/gas/testsuite/gas/avr32/pic_reloc.d
18168 +.*: +file format .*
18170 +Disassembly of section \.text:
18172 +00000000 <mcall_got>:
18173 + 0: f0 16 00 00 mcall r6\[0\]
18174 + 0: R_AVR32_GOT18SW extfunc
18175 + 4: f0 16 00 00 mcall r6\[0\]
18176 + 4: R_AVR32_GOT18SW \.L1
18177 + 8: f0 16 00 00 mcall r6\[0\]
18178 + 8: R_AVR32_GOT18SW \.L2
18179 + c: f0 16 00 00 mcall r6\[0\]
18180 + c: R_AVR32_GOT18SW mcall_got
18182 +00000010 <ldw_got>:
18183 + 10: ec f0 00 00 ld.w r0,r6\[0\]
18184 + 10: R_AVR32_GOT16S extvar
18185 + 14: ec f0 00 00 ld.w r0,r6\[0\]
18186 + 14: R_AVR32_GOT16S \.L3
18187 + 18: ec f0 00 00 ld.w r0,r6\[0\]
18188 + 18: R_AVR32_GOT16S \.L4
18189 + 1c: ec f0 00 00 ld.w r0,r6\[0\]
18190 + 1c: R_AVR32_GOT16S ldw_got
18192 +++ b/gas/testsuite/gas/avr32/pic_reloc.s
18196 + .global mcall_got
18199 + mcall r6[extfunc@got]
18200 + mcall r6[.L1@got]
18201 + mcall r6[.L2@got]
18202 + mcall r6[mcall_got@got]
18207 +.L3: ld.w r0,r6[extvar@got]
18208 + ld.w r0,r6[.L3@got]
18209 + ld.w r0,r6[.L4@got]
18210 + ld.w r0,r6[ldw_got@got]
18213 +++ b/gas/testsuite/gas/avr32/symdiff.d
18215 +#source: symdiff.s
18220 +.*: +file format .*
18222 +Disassembly of section \.text:
18224 +00000000 <diff32>:
18225 + 0: 00 00 add r0,r0
18226 + 2: 00 04 add r4,r0
18228 +00000004 <diff16>:
18229 + 4: 00 04 add r4,r0
18232 + 6: 04 00 add r0,r2
18234 +00000008 <symdiff_test>:
18240 +++ b/gas/testsuite/gas/avr32/symdiff_linkrelax.d
18242 +#source: symdiff.s
18245 +#name: symdiff_linkrelax
18247 +.*: +file format .*
18249 +Disassembly of section \.text:
18251 +00000000 <diff32>:
18252 + 0: 00 00 add r0,r0
18253 + 0: R_AVR32_DIFF32 \.text\+0xa
18254 + 2: 00 04 add r4,r0
18256 +00000004 <diff16>:
18257 + 4: 00 04 add r4,r0
18258 + 4: R_AVR32_DIFF16 \.text\+0xa
18261 + 6: 04 00 add r0,r2
18262 + 6: R_AVR32_DIFF8 \.text\+0xa
18263 + 7: R_AVR32_ALIGN \*ABS\*\+0x1
18265 +00000008 <symdiff_test>:
18271 +++ b/gas/testsuite/gas/avr32/symdiff.s
18285 + .global symdiff_test
18294 @@ -2221,6 +2221,10 @@ relax_frag (segT segment, fragS *fragP,
18296 #endif /* defined (TC_GENERIC_RELAX_TABLE) */
18298 +#ifdef TC_RELAX_ALIGN
18299 +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR)
18301 +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset)
18302 /* Relax_align. Advance location counter to next address that has 'alignment'
18303 lowest order bits all 0s, return size of adjustment made. */
18304 static relax_addressT
18305 @@ -2240,6 +2244,7 @@ relax_align (register relax_addressT add
18307 return (new_address - address);
18311 /* Now we have a segment, not a crowd of sub-segments, we can make
18313 @@ -2286,7 +2291,7 @@ relax_segment (struct frag *segment_frag
18314 case rs_align_code:
18315 case rs_align_test:
18317 - addressT offset = relax_align (address, (int) fragP->fr_offset);
18318 + addressT offset = RELAX_ALIGN(segment, fragP, address);
18320 if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
18322 @@ -2497,10 +2502,10 @@ relax_segment (struct frag *segment_frag
18324 addressT oldoff, newoff;
18326 - oldoff = relax_align (was_address + fragP->fr_fix,
18328 - newoff = relax_align (address + fragP->fr_fix,
18330 + oldoff = RELAX_ALIGN (segment, fragP,
18331 + was_address + fragP->fr_fix);
18332 + newoff = RELAX_ALIGN (segment, fragP,
18333 + address + fragP->fr_fix);
18335 if (fragP->fr_subtype != 0)
18337 --- a/include/dis-asm.h
18338 +++ b/include/dis-asm.h
18339 @@ -222,6 +222,7 @@ typedef int (*disassembler_ftype) (bfd_v
18341 extern int print_insn_alpha (bfd_vma, disassemble_info *);
18342 extern int print_insn_avr (bfd_vma, disassemble_info *);
18343 +extern int print_insn_avr32 (bfd_vma, disassemble_info *);
18344 extern int print_insn_bfin (bfd_vma, disassemble_info *);
18345 extern int print_insn_big_arm (bfd_vma, disassemble_info *);
18346 extern int print_insn_big_mips (bfd_vma, disassemble_info *);
18347 @@ -304,7 +305,9 @@ extern void print_i386_disassembler_opti
18348 extern void print_mips_disassembler_options (FILE *);
18349 extern void print_ppc_disassembler_options (FILE *);
18350 extern void print_arm_disassembler_options (FILE *);
18351 +extern void print_avr32_disassembler_options (FILE *);
18352 extern void parse_arm_disassembler_option (char *);
18353 +extern void parse_avr32_disassembler_option (char *);
18354 extern void print_s390_disassembler_options (FILE *);
18355 extern int get_arm_regname_num_options (void);
18356 extern int set_arm_regname_option (int);
18358 +++ b/include/elf/avr32.h
18360 +/* AVR32 ELF support for BFD.
18361 + Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
18363 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
18365 + This file is part of BFD, the Binary File Descriptor library.
18367 + This program is free software; you can redistribute it and/or
18368 + modify it under the terms of the GNU General Public License as
18369 + published by the Free Software Foundation; either version 2 of the
18370 + License, or (at your option) any later version.
18372 + This program is distributed in the hope that it will be useful, but
18373 + WITHOUT ANY WARRANTY; without even the implied warranty of
18374 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18375 + General Public License for more details.
18377 + You should have received a copy of the GNU General Public License
18378 + along with this program; if not, write to the Free Software
18379 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
18380 + 02111-1307, USA. */
18382 +#include "elf/reloc-macros.h"
18384 +/* CPU-specific flags for the ELF header e_flags field */
18385 +#define EF_AVR32_LINKRELAX 0x01
18386 +#define EF_AVR32_PIC 0x02
18388 +START_RELOC_NUMBERS (elf_avr32_reloc_type)
18389 + RELOC_NUMBER (R_AVR32_NONE, 0)
18391 + /* Data Relocations */
18392 + RELOC_NUMBER (R_AVR32_32, 1)
18393 + RELOC_NUMBER (R_AVR32_16, 2)
18394 + RELOC_NUMBER (R_AVR32_8, 3)
18395 + RELOC_NUMBER (R_AVR32_32_PCREL, 4)
18396 + RELOC_NUMBER (R_AVR32_16_PCREL, 5)
18397 + RELOC_NUMBER (R_AVR32_8_PCREL, 6)
18398 + RELOC_NUMBER (R_AVR32_DIFF32, 7)
18399 + RELOC_NUMBER (R_AVR32_DIFF16, 8)
18400 + RELOC_NUMBER (R_AVR32_DIFF8, 9)
18401 + RELOC_NUMBER (R_AVR32_GOT32, 10)
18402 + RELOC_NUMBER (R_AVR32_GOT16, 11)
18403 + RELOC_NUMBER (R_AVR32_GOT8, 12)
18405 + /* Normal Code Relocations */
18406 + RELOC_NUMBER (R_AVR32_21S, 13)
18407 + RELOC_NUMBER (R_AVR32_16U, 14)
18408 + RELOC_NUMBER (R_AVR32_16S, 15)
18409 + RELOC_NUMBER (R_AVR32_8S, 16)
18410 + RELOC_NUMBER (R_AVR32_8S_EXT, 17)
18412 + /* PC-Relative Code Relocations */
18413 + RELOC_NUMBER (R_AVR32_22H_PCREL, 18)
18414 + RELOC_NUMBER (R_AVR32_18W_PCREL, 19)
18415 + RELOC_NUMBER (R_AVR32_16B_PCREL, 20)
18416 + RELOC_NUMBER (R_AVR32_16N_PCREL, 21)
18417 + RELOC_NUMBER (R_AVR32_14UW_PCREL, 22)
18418 + RELOC_NUMBER (R_AVR32_11H_PCREL, 23)
18419 + RELOC_NUMBER (R_AVR32_10UW_PCREL, 24)
18420 + RELOC_NUMBER (R_AVR32_9H_PCREL, 25)
18421 + RELOC_NUMBER (R_AVR32_9UW_PCREL, 26)
18423 + /* Special Code Relocations */
18424 + RELOC_NUMBER (R_AVR32_HI16, 27)
18425 + RELOC_NUMBER (R_AVR32_LO16, 28)
18427 + /* PIC Relocations */
18428 + RELOC_NUMBER (R_AVR32_GOTPC, 29)
18429 + RELOC_NUMBER (R_AVR32_GOTCALL, 30)
18430 + RELOC_NUMBER (R_AVR32_LDA_GOT, 31)
18431 + RELOC_NUMBER (R_AVR32_GOT21S, 32)
18432 + RELOC_NUMBER (R_AVR32_GOT18SW, 33)
18433 + RELOC_NUMBER (R_AVR32_GOT16S, 34)
18434 + RELOC_NUMBER (R_AVR32_GOT7UW, 35)
18436 + /* Constant Pool Relocations */
18437 + RELOC_NUMBER (R_AVR32_32_CPENT, 36)
18438 + RELOC_NUMBER (R_AVR32_CPCALL, 37)
18439 + RELOC_NUMBER (R_AVR32_16_CP, 38)
18440 + RELOC_NUMBER (R_AVR32_9W_CP, 39)
18442 + /* Dynamic Relocations */
18443 + RELOC_NUMBER (R_AVR32_RELATIVE, 40)
18444 + RELOC_NUMBER (R_AVR32_GLOB_DAT, 41)
18445 + RELOC_NUMBER (R_AVR32_JMP_SLOT, 42)
18447 + /* Linkrelax Information */
18448 + RELOC_NUMBER (R_AVR32_ALIGN, 43)
18450 + RELOC_NUMBER (R_AVR32_15S, 44)
18452 +END_RELOC_NUMBERS (R_AVR32_max)
18454 +/* Processor specific dynamic array tags. */
18456 +/* The total size in bytes of the Global Offset Table */
18457 +#define DT_AVR32_GOTSZ 0x70000001
18458 --- a/include/elf/common.h
18459 +++ b/include/elf/common.h
18460 @@ -289,7 +289,7 @@
18461 #define EM_INTEL182 182 /* Reserved by Intel */
18462 #define EM_res183 183 /* Reserved by ARM */
18463 #define EM_res184 184 /* Reserved by ARM */
18464 -#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */
18465 +#define EM_AVR32_OLD 185 /* Atmel Corporation 32-bit microprocessor family */
18466 #define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */
18467 #define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
18468 #define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */
18469 @@ -369,6 +369,9 @@
18470 /* V850 backend magic number. Written in the absense of an ABI. */
18471 #define EM_CYGNUS_V850 0x9080
18473 +/* AVR32 magic number, picked by IAR Systems. */
18474 +#define EM_AVR32 0x18ad
18476 /* old S/390 backend magic number. Written in the absence of an ABI. */
18477 #define EM_S390_OLD 0xa390
18479 --- a/ld/configdoc.texi
18480 +++ b/ld/configdoc.texi
18489 --- a/ld/configure.tgt
18490 +++ b/ld/configure.tgt
18491 @@ -113,6 +113,9 @@ xscale-*-elf) targ_emul=armelf
18492 avr-*-*) targ_emul=avr2
18493 targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
18495 +avr32-*-none) targ_emul=avr32elf_ap7000
18496 + targ_extra_emuls="avr32elf_ap7001 avr32elf_ap7002 avr32elf_ap7200 avr32elf_uc3a0128 avr32elf_uc3a0256 avr32elf_uc3a0512 avr32elf_uc3a0512es avr32elf_uc3a1128 avr32elf_uc3a1256 avr32elf_uc3a1512es avr32elf_uc3a1512 avr32elf_uc3a364 avr32elf_uc3a364s avr32elf_uc3a3128 avr32elf_uc3a3128s avr32elf_uc3a3256 avr32elf_uc3a3256s avr32elf_uc3b064 avr32elf_uc3b0128 avr32elf_uc3b0256es avr32elf_uc3b0256 avr32elf_uc3b0512 avr32elf_uc3b0512revc avr32elf_uc3b164 avr32elf_uc3b1128 avr32elf_uc3b1256es avr32elf_uc3b1256 avr32elf_uc3b1512 avr32elf_uc3b1512revc avr32elf_uc3c0512crevc avr32elf_uc3c1512crevc avr32elf_uc3c2512crevc avr32elf_atuc3l0256 avr32elf_mxt768e avr32elf_uc3l064 avr32elf_uc3l032 avr32elf_uc3l016 avr32elf_uc3l064revb avr32elf_uc3c064c avr32elf_uc3c0128c avr32elf_uc3c0256c avr32elf_uc3c0512c avr32elf_uc3c164c avr32elf_uc3c1128c avr32elf_uc3c1256c avr32elf_uc3c1512c avr32elf_uc3c264c avr32elf_uc3c2128c avr32elf_uc3c2256c avr32elf_uc3c2512c" ;;
18497 +avr32-*-linux*) targ_emul=avr32linux ;;
18498 bfin-*-elf) targ_emul=elf32bfin;
18499 targ_extra_emuls="elf32bfinfd"
18500 targ_extra_libpath=$targ_extra_emuls
18502 +++ b/ld/emulparams/avr32elf.sh
18504 +# This script is called from ld/genscript.sh
18505 +# There is a difference on how 'bash' and POSIX handles
18506 +# the '.' (source) command in a script.
18507 +# genscript.sh calls this script with argument ${EMULATION_NAME}
18508 +# but that will fail on POSIX compilant shells like 'sh' or 'dash'
18509 +# therefor I use the variable directly instead of $1
18510 +EMULATION=${EMULATION_NAME}
18512 +TEMPLATE_NAME=elf32
18513 +EXTRA_EM_FILE=avr32elf
18514 +OUTPUT_FORMAT="elf32-avr32"
18522 +DATA_SEGMENT_ALIGN=8
18525 +RO_LMA_REGION="FLASH"
18526 +RO_VMA_REGION="FLASH"
18527 +RW_LMA_REGION="FLASH"
18528 +RW_VMA_REGION="CPUSRAM"
18530 +STACK_SIZE=_stack_size
18531 +STACK_ADDR="ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - ${STACK_SIZE}"
18533 +DATA_SEGMENT_END="
18534 + __heap_start__ = ALIGN(8);
18535 + . = ${STACK_ADDR};
18536 + __heap_end__ = .;
18539 +case "$EMULATION" in
18542 + INITIAL_READONLY_SECTIONS="
18543 + .reset : { *(.reset) } >FLASH AT>FLASH
18544 + . = . & 0x9fffffff;
18546 + TEXT_START_ADDR=0xa0000000
18547 + case "$EMULATION" in
18548 + avr32elf_ap700[0-2])
18552 + FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18553 + CPUSRAM (rwxa) : ORIGIN = 0x24000000, LENGTH = 32K
18561 + FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18562 + CPUSRAM (rwxa) : ORIGIN = 0x08000000, LENGTH = 64K
18571 + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
18572 + TEXT_START_ADDR=0x80000000
18574 + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
18575 + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
18580 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18581 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18582 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18583 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18584 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18585 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18588 + OTHER_SECTIONS="${OTHER_SECTIONS}
18589 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18590 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18596 + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
18597 + TEXT_START_ADDR=0x80000000
18599 + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
18600 + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
18602 + case "$EMULATION" in
18603 + avr32elf_atuc3l0256)
18607 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18608 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18609 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18610 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18611 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18612 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18615 + OTHER_SECTIONS="${OTHER_SECTIONS}
18616 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18617 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18625 + INITIAL_READONLY_SECTIONS=".reset : { *(.reset) } >FLASH AT>FLASH"
18626 + TEXT_START_ADDR=0x80000000
18628 + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
18629 + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
18632 + case "$EMULATION" in
18633 + avr32elf_uc3c[012]512c)
18637 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18638 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18639 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18640 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18641 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18642 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18645 + OTHER_SECTIONS="${OTHER_SECTIONS}
18646 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18647 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18651 + avr32elf_uc3c[012]256c)
18655 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18656 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18657 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18658 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18659 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18660 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18663 + OTHER_SECTIONS="${OTHER_SECTIONS}
18664 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18665 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18669 + avr32elf_uc3c[012]128c)
18673 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18674 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18675 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18676 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18677 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18678 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18681 + OTHER_SECTIONS="${OTHER_SECTIONS}
18682 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18683 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18687 + avr32elf_uc3c[012]64c)
18691 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18692 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18693 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18694 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18695 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18696 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18699 + OTHER_SECTIONS="${OTHER_SECTIONS}
18700 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18701 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18705 + avr32elf_uc3[ac][012]512*)
18709 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18710 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18711 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18712 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18717 + avr32elf_uc3a[012]256*)
18721 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18722 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18723 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18724 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18729 + avr32elf_uc3b[01]512revc)
18733 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18734 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18735 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18736 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18745 + } >FLASH AT>FLASH
18749 + avr32elf_uc3b[01]512)
18753 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18754 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18755 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18756 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18761 + avr32elf_uc3b[01]256*)
18765 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18766 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18767 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18768 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18773 + avr32elf_uc3[ab][012]128*)
18777 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18778 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18779 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18780 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18785 + avr32elf_uc3b[0123]64*)
18789 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18790 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18791 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18792 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18797 + avr32elf_uc3a3256*)
18801 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18802 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18803 + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18804 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18805 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18808 + OTHER_SECTIONS="${OTHER_SECTIONS}
18809 + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18814 + avr32elf_uc3a3128*)
18818 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18819 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18820 + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18821 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18822 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18825 + OTHER_SECTIONS="${OTHER_SECTIONS}
18826 + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18830 + avr32elf_uc3a364*)
18834 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18835 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18836 + HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18837 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18838 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18841 + OTHER_SECTIONS="${OTHER_SECTIONS}
18842 + .hsbsram : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18847 + avr32elf_uc3l[0123]64*)
18851 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18852 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18853 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18854 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18855 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18856 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18859 + OTHER_SECTIONS="${OTHER_SECTIONS}
18860 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18861 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18865 + avr32elf_uc3l[0123]32*)
18869 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 32K
18870 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18871 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18872 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18873 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18874 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18877 + OTHER_SECTIONS="${OTHER_SECTIONS}
18878 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18879 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18883 + avr32elf_uc3l[0123]16*)
18887 + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K
18888 + CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x1FFC
18889 + USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18890 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18891 + FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18892 + FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18895 + OTHER_SECTIONS="${OTHER_SECTIONS}
18896 + .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18897 + .flashvault_ram_size : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18907 +++ b/ld/emulparams/avr32linux.sh
18911 +TEMPLATE_NAME=elf32
18912 +EXTRA_EM_FILE=avr32elf
18913 +OUTPUT_FORMAT="elf32-avr32"
18914 +GENERATE_SHLIB_SCRIPT=yes
18915 +MAXPAGESIZE=0x1000
18916 +TEXT_START_ADDR=0x00001000
18919 +# This appears to place the GOT before the data section, which is
18920 +# essential for uClinux. We don't use those .s* sections on AVR32
18921 +# anyway, so it shouldn't hurt for regular Linux either...
18924 +++ b/ld/emultempl/avr32elf.em
18926 +# This shell script emits a C file. -*- C -*-
18927 +# Copyright (C) 2007,2008,2009 Atmel Corporation
18929 +# This file is part of GLD, the Gnu Linker.
18931 +# This program is free software; you can redistribute it and/or modify
18932 +# it under the terms of the GNU General Public License as published by
18933 +# the Free Software Foundation; either version 2 of the License, or
18934 +# (at your option) any later version.
18936 +# This program is distributed in the hope that it will be useful,
18937 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
18938 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18939 +# GNU General Public License for more details.
18941 +# You should have received a copy of the GNU General Public License
18942 +# along with this program; if not, write to the Free Software
18943 +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
18946 +# This file is sourced from elf32.em, and defines extra avr32-elf
18947 +# specific routines.
18950 +# Generate linker script for writable rodata
18951 +LD_FLAG=rodata-writable
18952 +DATA_ALIGNMENT=${DATA_ALIGNMENT_}
18954 +WRITABLE_RODATA=" "
18955 +( echo "/* Linker script for writable rodata */"
18956 + . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME}
18957 + . ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
18958 +) | sed -e '/^ *$/d;s/[ ]*$//' > ldscripts/${EMULATION_NAME}.xwr
18961 +cat >> e${EMULATION_NAME}.c <<EOF
18963 +#include "libbfd.h"
18964 +#include "elf32-avr32.h"
18966 +/* Whether to allow direct references (sub or mov) to SEC_DATA and
18967 + !SEC_CONTENTS sections when optimizing. Not enabled by default
18968 + since it might cause link errors. */
18969 +static int direct_data_refs = 0;
18971 +static void avr32_elf_after_open (void)
18973 + bfd_elf32_avr32_set_options (&link_info, direct_data_refs);
18974 + gld${EMULATION_NAME}_after_open ();
18977 +static int rodata_writable = 0;
18979 +static int stack_size = 0x1000;
18981 +static void avr32_elf_set_symbols (void)
18983 + /* Glue the assignments into the abs section. */
18984 + lang_statement_list_type *save = stat_ptr;
18987 + stat_ptr = &(abs_output_section->children);
18989 + lang_add_assignment (exp_assop ('=', "_stack_size",
18990 + exp_intop (stack_size)));
18995 +static char * gld${EMULATION_NAME}_get_script (int *isfile);
18997 +static char * avr32_elf_get_script (int *isfile)
18999 + if ( rodata_writable )
19002 +if test -n "$COMPILE_IN"
19004 +# Scripts compiled in.
19006 +# sed commands to quote an ld script as a C string.
19007 +sc="-f stringify.sed"
19009 +cat >>e${EMULATION_NAME}.c <<EOF
19013 +sed $sc ldscripts/${EMULATION_NAME}.xwr >> e${EMULATION_NAME}.c
19014 +echo ';' >> e${EMULATION_NAME}.c
19016 +# Scripts read from the filesystem.
19018 +cat >>e${EMULATION_NAME}.c <<EOF
19020 + return "ldscripts/${EMULATION_NAME}.xwr";
19024 +cat >>e${EMULATION_NAME}.c <<EOF
19026 + return gld${EMULATION_NAME}_get_script (isfile);
19032 +# Define some shell vars to insert bits of code into the standard elf
19033 +# parse_args and list_options functions.
19035 +PARSE_AND_LIST_PROLOGUE='
19036 +#define OPTION_DIRECT_DATA 300
19037 +#define OPTION_NO_DIRECT_DATA 301
19038 +#define OPTION_RODATA_WRITABLE 302
19039 +#define OPTION_NO_RODATA_WRITABLE 303
19040 +#define OPTION_STACK 304
19043 +PARSE_AND_LIST_LONGOPTS='
19044 + { "direct-data", no_argument, NULL, OPTION_DIRECT_DATA },
19045 + { "no-direct-data", no_argument, NULL, OPTION_NO_DIRECT_DATA },
19046 + { "rodata-writable", no_argument, NULL, OPTION_RODATA_WRITABLE },
19047 + { "no-rodata-writable", no_argument, NULL, OPTION_NO_RODATA_WRITABLE },
19048 + { "stack", required_argument, NULL, OPTION_STACK },
19051 +PARSE_AND_LIST_OPTIONS='
19052 + fprintf (file, _(" --direct-data\t\tAllow direct data references when optimizing\n"));
19053 + fprintf (file, _(" --no-direct-data\tDo not allow direct data references when optimizing\n"));
19054 + fprintf (file, _(" --rodata-writable\tPut read-only data in writable data section\n"));
19055 + fprintf (file, _(" --no-rodata-writable\tDo not put read-only data in writable data section\n"));
19056 + fprintf (file, _(" --stack <size>\tSet the initial size of the stack\n"));
19059 +PARSE_AND_LIST_ARGS_CASES='
19060 + case OPTION_DIRECT_DATA:
19061 + direct_data_refs = 1;
19063 + case OPTION_NO_DIRECT_DATA:
19064 + direct_data_refs = 0;
19066 + case OPTION_RODATA_WRITABLE:
19067 + rodata_writable = 1;
19069 + case OPTION_NO_RODATA_WRITABLE:
19070 + rodata_writable = 0;
19072 + case OPTION_STACK:
19075 + stack_size = strtoul (optarg, &end, 0);
19076 + if (end == optarg)
19077 + einfo (_("%P%F: invalid hex number for parameter '%s'\n"), optarg);
19083 +# Replace some of the standard ELF functions with our own versions.
19085 +LDEMUL_AFTER_OPEN=avr32_elf_after_open
19086 +LDEMUL_GET_SCRIPT=avr32_elf_get_script
19087 +LDEMUL_SET_SYMBOLS=avr32_elf_set_symbols
19088 --- a/ld/Makefile.am
19089 +++ b/ld/Makefile.am
19090 @@ -162,6 +162,53 @@ ALL_EMULATION_SOURCES = \
19094 + eavr32elf_ap7000.c \
19095 + eavr32elf_ap7001.c \
19096 + eavr32elf_ap7002.c \
19097 + eavr32elf_ap7200.c \
19098 + eavr32elf_uc3a0128.c \
19099 + eavr32elf_uc3a0256.c \
19100 + eavr32elf_uc3a0512.c \
19101 + eavr32elf_uc3a0512es.c \
19102 + eavr32elf_uc3a1128.c \
19103 + eavr32elf_uc3a1256.c \
19104 + eavr32elf_uc3a1512es.c \
19105 + eavr32elf_uc3a1512.c \
19106 + eavr32elf_uc3a364.c \
19107 + eavr32elf_uc3a364s.c \
19108 + eavr32elf_uc3a3128.c \
19109 + eavr32elf_uc3a3128s.c \
19110 + eavr32elf_uc3a3256.c \
19111 + eavr32elf_uc3a3256s.c \
19112 + eavr32elf_uc3b064.c \
19113 + eavr32elf_uc3b0128.c \
19114 + eavr32elf_uc3b0256es.c \
19115 + eavr32elf_uc3b0256.c \
19116 + eavr32elf_uc3b0512.c \
19117 + eavr32elf_uc3b0512revc.c \
19118 + eavr32elf_uc3b164.c \
19119 + eavr32elf_uc3b1128.c \
19120 + eavr32elf_uc3b1256es.c \
19121 + eavr32elf_uc3b1256.c \
19122 + eavr32elf_uc3b1512.c \
19123 + eavr32elf_uc3b1512revc.c \
19124 + eavr32elf_uc3c064c.c \
19125 + eavr32elf_uc3c0128c.c \
19126 + eavr32elf_uc3c0256c.c \
19127 + eavr32elf_uc3c0512crevc.c \
19128 + eavr32elf_uc3c164c.c \
19129 + eavr32elf_uc3c1128c.c \
19130 + eavr32elf_uc3c1256c.c \
19131 + eavr32elf_uc3c1512crevc.c \
19132 + eavr32elf_uc3c264c.c \
19133 + eavr32elf_uc3c2128c.c \
19134 + eavr32elf_uc3c2256c.c \
19135 + eavr32elf_uc3c2512crevc.c \
19136 + eavr32elf_uc3l064.c \
19137 + eavr32elf_uc3l032.c \
19138 + eavr32elf_uc3l016.c \
19139 + eavr32elf_uc3l064revb.c \
19144 @@ -760,6 +807,214 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
19145 $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
19147 ${GENSCRIPTS} avr6 "$(tdir_avr2)"
19148 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
19149 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19150 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19151 + ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
19152 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
19153 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19154 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19155 + ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
19156 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
19157 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19158 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19159 + ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
19160 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
19161 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19162 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19163 + ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19164 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19165 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19166 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19167 + ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19168 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19169 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19170 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19171 + ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19172 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19173 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19174 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19175 + ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19176 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19177 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19178 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19179 + ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19180 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19181 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19182 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19183 + ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19184 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19185 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19186 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19187 + ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19188 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19189 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19190 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19191 + ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19192 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19193 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19194 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19195 + ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19196 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19197 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19198 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19199 + ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19200 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19201 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19202 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19203 + ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19204 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19205 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19206 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19207 + ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19208 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19209 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19210 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19211 + ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19212 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19213 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19214 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19215 + ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19216 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19217 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19218 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19219 + ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19220 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19221 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19222 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19223 + ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19224 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19225 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19226 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19227 + ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19228 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19229 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19230 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19231 + ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19232 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19233 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19234 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19235 + ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19236 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19237 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19238 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19239 + ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19240 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19241 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19242 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19243 + ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19244 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19245 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19246 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19247 + ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19248 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19249 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19250 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19251 + ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19252 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19253 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19254 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19255 + ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19256 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19257 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19258 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19259 + ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19260 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19261 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19262 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19263 + ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19264 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19265 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19266 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19267 + ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19268 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19269 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19270 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19271 + ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19272 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19273 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19274 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19275 + ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19276 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19277 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19278 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19279 + ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19280 +eavr32elf_atuc3l0256.c: $(srcdir)/emulparams/avr32elf.sh \
19281 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19282 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19283 + ${GENSCRIPTS} avr32elf_atuc3l0256 "$(tdir_avr32)" avr32elf
19284 +eavr32elf_mxt768e.c: $(srcdir)/emulparams/avr32elf.sh \
19285 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19286 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19287 + ${GENSCRIPTS} avr32elf_mxt768e "$(tdir_avr32)" avr32elf
19288 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19289 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19290 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19291 + ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19292 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19293 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19294 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19295 + ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19296 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19297 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19298 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19299 + ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19300 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19301 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19302 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19303 + ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19304 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19305 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19306 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19307 + ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19308 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19309 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19310 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19311 + ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19312 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19313 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19314 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19315 + ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19316 +eavr32elf_uc3c0512c.c: $(srcdir)/emulparams/avr32elf.sh \
19317 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19318 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19319 + ${GENSCRIPTS} avr32elf_uc3c0512c "$(tdir_avr32)" avr32elf
19320 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19321 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19322 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19323 + ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19324 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19325 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19326 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19327 + ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19328 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19329 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19330 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19331 + ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19332 +eavr32elf_uc3c1512c.c: $(srcdir)/emulparams/avr32elf.sh \
19333 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19334 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19335 + ${GENSCRIPTS} avr32elf_uc3c1512c "$(tdir_avr32)" avr32elf
19336 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19337 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19338 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19339 + ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19340 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19341 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19342 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19343 + ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19344 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19345 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19346 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19347 + ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19348 +eavr32elf_uc3c2512c.c: $(srcdir)/emulparams/avr32elf.sh \
19349 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19350 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19351 + ${GENSCRIPTS} avr32elf_uc3c2512c "$(tdir_avr32)" avr32elf
19352 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19353 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19354 + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19355 + ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19356 ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19357 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19358 ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19359 @@ -2052,7 +2307,9 @@ install-exec-local: ld-new$(EXEEXT) inst
19363 -install-data-local:
19364 +# We want install to imply install-info as per GNU standards, despite the
19366 +install-data-local: install-info
19367 $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts
19368 for f in ldscripts/*; do \
19369 $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \
19370 --- a/ld/Makefile.in
19371 +++ b/ld/Makefile.in
19372 @@ -462,6 +462,53 @@ ALL_EMULATION_SOURCES = \
19376 + eavr32elf_ap7000.c \
19377 + eavr32elf_ap7001.c \
19378 + eavr32elf_ap7002.c \
19379 + eavr32elf_ap7200.c \
19380 + eavr32elf_uc3a0128.c \
19381 + eavr32elf_uc3a0256.c \
19382 + eavr32elf_uc3a0512.c \
19383 + eavr32elf_uc3a0512es.c \
19384 + eavr32elf_uc3a1128.c \
19385 + eavr32elf_uc3a1256.c \
19386 + eavr32elf_uc3a1512es.c \
19387 + eavr32elf_uc3a1512.c \
19388 + eavr32elf_uc3a364.c \
19389 + eavr32elf_uc3a364s.c \
19390 + eavr32elf_uc3a3128.c \
19391 + eavr32elf_uc3a3128s.c \
19392 + eavr32elf_uc3a3256.c \
19393 + eavr32elf_uc3a3256s.c \
19394 + eavr32elf_uc3b064.c \
19395 + eavr32elf_uc3b0128.c \
19396 + eavr32elf_uc3b0256es.c \
19397 + eavr32elf_uc3b0256.c \
19398 + eavr32elf_uc3b0512.c \
19399 + eavr32elf_uc3b0512revc.c \
19400 + eavr32elf_uc3b164.c \
19401 + eavr32elf_uc3b1128.c \
19402 + eavr32elf_uc3b1256es.c \
19403 + eavr32elf_uc3b1256.c \
19404 + eavr32elf_uc3b1512.c \
19405 + eavr32elf_uc3b1512revc.c \
19406 + eavr32elf_uc3c064c.c \
19407 + eavr32elf_uc3c0128c.c \
19408 + eavr32elf_uc3c0256c.c \
19409 + eavr32elf_uc3c0512crevc.c \
19410 + eavr32elf_uc3c164c.c \
19411 + eavr32elf_uc3c1128c.c \
19412 + eavr32elf_uc3c1256c.c \
19413 + eavr32elf_uc3c1512crevc.c \
19414 + eavr32elf_uc3c264c.c \
19415 + eavr32elf_uc3c2128c.c \
19416 + eavr32elf_uc3c2256c.c \
19417 + eavr32elf_uc3c2512crevc.c \
19418 + eavr32elf_uc3l064.c \
19419 + eavr32elf_uc3l032.c \
19420 + eavr32elf_uc3l016.c \
19421 + eavr32elf_uc3l064revb.c \
19426 @@ -2183,6 +2230,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
19427 $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
19429 ${GENSCRIPTS} avr6 "$(tdir_avr2)"
19430 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
19431 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19432 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19433 + ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
19434 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
19435 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19436 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19437 + ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
19438 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
19439 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19440 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19441 + ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
19442 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
19443 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19444 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19445 + ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19446 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19447 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19448 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19449 + ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19450 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19451 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19452 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19453 + ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19454 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19455 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19456 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19457 + ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19458 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19459 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19460 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19461 + ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19462 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19463 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19464 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19465 + ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19466 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19467 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19468 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19469 + ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19470 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19471 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19472 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19473 + ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19474 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19475 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19476 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19477 + ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19478 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19479 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19480 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19481 + ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19482 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19483 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19484 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19485 + ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19486 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19487 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19488 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19489 + ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19490 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19491 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19492 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19493 + ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19494 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19495 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19496 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19497 + ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19498 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19499 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19500 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19501 + ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19502 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19503 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19504 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19505 + ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19506 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19507 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19508 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19509 + ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19510 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19511 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19512 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19513 + ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19514 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19515 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19516 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19517 + ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19518 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19519 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19520 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19521 + ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19522 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19523 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19524 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19525 + ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19526 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19527 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19528 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19529 + ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19530 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19531 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19532 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19533 + ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19534 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19535 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19536 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19537 + ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19538 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19539 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19540 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19541 + ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19542 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19543 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19544 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19545 + ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19546 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19547 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19548 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19549 + ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19550 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19551 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19552 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19553 + ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19554 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19555 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19556 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19557 + ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19558 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19559 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19560 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19561 + ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19562 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19563 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19564 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19565 + ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19566 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19567 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19568 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19569 + ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19570 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19571 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19572 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19573 + ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19574 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19575 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19576 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19577 + ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19578 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19579 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19580 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19581 + ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19582 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19583 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19584 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19585 + ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19586 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19587 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19588 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19589 + ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19590 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19591 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19592 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19593 + ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19594 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19595 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19596 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19597 + ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19598 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19599 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19600 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19601 + ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19602 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19603 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19604 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19605 + ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19606 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19607 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19608 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19609 + ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19610 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19611 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19612 + $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19613 + ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19614 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19615 + $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19616 + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19617 + ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19618 ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19619 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19620 ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19622 +++ b/ld/scripttempl/avr32.sc
19625 +# Unusual variables checked by this code:
19626 +# NOP - four byte opcode for no-op (defaults to 0)
19627 +# NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
19629 +# SMALL_DATA_CTOR - .ctors contains small data.
19630 +# SMALL_DATA_DTOR - .dtors contains small data.
19631 +# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
19632 +# INITIAL_READONLY_SECTIONS - at start of text segment
19633 +# OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
19634 +# (e.g., .PARISC.milli)
19635 +# OTHER_TEXT_SECTIONS - these get put in .text when relocating
19636 +# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
19637 +# (e.g., .PARISC.global)
19638 +# OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
19639 +# (e.g. PPC32 .fixup, .got[12])
19640 +# OTHER_BSS_SECTIONS - other than .bss .sbss ...
19641 +# OTHER_SECTIONS - at the end
19642 +# EXECUTABLE_SYMBOLS - symbols that must be defined for an
19643 +# executable (e.g., _DYNAMIC_LINK)
19644 +# TEXT_START_ADDR - the first byte of the text segment, after any
19646 +# TEXT_BASE_ADDRESS - the first byte of the text segment.
19647 +# TEXT_START_SYMBOLS - symbols that appear at the start of the
19649 +# DATA_START_SYMBOLS - symbols that appear at the start of the
19651 +# OTHER_GOT_SYMBOLS - symbols defined just before .got.
19652 +# OTHER_GOT_SECTIONS - sections just after .got.
19653 +# OTHER_SDATA_SECTIONS - sections just after .sdata.
19654 +# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
19655 +# .bss section besides __bss_start.
19656 +# DATA_PLT - .plt should be in data segment, not text segment.
19657 +# PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
19658 +# BSS_PLT - .plt should be in bss segment
19659 +# TEXT_DYNAMIC - .dynamic in text segment, not data segment.
19660 +# EMBEDDED - whether this is for an embedded system.
19661 +# SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
19662 +# start address of shared library.
19663 +# INPUT_FILES - INPUT command of files to always include
19664 +# WRITABLE_RODATA - if set, the .rodata section should be writable
19665 +# INIT_START, INIT_END - statements just before and just after
19666 +# combination of .init sections.
19667 +# FINI_START, FINI_END - statements just before and just after
19668 +# combination of .fini sections.
19669 +# STACK_ADDR - start of a .stack section.
19670 +# OTHER_END_SYMBOLS - symbols to place right at the end of the script.
19671 +# SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
19672 +# so that .got can be in the RELRO area. It should be set to
19673 +# the number of bytes in the beginning of .got.plt which can be
19674 +# in the RELRO area as well.
19676 +# When adding sections, do note that the names of some sections are used
19677 +# when specifying the start address of the next.
19680 +# Many sections come in three flavours. There is the 'real' section,
19681 +# like ".data". Then there are the per-procedure or per-variable
19682 +# sections, generated by -ffunction-sections and -fdata-sections in GCC,
19683 +# and useful for --gc-sections, which for a variable "foo" might be
19684 +# ".data.foo". Then there are the linkonce sections, for which the linker
19685 +# eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
19686 +# The exact correspondences are:
19688 +# Section Linkonce section
19689 +# .text .gnu.linkonce.t.foo
19690 +# .rodata .gnu.linkonce.r.foo
19691 +# .data .gnu.linkonce.d.foo
19692 +# .bss .gnu.linkonce.b.foo
19693 +# .sdata .gnu.linkonce.s.foo
19694 +# .sbss .gnu.linkonce.sb.foo
19695 +# .sdata2 .gnu.linkonce.s2.foo
19696 +# .sbss2 .gnu.linkonce.sb2.foo
19697 +# .debug_info .gnu.linkonce.wi.foo
19698 +# .tdata .gnu.linkonce.td.foo
19699 +# .tbss .gnu.linkonce.tb.foo
19701 +# Each of these can also have corresponding .rel.* and .rela.* sections.
19703 +test -z "$ENTRY" && ENTRY=_start
19704 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19705 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19706 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
19707 +test -z "${ELFSIZE}" && ELFSIZE=32
19708 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
19709 +test "$LD_FLAG" = "N" && DATA_ADDR=.
19710 +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
19711 +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
19712 +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
19713 +if test -n "$RELOCATING"; then
19714 + RO_REGION="${RO_VMA_REGION+ >}${RO_VMA_REGION}${RO_LMA_REGION+ AT>}${RO_LMA_REGION}"
19715 + RW_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}${RW_LMA_REGION+ AT>}${RW_LMA_REGION}"
19716 + RW_BSS_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}"
19722 +INTERP=".interp ${RELOCATING-0} : { *(.interp) }${RO_REGION}"
19723 +PLT=".plt ${RELOCATING-0} : { *(.plt) }"
19724 +if test -z "$GOT"; then
19725 + if test -z "$SEPARATE_GOTPLT"; then
19726 + GOT=".got ${RELOCATING-0} : { *(.got.plt) *(.got) }"
19728 + GOT=".got ${RELOCATING-0} : { *(.got) }"
19729 + GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
19730 + .got.plt ${RELOCATING-0} : { *(.got.plt) }"
19733 +DALIGN=".dalign : { . = ALIGN(${DATA_SEGMENT_ALIGN}); PROVIDE(_data_lma = .); }${RO_REGION}"
19734 +BALIGN=".balign : { . = ALIGN(${BSS_ALIGNMENT}); _edata = .; }${RW_REGION}"
19735 +DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) }"
19736 +RODATA=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
19737 +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }${RW_REGION}"
19738 +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
19739 +if test -z "${NO_SMALL_DATA}"; then
19740 + SBSS=".sbss ${RELOCATING-0} :
19742 + ${RELOCATING+PROVIDE (__sbss_start = .);}
19743 + ${RELOCATING+PROVIDE (___sbss_start = .);}
19744 + ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
19746 + *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
19748 + ${RELOCATING+PROVIDE (__sbss_end = .);}
19749 + ${RELOCATING+PROVIDE (___sbss_end = .);}
19750 + }${RW_BSS_REGION}"
19751 + SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }${RW_REGION}"
19752 + SDATA="/* We want the small data sections together, so single-instruction offsets
19753 + can access them all, and initialized data all before uninitialized, so
19754 + we can shorten the on-disk segment size. */
19755 + .sdata ${RELOCATING-0} :
19757 + ${RELOCATING+${SDATA_START_SYMBOLS}}
19758 + ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
19759 + *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
19761 + SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }${RW_REGION}"
19762 + REL_SDATA=".rel.sdata ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }${RO_REGION}
19763 + .rela.sdata ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
19764 + REL_SBSS=".rel.sbss ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }${RO_REGION}
19765 + .rela.sbss ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }${RO_REGION}"
19766 + REL_SDATA2=".rel.sdata2 ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }${RO_REGION}
19767 + .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }${RO_REGION}"
19768 + REL_SBSS2=".rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }${RO_REGION}
19769 + .rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }${RO_REGION}"
19771 + NO_SMALL_DATA=" "
19773 +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
19774 +CTOR=".ctors ${CONSTRUCTING-0} :
19776 + ${CONSTRUCTING+${CTOR_START}}
19777 + /* gcc uses crtbegin.o to find the start of
19778 + the constructors, so we make sure it is
19779 + first. Because this is a wildcard, it
19780 + doesn't matter if the user does not
19781 + actually link against crtbegin.o; the
19782 + linker won't look for a file to match a
19783 + wildcard. The wildcard also means that it
19784 + doesn't matter which directory crtbegin.o
19787 + KEEP (*crtbegin*.o(.ctors))
19789 + /* We don't want to include the .ctor section from
19790 + from the crtend.o file until after the sorted ctors.
19791 + The .ctor section from the crtend file contains the
19792 + end of ctors marker and it must be last */
19794 + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
19795 + KEEP (*(SORT(.ctors.*)))
19797 + ${CONSTRUCTING+${CTOR_END}}
19799 +DTOR=".dtors ${CONSTRUCTING-0} :
19801 + ${CONSTRUCTING+${DTOR_START}}
19802 + KEEP (*crtbegin*.o(.dtors))
19803 + KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
19804 + KEEP (*(SORT(.dtors.*)))
19806 + ${CONSTRUCTING+${DTOR_END}}
19808 +STACK=".stack ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
19810 + ${RELOCATING+_stack = .;}
19812 + ${RELOCATING+${STACK_SIZE+. = ${STACK_SIZE};}}
19813 + ${RELOCATING+_estack = .;}
19814 + }${RW_BSS_REGION}"
19816 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
19817 +if [ -z "$EMBEDDED" ]; then
19818 + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
19820 + test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
19824 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
19825 + "${LITTLE_OUTPUT_FORMAT}")
19826 +OUTPUT_ARCH(${OUTPUT_ARCH})
19829 +${RELOCATING+${LIB_SEARCH_DIRS}}
19830 +${RELOCATING+/* Do we need any of these for elf?
19831 + __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}} */}
19832 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
19833 +${RELOCATING+${INPUT_FILES}}
19834 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
19835 + if gld -r is used and the intermediate file has sections starting
19836 + at non-zero addresses. Could be a Solaris ld bug, could be a GNU ld
19837 + bug. But for now assigning the zero vmas works. */}
19839 +${RELOCATING+${MEMORY}}
19843 + /* Read-only sections, merged into text segment: */
19844 + ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
19846 + ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19847 + ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19848 + ${CREATE_SHLIB-${INTERP}}
19849 + ${INITIAL_READONLY_SECTIONS}
19850 + ${TEXT_DYNAMIC+${DYNAMIC}${RO_REGION}}
19851 + .hash ${RELOCATING-0} : { *(.hash) }${RO_REGION}
19852 + .dynsym ${RELOCATING-0} : { *(.dynsym) }${RO_REGION}
19853 + .dynstr ${RELOCATING-0} : { *(.dynstr) }${RO_REGION}
19854 + .gnu.version ${RELOCATING-0} : { *(.gnu.version) }${RO_REGION}
19855 + .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }${RO_REGION}
19856 + .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }${RO_REGION}
19859 +if [ "x$COMBRELOC" = x ]; then
19862 + COMBRELOCCAT="cat > $COMBRELOC"
19864 +eval $COMBRELOCCAT <<EOF
19865 + .rel.init ${RELOCATING-0} : { *(.rel.init) }${RO_REGION}
19866 + .rela.init ${RELOCATING-0} : { *(.rela.init) }${RO_REGION}
19867 + .rel.text ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }${RO_REGION}
19868 + .rela.text ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }${RO_REGION}
19869 + .rel.fini ${RELOCATING-0} : { *(.rel.fini) }${RO_REGION}
19870 + .rela.fini ${RELOCATING-0} : { *(.rela.fini) }${RO_REGION}
19871 + .rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }${RO_REGION}
19872 + .rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }${RO_REGION}
19873 + ${OTHER_READONLY_RELOC_SECTIONS}
19874 + .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19875 + .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19876 + .rel.data ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }${RO_REGION}
19877 + .rela.data ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }${RO_REGION}
19878 + .rel.tdata ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }${RO_REGION}
19879 + .rela.tdata ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }${RO_REGION}
19880 + .rel.tbss ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }${RO_REGION}
19881 + .rela.tbss ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }${RO_REGION}
19882 + .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }${RO_REGION}
19883 + .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }${RO_REGION}
19884 + .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }${RO_REGION}
19885 + .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }${RO_REGION}
19886 + .rel.got ${RELOCATING-0} : { *(.rel.got) }${RO_REGION}
19887 + .rela.got ${RELOCATING-0} : { *(.rela.got) }${RO_REGION}
19888 + ${OTHER_GOT_RELOC_SECTIONS}
19893 + .rel.bss ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }${RO_REGION}
19894 + .rela.bss ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }${RO_REGION}
19896 +if [ -n "$COMBRELOC" ]; then
19898 + .rel.dyn ${RELOCATING-0} :
19901 +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/ \1/' $COMBRELOC
19904 + .rela.dyn ${RELOCATING-0} :
19907 +sed -e '/^[ ]*[{}][ ]*$/d;/:[ ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/ \1/' $COMBRELOC
19913 + .rel.plt ${RELOCATING-0} : { *(.rel.plt) }${RO_REGION}
19914 + .rela.plt ${RELOCATING-0} : { *(.rela.plt) }${RO_REGION}
19915 + ${OTHER_PLT_RELOC_SECTIONS}
19917 + .init ${RELOCATING-0} :
19919 + ${RELOCATING+${INIT_START}}
19921 + ${RELOCATING+${INIT_END}}
19922 + }${RO_REGION} =${NOP-0}
19924 + ${DATA_PLT-${BSS_PLT-${PLT}${RO_REGION}}}
19925 + .text ${RELOCATING-0} :
19927 + ${RELOCATING+${TEXT_START_SYMBOLS}}
19928 + *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
19929 + KEEP (*(.text.*personality*))
19930 + /* .gnu.warning sections are handled specially by elf32.em. */
19932 + ${RELOCATING+${OTHER_TEXT_SECTIONS}}
19933 + }${RO_REGION} =${NOP-0}
19934 + .fini ${RELOCATING-0} :
19936 + ${RELOCATING+${FINI_START}}
19938 + ${RELOCATING+${FINI_END}}
19939 + }${RO_REGION} =${NOP-0}
19940 + ${RELOCATING+PROVIDE (__etext = .);}
19941 + ${RELOCATING+PROVIDE (_etext = .);}
19942 + ${RELOCATING+PROVIDE (etext = .);}
19943 + ${WRITABLE_RODATA-${RODATA}${RO_REGION}}
19944 + .rodata1 ${RELOCATING-0} : { *(.rodata1) }${RO_REGION}
19945 + ${CREATE_SHLIB-${SDATA2}}
19946 + ${CREATE_SHLIB-${SBSS2}}
19947 + ${OTHER_READONLY_SECTIONS}
19948 + .eh_frame_hdr : { *(.eh_frame_hdr) }${RO_REGION}
19949 + .eh_frame ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }${RO_REGION}
19950 + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RO_REGION}
19952 + ${RELOCATING+${DALIGN}}
19953 + ${RELOCATING+PROVIDE (_data = ORIGIN(${RW_VMA_REGION}));}
19954 + . = ORIGIN(${RW_VMA_REGION});
19955 + /* Exception handling */
19956 + .eh_frame ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }${RW_REGION}
19957 + .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RW_REGION}
19959 + /* Thread Local Storage sections */
19960 + .tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }${RW_REGION}
19961 + .tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }${RW_BSS_REGION}
19963 + /* Ensure the __preinit_array_start label is properly aligned. We
19964 + could instead move the label definition inside the section, but
19965 + the linker would then create the section even if it turns out to
19966 + be empty, which isn't pretty. */
19967 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = ALIGN(${ALIGNMENT}));}}
19968 + .preinit_array ${RELOCATING-0} : { KEEP (*(.preinit_array)) }${RW_REGION}
19969 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
19971 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
19972 + .init_array ${RELOCATING-0} : { KEEP (*(.init_array)) }${RW_REGION}
19973 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
19975 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
19976 + .fini_array ${RELOCATING-0} : { KEEP (*(.fini_array)) }${RW_REGION}
19977 + ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
19979 + ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}${RW_REGION}}}
19980 + ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}${RW_REGION}}}
19981 + .jcr ${RELOCATING-0} : { KEEP (*(.jcr)) }${RW_REGION}
19983 + ${RELOCATING+${DATARELRO}}
19984 + ${OTHER_RELRO_SECTIONS}
19985 + ${TEXT_DYNAMIC-${DYNAMIC}${RW_REGION}}
19986 + ${NO_SMALL_DATA+${RELRO_NOW+${GOT}${RW_REGION}}}
19987 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}${RW_REGION}}}}
19988 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}${RW_REGION}}}}
19989 + ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
19990 + ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}${RW_REGION}}}}
19992 + ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}${RW_REGION}}}
19994 + .data ${RELOCATING-0} :
19996 + ${RELOCATING+${DATA_START_SYMBOLS}}
19997 + *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
19998 + KEEP (*(.gnu.linkonce.d.*personality*))
19999 + ${CONSTRUCTING+SORT(CONSTRUCTORS)}
20001 + .data1 ${RELOCATING-0} : { *(.data1) }${RW_REGION}
20002 + ${WRITABLE_RODATA+${RODATA}${RW_REGION}}
20003 + ${OTHER_READWRITE_SECTIONS}
20004 + ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}${RW_REGION}}}
20005 + ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}${RW_REGION}}}
20006 + ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}${RW_REGION}}}
20007 + ${RELOCATING+${OTHER_GOT_SYMBOLS}}
20008 + ${NO_SMALL_DATA-${GOT}${RW_REGION}}
20009 + ${OTHER_GOT_SECTIONS}
20011 + ${OTHER_SDATA_SECTIONS}
20012 + ${RELOCATING+${BALIGN}}
20013 + ${RELOCATING+_edata = .;}
20014 + ${RELOCATING+PROVIDE (edata = .);}
20015 + ${RELOCATING+__bss_start = .;}
20016 + ${RELOCATING+${OTHER_BSS_SYMBOLS}}
20018 + ${BSS_PLT+${PLT}${RW_REGION}}
20019 + .bss ${RELOCATING-0} :
20022 + *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
20024 + /* Align here to ensure that the .bss section occupies space up to
20025 + _end. Align after .bss to ensure correct alignment even if the
20026 + .bss section disappears because there are no input sections. */
20027 + ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
20028 + }${RW_BSS_REGION}
20029 + ${OTHER_BSS_SECTIONS}
20030 + ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
20031 + ${RELOCATING+_end = .;}
20032 + ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
20033 + ${RELOCATING+PROVIDE (end = .);}
20034 + ${RELOCATING+${DATA_SEGMENT_END}}
20036 + /* Stabs debugging sections. */
20037 + .stab 0 : { *(.stab) }
20038 + .stabstr 0 : { *(.stabstr) }
20039 + .stab.excl 0 : { *(.stab.excl) }
20040 + .stab.exclstr 0 : { *(.stab.exclstr) }
20041 + .stab.index 0 : { *(.stab.index) }
20042 + .stab.indexstr 0 : { *(.stab.indexstr) }
20044 + .comment 0 : { *(.comment) }
20046 + /* DWARF debug sections.
20047 + Symbols in the DWARF debugging sections are relative to the beginning
20048 + of the section so we begin them at 0. */
20051 + .debug 0 : { *(.debug) }
20052 + .line 0 : { *(.line) }
20054 + /* GNU DWARF 1 extensions */
20055 + .debug_srcinfo 0 : { *(.debug_srcinfo) }
20056 + .debug_sfnames 0 : { *(.debug_sfnames) }
20058 + /* DWARF 1.1 and DWARF 2 */
20059 + .debug_aranges 0 : { *(.debug_aranges) }
20060 + .debug_pubnames 0 : { *(.debug_pubnames) }
20063 + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
20064 + .debug_abbrev 0 : { *(.debug_abbrev) }
20065 + .debug_line 0 : { *(.debug_line) }
20066 + .debug_frame 0 : { *(.debug_frame) }
20067 + .debug_str 0 : { *(.debug_str) }
20068 + .debug_loc 0 : { *(.debug_loc) }
20069 + .debug_macinfo 0 : { *(.debug_macinfo) }
20071 + /* SGI/MIPS DWARF 2 extensions */
20072 + .debug_weaknames 0 : { *(.debug_weaknames) }
20073 + .debug_funcnames 0 : { *(.debug_funcnames) }
20074 + .debug_typenames 0 : { *(.debug_typenames) }
20075 + .debug_varnames 0 : { *(.debug_varnames) }
20077 + ${STACK_ADDR+${STACK}}
20078 + ${OTHER_SECTIONS}
20079 + ${RELOCATING+${OTHER_END_SYMBOLS}}
20080 + ${RELOCATING+${STACKNOTE}}
20084 +++ b/ld/testsuite/ld-avr32/avr32.exp
20086 +# Expect script for AVR32 ELF linker tests.
20087 +# Copyright 2004-2006 Atmel Corporation.
20089 +# This file is free software; you can redistribute it and/or modify
20090 +# it under the terms of the GNU General Public License as published by
20091 +# the Free Software Foundation; either version 2 of the License, or
20092 +# (at your option) any later version.
20094 +# This program is distributed in the hope that it will be useful,
20095 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
20096 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20097 +# GNU General Public License for more details.
20099 +# You should have received a copy of the GNU General Public License
20100 +# along with this program; if not, write to the Free Software
20101 +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20103 +# Written by Haavard Skinnemoen (hskinnemoen@atmel.com)
20106 +if ![istarget avr32-*-*] {
20110 +run_dump_test "pcrel"
20112 +++ b/ld/testsuite/ld-avr32/pcrel.d
20114 +#name: AVR32 ELF PC-relative external relocs
20115 +#source: symbols.s
20116 +#source: ../../../gas/testsuite/gas/avr32/pcrel.s
20117 +#ld: -T $srcdir/$subdir/pcrel.ld
20120 +.*: file format elf.*avr32.*
20122 +Disassembly of section .text:
20124 +a0000000 <_start>:
20125 +a0000000: d7 03 nop
20126 +a0000002: d7 03 nop
20128 +a0000004 <test_rjmp>:
20129 +a0000004: d7 03 nop
20130 +a0000006: c0 28 rjmp a000000a <test_rjmp\+0x6>
20131 +a0000008: d7 03 nop
20132 +a000000a: e0 8f 01 fb bral a0000400 <extsym10>
20134 +a000000e <test_rcall>:
20135 +a000000e: d7 03 nop
20136 +a0000010 <test_rcall2>:
20137 +a0000010: c0 2c rcall a0000014 <test_rcall2\+0x4>
20138 +a0000012: d7 03 nop
20139 +a0000014: ee b0 ff f6 rcall a0200000 <extsym21>
20141 +a0000018 <test_branch>:
20142 +a0000018: c0 31 brne a000001e <test_branch\+0x6>
20143 +a000001a: fe 9f ff ff bral a0000018 <test_branch>
20144 +a000001e: ee 90 ff f1 breq a0200000 <extsym21>
20146 +a0000022 <test_lddpc>:
20147 +a0000022: 48 30 lddpc r0,a000002c <sym1>
20148 +a0000024: 48 20 lddpc r0,a000002c <sym1>
20149 +a0000026: fe f0 7f da ld.w r0,pc\[32730\]
20153 +a000002c: d7 03 nop
20154 +a000002e: d7 03 nop
20156 +a0000030 <test_local>:
20157 +a0000030: 48 20 lddpc r0,a0000038 <test_local\+0x8>
20158 +a0000032: 48 30 lddpc r0,a000003c <test_local\+0xc>
20159 +a0000034: 48 20 lddpc r0,a000003c <test_local\+0xc>
20160 +a0000036: 00 00 add r0,r0
20161 +a0000038: d7 03 nop
20162 +a000003a: d7 03 nop
20163 +a000003c: d7 03 nop
20164 +a000003e: d7 03 nop
20166 +Disassembly of section \.text\.init:
20167 +a0000040 <test_inter_section>:
20168 +a0000040: fe b0 ff e7 rcall a000000e <test_rcall>
20169 +a0000044: d7 03 nop
20170 +a0000046: fe b0 ff e4 rcall a000000e <test_rcall>
20171 +a000004a: fe b0 ff e3 rcall a0000010 <test_rcall2>
20172 +a000004e: d7 03 nop
20173 +a0000050: fe b0 ff e0 rcall a0000010 <test_rcall2>
20175 +Disassembly of section \.text\.pcrel10:
20177 +a0000400 <extsym10>:
20178 +a0000400: d7 03 nop
20180 +Disassembly of section \.text\.pcrel16:
20182 +a0008000 <extsym16>:
20183 +a0008000: d7 03 nop
20185 +Disassembly of section \.text\.pcrel21:
20186 +a0200000 <extsym21>:
20187 +a0200000: d7 03 nop
20189 +++ b/ld/testsuite/ld-avr32/pcrel.ld
20194 + .text 0xa0000000:
20199 + .text.pcrel10 0xa0000400:
20204 + .text.pcrel16 0xa0008000:
20209 + .text.pcrel21 0xa0200000:
20215 +++ b/ld/testsuite/ld-avr32/symbols.s
20223 + .section .text.pcrel10,"ax"
20228 + .section .text.pcrel16,"ax"
20233 + .section .text.pcrel21,"ax"
20238 +++ b/opcodes/avr32-asm.c
20240 +/* Assembler interface for AVR32.
20241 + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20243 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20245 + This file is part of libopcodes.
20247 + This program is free software; you can redistribute it and/or
20248 + modify it under the terms of the GNU General Public License as
20249 + published by the Free Software Foundation; either version 2 of the
20250 + License, or (at your option) any later version.
20252 + This program is distributed in the hope that it will be useful, but
20253 + WITHOUT ANY WARRANTY; without even the implied warranty of
20254 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20255 + General Public License for more details.
20257 + You should have received a copy of the GNU General Public License
20258 + along with this program; if not, write to the Free Software
20259 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20260 + 02111-1307, USA. */
20262 +#include <string.h>
20264 +#include "avr32-opc.h"
20265 +#include "avr32-asm.h"
20267 +/* Structure for a register hash table entry. */
20270 + const char *name;
20274 +/* Integer Registers. */
20275 +static const struct reg_entry reg_table[] =
20277 + /* Primary names (used by the disassembler) */
20278 + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 },
20279 + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
20280 + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
20281 + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 },
20282 + /* Alternatives to sp, lr and pc. */
20283 + { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20285 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20287 +/* Coprocessor Registers. */
20288 +static const struct reg_entry cr_table[] =
20290 + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 },
20291 + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 },
20292 + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 },
20293 + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20295 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20297 +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0]))
20299 +/* PiCo Registers. */
20300 +static const struct reg_entry pico_table[] =
20302 + { "inpix2", 0 }, { "inpix1", 1 }, { "inpix0", 2 },
20303 + { "outpix2", 3 }, { "outpix1", 4 }, { "outpix0", 5 },
20304 + { "coeff0_a", 6 }, { "coeff0_b", 7 }, { "coeff1_a", 8 },
20305 + { "coeff1_b", 9 }, { "coeff2_a", 10 }, { "coeff2_b", 11 },
20306 + { "vmu0_out", 12 }, { "vmu1_out", 13 }, { "vmu2_out", 14 },
20307 + { "config", 15 },
20309 +#define AVR32_NR_PICOREGS (sizeof(pico_table)/sizeof(pico_table[0]))
20312 +avr32_parse_intreg(const char *str)
20316 + for (i = 0; i < AVR32_NR_INTREGS; i++)
20318 + if (strcasecmp(reg_table[i].name, str) == 0)
20319 + return reg_table[i].number;
20326 +avr32_parse_cpreg(const char *str)
20330 + for (i = 0; i < AVR32_NR_CPREGS; i++)
20332 + if (strcasecmp(cr_table[i].name, str) == 0)
20333 + return cr_table[i].number;
20340 +int avr32_parse_picoreg(const char *str)
20344 + for (i = 0; i < AVR32_NR_PICOREGS; i++)
20346 + if (strcasecmp(pico_table[i].name, str) == 0)
20347 + return pico_table[i].number;
20353 +static unsigned long
20354 +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *))
20356 + int reg_from, reg_to;
20357 + unsigned long result = 0;
20358 + char *p1, *p2, c;
20362 + for (p1 = str; *p1; p1++)
20363 + if (*p1 == ',' || *p1 == '-')
20366 + c = *p1, *p1 = 0;
20367 + reg_from = parse_reg(str);
20370 + if (reg_from < 0)
20375 + for (p2 = ++p1; *p2; p2++)
20379 + c = *p2, *p2 = 0;
20380 + /* printf("going to parse reg_to from `%s'\n", p1); */
20381 + reg_to = parse_reg(p1);
20387 + while (reg_from <= reg_to)
20388 + result |= (1 << reg_from++);
20392 + result |= (1 << reg_from);
20405 +avr32_parse_reglist(char *str, char **endptr)
20407 + return parse_reglist(str, endptr, avr32_parse_intreg);
20411 +avr32_parse_cpreglist(char *str, char **endptr)
20413 + return parse_reglist(str, endptr, avr32_parse_cpreg);
20417 +avr32_parse_pico_reglist(char *str, char **endptr)
20419 + return parse_reglist(str, endptr, avr32_parse_picoreg);
20423 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8)
20425 + unsigned long result = 0;
20427 + /* printf("convert regmask16 0x%04lx\n", regmask16); */
20429 + if (regmask16 & 0xf)
20431 + if ((regmask16 & 0xf) == 0xf)
20432 + result |= 1 << 0;
20436 + if (regmask16 & 0xf0)
20438 + if ((regmask16 & 0xf0) == 0xf0)
20439 + result |= 1 << 1;
20443 + if (regmask16 & 0x300)
20445 + if ((regmask16 & 0x300) == 0x300)
20446 + result |= 1 << 2;
20450 + if (regmask16 & (1 << 13))
20453 + if (regmask16 & (1 << 10))
20454 + result |= 1 << 3;
20455 + if (regmask16 & (1 << 11))
20456 + result |= 1 << 4;
20457 + if (regmask16 & (1 << 12))
20458 + result |= 1 << 5;
20459 + if (regmask16 & (1 << 14))
20460 + result |= 1 << 6;
20461 + if (regmask16 & (1 << 15))
20462 + result |= 1 << 7;
20464 + *regmask8 = result;
20472 + const struct reg_entry *names;
20474 + struct hash_control *htab;
20475 + const char *errmsg;
20478 +struct reg_map all_reg_maps[] =
20480 + { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") },
20481 + { cr_table, AVR32_NR_CPREGS, NULL, N_("coprocessor register expected") },
20485 +++ b/opcodes/avr32-asm.h
20487 +/* Assembler interface for AVR32.
20488 + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20490 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20492 + This file is part of libopcodes.
20494 + This program is free software; you can redistribute it and/or
20495 + modify it under the terms of the GNU General Public License as
20496 + published by the Free Software Foundation; either version 2 of the
20497 + License, or (at your option) any later version.
20499 + This program is distributed in the hope that it will be useful, but
20500 + WITHOUT ANY WARRANTY; without even the implied warranty of
20501 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20502 + General Public License for more details.
20504 + You should have received a copy of the GNU General Public License
20505 + along with this program; if not, write to the Free Software
20506 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20507 + 02111-1307, USA. */
20508 +#ifndef __OPCODES_AVR32_ASM_H
20509 +#define __OPCODES_AVR32_ASM_H
20512 +avr32_parse_intreg(const char *str);
20514 +avr32_parse_cpreg(const char *str);
20516 +avr32_parse_picoreg(const char *str);
20517 +extern unsigned long
20518 +avr32_parse_reglist(char *str, char **endptr);
20519 +extern unsigned long
20520 +avr32_parse_cpreglist(char *str, char **endptr);
20521 +extern unsigned long
20522 +avr32_parse_pico_reglist(char *str, char **endptr);
20524 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8);
20526 +#endif /* __OPCODES_AVR32_ASM_H */
20528 +++ b/opcodes/avr32-dis.c
20530 +/* Print AVR32 instructions for GDB and objdump.
20531 + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20533 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20535 + This file is part of libopcodes.
20537 + This program is free software; you can redistribute it and/or
20538 + modify it under the terms of the GNU General Public License as
20539 + published by the Free Software Foundation; either version 2 of the
20540 + License, or (at your option) any later version.
20542 + This program is distributed in the hope that it will be useful, but
20543 + WITHOUT ANY WARRANTY; without even the implied warranty of
20544 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20545 + General Public License for more details.
20547 + You should have received a copy of the GNU General Public License
20548 + along with this program; if not, write to the Free Software
20549 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20550 + 02111-1307, USA. */
20552 +#include "sysdep.h"
20553 +#include "dis-asm.h"
20554 +#include "avr32-opc.h"
20555 +#include "opintl.h"
20556 +#include "safe-ctype.h"
20558 +/* TODO: Share this with -asm */
20560 +/* Structure for a register hash table entry. */
20563 + const char *name;
20568 +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
20571 +static char avr32_opt_decode_fpu = 0;
20573 +static const struct reg_entry reg_table[] =
20575 + /* Primary names (used by the disassembler) */
20576 + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 },
20577 + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
20578 + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
20579 + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 },
20580 + /* Alternatives to sp, lr and pc. */
20581 + { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20583 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20585 +/* Coprocessor Registers. */
20586 +static const struct reg_entry cr_table[] =
20588 + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 },
20589 + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 },
20590 + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 },
20591 + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20593 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20595 +static const char bparts[4] = { 'b', 'l', 'u', 't' };
20596 +static bfd_vma current_pc;
20598 +struct avr32_field_value
20600 + const struct avr32_ifield *ifield;
20601 + unsigned long value;
20604 +struct avr32_operand
20609 + int (*print)(struct avr32_operand *op, struct disassemble_info *info,
20610 + struct avr32_field_value *ifields);
20613 +static signed long
20614 +get_signed_value(const struct avr32_field_value *fv)
20616 + signed long value = fv->value;
20618 + if (fv->value & (1 << (fv->ifield->bitsize - 1)))
20619 + value |= (~0UL << fv->ifield->bitsize);
20625 +print_reglist_range(unsigned int first, unsigned int last,
20626 + const struct reg_entry *reg_names,
20628 + struct disassemble_info *info)
20631 + info->fprintf_func(info->stream, ",");
20633 + if (first == last)
20634 + info->fprintf_func(info->stream, "%s",
20635 + reg_names[first].name);
20637 + info->fprintf_func(info->stream, "%s-%s",
20638 + reg_names[first].name, reg_names[last].name);
20642 +print_intreg(struct avr32_operand *op,
20643 + struct disassemble_info *info,
20644 + struct avr32_field_value *ifields)
20646 + unsigned long regid = ifields[0].value << op->align_order;
20648 + info->fprintf_func(info->stream, "%s",
20649 + reg_table[regid].name);
20654 +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED,
20655 + struct disassemble_info *info,
20656 + struct avr32_field_value *ifields)
20658 + info->fprintf_func(info->stream, "--%s",
20659 + reg_table[ifields[0].value].name);
20664 +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
20665 + struct disassemble_info *info,
20666 + struct avr32_field_value *ifields)
20668 + info->fprintf_func(info->stream, "%s++",
20669 + reg_table[ifields[0].value].name);
20674 +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED,
20675 + struct disassemble_info *info,
20676 + struct avr32_field_value *ifields)
20678 + const char *rp = reg_table[ifields[0].value].name;
20679 + unsigned long sa = ifields[1].value;
20682 + info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa);
20684 + info->fprintf_func(info->stream, "%s", rp);
20690 +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED,
20691 + struct disassemble_info *info,
20692 + struct avr32_field_value *ifields)
20694 + const char *rp = reg_table[ifields[0].value].name;
20695 + unsigned long sa = ifields[1].value;
20698 + info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa);
20700 + info->fprintf_func(info->stream, "%s", rp);
20706 +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20707 + struct disassemble_info *info,
20708 + struct avr32_field_value *ifields)
20710 + info->fprintf_func(info->stream, "%s:%c",
20711 + reg_table[ifields[0].value].name,
20712 + bparts[ifields[1].value]);
20717 +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20718 + struct disassemble_info *info,
20719 + struct avr32_field_value *ifields)
20721 + info->fprintf_func(info->stream, "%s:%c",
20722 + reg_table[ifields[0].value].name,
20723 + ifields[1].value ? 't' : 'b');
20728 +print_intreg_sdisp(struct avr32_operand *op,
20729 + struct disassemble_info *info,
20730 + struct avr32_field_value *ifields)
20732 + signed long disp;
20734 + disp = get_signed_value(&ifields[1]) << op->align_order;
20736 + info->fprintf_func(info->stream, "%s[%ld]",
20737 + reg_table[ifields[0].value].name, disp);
20742 +print_intreg_udisp(struct avr32_operand *op,
20743 + struct disassemble_info *info,
20744 + struct avr32_field_value *ifields)
20746 + info->fprintf_func(info->stream, "%s[0x%lx]",
20747 + reg_table[ifields[0].value].name,
20748 + ifields[1].value << op->align_order);
20753 +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED,
20754 + struct disassemble_info *info,
20755 + struct avr32_field_value *ifields)
20757 + const char *rb, *ri;
20758 + unsigned long sa = ifields[2].value;
20760 + rb = reg_table[ifields[0].value].name;
20761 + ri = reg_table[ifields[1].value].name;
20764 + info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa);
20766 + info->fprintf_func(info->stream, "%s[%s]", rb, ri);
20772 +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED,
20773 + struct disassemble_info *info,
20774 + struct avr32_field_value *ifields)
20776 + info->fprintf_func(info->stream, "%s[%s:%c<<2]",
20777 + reg_table[ifields[0].value].name,
20778 + reg_table[ifields[1].value].name,
20779 + bparts[ifields[2].value]);
20784 +print_jmplabel(struct avr32_operand *op,
20785 + struct disassemble_info *info,
20786 + struct avr32_field_value *ifields)
20788 + bfd_vma address, offset;
20790 + offset = get_signed_value(ifields) << op->align_order;
20791 + address = (current_pc & (~0UL << op->align_order)) + offset;
20793 + info->print_address_func(address, info);
20799 +print_pc_disp(struct avr32_operand *op,
20800 + struct disassemble_info *info,
20801 + struct avr32_field_value *ifields)
20803 + bfd_vma address, offset;
20805 + offset = ifields[0].value << op->align_order;
20806 + address = (current_pc & (~0UL << op->align_order)) + offset;
20808 + info->print_address_func(address, info);
20814 +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED,
20815 + struct disassemble_info *info,
20816 + struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
20818 + info->fprintf_func(info->stream, "sp");
20823 +print_sp_disp(struct avr32_operand *op,
20824 + struct disassemble_info *info,
20825 + struct avr32_field_value *ifields)
20827 + info->fprintf_func(info->stream, "sp[0x%lx]",
20828 + ifields[0].value << op->align_order);
20833 +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED,
20834 + struct disassemble_info *info,
20835 + struct avr32_field_value *ifields)
20837 + info->fprintf_func(info->stream, "cp%lu", ifields[0].value);
20842 +print_cpreg(struct avr32_operand *op,
20843 + struct disassemble_info *info,
20844 + struct avr32_field_value *ifields)
20846 + info->fprintf_func(info->stream, "cr%lu",
20847 + ifields[0].value << op->align_order);
20852 +print_uconst(struct avr32_operand *op,
20853 + struct disassemble_info *info,
20854 + struct avr32_field_value *ifields)
20856 + info->fprintf_func(info->stream, "0x%lx",
20857 + ifields[0].value << op->align_order);
20862 +print_sconst(struct avr32_operand *op,
20863 + struct disassemble_info *info,
20864 + struct avr32_field_value *ifields)
20866 + info->fprintf_func(info->stream, "%ld",
20867 + get_signed_value(ifields) << op->align_order);
20872 +print_reglist8_head(unsigned long regmask, int *commap,
20873 + struct disassemble_info *info)
20875 + int first = -1, last, i = 0;
20876 + int need_comma = 0;
20880 + if (first == -1 && (regmask & 1))
20884 + else if (first != -1 && !(regmask & 1))
20888 + print_reglist_range(first, last, reg_table, need_comma, info);
20902 + *commap = need_comma;
20907 +print_reglist8_tail(unsigned long regmask, int first, int need_comma,
20908 + struct disassemble_info *info)
20912 + if (regmask & 0x20)
20921 + print_reglist_range(first, last, reg_table, need_comma, info);
20926 + if (regmask & 0x40)
20933 + if (regmask & 0x80)
20941 + print_reglist_range(first, last, reg_table, need_comma, info);
20945 +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20946 + struct disassemble_info *info,
20947 + struct avr32_field_value *ifields)
20949 + unsigned long regmask = ifields[0].value;
20950 + int first, need_comma;
20952 + first = print_reglist8_head(regmask, &need_comma, info);
20953 + print_reglist8_tail(regmask, first, need_comma, info);
20959 +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED,
20960 + struct disassemble_info *info,
20961 + struct avr32_field_value *ifields)
20963 + unsigned long regmask = ifields[0].value >> 1;
20964 + int first, last, need_comma;
20966 + first = print_reglist8_head(regmask, &need_comma, info);
20968 + if ((ifields[0].value & 0x101) == 0x101)
20974 + print_reglist_range(first, last, reg_table, need_comma, info);
20979 + print_reglist_range(15, 15, reg_table, need_comma, info);
20983 + if ((regmask & 3) == 0)
20984 + info->fprintf_func(info->stream, ",r12=0");
20985 + else if ((regmask & 3) == 1)
20986 + info->fprintf_func(info->stream, ",r12=1");
20988 + info->fprintf_func(info->stream, ",r12=-1");
20991 + print_reglist8_tail(regmask, first, need_comma, info);
20997 +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED,
20998 + struct disassemble_info *info,
20999 + struct avr32_field_value *ifields)
21001 + unsigned long regmask = ifields[0].value;
21002 + unsigned int i = 0, first, last;
21003 + int need_comma = 0;
21014 + if (!(regmask & 1))
21018 + print_reglist_range(first, last, reg_table, need_comma, info);
21032 +print_reglist_ldm(struct avr32_operand *op,
21033 + struct disassemble_info *info,
21034 + struct avr32_field_value *ifields)
21037 + int i, first, last;
21038 + unsigned long regmask;
21040 + rp = ifields[0].value;
21041 + w_bit = ifields[1].value;
21042 + regmask = ifields[2].value;
21044 + if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC)
21047 + info->fprintf_func(info->stream, "sp++");
21049 + info->fprintf_func(info->stream, "sp");
21051 + for (i = 0; i < 12; )
21053 + if (regmask & (1 << i))
21059 + if (!(regmask & (1 << i)))
21063 + print_reglist_range(first, last, reg_table, 1, info);
21069 + info->fprintf_func(info->stream, ",pc");
21070 + if (regmask & (1 << AVR32_REG_LR))
21071 + info->fprintf_func(info->stream, ",r12=-1");
21072 + else if (regmask & (1 << AVR32_REG_R12))
21073 + info->fprintf_func(info->stream, ",r12=1");
21075 + info->fprintf_func(info->stream, ",r12=0");
21080 + info->fprintf_func(info->stream, "%s++,", reg_table[rp].name);
21082 + info->fprintf_func(info->stream, "%s,", reg_table[rp].name);
21084 + print_reglist16(op, info, ifields + 2);
21091 +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED,
21092 + struct disassemble_info *info,
21093 + struct avr32_field_value *ifields)
21095 + unsigned long regmask = ifields[0].value;
21096 + unsigned int i = 0, first, last, offset = 0;
21097 + int need_comma = 0;
21099 + if (ifields[1].value)
21111 + if (!(regmask & 1))
21115 + print_reglist_range(offset + first, offset + last,
21116 + cr_table, need_comma, info);
21130 +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED,
21131 + struct disassemble_info *info,
21132 + struct avr32_field_value *ifields)
21134 + unsigned long regmask = ifields[0].value;
21135 + unsigned int i = 0, first, last;
21136 + int need_comma = 0;
21147 + if (!(regmask & 1))
21150 + last = 2 * (i - 1) + 1;
21151 + print_reglist_range(first, last, cr_table, need_comma, info);
21165 +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED,
21166 + struct disassemble_info *info,
21167 + struct avr32_field_value *ifields)
21169 + unsigned long regid = ifields[0].value;
21170 + const char *retval;
21172 + if (regid < AVR32_REG_SP)
21173 + retval = reg_table[regid].name;
21174 + else if (regid == AVR32_REG_SP)
21176 + else if (regid == AVR32_REG_LR)
21181 + info->fprintf_func(info->stream, "%s", retval);
21187 +print_mcall(struct avr32_operand *op,
21188 + struct disassemble_info *info,
21189 + struct avr32_field_value *ifields)
21191 + unsigned long regid = ifields[0].value;
21193 + if (regid == AVR32_REG_PC)
21194 + print_jmplabel(op, info, ifields + 1);
21196 + print_intreg_sdisp(op, info, ifields);
21202 +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
21203 + struct disassemble_info *info,
21204 + struct avr32_field_value *ifields)
21206 + signed long value = ifields[0].value;
21213 + info->fprintf_func(info->stream, "%ld", value);
21219 +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED,
21220 + struct disassemble_info *info,
21221 + struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
21223 + info->fprintf_func(info->stream, "COH");
21227 +#define OP(name, sgn, pcrel, align, func) \
21228 + { AVR32_OPERAND_##name, pcrel, align, print_##func }
21230 +struct avr32_operand operand[AVR32_NR_OPERANDS] =
21232 + OP(INTREG, 0, 0, 0, intreg),
21233 + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
21234 + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
21235 + OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
21236 + OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
21237 + OP(INTREG_BSEL, 0, 0, 0, intreg_bpart),
21238 + OP(INTREG_HSEL, 0, 0, 1, intreg_hpart),
21239 + OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp),
21240 + OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp),
21241 + OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp),
21242 + OP(INTREG_UDISP, 0, 0, 0, intreg_udisp),
21243 + OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp),
21244 + OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp),
21245 + OP(INTREG_INDEX, 0, 0, 0, intreg_index),
21246 + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
21247 + OP(DWREG, 0, 0, 1, intreg),
21248 + OP(PC_UDISP_W, 0, 1, 2, pc_disp),
21249 + OP(SP, 0, 0, 0, sp),
21250 + OP(SP_UDISP_W, 0, 0, 2, sp_disp),
21251 + OP(CPNO, 0, 0, 0, cpno),
21252 + OP(CPREG, 0, 0, 0, cpreg),
21253 + OP(CPREG_D, 0, 0, 1, cpreg),
21254 + OP(UNSIGNED_CONST, 0, 0, 0, uconst),
21255 + OP(UNSIGNED_CONST_W, 0, 0, 2, uconst),
21256 + OP(SIGNED_CONST, 1, 0, 0, sconst),
21257 + OP(SIGNED_CONST_W, 1, 0, 2, sconst),
21258 + OP(JMPLABEL, 1, 1, 1, jmplabel),
21259 + OP(UNSIGNED_NUMBER, 0, 0, 0, uconst),
21260 + OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst),
21261 + OP(REGLIST8, 0, 0, 0, reglist8),
21262 + OP(REGLIST9, 0, 0, 0, reglist9),
21263 + OP(REGLIST16, 0, 0, 0, reglist16),
21264 + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
21265 + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
21266 + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
21267 + OP(RETVAL, 0, 0, 0, retval),
21268 + OP(MCALL, 1, 0, 2, mcall),
21269 + OP(JOSPINC, 0, 0, 0, jospinc),
21270 + OP(COH, 0, 0, 0, coh),
21274 +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc,
21275 + bfd_vma pc, struct disassemble_info *info)
21277 + const struct avr32_syntax *syntax = opc->syntax;
21278 + struct avr32_field_value fields[AVR32_MAX_FIELDS];
21279 + unsigned int i, next_field = 0, nr_operands;
21281 + for (i = 0; i < opc->nr_fields; i++)
21283 + opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value);
21284 + fields[i].ifield = opc->fields[i];
21288 + info->fprintf_func(info->stream, "%s", syntax->mnemonic->name);
21290 + if (syntax->nr_operands < 0)
21291 + nr_operands = (unsigned int) -syntax->nr_operands;
21293 + nr_operands = (unsigned int) syntax->nr_operands;
21295 + for (i = 0; i < nr_operands; i++)
21297 + struct avr32_operand *op = &operand[syntax->operand[i]];
21300 + info->fprintf_func(info->stream, ",");
21302 + info->fprintf_func(info->stream, "\t");
21303 + next_field += op->print(op, info, &fields[next_field]);
21307 +#define is_fpu_insn(iw) ((iw&0xf9f0e000)==0xe1a00000)
21309 +static const struct avr32_opcode *
21310 +find_opcode(bfd_vma insn_word)
21314 + for (i = 0; i < AVR32_NR_OPCODES; i++)
21316 + const struct avr32_opcode *opc = &avr32_opc_table[i];
21318 + if ((insn_word & opc->mask) == opc->value)
21320 + if (avr32_opt_decode_fpu)
21322 + if (is_fpu_insn(insn_word))
21324 + if (opc->id != AVR32_OPC_COP)
21339 +read_insn_word(bfd_vma pc, bfd_vma *valuep,
21340 + struct disassemble_info *info)
21345 + status = info->read_memory_func(pc, b, 4, info);
21348 + status = info->read_memory_func(pc, b, 2, info);
21351 + info->memory_error_func(status, pc, info);
21357 + *valuep = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
21361 +/* Parse an individual disassembler option. */
21364 +parse_avr32_disassembler_option (option)
21367 + if (option == NULL)
21370 + if (!strcmp(option,"decode-fpu"))
21372 + avr32_opt_decode_fpu = 1;
21376 + printf("\n%s--",option);
21377 + /* XXX - should break 'option' at following delimiter. */
21378 + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
21383 +/* Parse the string of disassembler options, spliting it at whitespaces
21384 + or commas. (Whitespace separators supported for backwards compatibility). */
21387 +parse_disassembler_options (char *options)
21389 + if (options == NULL)
21394 + parse_avr32_disassembler_option (options);
21396 + /* Skip forward to next seperator. */
21397 + while ((*options) && (! ISSPACE (*options)) && (*options != ','))
21399 + /* Skip forward past seperators. */
21400 + while (ISSPACE (*options) || (*options == ','))
21406 +print_insn_avr32(bfd_vma pc, struct disassemble_info *info)
21408 + bfd_vma insn_word;
21409 + const struct avr32_opcode *opc;
21411 + if (info->disassembler_options)
21413 + parse_disassembler_options (info->disassembler_options);
21415 + /* To avoid repeated parsing of these options, we remove them here. */
21416 + info->disassembler_options = NULL;
21419 + info->bytes_per_chunk = 1;
21420 + info->display_endian = BFD_ENDIAN_BIG;
21422 + if (read_insn_word(pc, &insn_word, info))
21425 + opc = find_opcode(insn_word);
21428 + print_opcode(insn_word, opc, pc, info);
21429 + return opc->size;
21433 + info->fprintf_func(info->stream, _("*unknown*"));
21440 +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED)
21442 + fprintf(stream, "\n AVR32 Specific Disassembler Options:\n");
21443 + fprintf(stream, " -M decode-fpu Print FPU instructions instead of 'cop' \n");
21447 +++ b/opcodes/avr32-opc.c
21449 +/* Opcode tables for AVR32.
21450 + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
21452 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
21454 + This file is part of libopcodes.
21456 + This program is free software; you can redistribute it and/or
21457 + modify it under the terms of the GNU General Public License as
21458 + published by the Free Software Foundation; either version 2 of the
21459 + License, or (at your option) any later version.
21461 + This program is distributed in the hope that it will be useful, but
21462 + WITHOUT ANY WARRANTY; without even the implied warranty of
21463 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21464 + General Public License for more details.
21466 + You should have received a copy of the GNU General Public License
21467 + along with this program; if not, write to the Free Software
21468 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21469 + 02111-1307, USA. */
21471 +#include <stdlib.h>
21472 +#include <assert.h>
21474 +#include "avr32-opc.h"
21476 +#define PICO_CPNO 1
21479 +avr32_insert_simple(const struct avr32_ifield *field,
21480 + void *buf, unsigned long value)
21484 + word = bfd_getb32(buf);
21485 + word &= ~field->mask;
21486 + word |= (value << field->shift) & field->mask;
21487 + bfd_putb32(word, buf);
21491 +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21492 + void *buf, unsigned long value)
21494 + char *opcode = buf;
21496 + opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e);
21497 + opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4);
21501 +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21502 + void *buf, unsigned long value)
21504 + char *opcode = buf;
21506 + opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4);
21507 + opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4)
21508 + | ((value & 0x300) >> 8));
21513 +avr32_insert_k21(const struct avr32_ifield *field,
21514 + void *buf, unsigned long value)
21519 + word = bfd_getb32(buf);
21520 + word &= ~field->mask;
21521 + k21 = ((value & 0xffff) | ((value & 0x10000) << 4)
21522 + | ((value & 0x1e0000) << 8));
21523 + assert(!(k21 & ~field->mask));
21525 + bfd_putb32(word, buf);
21529 +avr32_insert_cpop(const struct avr32_ifield *field,
21530 + void *buf, unsigned long value)
21534 + word = bfd_getb32(buf);
21535 + word &= ~field->mask;
21536 + word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20)
21537 + | ((value & 0x01) << 12));
21538 + bfd_putb32(word, buf);
21542 +avr32_insert_k12cp(const struct avr32_ifield *field,
21543 + void *buf, unsigned long value)
21547 + word = bfd_getb32(buf);
21548 + word &= ~field->mask;
21549 + word |= ((value & 0xf00) << 4) | (value & 0xff);
21550 + bfd_putb32(word, buf);
21553 +void avr32_extract_simple(const struct avr32_ifield *field,
21554 + void *buf, unsigned long *value)
21556 + /* XXX: The disassembler has done any necessary byteswapping already */
21557 + bfd_vma word = *(bfd_vma *)buf;
21559 + *value = (word & field->mask) >> field->shift;
21562 +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21563 + void *buf, unsigned long *value)
21565 + bfd_vma word = *(bfd_vma *)buf;
21567 + *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e);
21570 +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21571 + void *buf, unsigned long *value)
21573 + bfd_vma word = *(bfd_vma *)buf;
21575 + *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff);
21578 +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21579 + void *buf, unsigned long *value)
21581 + bfd_vma word = *(bfd_vma *)buf;
21583 + *value = ((word & 0xffff) | ((word >> 4) & 0x10000)
21584 + | ((word >> 8) & 0x1e0000));
21587 +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21588 + void *buf, unsigned long *value)
21590 + bfd_vma word = *(bfd_vma *)buf;
21592 + *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e)
21593 + | ((word >> 20) & 0x60));
21596 +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21597 + void *buf, unsigned long *value)
21599 + bfd_vma word = *(bfd_vma *)buf;
21601 + *value = ((word >> 4) & 0xf00) | (word & 0xff);
21605 +#define IFLD(id, bitsz, shift, mask, func) \
21606 + { AVR32_IFIELD_##id, bitsz, shift, mask, \
21607 + avr32_insert_##func, avr32_extract_##func }
21609 +const struct avr32_ifield avr32_ifield_table[] =
21611 + IFLD(RX, 4, 25, 0x1e000000, simple),
21612 + IFLD(RY, 4, 16, 0x000f0000, simple),
21613 + IFLD(COND4C, 4, 20, 0x00f00000, simple),
21614 + IFLD(K8C, 8, 20, 0x0ff00000, simple),
21615 + IFLD(K7C, 7, 20, 0x07f00000, simple),
21616 + IFLD(K5C, 5, 20, 0x01f00000, simple),
21617 + IFLD(K3, 3, 20, 0x00700000, simple),
21618 + IFLD(RY_DW, 3, 17, 0x000e0000, simple),
21619 + IFLD(COND4E, 4, 8, 0x00000f00, simple),
21620 + IFLD(K8E, 8, 0, 0x000000ff, simple),
21621 + IFLD(BIT5C, 5, 20, 0x1e100000, bit5c),
21622 + IFLD(COND3, 3, 16, 0x00070000, simple),
21623 + IFLD(K10, 10, 16, 0x0ff30000, k10),
21624 + IFLD(POPM, 9, 19, 0x0ff80000, simple),
21625 + IFLD(K2, 2, 4, 0x00000030, simple),
21626 + IFLD(RD_E, 4, 0, 0x0000000f, simple),
21627 + IFLD(RD_DW, 3, 1, 0x0000000e, simple),
21628 + IFLD(X, 1, 5, 0x00000020, simple),
21629 + IFLD(Y, 1, 4, 0x00000010, simple),
21630 + IFLD(X2, 1, 13, 0x00002000, simple),
21631 + IFLD(Y2, 1, 12, 0x00001000, simple),
21632 + IFLD(K5E, 5, 0, 0x0000001f, simple),
21633 + IFLD(PART2, 2, 0, 0x00000003, simple),
21634 + IFLD(PART1, 1, 0, 0x00000001, simple),
21635 + IFLD(K16, 16, 0, 0x0000ffff, simple),
21636 + IFLD(CACHEOP, 5, 11, 0x0000f800, simple),
21637 + IFLD(K11, 11, 0, 0x000007ff, simple),
21638 + IFLD(K21, 21, 0, 0x1e10ffff, k21),
21639 + IFLD(CPOP, 7, 12, 0x060f1000, cpop),
21640 + IFLD(CPNO, 3, 13, 0x0000e000, simple),
21641 + IFLD(CRD_RI, 4, 8, 0x00000f00, simple),
21642 + IFLD(CRX, 4, 4, 0x000000f0, simple),
21643 + IFLD(CRY, 4, 0, 0x0000000f, simple),
21644 + IFLD(K7E, 7, 0, 0x0000007f, simple),
21645 + IFLD(CRD_DW, 3, 9, 0x00000e00, simple),
21646 + IFLD(PART1_K12, 1, 12, 0x00001000, simple),
21647 + IFLD(PART2_K12, 2, 12, 0x00003000, simple),
21648 + IFLD(K12, 12, 0, 0x00000fff, simple),
21649 + IFLD(S5, 5, 5, 0x000003e0, simple),
21650 + IFLD(K5E2, 5, 4, 0x000001f0, simple),
21651 + IFLD(K4, 4, 20, 0x00f00000, simple),
21652 + IFLD(COND4E2, 4, 4, 0x000000f0, simple),
21653 + IFLD(K8E2, 8, 4, 0x00000ff0, simple),
21654 + IFLD(K6, 6, 20, 0x03f00000, simple),
21655 + IFLD(MEM15, 15, 0, 0x00007fff, simple),
21656 + IFLD(MEMB5, 5, 15, 0x000f8000, simple),
21657 + IFLD(W, 1, 25, 0x02000000, simple),
21658 + /* Coprocessor Multiple High/Low */
21659 + IFLD(CM_HL, 1, 8, 0x00000100, simple),
21660 + IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp),
21661 + IFLD(K9E, 9 ,0, 0x000001ff, simple),
21662 + IFLD (FP_RX, 4, 4, 0x000000F0, simple),
21663 + IFLD (FP_RY, 4, 0, 0x0000000F, simple),
21664 + IFLD (FP_RD, 4, 8, 0x00000F00, simple),
21665 + IFLD (FP_RA, 4, 16, 0x000F0000, simple)
21670 +struct avr32_opcode avr32_opc_table[] =
21673 + AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000,
21674 + &avr32_syntax_table[AVR32_SYNTAX_ABS],
21675 + BFD_RELOC_UNUSED, 1, -1,
21677 + &avr32_ifield_table[AVR32_IFIELD_RY],
21681 + AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000,
21682 + &avr32_syntax_table[AVR32_SYNTAX_ACALL],
21683 + BFD_RELOC_UNUSED, 1, -1,
21685 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21689 + AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000,
21690 + &avr32_syntax_table[AVR32_SYNTAX_ACR],
21691 + BFD_RELOC_UNUSED, 1, -1,
21693 + &avr32_ifield_table[AVR32_IFIELD_RY],
21697 + AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0,
21698 + &avr32_syntax_table[AVR32_SYNTAX_ADC],
21699 + BFD_RELOC_UNUSED, 3, -1,
21701 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21702 + &avr32_ifield_table[AVR32_IFIELD_RX],
21703 + &avr32_ifield_table[AVR32_IFIELD_RY],
21707 + AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000,
21708 + &avr32_syntax_table[AVR32_SYNTAX_ADD1],
21709 + BFD_RELOC_UNUSED, 2, -1,
21711 + &avr32_ifield_table[AVR32_IFIELD_RY],
21712 + &avr32_ifield_table[AVR32_IFIELD_RX],
21716 + AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0,
21717 + &avr32_syntax_table[AVR32_SYNTAX_ADD2],
21718 + BFD_RELOC_UNUSED, 4, -1,
21720 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21721 + &avr32_ifield_table[AVR32_IFIELD_RX],
21722 + &avr32_ifield_table[AVR32_IFIELD_RY],
21723 + &avr32_ifield_table[AVR32_IFIELD_K2],
21727 + AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0,
21728 + &avr32_syntax_table[AVR32_SYNTAX_ADDABS],
21729 + BFD_RELOC_UNUSED, 3, -1,
21731 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21732 + &avr32_ifield_table[AVR32_IFIELD_RX],
21733 + &avr32_ifield_table[AVR32_IFIELD_RY],
21737 + AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0,
21738 + &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W],
21739 + BFD_RELOC_UNUSED, 5, -1,
21741 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21742 + &avr32_ifield_table[AVR32_IFIELD_RX],
21743 + &avr32_ifield_table[AVR32_IFIELD_X],
21744 + &avr32_ifield_table[AVR32_IFIELD_RY],
21745 + &avr32_ifield_table[AVR32_IFIELD_Y],
21749 + AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000,
21750 + &avr32_syntax_table[AVR32_SYNTAX_AND1],
21751 + BFD_RELOC_UNUSED, 2, -1,
21753 + &avr32_ifield_table[AVR32_IFIELD_RY],
21754 + &avr32_ifield_table[AVR32_IFIELD_RX],
21758 + AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00,
21759 + &avr32_syntax_table[AVR32_SYNTAX_AND2],
21760 + BFD_RELOC_UNUSED, 4, -1,
21762 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21763 + &avr32_ifield_table[AVR32_IFIELD_RX],
21764 + &avr32_ifield_table[AVR32_IFIELD_RY],
21765 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
21769 + AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00,
21770 + &avr32_syntax_table[AVR32_SYNTAX_AND3],
21771 + BFD_RELOC_UNUSED, 4, -1,
21773 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21774 + &avr32_ifield_table[AVR32_IFIELD_RX],
21775 + &avr32_ifield_table[AVR32_IFIELD_RY],
21776 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
21780 + AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000,
21781 + &avr32_syntax_table[AVR32_SYNTAX_ANDH],
21782 + BFD_RELOC_AVR32_16U, 2, 1,
21784 + &avr32_ifield_table[AVR32_IFIELD_RY],
21785 + &avr32_ifield_table[AVR32_IFIELD_K16],
21789 + AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000,
21790 + &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH],
21791 + BFD_RELOC_AVR32_16U, 2, 1,
21793 + &avr32_ifield_table[AVR32_IFIELD_RY],
21794 + &avr32_ifield_table[AVR32_IFIELD_K16],
21798 + AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000,
21799 + &avr32_syntax_table[AVR32_SYNTAX_ANDL],
21800 + BFD_RELOC_AVR32_16U, 2, 1,
21802 + &avr32_ifield_table[AVR32_IFIELD_RY],
21803 + &avr32_ifield_table[AVR32_IFIELD_K16],
21807 + AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000,
21808 + &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH],
21809 + BFD_RELOC_AVR32_16U, 2, 1,
21811 + &avr32_ifield_table[AVR32_IFIELD_RY],
21812 + &avr32_ifield_table[AVR32_IFIELD_K16],
21816 + AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000,
21817 + &avr32_syntax_table[AVR32_SYNTAX_ANDN],
21818 + BFD_RELOC_UNUSED, 2, -1,
21820 + &avr32_ifield_table[AVR32_IFIELD_RY],
21821 + &avr32_ifield_table[AVR32_IFIELD_RX],
21825 + AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0,
21826 + &avr32_syntax_table[AVR32_SYNTAX_ASR1],
21827 + BFD_RELOC_UNUSED, 3, -1,
21829 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
21830 + &avr32_ifield_table[AVR32_IFIELD_RX],
21831 + &avr32_ifield_table[AVR32_IFIELD_RY],
21835 + AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0,
21836 + &avr32_syntax_table[AVR32_SYNTAX_ASR3],
21837 + BFD_RELOC_UNUSED, 3, -1,
21839 + &avr32_ifield_table[AVR32_IFIELD_RY],
21840 + &avr32_ifield_table[AVR32_IFIELD_RX],
21841 + &avr32_ifield_table[AVR32_IFIELD_K5E],
21845 + AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000,
21846 + &avr32_syntax_table[AVR32_SYNTAX_ASR2],
21847 + BFD_RELOC_UNUSED, 2, -1,
21849 + &avr32_ifield_table[AVR32_IFIELD_RY],
21850 + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21854 + AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0,
21855 + &avr32_syntax_table[AVR32_SYNTAX_BLD],
21856 + BFD_RELOC_UNUSED, 2, -1,
21858 + &avr32_ifield_table[AVR32_IFIELD_RY],
21859 + &avr32_ifield_table[AVR32_IFIELD_K5E],
21863 + AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000,
21864 + &avr32_syntax_table[AVR32_SYNTAX_BREQ1],
21865 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21867 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21871 + AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000,
21872 + &avr32_syntax_table[AVR32_SYNTAX_BRNE1],
21873 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21875 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21879 + AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000,
21880 + &avr32_syntax_table[AVR32_SYNTAX_BRCC1],
21881 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21883 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21887 + AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000,
21888 + &avr32_syntax_table[AVR32_SYNTAX_BRCS1],
21889 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21891 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21895 + AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000,
21896 + &avr32_syntax_table[AVR32_SYNTAX_BRGE1],
21897 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21899 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21903 + AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000,
21904 + &avr32_syntax_table[AVR32_SYNTAX_BRLT1],
21905 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21907 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21911 + AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000,
21912 + &avr32_syntax_table[AVR32_SYNTAX_BRMI1],
21913 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21915 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21919 + AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000,
21920 + &avr32_syntax_table[AVR32_SYNTAX_BRPL1],
21921 + BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21923 + &avr32_ifield_table[AVR32_IFIELD_K8C],
21927 + AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000,
21928 + &avr32_syntax_table[AVR32_SYNTAX_BREQ2],
21929 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21931 + &avr32_ifield_table[AVR32_IFIELD_K21],
21935 + AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000,
21936 + &avr32_syntax_table[AVR32_SYNTAX_BRNE2],
21937 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21939 + &avr32_ifield_table[AVR32_IFIELD_K21],
21943 + AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000,
21944 + &avr32_syntax_table[AVR32_SYNTAX_BRHS2],
21945 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21947 + &avr32_ifield_table[AVR32_IFIELD_K21],
21951 + AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000,
21952 + &avr32_syntax_table[AVR32_SYNTAX_BRLO2],
21953 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21955 + &avr32_ifield_table[AVR32_IFIELD_K21],
21959 + AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000,
21960 + &avr32_syntax_table[AVR32_SYNTAX_BRGE2],
21961 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21963 + &avr32_ifield_table[AVR32_IFIELD_K21],
21967 + AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000,
21968 + &avr32_syntax_table[AVR32_SYNTAX_BRLT2],
21969 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21971 + &avr32_ifield_table[AVR32_IFIELD_K21],
21975 + AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000,
21976 + &avr32_syntax_table[AVR32_SYNTAX_BRMI2],
21977 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21979 + &avr32_ifield_table[AVR32_IFIELD_K21],
21983 + AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000,
21984 + &avr32_syntax_table[AVR32_SYNTAX_BRPL2],
21985 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21987 + &avr32_ifield_table[AVR32_IFIELD_K21],
21991 + AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000,
21992 + &avr32_syntax_table[AVR32_SYNTAX_BRLS],
21993 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21995 + &avr32_ifield_table[AVR32_IFIELD_K21],
21999 + AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000,
22000 + &avr32_syntax_table[AVR32_SYNTAX_BRGT],
22001 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22003 + &avr32_ifield_table[AVR32_IFIELD_K21],
22007 + AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000,
22008 + &avr32_syntax_table[AVR32_SYNTAX_BRLE],
22009 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22011 + &avr32_ifield_table[AVR32_IFIELD_K21],
22015 + AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000,
22016 + &avr32_syntax_table[AVR32_SYNTAX_BRHI],
22017 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22019 + &avr32_ifield_table[AVR32_IFIELD_K21],
22023 + AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000,
22024 + &avr32_syntax_table[AVR32_SYNTAX_BRVS],
22025 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22027 + &avr32_ifield_table[AVR32_IFIELD_K21],
22031 + AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000,
22032 + &avr32_syntax_table[AVR32_SYNTAX_BRVC],
22033 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22035 + &avr32_ifield_table[AVR32_IFIELD_K21],
22039 + AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000,
22040 + &avr32_syntax_table[AVR32_SYNTAX_BRQS],
22041 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22043 + &avr32_ifield_table[AVR32_IFIELD_K21],
22047 + AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000,
22048 + &avr32_syntax_table[AVR32_SYNTAX_BRAL],
22049 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22051 + &avr32_ifield_table[AVR32_IFIELD_K21],
22055 + AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000,
22056 + &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT],
22057 + BFD_RELOC_UNUSED, 0, -1, { NULL },
22060 + AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000,
22061 + &avr32_syntax_table[AVR32_SYNTAX_BREV],
22062 + BFD_RELOC_UNUSED, 1, -1,
22064 + &avr32_ifield_table[AVR32_IFIELD_RY],
22068 + AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0,
22069 + &avr32_syntax_table[AVR32_SYNTAX_BST],
22070 + BFD_RELOC_UNUSED, 2, -1,
22072 + &avr32_ifield_table[AVR32_IFIELD_RY],
22073 + &avr32_ifield_table[AVR32_IFIELD_K5E],
22077 + AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000,
22078 + &avr32_syntax_table[AVR32_SYNTAX_CACHE],
22079 + BFD_RELOC_UNUSED, 3, -1,
22081 + &avr32_ifield_table[AVR32_IFIELD_RY],
22082 + &avr32_ifield_table[AVR32_IFIELD_K11],
22083 + &avr32_ifield_table[AVR32_IFIELD_CACHEOP],
22087 + AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000,
22088 + &avr32_syntax_table[AVR32_SYNTAX_CASTS_B],
22089 + BFD_RELOC_UNUSED, 1, -1,
22091 + &avr32_ifield_table[AVR32_IFIELD_RY],
22095 + AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000,
22096 + &avr32_syntax_table[AVR32_SYNTAX_CASTS_H],
22097 + BFD_RELOC_UNUSED, 1, -1,
22099 + &avr32_ifield_table[AVR32_IFIELD_RY],
22103 + AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000,
22104 + &avr32_syntax_table[AVR32_SYNTAX_CASTU_B],
22105 + BFD_RELOC_UNUSED, 1, -1,
22107 + &avr32_ifield_table[AVR32_IFIELD_RY],
22111 + AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000,
22112 + &avr32_syntax_table[AVR32_SYNTAX_CASTU_H],
22113 + BFD_RELOC_UNUSED, 1, -1,
22115 + &avr32_ifield_table[AVR32_IFIELD_RY],
22119 + AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000,
22120 + &avr32_syntax_table[AVR32_SYNTAX_CBR],
22121 + BFD_RELOC_UNUSED, 2, -1,
22123 + &avr32_ifield_table[AVR32_IFIELD_RY],
22124 + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22128 + AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff,
22129 + &avr32_syntax_table[AVR32_SYNTAX_CLZ],
22130 + BFD_RELOC_UNUSED, 2, -1,
22132 + &avr32_ifield_table[AVR32_IFIELD_RY],
22133 + &avr32_ifield_table[AVR32_IFIELD_RX],
22137 + AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000,
22138 + &avr32_syntax_table[AVR32_SYNTAX_COM],
22139 + BFD_RELOC_UNUSED, 1, -1,
22141 + &avr32_ifield_table[AVR32_IFIELD_RY],
22145 + AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000,
22146 + &avr32_syntax_table[AVR32_SYNTAX_COP],
22147 + BFD_RELOC_UNUSED, 5, -1,
22149 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22150 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22151 + &avr32_ifield_table[AVR32_IFIELD_CRX],
22152 + &avr32_ifield_table[AVR32_IFIELD_CRY],
22153 + &avr32_ifield_table[AVR32_IFIELD_CPOP],
22157 + AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff,
22158 + &avr32_syntax_table[AVR32_SYNTAX_CP_B],
22159 + BFD_RELOC_UNUSED, 2, -1,
22161 + &avr32_ifield_table[AVR32_IFIELD_RY],
22162 + &avr32_ifield_table[AVR32_IFIELD_RX],
22166 + AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff,
22167 + &avr32_syntax_table[AVR32_SYNTAX_CP_H],
22168 + BFD_RELOC_UNUSED, 2, -1,
22170 + &avr32_ifield_table[AVR32_IFIELD_RY],
22171 + &avr32_ifield_table[AVR32_IFIELD_RX],
22175 + AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000,
22176 + &avr32_syntax_table[AVR32_SYNTAX_CP_W1],
22177 + BFD_RELOC_UNUSED, 2, -1,
22179 + &avr32_ifield_table[AVR32_IFIELD_RY],
22180 + &avr32_ifield_table[AVR32_IFIELD_RX],
22184 + AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000,
22185 + &avr32_syntax_table[AVR32_SYNTAX_CP_W2],
22186 + BFD_RELOC_AVR32_6S, 2, 1,
22188 + &avr32_ifield_table[AVR32_IFIELD_RY],
22189 + &avr32_ifield_table[AVR32_IFIELD_K6],
22193 + AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000,
22194 + &avr32_syntax_table[AVR32_SYNTAX_CP_W3],
22195 + BFD_RELOC_AVR32_21S, 2, 1,
22197 + &avr32_ifield_table[AVR32_IFIELD_RY],
22198 + &avr32_ifield_table[AVR32_IFIELD_K21],
22202 + AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff,
22203 + &avr32_syntax_table[AVR32_SYNTAX_CPC1],
22204 + BFD_RELOC_UNUSED, 2, -1,
22206 + &avr32_ifield_table[AVR32_IFIELD_RY],
22207 + &avr32_ifield_table[AVR32_IFIELD_RX],
22211 + AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000,
22212 + &avr32_syntax_table[AVR32_SYNTAX_CPC2],
22213 + BFD_RELOC_UNUSED, 1, -1,
22215 + &avr32_ifield_table[AVR32_IFIELD_RY],
22219 + AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000,
22220 + &avr32_syntax_table[AVR32_SYNTAX_CSRF],
22221 + BFD_RELOC_UNUSED, 1, -1,
22223 + &avr32_ifield_table[AVR32_IFIELD_K5C],
22227 + AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000,
22228 + &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ],
22229 + BFD_RELOC_UNUSED, 1, -1,
22231 + &avr32_ifield_table[AVR32_IFIELD_K5C],
22235 + AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0,
22236 + &avr32_syntax_table[AVR32_SYNTAX_DIVS],
22237 + BFD_RELOC_UNUSED, 3, -1,
22239 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22240 + &avr32_ifield_table[AVR32_IFIELD_RX],
22241 + &avr32_ifield_table[AVR32_IFIELD_RY],
22245 + AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0,
22246 + &avr32_syntax_table[AVR32_SYNTAX_DIVU],
22247 + BFD_RELOC_UNUSED, 3, -1,
22249 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22250 + &avr32_ifield_table[AVR32_IFIELD_RX],
22251 + &avr32_ifield_table[AVR32_IFIELD_RY],
22255 + AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000,
22256 + &avr32_syntax_table[AVR32_SYNTAX_EOR1],
22257 + BFD_RELOC_UNUSED, 2, -1,
22259 + &avr32_ifield_table[AVR32_IFIELD_RY],
22260 + &avr32_ifield_table[AVR32_IFIELD_RX],
22264 + AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00,
22265 + &avr32_syntax_table[AVR32_SYNTAX_EOR2],
22266 + BFD_RELOC_UNUSED, 4, -1,
22268 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22269 + &avr32_ifield_table[AVR32_IFIELD_RX],
22270 + &avr32_ifield_table[AVR32_IFIELD_RY],
22271 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
22275 + AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00,
22276 + &avr32_syntax_table[AVR32_SYNTAX_EOR3],
22277 + BFD_RELOC_UNUSED, 4, -1,
22279 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22280 + &avr32_ifield_table[AVR32_IFIELD_RX],
22281 + &avr32_ifield_table[AVR32_IFIELD_RY],
22282 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
22286 + AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000,
22287 + &avr32_syntax_table[AVR32_SYNTAX_EORL],
22288 + BFD_RELOC_AVR32_16U, 2, 1,
22290 + &avr32_ifield_table[AVR32_IFIELD_RY],
22291 + &avr32_ifield_table[AVR32_IFIELD_K16],
22295 + AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000,
22296 + &avr32_syntax_table[AVR32_SYNTAX_EORH],
22297 + BFD_RELOC_AVR32_16U, 2, 1,
22299 + &avr32_ifield_table[AVR32_IFIELD_RY],
22300 + &avr32_ifield_table[AVR32_IFIELD_K16],
22304 + AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000,
22305 + &avr32_syntax_table[AVR32_SYNTAX_FRS],
22306 + BFD_RELOC_UNUSED, 0, -1, { NULL },
22309 + AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000,
22310 + &avr32_syntax_table[AVR32_SYNTAX_ICALL],
22311 + BFD_RELOC_UNUSED, 1, -1,
22313 + &avr32_ifield_table[AVR32_IFIELD_RY],
22317 + AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000,
22318 + &avr32_syntax_table[AVR32_SYNTAX_INCJOSP],
22319 + BFD_RELOC_UNUSED, 1, -1,
22321 + &avr32_ifield_table[AVR32_IFIELD_K3],
22325 + AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000,
22326 + &avr32_syntax_table[AVR32_SYNTAX_LD_D1],
22327 + BFD_RELOC_UNUSED, 2, -1,
22329 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22330 + &avr32_ifield_table[AVR32_IFIELD_RX],
22334 + AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000,
22335 + &avr32_syntax_table[AVR32_SYNTAX_LD_D2],
22336 + BFD_RELOC_UNUSED, 2, -1,
22338 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22339 + &avr32_ifield_table[AVR32_IFIELD_RX],
22343 + AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000,
22344 + &avr32_syntax_table[AVR32_SYNTAX_LD_D3],
22345 + BFD_RELOC_UNUSED, 2, -1,
22347 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22348 + &avr32_ifield_table[AVR32_IFIELD_RX],
22352 + AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1,
22353 + &avr32_syntax_table[AVR32_SYNTAX_LD_D5],
22354 + BFD_RELOC_UNUSED, 4, -1,
22356 + &avr32_ifield_table[AVR32_IFIELD_RD_DW],
22357 + &avr32_ifield_table[AVR32_IFIELD_RX],
22358 + &avr32_ifield_table[AVR32_IFIELD_RY],
22359 + &avr32_ifield_table[AVR32_IFIELD_K2],
22363 + AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000,
22364 + &avr32_syntax_table[AVR32_SYNTAX_LD_D4],
22365 + BFD_RELOC_AVR32_16S, 3, 2,
22367 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22368 + &avr32_ifield_table[AVR32_IFIELD_RX],
22369 + &avr32_ifield_table[AVR32_IFIELD_K16],
22373 + AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0,
22374 + &avr32_syntax_table[AVR32_SYNTAX_LD_SB2],
22375 + BFD_RELOC_UNUSED, 4, -1,
22377 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22378 + &avr32_ifield_table[AVR32_IFIELD_RX],
22379 + &avr32_ifield_table[AVR32_IFIELD_RY],
22380 + &avr32_ifield_table[AVR32_IFIELD_K2],
22384 + AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000,
22385 + &avr32_syntax_table[AVR32_SYNTAX_LD_SB1],
22386 + BFD_RELOC_AVR32_16S, 3, -1,
22388 + &avr32_ifield_table[AVR32_IFIELD_RY],
22389 + &avr32_ifield_table[AVR32_IFIELD_RX],
22390 + &avr32_ifield_table[AVR32_IFIELD_K16],
22394 + AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000,
22395 + &avr32_syntax_table[AVR32_SYNTAX_LD_UB1],
22396 + BFD_RELOC_UNUSED, 2, -1,
22398 + &avr32_ifield_table[AVR32_IFIELD_RY],
22399 + &avr32_ifield_table[AVR32_IFIELD_RX],
22403 + AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000,
22404 + &avr32_syntax_table[AVR32_SYNTAX_LD_UB2],
22405 + BFD_RELOC_UNUSED, 2, -1,
22407 + &avr32_ifield_table[AVR32_IFIELD_RY],
22408 + &avr32_ifield_table[AVR32_IFIELD_RX],
22412 + AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0,
22413 + &avr32_syntax_table[AVR32_SYNTAX_LD_UB5],
22414 + BFD_RELOC_UNUSED, 4, -1,
22416 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22417 + &avr32_ifield_table[AVR32_IFIELD_RX],
22418 + &avr32_ifield_table[AVR32_IFIELD_RY],
22419 + &avr32_ifield_table[AVR32_IFIELD_K2],
22423 + AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000,
22424 + &avr32_syntax_table[AVR32_SYNTAX_LD_UB3],
22425 + BFD_RELOC_AVR32_3U, 3, 2,
22427 + &avr32_ifield_table[AVR32_IFIELD_RY],
22428 + &avr32_ifield_table[AVR32_IFIELD_RX],
22429 + &avr32_ifield_table[AVR32_IFIELD_K3],
22433 + AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000,
22434 + &avr32_syntax_table[AVR32_SYNTAX_LD_UB4],
22435 + BFD_RELOC_AVR32_16S, 3, 2,
22437 + &avr32_ifield_table[AVR32_IFIELD_RY],
22438 + &avr32_ifield_table[AVR32_IFIELD_RX],
22439 + &avr32_ifield_table[AVR32_IFIELD_K16],
22443 + AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000,
22444 + &avr32_syntax_table[AVR32_SYNTAX_LD_SH1],
22445 + BFD_RELOC_UNUSED, 2, -1,
22447 + &avr32_ifield_table[AVR32_IFIELD_RY],
22448 + &avr32_ifield_table[AVR32_IFIELD_RX],
22452 + AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000,
22453 + &avr32_syntax_table[AVR32_SYNTAX_LD_SH2],
22454 + BFD_RELOC_UNUSED, 2, -1,
22456 + &avr32_ifield_table[AVR32_IFIELD_RY],
22457 + &avr32_ifield_table[AVR32_IFIELD_RX],
22461 + AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0,
22462 + &avr32_syntax_table[AVR32_SYNTAX_LD_SH5],
22463 + BFD_RELOC_UNUSED, 4, -1,
22465 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22466 + &avr32_ifield_table[AVR32_IFIELD_RX],
22467 + &avr32_ifield_table[AVR32_IFIELD_RY],
22468 + &avr32_ifield_table[AVR32_IFIELD_K2],
22472 + AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000,
22473 + &avr32_syntax_table[AVR32_SYNTAX_LD_SH3],
22474 + BFD_RELOC_AVR32_4UH, 3, 2,
22476 + &avr32_ifield_table[AVR32_IFIELD_RY],
22477 + &avr32_ifield_table[AVR32_IFIELD_RX],
22478 + &avr32_ifield_table[AVR32_IFIELD_K3],
22482 + AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000,
22483 + &avr32_syntax_table[AVR32_SYNTAX_LD_SH4],
22484 + BFD_RELOC_AVR32_16S, 3, 2,
22486 + &avr32_ifield_table[AVR32_IFIELD_RY],
22487 + &avr32_ifield_table[AVR32_IFIELD_RX],
22488 + &avr32_ifield_table[AVR32_IFIELD_K16],
22492 + AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000,
22493 + &avr32_syntax_table[AVR32_SYNTAX_LD_UH1],
22494 + BFD_RELOC_UNUSED, 2, -1,
22496 + &avr32_ifield_table[AVR32_IFIELD_RY],
22497 + &avr32_ifield_table[AVR32_IFIELD_RX],
22501 + AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000,
22502 + &avr32_syntax_table[AVR32_SYNTAX_LD_UH2],
22503 + BFD_RELOC_UNUSED, 2, -1,
22505 + &avr32_ifield_table[AVR32_IFIELD_RY],
22506 + &avr32_ifield_table[AVR32_IFIELD_RX],
22510 + AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0,
22511 + &avr32_syntax_table[AVR32_SYNTAX_LD_UH5],
22512 + BFD_RELOC_UNUSED, 4, -1,
22514 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22515 + &avr32_ifield_table[AVR32_IFIELD_RX],
22516 + &avr32_ifield_table[AVR32_IFIELD_RY],
22517 + &avr32_ifield_table[AVR32_IFIELD_K2],
22521 + AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000,
22522 + &avr32_syntax_table[AVR32_SYNTAX_LD_UH3],
22523 + BFD_RELOC_AVR32_4UH, 3, 2,
22525 + &avr32_ifield_table[AVR32_IFIELD_RY],
22526 + &avr32_ifield_table[AVR32_IFIELD_RX],
22527 + &avr32_ifield_table[AVR32_IFIELD_K3],
22531 + AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000,
22532 + &avr32_syntax_table[AVR32_SYNTAX_LD_UH4],
22533 + BFD_RELOC_AVR32_16S, 3, 2,
22535 + &avr32_ifield_table[AVR32_IFIELD_RY],
22536 + &avr32_ifield_table[AVR32_IFIELD_RX],
22537 + &avr32_ifield_table[AVR32_IFIELD_K16],
22541 + AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000,
22542 + &avr32_syntax_table[AVR32_SYNTAX_LD_W1],
22543 + BFD_RELOC_UNUSED, 2, -1,
22545 + &avr32_ifield_table[AVR32_IFIELD_RY],
22546 + &avr32_ifield_table[AVR32_IFIELD_RX],
22550 + AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000,
22551 + &avr32_syntax_table[AVR32_SYNTAX_LD_W2],
22552 + BFD_RELOC_UNUSED, 2, -1,
22554 + &avr32_ifield_table[AVR32_IFIELD_RY],
22555 + &avr32_ifield_table[AVR32_IFIELD_RX],
22559 + AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0,
22560 + &avr32_syntax_table[AVR32_SYNTAX_LD_W5],
22561 + BFD_RELOC_UNUSED, 4, -1,
22563 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22564 + &avr32_ifield_table[AVR32_IFIELD_RX],
22565 + &avr32_ifield_table[AVR32_IFIELD_RY],
22566 + &avr32_ifield_table[AVR32_IFIELD_K2],
22570 + AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0,
22571 + &avr32_syntax_table[AVR32_SYNTAX_LD_W6],
22572 + BFD_RELOC_UNUSED, 4, -1,
22574 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22575 + &avr32_ifield_table[AVR32_IFIELD_RX],
22576 + &avr32_ifield_table[AVR32_IFIELD_RY],
22577 + &avr32_ifield_table[AVR32_IFIELD_K2],
22581 + AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000,
22582 + &avr32_syntax_table[AVR32_SYNTAX_LD_W3],
22583 + BFD_RELOC_AVR32_7UW, 3, 2,
22585 + &avr32_ifield_table[AVR32_IFIELD_RY],
22586 + &avr32_ifield_table[AVR32_IFIELD_RX],
22587 + &avr32_ifield_table[AVR32_IFIELD_K5C],
22591 + AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000,
22592 + &avr32_syntax_table[AVR32_SYNTAX_LD_W4],
22593 + BFD_RELOC_AVR32_16S, 3, 2,
22595 + &avr32_ifield_table[AVR32_IFIELD_RY],
22596 + &avr32_ifield_table[AVR32_IFIELD_RX],
22597 + &avr32_ifield_table[AVR32_IFIELD_K16],
22601 + AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100,
22602 + &avr32_syntax_table[AVR32_SYNTAX_LDC_D1],
22603 + BFD_RELOC_AVR32_10UW, 4, 3,
22605 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22606 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22607 + &avr32_ifield_table[AVR32_IFIELD_RY],
22608 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22612 + AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff,
22613 + &avr32_syntax_table[AVR32_SYNTAX_LDC_D2],
22614 + BFD_RELOC_UNUSED, 3, -1,
22616 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22617 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22618 + &avr32_ifield_table[AVR32_IFIELD_RY],
22622 + AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0,
22623 + &avr32_syntax_table[AVR32_SYNTAX_LDC_D3],
22624 + BFD_RELOC_UNUSED, 5, -1,
22626 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22627 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22628 + &avr32_ifield_table[AVR32_IFIELD_RY],
22629 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22630 + &avr32_ifield_table[AVR32_IFIELD_K2],
22634 + AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000,
22635 + &avr32_syntax_table[AVR32_SYNTAX_LDC_W1],
22636 + BFD_RELOC_AVR32_10UW, 4, 3,
22638 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22639 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22640 + &avr32_ifield_table[AVR32_IFIELD_RY],
22641 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22645 + AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff,
22646 + &avr32_syntax_table[AVR32_SYNTAX_LDC_W2],
22647 + BFD_RELOC_UNUSED, 3, -1,
22649 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22650 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22651 + &avr32_ifield_table[AVR32_IFIELD_RY],
22655 + AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0,
22656 + &avr32_syntax_table[AVR32_SYNTAX_LDC_W3],
22657 + BFD_RELOC_UNUSED, 5, -1,
22659 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22660 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22661 + &avr32_ifield_table[AVR32_IFIELD_RY],
22662 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22663 + &avr32_ifield_table[AVR32_IFIELD_K2],
22667 + AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100,
22668 + &avr32_syntax_table[AVR32_SYNTAX_LDC0_D],
22669 + BFD_RELOC_AVR32_14UW, 3, 2,
22671 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22672 + &avr32_ifield_table[AVR32_IFIELD_RY],
22673 + &avr32_ifield_table[AVR32_IFIELD_K12CP],
22677 + AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000,
22678 + &avr32_syntax_table[AVR32_SYNTAX_LDC0_W],
22679 + BFD_RELOC_AVR32_14UW, 3, 2,
22681 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22682 + &avr32_ifield_table[AVR32_IFIELD_RY],
22683 + &avr32_ifield_table[AVR32_IFIELD_K12CP],
22687 + AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00,
22688 + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D],
22689 + BFD_RELOC_UNUSED, 3, -1,
22691 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22692 + &avr32_ifield_table[AVR32_IFIELD_RY],
22693 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22697 + AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00,
22698 + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU],
22699 + BFD_RELOC_UNUSED, 3, -1,
22701 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22702 + &avr32_ifield_table[AVR32_IFIELD_RY],
22703 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22707 + AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00,
22708 + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W],
22709 + BFD_RELOC_UNUSED, 4, -1,
22711 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22712 + &avr32_ifield_table[AVR32_IFIELD_RY],
22713 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22714 + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22718 + AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00,
22719 + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU],
22720 + BFD_RELOC_UNUSED, 4, -1,
22722 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
22723 + &avr32_ifield_table[AVR32_IFIELD_RY],
22724 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22725 + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22729 + AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000,
22730 + &avr32_syntax_table[AVR32_SYNTAX_LDDPC],
22731 + BFD_RELOC_AVR32_9UW_PCREL, 2, 1,
22733 + &avr32_ifield_table[AVR32_IFIELD_RY],
22734 + &avr32_ifield_table[AVR32_IFIELD_K7C],
22738 + AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000,
22739 + &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT],
22740 + BFD_RELOC_AVR32_16B_PCREL, 2, 1,
22742 + &avr32_ifield_table[AVR32_IFIELD_RY],
22743 + &avr32_ifield_table[AVR32_IFIELD_K16],
22747 + AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000,
22748 + &avr32_syntax_table[AVR32_SYNTAX_LDDSP],
22749 + BFD_RELOC_UNUSED, 2, -1,
22751 + &avr32_ifield_table[AVR32_IFIELD_RY],
22752 + &avr32_ifield_table[AVR32_IFIELD_K7C],
22756 + AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000,
22757 + &avr32_syntax_table[AVR32_SYNTAX_LDINS_B],
22758 + BFD_RELOC_UNUSED, 4, -1,
22760 + &avr32_ifield_table[AVR32_IFIELD_RY],
22761 + &avr32_ifield_table[AVR32_IFIELD_PART2_K12],
22762 + &avr32_ifield_table[AVR32_IFIELD_RX],
22763 + &avr32_ifield_table[AVR32_IFIELD_K12],
22767 + AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000,
22768 + &avr32_syntax_table[AVR32_SYNTAX_LDINS_H],
22769 + BFD_RELOC_UNUSED, 4, -1,
22771 + &avr32_ifield_table[AVR32_IFIELD_RY],
22772 + &avr32_ifield_table[AVR32_IFIELD_PART1_K12],
22773 + &avr32_ifield_table[AVR32_IFIELD_RX],
22774 + &avr32_ifield_table[AVR32_IFIELD_K12],
22778 + AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000,
22779 + &avr32_syntax_table[AVR32_SYNTAX_LDM],
22780 + BFD_RELOC_UNUSED, 3, -1,
22782 + &avr32_ifield_table[AVR32_IFIELD_RY],
22783 + &avr32_ifield_table[AVR32_IFIELD_W],
22784 + &avr32_ifield_table[AVR32_IFIELD_K16],
22788 + AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000,
22789 + &avr32_syntax_table[AVR32_SYNTAX_LDMTS],
22790 + BFD_RELOC_UNUSED, 2, -1,
22792 + &avr32_ifield_table[AVR32_IFIELD_RY],
22793 + &avr32_ifield_table[AVR32_IFIELD_K16],
22797 + AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000,
22798 + &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU],
22799 + BFD_RELOC_UNUSED, 2, -1,
22801 + &avr32_ifield_table[AVR32_IFIELD_RY],
22802 + &avr32_ifield_table[AVR32_IFIELD_K16],
22806 + AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000,
22807 + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH],
22808 + BFD_RELOC_UNUSED, 3, -1,
22810 + &avr32_ifield_table[AVR32_IFIELD_RY],
22811 + &avr32_ifield_table[AVR32_IFIELD_RX],
22812 + &avr32_ifield_table[AVR32_IFIELD_K12],
22816 + AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000,
22817 + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH],
22818 + BFD_RELOC_UNUSED, 3, -1,
22820 + &avr32_ifield_table[AVR32_IFIELD_RY],
22821 + &avr32_ifield_table[AVR32_IFIELD_RX],
22822 + &avr32_ifield_table[AVR32_IFIELD_K12],
22826 + AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000,
22827 + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W],
22828 + BFD_RELOC_UNUSED, 3, -1,
22830 + &avr32_ifield_table[AVR32_IFIELD_RY],
22831 + &avr32_ifield_table[AVR32_IFIELD_RX],
22832 + &avr32_ifield_table[AVR32_IFIELD_K12],
22836 + AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0,
22837 + &avr32_syntax_table[AVR32_SYNTAX_LSL1],
22838 + BFD_RELOC_UNUSED, 3, -1,
22840 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22841 + &avr32_ifield_table[AVR32_IFIELD_RX],
22842 + &avr32_ifield_table[AVR32_IFIELD_RY],
22846 + AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0,
22847 + &avr32_syntax_table[AVR32_SYNTAX_LSL3],
22848 + BFD_RELOC_UNUSED, 3, -1,
22850 + &avr32_ifield_table[AVR32_IFIELD_RY],
22851 + &avr32_ifield_table[AVR32_IFIELD_RX],
22852 + &avr32_ifield_table[AVR32_IFIELD_K5E],
22856 + AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000,
22857 + &avr32_syntax_table[AVR32_SYNTAX_LSL2],
22858 + BFD_RELOC_UNUSED, 2, -1,
22860 + &avr32_ifield_table[AVR32_IFIELD_RY],
22861 + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22865 + AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0,
22866 + &avr32_syntax_table[AVR32_SYNTAX_LSR1],
22867 + BFD_RELOC_UNUSED, 3, -1,
22869 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22870 + &avr32_ifield_table[AVR32_IFIELD_RX],
22871 + &avr32_ifield_table[AVR32_IFIELD_RY],
22875 + AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0,
22876 + &avr32_syntax_table[AVR32_SYNTAX_LSR3],
22877 + BFD_RELOC_UNUSED, 3, -1,
22879 + &avr32_ifield_table[AVR32_IFIELD_RY],
22880 + &avr32_ifield_table[AVR32_IFIELD_RX],
22881 + &avr32_ifield_table[AVR32_IFIELD_K5E],
22885 + AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000,
22886 + &avr32_syntax_table[AVR32_SYNTAX_LSR2],
22887 + BFD_RELOC_UNUSED, 2, -1,
22889 + &avr32_ifield_table[AVR32_IFIELD_RY],
22890 + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22894 + AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0,
22895 + &avr32_syntax_table[AVR32_SYNTAX_MAC],
22896 + BFD_RELOC_UNUSED, 3, -1,
22898 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22899 + &avr32_ifield_table[AVR32_IFIELD_RX],
22900 + &avr32_ifield_table[AVR32_IFIELD_RY],
22904 + AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1,
22905 + &avr32_syntax_table[AVR32_SYNTAX_MACHH_D],
22906 + BFD_RELOC_UNUSED, 5, -1,
22908 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22909 + &avr32_ifield_table[AVR32_IFIELD_RX],
22910 + &avr32_ifield_table[AVR32_IFIELD_X],
22911 + &avr32_ifield_table[AVR32_IFIELD_RY],
22912 + &avr32_ifield_table[AVR32_IFIELD_Y],
22916 + AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0,
22917 + &avr32_syntax_table[AVR32_SYNTAX_MACHH_W],
22918 + BFD_RELOC_UNUSED, 5, -1,
22920 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22921 + &avr32_ifield_table[AVR32_IFIELD_RX],
22922 + &avr32_ifield_table[AVR32_IFIELD_X],
22923 + &avr32_ifield_table[AVR32_IFIELD_RY],
22924 + &avr32_ifield_table[AVR32_IFIELD_Y],
22928 + AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1,
22929 + &avr32_syntax_table[AVR32_SYNTAX_MACS_D],
22930 + BFD_RELOC_UNUSED, 3, -1,
22932 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22933 + &avr32_ifield_table[AVR32_IFIELD_RX],
22934 + &avr32_ifield_table[AVR32_IFIELD_RY],
22938 + AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0,
22939 + &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W],
22940 + BFD_RELOC_UNUSED, 5, -1,
22942 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22943 + &avr32_ifield_table[AVR32_IFIELD_RX],
22944 + &avr32_ifield_table[AVR32_IFIELD_X],
22945 + &avr32_ifield_table[AVR32_IFIELD_RY],
22946 + &avr32_ifield_table[AVR32_IFIELD_Y],
22950 + AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1,
22951 + &avr32_syntax_table[AVR32_SYNTAX_MACUD],
22952 + BFD_RELOC_UNUSED, 3, -1,
22954 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22955 + &avr32_ifield_table[AVR32_IFIELD_RX],
22956 + &avr32_ifield_table[AVR32_IFIELD_RY],
22960 + AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1,
22961 + &avr32_syntax_table[AVR32_SYNTAX_MACWH_D],
22962 + BFD_RELOC_UNUSED, 4, -1,
22964 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22965 + &avr32_ifield_table[AVR32_IFIELD_RX],
22966 + &avr32_ifield_table[AVR32_IFIELD_RY],
22967 + &avr32_ifield_table[AVR32_IFIELD_Y],
22971 + AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0,
22972 + &avr32_syntax_table[AVR32_SYNTAX_MAX],
22973 + BFD_RELOC_UNUSED, 3, -1,
22975 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
22976 + &avr32_ifield_table[AVR32_IFIELD_RX],
22977 + &avr32_ifield_table[AVR32_IFIELD_RY],
22981 + AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000,
22982 + &avr32_syntax_table[AVR32_SYNTAX_MCALL],
22983 + BFD_RELOC_AVR32_18W_PCREL, 2, 1,
22985 + &avr32_ifield_table[AVR32_IFIELD_RY],
22986 + &avr32_ifield_table[AVR32_IFIELD_K16],
22990 + AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00,
22991 + &avr32_syntax_table[AVR32_SYNTAX_MFDR],
22992 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
22994 + &avr32_ifield_table[AVR32_IFIELD_RY],
22995 + &avr32_ifield_table[AVR32_IFIELD_K8E],
22999 + AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00,
23000 + &avr32_syntax_table[AVR32_SYNTAX_MFSR],
23001 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23003 + &avr32_ifield_table[AVR32_IFIELD_RY],
23004 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23008 + AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0,
23009 + &avr32_syntax_table[AVR32_SYNTAX_MIN],
23010 + BFD_RELOC_UNUSED, 3, -1,
23012 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23013 + &avr32_ifield_table[AVR32_IFIELD_RX],
23014 + &avr32_ifield_table[AVR32_IFIELD_RY],
23018 + AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000,
23019 + &avr32_syntax_table[AVR32_SYNTAX_MOV3],
23020 + BFD_RELOC_NONE, 2, -1,
23022 + &avr32_ifield_table[AVR32_IFIELD_RY],
23023 + &avr32_ifield_table[AVR32_IFIELD_RX],
23027 + AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000,
23028 + &avr32_syntax_table[AVR32_SYNTAX_MOV1],
23029 + BFD_RELOC_AVR32_8S, 2, 1,
23031 + &avr32_ifield_table[AVR32_IFIELD_RY],
23032 + &avr32_ifield_table[AVR32_IFIELD_K8C],
23036 + AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000,
23037 + &avr32_syntax_table[AVR32_SYNTAX_MOV2],
23038 + BFD_RELOC_AVR32_21S, 2, 1,
23040 + &avr32_ifield_table[AVR32_IFIELD_RY],
23041 + &avr32_ifield_table[AVR32_IFIELD_K21],
23045 + AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff,
23046 + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1],
23047 + BFD_RELOC_UNUSED, 2, -1,
23049 + &avr32_ifield_table[AVR32_IFIELD_RY],
23050 + &avr32_ifield_table[AVR32_IFIELD_RX],
23054 + AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff,
23055 + &avr32_syntax_table[AVR32_SYNTAX_MOVNE1],
23056 + BFD_RELOC_UNUSED, 2, -1,
23058 + &avr32_ifield_table[AVR32_IFIELD_RY],
23059 + &avr32_ifield_table[AVR32_IFIELD_RX],
23063 + AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff,
23064 + &avr32_syntax_table[AVR32_SYNTAX_MOVHS1],
23065 + BFD_RELOC_UNUSED, 2, -1,
23067 + &avr32_ifield_table[AVR32_IFIELD_RY],
23068 + &avr32_ifield_table[AVR32_IFIELD_RX],
23072 + AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff,
23073 + &avr32_syntax_table[AVR32_SYNTAX_MOVLO1],
23074 + BFD_RELOC_UNUSED, 2, -1,
23076 + &avr32_ifield_table[AVR32_IFIELD_RY],
23077 + &avr32_ifield_table[AVR32_IFIELD_RX],
23081 + AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff,
23082 + &avr32_syntax_table[AVR32_SYNTAX_MOVGE1],
23083 + BFD_RELOC_UNUSED, 2, -1,
23085 + &avr32_ifield_table[AVR32_IFIELD_RY],
23086 + &avr32_ifield_table[AVR32_IFIELD_RX],
23090 + AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff,
23091 + &avr32_syntax_table[AVR32_SYNTAX_MOVLT1],
23092 + BFD_RELOC_UNUSED, 2, -1,
23094 + &avr32_ifield_table[AVR32_IFIELD_RY],
23095 + &avr32_ifield_table[AVR32_IFIELD_RX],
23099 + AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff,
23100 + &avr32_syntax_table[AVR32_SYNTAX_MOVMI1],
23101 + BFD_RELOC_UNUSED, 2, -1,
23103 + &avr32_ifield_table[AVR32_IFIELD_RY],
23104 + &avr32_ifield_table[AVR32_IFIELD_RX],
23108 + AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff,
23109 + &avr32_syntax_table[AVR32_SYNTAX_MOVPL1],
23110 + BFD_RELOC_UNUSED, 2, -1,
23112 + &avr32_ifield_table[AVR32_IFIELD_RY],
23113 + &avr32_ifield_table[AVR32_IFIELD_RX],
23117 + AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff,
23118 + &avr32_syntax_table[AVR32_SYNTAX_MOVLS1],
23119 + BFD_RELOC_UNUSED, 2, -1,
23121 + &avr32_ifield_table[AVR32_IFIELD_RY],
23122 + &avr32_ifield_table[AVR32_IFIELD_RX],
23126 + AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff,
23127 + &avr32_syntax_table[AVR32_SYNTAX_MOVGT1],
23128 + BFD_RELOC_UNUSED, 2, -1,
23130 + &avr32_ifield_table[AVR32_IFIELD_RY],
23131 + &avr32_ifield_table[AVR32_IFIELD_RX],
23135 + AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff,
23136 + &avr32_syntax_table[AVR32_SYNTAX_MOVLE1],
23137 + BFD_RELOC_UNUSED, 2, -1,
23139 + &avr32_ifield_table[AVR32_IFIELD_RY],
23140 + &avr32_ifield_table[AVR32_IFIELD_RX],
23144 + AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff,
23145 + &avr32_syntax_table[AVR32_SYNTAX_MOVHI1],
23146 + BFD_RELOC_UNUSED, 2, -1,
23148 + &avr32_ifield_table[AVR32_IFIELD_RY],
23149 + &avr32_ifield_table[AVR32_IFIELD_RX],
23153 + AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff,
23154 + &avr32_syntax_table[AVR32_SYNTAX_MOVVS1],
23155 + BFD_RELOC_UNUSED, 2, -1,
23157 + &avr32_ifield_table[AVR32_IFIELD_RY],
23158 + &avr32_ifield_table[AVR32_IFIELD_RX],
23162 + AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff,
23163 + &avr32_syntax_table[AVR32_SYNTAX_MOVVC1],
23164 + BFD_RELOC_UNUSED, 2, -1,
23166 + &avr32_ifield_table[AVR32_IFIELD_RY],
23167 + &avr32_ifield_table[AVR32_IFIELD_RX],
23171 + AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff,
23172 + &avr32_syntax_table[AVR32_SYNTAX_MOVQS1],
23173 + BFD_RELOC_UNUSED, 2, -1,
23175 + &avr32_ifield_table[AVR32_IFIELD_RY],
23176 + &avr32_ifield_table[AVR32_IFIELD_RX],
23180 + AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff,
23181 + &avr32_syntax_table[AVR32_SYNTAX_MOVAL1],
23182 + BFD_RELOC_UNUSED, 2, -1,
23184 + &avr32_ifield_table[AVR32_IFIELD_RY],
23185 + &avr32_ifield_table[AVR32_IFIELD_RX],
23189 + AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00,
23190 + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2],
23191 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23193 + &avr32_ifield_table[AVR32_IFIELD_RY],
23194 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23198 + AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00,
23199 + &avr32_syntax_table[AVR32_SYNTAX_MOVNE2],
23200 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23202 + &avr32_ifield_table[AVR32_IFIELD_RY],
23203 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23207 + AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00,
23208 + &avr32_syntax_table[AVR32_SYNTAX_MOVHS2],
23209 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23211 + &avr32_ifield_table[AVR32_IFIELD_RY],
23212 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23216 + AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00,
23217 + &avr32_syntax_table[AVR32_SYNTAX_MOVLO2],
23218 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23220 + &avr32_ifield_table[AVR32_IFIELD_RY],
23221 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23225 + AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00,
23226 + &avr32_syntax_table[AVR32_SYNTAX_MOVGE2],
23227 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23229 + &avr32_ifield_table[AVR32_IFIELD_RY],
23230 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23234 + AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00,
23235 + &avr32_syntax_table[AVR32_SYNTAX_MOVLT2],
23236 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23238 + &avr32_ifield_table[AVR32_IFIELD_RY],
23239 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23243 + AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00,
23244 + &avr32_syntax_table[AVR32_SYNTAX_MOVMI2],
23245 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23247 + &avr32_ifield_table[AVR32_IFIELD_RY],
23248 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23252 + AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00,
23253 + &avr32_syntax_table[AVR32_SYNTAX_MOVPL2],
23254 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23256 + &avr32_ifield_table[AVR32_IFIELD_RY],
23257 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23261 + AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00,
23262 + &avr32_syntax_table[AVR32_SYNTAX_MOVLS2],
23263 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23265 + &avr32_ifield_table[AVR32_IFIELD_RY],
23266 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23270 + AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00,
23271 + &avr32_syntax_table[AVR32_SYNTAX_MOVGT2],
23272 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23274 + &avr32_ifield_table[AVR32_IFIELD_RY],
23275 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23279 + AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00,
23280 + &avr32_syntax_table[AVR32_SYNTAX_MOVLE2],
23281 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23283 + &avr32_ifield_table[AVR32_IFIELD_RY],
23284 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23288 + AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00,
23289 + &avr32_syntax_table[AVR32_SYNTAX_MOVHI2],
23290 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23292 + &avr32_ifield_table[AVR32_IFIELD_RY],
23293 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23297 + AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00,
23298 + &avr32_syntax_table[AVR32_SYNTAX_MOVVS2],
23299 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23301 + &avr32_ifield_table[AVR32_IFIELD_RY],
23302 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23306 + AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00,
23307 + &avr32_syntax_table[AVR32_SYNTAX_MOVVC2],
23308 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23310 + &avr32_ifield_table[AVR32_IFIELD_RY],
23311 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23315 + AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00,
23316 + &avr32_syntax_table[AVR32_SYNTAX_MOVQS2],
23317 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23319 + &avr32_ifield_table[AVR32_IFIELD_RY],
23320 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23324 + AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00,
23325 + &avr32_syntax_table[AVR32_SYNTAX_MOVAL2],
23326 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
23328 + &avr32_ifield_table[AVR32_IFIELD_RY],
23329 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23333 + AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00,
23334 + &avr32_syntax_table[AVR32_SYNTAX_MTDR],
23335 + BFD_RELOC_AVR32_8S_EXT, 2, 0,
23337 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23338 + &avr32_ifield_table[AVR32_IFIELD_RY],
23342 + AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00,
23343 + &avr32_syntax_table[AVR32_SYNTAX_MTSR],
23344 + BFD_RELOC_AVR32_8S_EXT, 2, 0,
23346 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23347 + &avr32_ifield_table[AVR32_IFIELD_RY],
23351 + AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000,
23352 + &avr32_syntax_table[AVR32_SYNTAX_MUL1],
23353 + BFD_RELOC_UNUSED, 2, -1,
23355 + &avr32_ifield_table[AVR32_IFIELD_RY],
23356 + &avr32_ifield_table[AVR32_IFIELD_RX],
23360 + AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0,
23361 + &avr32_syntax_table[AVR32_SYNTAX_MUL2],
23362 + BFD_RELOC_UNUSED, 3, -1,
23364 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23365 + &avr32_ifield_table[AVR32_IFIELD_RX],
23366 + &avr32_ifield_table[AVR32_IFIELD_RY],
23370 + AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00,
23371 + &avr32_syntax_table[AVR32_SYNTAX_MUL3],
23372 + BFD_RELOC_AVR32_8S_EXT, 3, 2,
23374 + &avr32_ifield_table[AVR32_IFIELD_RY],
23375 + &avr32_ifield_table[AVR32_IFIELD_RX],
23376 + &avr32_ifield_table[AVR32_IFIELD_K8E],
23380 + AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0,
23381 + &avr32_syntax_table[AVR32_SYNTAX_MULHH_W],
23382 + BFD_RELOC_UNUSED, 5, -1,
23384 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23385 + &avr32_ifield_table[AVR32_IFIELD_RX],
23386 + &avr32_ifield_table[AVR32_IFIELD_X],
23387 + &avr32_ifield_table[AVR32_IFIELD_RY],
23388 + &avr32_ifield_table[AVR32_IFIELD_Y],
23392 + AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0,
23393 + &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W],
23394 + BFD_RELOC_UNUSED, 5, -1,
23396 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23397 + &avr32_ifield_table[AVR32_IFIELD_RX],
23398 + &avr32_ifield_table[AVR32_IFIELD_X],
23399 + &avr32_ifield_table[AVR32_IFIELD_RY],
23400 + &avr32_ifield_table[AVR32_IFIELD_Y],
23404 + AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1,
23405 + &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D],
23406 + BFD_RELOC_UNUSED, 4, -1,
23408 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23409 + &avr32_ifield_table[AVR32_IFIELD_RX],
23410 + &avr32_ifield_table[AVR32_IFIELD_RY],
23411 + &avr32_ifield_table[AVR32_IFIELD_Y],
23415 + AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0,
23416 + &avr32_syntax_table[AVR32_SYNTAX_MULSD],
23417 + BFD_RELOC_UNUSED, 3, -1,
23419 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23420 + &avr32_ifield_table[AVR32_IFIELD_RX],
23421 + &avr32_ifield_table[AVR32_IFIELD_RY],
23425 + AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0,
23426 + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H],
23427 + BFD_RELOC_UNUSED, 5, -1,
23429 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23430 + &avr32_ifield_table[AVR32_IFIELD_RX],
23431 + &avr32_ifield_table[AVR32_IFIELD_X],
23432 + &avr32_ifield_table[AVR32_IFIELD_RY],
23433 + &avr32_ifield_table[AVR32_IFIELD_Y],
23437 + AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0,
23438 + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W],
23439 + BFD_RELOC_UNUSED, 5, -1,
23441 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23442 + &avr32_ifield_table[AVR32_IFIELD_RX],
23443 + &avr32_ifield_table[AVR32_IFIELD_X],
23444 + &avr32_ifield_table[AVR32_IFIELD_RY],
23445 + &avr32_ifield_table[AVR32_IFIELD_Y],
23449 + AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0,
23450 + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H],
23451 + BFD_RELOC_UNUSED, 5, -1,
23453 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23454 + &avr32_ifield_table[AVR32_IFIELD_RX],
23455 + &avr32_ifield_table[AVR32_IFIELD_X],
23456 + &avr32_ifield_table[AVR32_IFIELD_RY],
23457 + &avr32_ifield_table[AVR32_IFIELD_Y],
23461 + AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0,
23462 + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W],
23463 + BFD_RELOC_UNUSED, 4, -1,
23465 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23466 + &avr32_ifield_table[AVR32_IFIELD_RX],
23467 + &avr32_ifield_table[AVR32_IFIELD_RY],
23468 + &avr32_ifield_table[AVR32_IFIELD_Y],
23472 + AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0,
23473 + &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W],
23474 + BFD_RELOC_UNUSED, 4, -1,
23476 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23477 + &avr32_ifield_table[AVR32_IFIELD_RX],
23478 + &avr32_ifield_table[AVR32_IFIELD_RY],
23479 + &avr32_ifield_table[AVR32_IFIELD_Y],
23483 + AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1,
23484 + &avr32_syntax_table[AVR32_SYNTAX_MULU_D],
23485 + BFD_RELOC_UNUSED, 3, -1,
23487 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23488 + &avr32_ifield_table[AVR32_IFIELD_RX],
23489 + &avr32_ifield_table[AVR32_IFIELD_RY],
23493 + AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1,
23494 + &avr32_syntax_table[AVR32_SYNTAX_MULWH_D],
23495 + BFD_RELOC_UNUSED, 4, -1,
23497 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23498 + &avr32_ifield_table[AVR32_IFIELD_RX],
23499 + &avr32_ifield_table[AVR32_IFIELD_RY],
23500 + &avr32_ifield_table[AVR32_IFIELD_Y],
23504 + AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000,
23505 + &avr32_syntax_table[AVR32_SYNTAX_MUSFR],
23506 + BFD_RELOC_UNUSED, 1, -1,
23508 + &avr32_ifield_table[AVR32_IFIELD_RY],
23512 + AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000,
23513 + &avr32_syntax_table[AVR32_SYNTAX_MUSTR],
23514 + BFD_RELOC_UNUSED, 1, -1,
23516 + &avr32_ifield_table[AVR32_IFIELD_RY],
23520 + AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff,
23521 + &avr32_syntax_table[AVR32_SYNTAX_MVCR_D],
23522 + BFD_RELOC_UNUSED, 3, -1,
23524 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
23525 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23526 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23530 + AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff,
23531 + &avr32_syntax_table[AVR32_SYNTAX_MVCR_W],
23532 + BFD_RELOC_UNUSED, 3, -1,
23534 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
23535 + &avr32_ifield_table[AVR32_IFIELD_RY],
23536 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23540 + AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff,
23541 + &avr32_syntax_table[AVR32_SYNTAX_MVRC_D],
23542 + BFD_RELOC_UNUSED, 3, -1,
23544 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
23545 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23546 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23550 + AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff,
23551 + &avr32_syntax_table[AVR32_SYNTAX_MVRC_W],
23552 + BFD_RELOC_UNUSED, 3, -1,
23554 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
23555 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23556 + &avr32_ifield_table[AVR32_IFIELD_RY],
23560 + AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000,
23561 + &avr32_syntax_table[AVR32_SYNTAX_NEG],
23562 + BFD_RELOC_UNUSED, 1, -1,
23564 + &avr32_ifield_table[AVR32_IFIELD_RY],
23568 + AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000,
23569 + &avr32_syntax_table[AVR32_SYNTAX_NOP],
23570 + BFD_RELOC_UNUSED, 0, -1, { NULL },
23573 + AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000,
23574 + &avr32_syntax_table[AVR32_SYNTAX_OR1],
23575 + BFD_RELOC_UNUSED, 2, -1,
23577 + &avr32_ifield_table[AVR32_IFIELD_RY],
23578 + &avr32_ifield_table[AVR32_IFIELD_RX],
23582 + AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00,
23583 + &avr32_syntax_table[AVR32_SYNTAX_OR2],
23584 + BFD_RELOC_UNUSED, 4, -1,
23586 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23587 + &avr32_ifield_table[AVR32_IFIELD_RX],
23588 + &avr32_ifield_table[AVR32_IFIELD_RY],
23589 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
23593 + AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00,
23594 + &avr32_syntax_table[AVR32_SYNTAX_OR3],
23595 + BFD_RELOC_UNUSED, 4, -1,
23597 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23598 + &avr32_ifield_table[AVR32_IFIELD_RX],
23599 + &avr32_ifield_table[AVR32_IFIELD_RY],
23600 + &avr32_ifield_table[AVR32_IFIELD_K5E2],
23604 + AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000,
23605 + &avr32_syntax_table[AVR32_SYNTAX_ORH],
23606 + BFD_RELOC_AVR32_16U, 2, 1,
23608 + &avr32_ifield_table[AVR32_IFIELD_RY],
23609 + &avr32_ifield_table[AVR32_IFIELD_K16],
23613 + AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000,
23614 + &avr32_syntax_table[AVR32_SYNTAX_ORL],
23615 + BFD_RELOC_AVR32_16U, 2, 1,
23617 + &avr32_ifield_table[AVR32_IFIELD_RY],
23618 + &avr32_ifield_table[AVR32_IFIELD_K16],
23622 + AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0,
23623 + &avr32_syntax_table[AVR32_SYNTAX_PABS_SB],
23624 + BFD_RELOC_UNUSED, 2, -1,
23626 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23627 + &avr32_ifield_table[AVR32_IFIELD_RY],
23631 + AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0,
23632 + &avr32_syntax_table[AVR32_SYNTAX_PABS_SH],
23633 + BFD_RELOC_UNUSED, 2, -1,
23635 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23636 + &avr32_ifield_table[AVR32_IFIELD_RY],
23640 + AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0,
23641 + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB],
23642 + BFD_RELOC_UNUSED, 3, -1,
23644 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23645 + &avr32_ifield_table[AVR32_IFIELD_RX],
23646 + &avr32_ifield_table[AVR32_IFIELD_RY],
23650 + AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0,
23651 + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB],
23652 + BFD_RELOC_UNUSED, 3, -1,
23654 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23655 + &avr32_ifield_table[AVR32_IFIELD_RX],
23656 + &avr32_ifield_table[AVR32_IFIELD_RY],
23660 + AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0,
23661 + &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH],
23662 + BFD_RELOC_UNUSED, 3, -1,
23664 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23665 + &avr32_ifield_table[AVR32_IFIELD_RX],
23666 + &avr32_ifield_table[AVR32_IFIELD_RY],
23670 + AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0,
23671 + &avr32_syntax_table[AVR32_SYNTAX_PADD_B],
23672 + BFD_RELOC_UNUSED, 3, -1,
23674 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23675 + &avr32_ifield_table[AVR32_IFIELD_RX],
23676 + &avr32_ifield_table[AVR32_IFIELD_RY],
23680 + AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0,
23681 + &avr32_syntax_table[AVR32_SYNTAX_PADD_H],
23682 + BFD_RELOC_UNUSED, 3, -1,
23684 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23685 + &avr32_ifield_table[AVR32_IFIELD_RX],
23686 + &avr32_ifield_table[AVR32_IFIELD_RY],
23690 + AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0,
23691 + &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH],
23692 + BFD_RELOC_UNUSED, 3, -1,
23694 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23695 + &avr32_ifield_table[AVR32_IFIELD_RX],
23696 + &avr32_ifield_table[AVR32_IFIELD_RY],
23700 + AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0,
23701 + &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB],
23702 + BFD_RELOC_UNUSED, 3, -1,
23704 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23705 + &avr32_ifield_table[AVR32_IFIELD_RX],
23706 + &avr32_ifield_table[AVR32_IFIELD_RY],
23710 + AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0,
23711 + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB],
23712 + BFD_RELOC_UNUSED, 3, -1,
23714 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23715 + &avr32_ifield_table[AVR32_IFIELD_RX],
23716 + &avr32_ifield_table[AVR32_IFIELD_RY],
23720 + AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0,
23721 + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH],
23722 + BFD_RELOC_UNUSED, 3, -1,
23724 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23725 + &avr32_ifield_table[AVR32_IFIELD_RX],
23726 + &avr32_ifield_table[AVR32_IFIELD_RY],
23730 + AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0,
23731 + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB],
23732 + BFD_RELOC_UNUSED, 3, -1,
23734 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23735 + &avr32_ifield_table[AVR32_IFIELD_RX],
23736 + &avr32_ifield_table[AVR32_IFIELD_RY],
23740 + AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0,
23741 + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH],
23742 + BFD_RELOC_UNUSED, 3, -1,
23744 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23745 + &avr32_ifield_table[AVR32_IFIELD_RX],
23746 + &avr32_ifield_table[AVR32_IFIELD_RY],
23750 + AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0,
23751 + &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H],
23752 + BFD_RELOC_UNUSED, 5, -1,
23754 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23755 + &avr32_ifield_table[AVR32_IFIELD_RX],
23756 + &avr32_ifield_table[AVR32_IFIELD_X],
23757 + &avr32_ifield_table[AVR32_IFIELD_RY],
23758 + &avr32_ifield_table[AVR32_IFIELD_Y],
23762 + AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0,
23763 + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH],
23764 + BFD_RELOC_UNUSED, 5, -1,
23766 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23767 + &avr32_ifield_table[AVR32_IFIELD_RX],
23768 + &avr32_ifield_table[AVR32_IFIELD_X],
23769 + &avr32_ifield_table[AVR32_IFIELD_RY],
23770 + &avr32_ifield_table[AVR32_IFIELD_Y],
23774 + AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0,
23775 + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH],
23776 + BFD_RELOC_UNUSED, 5, -1,
23778 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23779 + &avr32_ifield_table[AVR32_IFIELD_RX],
23780 + &avr32_ifield_table[AVR32_IFIELD_X],
23781 + &avr32_ifield_table[AVR32_IFIELD_RY],
23782 + &avr32_ifield_table[AVR32_IFIELD_Y],
23786 + AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0,
23787 + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH],
23788 + BFD_RELOC_UNUSED, 5, -1,
23790 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23791 + &avr32_ifield_table[AVR32_IFIELD_RX],
23792 + &avr32_ifield_table[AVR32_IFIELD_X],
23793 + &avr32_ifield_table[AVR32_IFIELD_RY],
23794 + &avr32_ifield_table[AVR32_IFIELD_Y],
23798 + AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0,
23799 + &avr32_syntax_table[AVR32_SYNTAX_PADDX_H],
23800 + BFD_RELOC_UNUSED, 3, -1,
23802 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23803 + &avr32_ifield_table[AVR32_IFIELD_RX],
23804 + &avr32_ifield_table[AVR32_IFIELD_RY],
23808 + AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0,
23809 + &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH],
23810 + BFD_RELOC_UNUSED, 3, -1,
23812 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23813 + &avr32_ifield_table[AVR32_IFIELD_RX],
23814 + &avr32_ifield_table[AVR32_IFIELD_RY],
23818 + AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0,
23819 + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH],
23820 + BFD_RELOC_UNUSED, 3, -1,
23822 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23823 + &avr32_ifield_table[AVR32_IFIELD_RX],
23824 + &avr32_ifield_table[AVR32_IFIELD_RY],
23828 + AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0,
23829 + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH],
23830 + BFD_RELOC_UNUSED, 3, -1,
23832 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23833 + &avr32_ifield_table[AVR32_IFIELD_RX],
23834 + &avr32_ifield_table[AVR32_IFIELD_RY],
23838 + AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0,
23839 + &avr32_syntax_table[AVR32_SYNTAX_PASR_B],
23840 + BFD_RELOC_UNUSED, 3, -1,
23842 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23843 + &avr32_ifield_table[AVR32_IFIELD_RX],
23844 + &avr32_ifield_table[AVR32_IFIELD_COND3],
23848 + AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0,
23849 + &avr32_syntax_table[AVR32_SYNTAX_PASR_H],
23850 + BFD_RELOC_UNUSED, 3, -1,
23852 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23853 + &avr32_ifield_table[AVR32_IFIELD_RX],
23854 + &avr32_ifield_table[AVR32_IFIELD_RY],
23858 + AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0,
23859 + &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH],
23860 + BFD_RELOC_UNUSED, 3, -1,
23862 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23863 + &avr32_ifield_table[AVR32_IFIELD_RX],
23864 + &avr32_ifield_table[AVR32_IFIELD_RY],
23868 + AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0,
23869 + &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB],
23870 + BFD_RELOC_UNUSED, 3, -1,
23872 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23873 + &avr32_ifield_table[AVR32_IFIELD_RX],
23874 + &avr32_ifield_table[AVR32_IFIELD_RY],
23878 + AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0,
23879 + &avr32_syntax_table[AVR32_SYNTAX_PLSL_B],
23880 + BFD_RELOC_UNUSED, 3, -1,
23882 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23883 + &avr32_ifield_table[AVR32_IFIELD_RX],
23884 + &avr32_ifield_table[AVR32_IFIELD_COND3],
23888 + AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0,
23889 + &avr32_syntax_table[AVR32_SYNTAX_PLSL_H],
23890 + BFD_RELOC_UNUSED, 3, -1,
23892 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23893 + &avr32_ifield_table[AVR32_IFIELD_RX],
23894 + &avr32_ifield_table[AVR32_IFIELD_RY],
23898 + AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0,
23899 + &avr32_syntax_table[AVR32_SYNTAX_PLSR_B],
23900 + BFD_RELOC_UNUSED, 3, -1,
23902 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23903 + &avr32_ifield_table[AVR32_IFIELD_RX],
23904 + &avr32_ifield_table[AVR32_IFIELD_COND3],
23908 + AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0,
23909 + &avr32_syntax_table[AVR32_SYNTAX_PLSR_H],
23910 + BFD_RELOC_UNUSED, 3, -1,
23912 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23913 + &avr32_ifield_table[AVR32_IFIELD_RX],
23914 + &avr32_ifield_table[AVR32_IFIELD_RY],
23918 + AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0,
23919 + &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH],
23920 + BFD_RELOC_UNUSED, 3, -1,
23922 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23923 + &avr32_ifield_table[AVR32_IFIELD_RX],
23924 + &avr32_ifield_table[AVR32_IFIELD_RY],
23928 + AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0,
23929 + &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB],
23930 + BFD_RELOC_UNUSED, 3, -1,
23932 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23933 + &avr32_ifield_table[AVR32_IFIELD_RX],
23934 + &avr32_ifield_table[AVR32_IFIELD_RY],
23938 + AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0,
23939 + &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH],
23940 + BFD_RELOC_UNUSED, 3, -1,
23942 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23943 + &avr32_ifield_table[AVR32_IFIELD_RX],
23944 + &avr32_ifield_table[AVR32_IFIELD_RY],
23948 + AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0,
23949 + &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB],
23950 + BFD_RELOC_UNUSED, 3, -1,
23952 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23953 + &avr32_ifield_table[AVR32_IFIELD_RX],
23954 + &avr32_ifield_table[AVR32_IFIELD_RY],
23958 + AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000,
23959 + &avr32_syntax_table[AVR32_SYNTAX_POPJC],
23960 + BFD_RELOC_UNUSED, 0, -1, { NULL },
23963 + AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000,
23964 + &avr32_syntax_table[AVR32_SYNTAX_POPM],
23965 + BFD_RELOC_UNUSED, 1, -1,
23967 + &avr32_ifield_table[AVR32_IFIELD_POPM],
23971 + AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000,
23972 + &avr32_syntax_table[AVR32_SYNTAX_POPM_E],
23973 + BFD_RELOC_UNUSED, 1, -1,
23975 + &avr32_ifield_table[AVR32_IFIELD_K16],
23979 + AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000,
23980 + &avr32_syntax_table[AVR32_SYNTAX_PREF],
23981 + BFD_RELOC_AVR32_16S, 2, -1,
23983 + &avr32_ifield_table[AVR32_IFIELD_RY],
23984 + &avr32_ifield_table[AVR32_IFIELD_K16],
23988 + AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0,
23989 + &avr32_syntax_table[AVR32_SYNTAX_PSAD],
23990 + BFD_RELOC_UNUSED, 3, -1,
23992 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
23993 + &avr32_ifield_table[AVR32_IFIELD_RX],
23994 + &avr32_ifield_table[AVR32_IFIELD_RY],
23998 + AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0,
23999 + &avr32_syntax_table[AVR32_SYNTAX_PSUB_B],
24000 + BFD_RELOC_UNUSED, 3, -1,
24002 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24003 + &avr32_ifield_table[AVR32_IFIELD_RX],
24004 + &avr32_ifield_table[AVR32_IFIELD_RY],
24008 + AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0,
24009 + &avr32_syntax_table[AVR32_SYNTAX_PSUB_H],
24010 + BFD_RELOC_UNUSED, 3, -1,
24012 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24013 + &avr32_ifield_table[AVR32_IFIELD_RX],
24014 + &avr32_ifield_table[AVR32_IFIELD_RY],
24018 + AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0,
24019 + &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H],
24020 + BFD_RELOC_UNUSED, 5, -1,
24022 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24023 + &avr32_ifield_table[AVR32_IFIELD_RX],
24024 + &avr32_ifield_table[AVR32_IFIELD_X],
24025 + &avr32_ifield_table[AVR32_IFIELD_RY],
24026 + &avr32_ifield_table[AVR32_IFIELD_Y],
24030 + AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0,
24031 + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH],
24032 + BFD_RELOC_UNUSED, 5, -1,
24034 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24035 + &avr32_ifield_table[AVR32_IFIELD_RX],
24036 + &avr32_ifield_table[AVR32_IFIELD_X],
24037 + &avr32_ifield_table[AVR32_IFIELD_RY],
24038 + &avr32_ifield_table[AVR32_IFIELD_Y],
24042 + AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0,
24043 + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH],
24044 + BFD_RELOC_UNUSED, 5, -1,
24046 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24047 + &avr32_ifield_table[AVR32_IFIELD_RX],
24048 + &avr32_ifield_table[AVR32_IFIELD_X],
24049 + &avr32_ifield_table[AVR32_IFIELD_RY],
24050 + &avr32_ifield_table[AVR32_IFIELD_Y],
24054 + AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0,
24055 + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH],
24056 + BFD_RELOC_UNUSED, 5, -1,
24058 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24059 + &avr32_ifield_table[AVR32_IFIELD_RX],
24060 + &avr32_ifield_table[AVR32_IFIELD_X],
24061 + &avr32_ifield_table[AVR32_IFIELD_RY],
24062 + &avr32_ifield_table[AVR32_IFIELD_Y],
24066 + AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0,
24067 + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH],
24068 + BFD_RELOC_UNUSED, 3, -1,
24070 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24071 + &avr32_ifield_table[AVR32_IFIELD_RX],
24072 + &avr32_ifield_table[AVR32_IFIELD_RY],
24076 + AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0,
24077 + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB],
24078 + BFD_RELOC_UNUSED, 3, -1,
24080 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24081 + &avr32_ifield_table[AVR32_IFIELD_RX],
24082 + &avr32_ifield_table[AVR32_IFIELD_RY],
24086 + AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0,
24087 + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB],
24088 + BFD_RELOC_UNUSED, 3, -1,
24090 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24091 + &avr32_ifield_table[AVR32_IFIELD_RX],
24092 + &avr32_ifield_table[AVR32_IFIELD_RY],
24096 + AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0,
24097 + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH],
24098 + BFD_RELOC_UNUSED, 3, -1,
24100 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24101 + &avr32_ifield_table[AVR32_IFIELD_RX],
24102 + &avr32_ifield_table[AVR32_IFIELD_RY],
24106 + AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0,
24107 + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB],
24108 + BFD_RELOC_UNUSED, 3, -1,
24110 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24111 + &avr32_ifield_table[AVR32_IFIELD_RX],
24112 + &avr32_ifield_table[AVR32_IFIELD_RY],
24116 + AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0,
24117 + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH],
24118 + BFD_RELOC_UNUSED, 3, -1,
24120 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24121 + &avr32_ifield_table[AVR32_IFIELD_RX],
24122 + &avr32_ifield_table[AVR32_IFIELD_RY],
24126 + AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0,
24127 + &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H],
24128 + BFD_RELOC_UNUSED, 3, -1,
24130 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24131 + &avr32_ifield_table[AVR32_IFIELD_RX],
24132 + &avr32_ifield_table[AVR32_IFIELD_RY],
24136 + AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0,
24137 + &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH],
24138 + BFD_RELOC_UNUSED, 3, -1,
24140 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24141 + &avr32_ifield_table[AVR32_IFIELD_RX],
24142 + &avr32_ifield_table[AVR32_IFIELD_RY],
24146 + AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0,
24147 + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH],
24148 + BFD_RELOC_UNUSED, 3, -1,
24150 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24151 + &avr32_ifield_table[AVR32_IFIELD_RX],
24152 + &avr32_ifield_table[AVR32_IFIELD_RY],
24156 + AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0,
24157 + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH],
24158 + BFD_RELOC_UNUSED, 3, -1,
24160 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24161 + &avr32_ifield_table[AVR32_IFIELD_RX],
24162 + &avr32_ifield_table[AVR32_IFIELD_RY],
24166 + AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0,
24167 + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H],
24168 + BFD_RELOC_UNUSED, 3, -1,
24170 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24171 + &avr32_ifield_table[AVR32_IFIELD_RX],
24172 + &avr32_ifield_table[AVR32_IFIELD_Y],
24176 + AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0,
24177 + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H],
24178 + BFD_RELOC_UNUSED, 3, -1,
24180 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24181 + &avr32_ifield_table[AVR32_IFIELD_RX],
24182 + &avr32_ifield_table[AVR32_IFIELD_Y],
24186 + AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000,
24187 + &avr32_syntax_table[AVR32_SYNTAX_PUSHJC],
24188 + BFD_RELOC_UNUSED, 0, -1, { NULL },
24191 + AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000,
24192 + &avr32_syntax_table[AVR32_SYNTAX_PUSHM],
24193 + BFD_RELOC_UNUSED, 1, -1,
24195 + &avr32_ifield_table[AVR32_IFIELD_K8C],
24199 + AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000,
24200 + &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E],
24201 + BFD_RELOC_UNUSED, 1, -1,
24203 + &avr32_ifield_table[AVR32_IFIELD_K16],
24207 + AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000,
24208 + &avr32_syntax_table[AVR32_SYNTAX_RCALL1],
24209 + BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24211 + &avr32_ifield_table[AVR32_IFIELD_K10],
24215 + AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000,
24216 + &avr32_syntax_table[AVR32_SYNTAX_RCALL2],
24217 + BFD_RELOC_AVR32_22H_PCREL, 1, 0,
24219 + &avr32_ifield_table[AVR32_IFIELD_K21],
24223 + AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000,
24224 + &avr32_syntax_table[AVR32_SYNTAX_RETEQ],
24225 + BFD_RELOC_NONE, 1, -1,
24227 + &avr32_ifield_table[AVR32_IFIELD_RY],
24231 + AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000,
24232 + &avr32_syntax_table[AVR32_SYNTAX_RETNE],
24233 + BFD_RELOC_NONE, 1, -1,
24235 + &avr32_ifield_table[AVR32_IFIELD_RY],
24239 + AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000,
24240 + &avr32_syntax_table[AVR32_SYNTAX_RETHS],
24241 + BFD_RELOC_NONE, 1, -1,
24243 + &avr32_ifield_table[AVR32_IFIELD_RY],
24247 + AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000,
24248 + &avr32_syntax_table[AVR32_SYNTAX_RETLO],
24249 + BFD_RELOC_NONE, 1, -1,
24251 + &avr32_ifield_table[AVR32_IFIELD_RY],
24255 + AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000,
24256 + &avr32_syntax_table[AVR32_SYNTAX_RETGE],
24257 + BFD_RELOC_NONE, 1, -1,
24259 + &avr32_ifield_table[AVR32_IFIELD_RY],
24263 + AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000,
24264 + &avr32_syntax_table[AVR32_SYNTAX_RETLT],
24265 + BFD_RELOC_NONE, 1, -1,
24267 + &avr32_ifield_table[AVR32_IFIELD_RY],
24271 + AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000,
24272 + &avr32_syntax_table[AVR32_SYNTAX_RETMI],
24273 + BFD_RELOC_NONE, 1, -1,
24275 + &avr32_ifield_table[AVR32_IFIELD_RY],
24279 + AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000,
24280 + &avr32_syntax_table[AVR32_SYNTAX_RETPL],
24281 + BFD_RELOC_NONE, 1, -1,
24283 + &avr32_ifield_table[AVR32_IFIELD_RY],
24287 + AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000,
24288 + &avr32_syntax_table[AVR32_SYNTAX_RETLS],
24289 + BFD_RELOC_NONE, 1, -1,
24291 + &avr32_ifield_table[AVR32_IFIELD_RY],
24295 + AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000,
24296 + &avr32_syntax_table[AVR32_SYNTAX_RETGT],
24297 + BFD_RELOC_NONE, 1, -1,
24299 + &avr32_ifield_table[AVR32_IFIELD_RY],
24303 + AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000,
24304 + &avr32_syntax_table[AVR32_SYNTAX_RETLE],
24305 + BFD_RELOC_NONE, 1, -1,
24307 + &avr32_ifield_table[AVR32_IFIELD_RY],
24311 + AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000,
24312 + &avr32_syntax_table[AVR32_SYNTAX_RETHI],
24313 + BFD_RELOC_NONE, 1, -1,
24315 + &avr32_ifield_table[AVR32_IFIELD_RY],
24319 + AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000,
24320 + &avr32_syntax_table[AVR32_SYNTAX_RETVS],
24321 + BFD_RELOC_NONE, 1, -1,
24323 + &avr32_ifield_table[AVR32_IFIELD_RY],
24327 + AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000,
24328 + &avr32_syntax_table[AVR32_SYNTAX_RETVC],
24329 + BFD_RELOC_NONE, 1, -1,
24331 + &avr32_ifield_table[AVR32_IFIELD_RY],
24335 + AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000,
24336 + &avr32_syntax_table[AVR32_SYNTAX_RETQS],
24337 + BFD_RELOC_NONE, 1, -1,
24339 + &avr32_ifield_table[AVR32_IFIELD_RY],
24343 + AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000,
24344 + &avr32_syntax_table[AVR32_SYNTAX_RETAL],
24345 + BFD_RELOC_NONE, 1, -1,
24347 + &avr32_ifield_table[AVR32_IFIELD_RY],
24351 + AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000,
24352 + &avr32_syntax_table[AVR32_SYNTAX_RETD],
24353 + BFD_RELOC_NONE, 0, -1, { NULL },
24356 + AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000,
24357 + &avr32_syntax_table[AVR32_SYNTAX_RETE],
24358 + BFD_RELOC_NONE, 0, -1, { NULL },
24361 + AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000,
24362 + &avr32_syntax_table[AVR32_SYNTAX_RETJ],
24363 + BFD_RELOC_NONE, 0, -1, { NULL },
24366 + AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000,
24367 + &avr32_syntax_table[AVR32_SYNTAX_RETS],
24368 + BFD_RELOC_NONE, 0, -1, { NULL },
24371 + AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000,
24372 + &avr32_syntax_table[AVR32_SYNTAX_RJMP],
24373 + BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24375 + &avr32_ifield_table[AVR32_IFIELD_K10],
24379 + AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000,
24380 + &avr32_syntax_table[AVR32_SYNTAX_ROL],
24381 + BFD_RELOC_UNUSED, 1, -1,
24383 + &avr32_ifield_table[AVR32_IFIELD_RY],
24387 + AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000,
24388 + &avr32_syntax_table[AVR32_SYNTAX_ROR],
24389 + BFD_RELOC_UNUSED, 1, -1,
24391 + &avr32_ifield_table[AVR32_IFIELD_RY],
24395 + AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000,
24396 + &avr32_syntax_table[AVR32_SYNTAX_RSUB1],
24397 + BFD_RELOC_UNUSED, 2, -1,
24399 + &avr32_ifield_table[AVR32_IFIELD_RY],
24400 + &avr32_ifield_table[AVR32_IFIELD_RX],
24404 + AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00,
24405 + &avr32_syntax_table[AVR32_SYNTAX_RSUB2],
24406 + BFD_RELOC_AVR32_8S_EXT, 3, 2,
24408 + &avr32_ifield_table[AVR32_IFIELD_RY],
24409 + &avr32_ifield_table[AVR32_IFIELD_RX],
24410 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24414 + AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0,
24415 + &avr32_syntax_table[AVR32_SYNTAX_SATADD_H],
24416 + BFD_RELOC_UNUSED, 3, -1,
24418 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24419 + &avr32_ifield_table[AVR32_IFIELD_RX],
24420 + &avr32_ifield_table[AVR32_IFIELD_RY],
24424 + AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0,
24425 + &avr32_syntax_table[AVR32_SYNTAX_SATADD_W],
24426 + BFD_RELOC_UNUSED, 3, -1,
24428 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24429 + &avr32_ifield_table[AVR32_IFIELD_RX],
24430 + &avr32_ifield_table[AVR32_IFIELD_RY],
24434 + AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00,
24435 + &avr32_syntax_table[AVR32_SYNTAX_SATRNDS],
24436 + BFD_RELOC_UNUSED, 3, -1,
24438 + &avr32_ifield_table[AVR32_IFIELD_RY],
24439 + &avr32_ifield_table[AVR32_IFIELD_K5E],
24440 + &avr32_ifield_table[AVR32_IFIELD_S5],
24444 + AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00,
24445 + &avr32_syntax_table[AVR32_SYNTAX_SATRNDU],
24446 + BFD_RELOC_UNUSED, 3, -1,
24448 + &avr32_ifield_table[AVR32_IFIELD_RY],
24449 + &avr32_ifield_table[AVR32_IFIELD_K5E],
24450 + &avr32_ifield_table[AVR32_IFIELD_S5],
24454 + AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00,
24455 + &avr32_syntax_table[AVR32_SYNTAX_SATS],
24456 + BFD_RELOC_UNUSED, 3, -1,
24458 + &avr32_ifield_table[AVR32_IFIELD_RY],
24459 + &avr32_ifield_table[AVR32_IFIELD_K5E],
24460 + &avr32_ifield_table[AVR32_IFIELD_S5],
24464 + AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0,
24465 + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H],
24466 + BFD_RELOC_UNUSED, 3, -1,
24468 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24469 + &avr32_ifield_table[AVR32_IFIELD_RX],
24470 + &avr32_ifield_table[AVR32_IFIELD_RY],
24474 + AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0,
24475 + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1],
24476 + BFD_RELOC_UNUSED, 3, -1,
24478 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24479 + &avr32_ifield_table[AVR32_IFIELD_RX],
24480 + &avr32_ifield_table[AVR32_IFIELD_RY],
24484 + AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000,
24485 + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2],
24486 + BFD_RELOC_UNUSED, 3, -1,
24488 + &avr32_ifield_table[AVR32_IFIELD_RY],
24489 + &avr32_ifield_table[AVR32_IFIELD_RX],
24490 + &avr32_ifield_table[AVR32_IFIELD_K16],
24494 + AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00,
24495 + &avr32_syntax_table[AVR32_SYNTAX_SATU],
24496 + BFD_RELOC_UNUSED, 3, -1,
24498 + &avr32_ifield_table[AVR32_IFIELD_RY],
24499 + &avr32_ifield_table[AVR32_IFIELD_K5E],
24500 + &avr32_ifield_table[AVR32_IFIELD_S5],
24504 + AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0,
24505 + &avr32_syntax_table[AVR32_SYNTAX_SBC],
24506 + BFD_RELOC_UNUSED, 3, -1,
24508 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24509 + &avr32_ifield_table[AVR32_IFIELD_RX],
24510 + &avr32_ifield_table[AVR32_IFIELD_RY],
24514 + AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000,
24515 + &avr32_syntax_table[AVR32_SYNTAX_SBR],
24516 + BFD_RELOC_UNUSED, 2, -1,
24518 + &avr32_ifield_table[AVR32_IFIELD_RY],
24519 + &avr32_ifield_table[AVR32_IFIELD_BIT5C],
24523 + AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000,
24524 + &avr32_syntax_table[AVR32_SYNTAX_SCALL],
24525 + BFD_RELOC_UNUSED, 0, -1, { NULL },
24528 + AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000,
24529 + &avr32_syntax_table[AVR32_SYNTAX_SCR],
24530 + BFD_RELOC_UNUSED, 1, -1,
24532 + &avr32_ifield_table[AVR32_IFIELD_RY],
24536 + AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00,
24537 + &avr32_syntax_table[AVR32_SYNTAX_SLEEP],
24538 + BFD_RELOC_AVR32_8S_EXT, 1, 0,
24540 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24544 + AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000,
24545 + &avr32_syntax_table[AVR32_SYNTAX_SREQ],
24546 + BFD_RELOC_UNUSED, 1, -1,
24548 + &avr32_ifield_table[AVR32_IFIELD_RY],
24552 + AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000,
24553 + &avr32_syntax_table[AVR32_SYNTAX_SRNE],
24554 + BFD_RELOC_UNUSED, 1, -1,
24556 + &avr32_ifield_table[AVR32_IFIELD_RY],
24560 + AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000,
24561 + &avr32_syntax_table[AVR32_SYNTAX_SRHS],
24562 + BFD_RELOC_UNUSED, 1, -1,
24564 + &avr32_ifield_table[AVR32_IFIELD_RY],
24568 + AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000,
24569 + &avr32_syntax_table[AVR32_SYNTAX_SRLO],
24570 + BFD_RELOC_UNUSED, 1, -1,
24572 + &avr32_ifield_table[AVR32_IFIELD_RY],
24576 + AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000,
24577 + &avr32_syntax_table[AVR32_SYNTAX_SRGE],
24578 + BFD_RELOC_UNUSED, 1, -1,
24580 + &avr32_ifield_table[AVR32_IFIELD_RY],
24584 + AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000,
24585 + &avr32_syntax_table[AVR32_SYNTAX_SRLT],
24586 + BFD_RELOC_UNUSED, 1, -1,
24588 + &avr32_ifield_table[AVR32_IFIELD_RY],
24592 + AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000,
24593 + &avr32_syntax_table[AVR32_SYNTAX_SRMI],
24594 + BFD_RELOC_UNUSED, 1, -1,
24596 + &avr32_ifield_table[AVR32_IFIELD_RY],
24600 + AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000,
24601 + &avr32_syntax_table[AVR32_SYNTAX_SRPL],
24602 + BFD_RELOC_UNUSED, 1, -1,
24604 + &avr32_ifield_table[AVR32_IFIELD_RY],
24608 + AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000,
24609 + &avr32_syntax_table[AVR32_SYNTAX_SRLS],
24610 + BFD_RELOC_UNUSED, 1, -1,
24612 + &avr32_ifield_table[AVR32_IFIELD_RY],
24616 + AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000,
24617 + &avr32_syntax_table[AVR32_SYNTAX_SRGT],
24618 + BFD_RELOC_UNUSED, 1, -1,
24620 + &avr32_ifield_table[AVR32_IFIELD_RY],
24624 + AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000,
24625 + &avr32_syntax_table[AVR32_SYNTAX_SRLE],
24626 + BFD_RELOC_UNUSED, 1, -1,
24628 + &avr32_ifield_table[AVR32_IFIELD_RY],
24632 + AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000,
24633 + &avr32_syntax_table[AVR32_SYNTAX_SRHI],
24634 + BFD_RELOC_UNUSED, 1, -1,
24636 + &avr32_ifield_table[AVR32_IFIELD_RY],
24640 + AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000,
24641 + &avr32_syntax_table[AVR32_SYNTAX_SRVS],
24642 + BFD_RELOC_UNUSED, 1, -1,
24644 + &avr32_ifield_table[AVR32_IFIELD_RY],
24648 + AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000,
24649 + &avr32_syntax_table[AVR32_SYNTAX_SRVC],
24650 + BFD_RELOC_UNUSED, 1, -1,
24652 + &avr32_ifield_table[AVR32_IFIELD_RY],
24656 + AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000,
24657 + &avr32_syntax_table[AVR32_SYNTAX_SRQS],
24658 + BFD_RELOC_UNUSED, 1, -1,
24660 + &avr32_ifield_table[AVR32_IFIELD_RY],
24664 + AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000,
24665 + &avr32_syntax_table[AVR32_SYNTAX_SRAL],
24666 + BFD_RELOC_UNUSED, 1, -1,
24668 + &avr32_ifield_table[AVR32_IFIELD_RY],
24672 + AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000,
24673 + &avr32_syntax_table[AVR32_SYNTAX_SSRF],
24674 + BFD_RELOC_UNUSED, 1, -1,
24676 + &avr32_ifield_table[AVR32_IFIELD_K5C],
24680 + AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000,
24681 + &avr32_syntax_table[AVR32_SYNTAX_ST_B1],
24682 + BFD_RELOC_UNUSED, 2, -1,
24684 + &avr32_ifield_table[AVR32_IFIELD_RX],
24685 + &avr32_ifield_table[AVR32_IFIELD_RY],
24689 + AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000,
24690 + &avr32_syntax_table[AVR32_SYNTAX_ST_B2],
24691 + BFD_RELOC_UNUSED, 2, -1,
24693 + &avr32_ifield_table[AVR32_IFIELD_RX],
24694 + &avr32_ifield_table[AVR32_IFIELD_RY],
24698 + AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0,
24699 + &avr32_syntax_table[AVR32_SYNTAX_ST_B5],
24700 + BFD_RELOC_UNUSED, 4, -1,
24702 + &avr32_ifield_table[AVR32_IFIELD_RX],
24703 + &avr32_ifield_table[AVR32_IFIELD_RY],
24704 + &avr32_ifield_table[AVR32_IFIELD_K2],
24705 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24709 + AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000,
24710 + &avr32_syntax_table[AVR32_SYNTAX_ST_B3],
24711 + BFD_RELOC_AVR32_3U, 3, 1,
24713 + &avr32_ifield_table[AVR32_IFIELD_RX],
24714 + &avr32_ifield_table[AVR32_IFIELD_K3],
24715 + &avr32_ifield_table[AVR32_IFIELD_RY],
24719 + AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000,
24720 + &avr32_syntax_table[AVR32_SYNTAX_ST_B4],
24721 + BFD_RELOC_AVR32_16S, 3, 1,
24723 + &avr32_ifield_table[AVR32_IFIELD_RX],
24724 + &avr32_ifield_table[AVR32_IFIELD_K16],
24725 + &avr32_ifield_table[AVR32_IFIELD_RY],
24729 + AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000,
24730 + &avr32_syntax_table[AVR32_SYNTAX_ST_D1],
24731 + BFD_RELOC_UNUSED, 2, -1,
24733 + &avr32_ifield_table[AVR32_IFIELD_RX],
24734 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24738 + AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000,
24739 + &avr32_syntax_table[AVR32_SYNTAX_ST_D2],
24740 + BFD_RELOC_UNUSED, 2, -1,
24742 + &avr32_ifield_table[AVR32_IFIELD_RX],
24743 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24747 + AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000,
24748 + &avr32_syntax_table[AVR32_SYNTAX_ST_D3],
24749 + BFD_RELOC_UNUSED, 2, -1,
24751 + &avr32_ifield_table[AVR32_IFIELD_RX],
24752 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24756 + AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1,
24757 + &avr32_syntax_table[AVR32_SYNTAX_ST_D5],
24758 + BFD_RELOC_UNUSED, 4, -1,
24760 + &avr32_ifield_table[AVR32_IFIELD_RX],
24761 + &avr32_ifield_table[AVR32_IFIELD_RY],
24762 + &avr32_ifield_table[AVR32_IFIELD_K2],
24763 + &avr32_ifield_table[AVR32_IFIELD_RD_DW],
24767 + AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000,
24768 + &avr32_syntax_table[AVR32_SYNTAX_ST_D4],
24769 + BFD_RELOC_AVR32_16S, 3, 1,
24771 + &avr32_ifield_table[AVR32_IFIELD_RX],
24772 + &avr32_ifield_table[AVR32_IFIELD_K16],
24773 + &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24777 + AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000,
24778 + &avr32_syntax_table[AVR32_SYNTAX_ST_H1],
24779 + BFD_RELOC_UNUSED, 2, -1,
24781 + &avr32_ifield_table[AVR32_IFIELD_RX],
24782 + &avr32_ifield_table[AVR32_IFIELD_RY],
24786 + AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000,
24787 + &avr32_syntax_table[AVR32_SYNTAX_ST_H2],
24788 + BFD_RELOC_UNUSED, 2, -1,
24790 + &avr32_ifield_table[AVR32_IFIELD_RX],
24791 + &avr32_ifield_table[AVR32_IFIELD_RY],
24795 + AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0,
24796 + &avr32_syntax_table[AVR32_SYNTAX_ST_H5],
24797 + BFD_RELOC_UNUSED, 4, -1,
24799 + &avr32_ifield_table[AVR32_IFIELD_RX],
24800 + &avr32_ifield_table[AVR32_IFIELD_RY],
24801 + &avr32_ifield_table[AVR32_IFIELD_K2],
24802 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24806 + AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000,
24807 + &avr32_syntax_table[AVR32_SYNTAX_ST_H3],
24808 + BFD_RELOC_AVR32_4UH, 3, 1,
24810 + &avr32_ifield_table[AVR32_IFIELD_RX],
24811 + &avr32_ifield_table[AVR32_IFIELD_K3],
24812 + &avr32_ifield_table[AVR32_IFIELD_RY],
24816 + AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000,
24817 + &avr32_syntax_table[AVR32_SYNTAX_ST_H4],
24818 + BFD_RELOC_AVR32_16S, 3, 1,
24820 + &avr32_ifield_table[AVR32_IFIELD_RX],
24821 + &avr32_ifield_table[AVR32_IFIELD_K16],
24822 + &avr32_ifield_table[AVR32_IFIELD_RY],
24826 + AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000,
24827 + &avr32_syntax_table[AVR32_SYNTAX_ST_W1],
24828 + BFD_RELOC_UNUSED, 2, -1,
24830 + &avr32_ifield_table[AVR32_IFIELD_RX],
24831 + &avr32_ifield_table[AVR32_IFIELD_RY],
24835 + AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000,
24836 + &avr32_syntax_table[AVR32_SYNTAX_ST_W2],
24837 + BFD_RELOC_UNUSED, 2, -1,
24839 + &avr32_ifield_table[AVR32_IFIELD_RX],
24840 + &avr32_ifield_table[AVR32_IFIELD_RY],
24844 + AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0,
24845 + &avr32_syntax_table[AVR32_SYNTAX_ST_W5],
24846 + BFD_RELOC_UNUSED, 4, -1,
24848 + &avr32_ifield_table[AVR32_IFIELD_RX],
24849 + &avr32_ifield_table[AVR32_IFIELD_RY],
24850 + &avr32_ifield_table[AVR32_IFIELD_K2],
24851 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24855 + AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000,
24856 + &avr32_syntax_table[AVR32_SYNTAX_ST_W3],
24857 + BFD_RELOC_AVR32_6UW, 3, 1,
24859 + &avr32_ifield_table[AVR32_IFIELD_RX],
24860 + &avr32_ifield_table[AVR32_IFIELD_K4],
24861 + &avr32_ifield_table[AVR32_IFIELD_RY],
24865 + AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000,
24866 + &avr32_syntax_table[AVR32_SYNTAX_ST_W4],
24867 + BFD_RELOC_AVR32_16S, 3, 1,
24869 + &avr32_ifield_table[AVR32_IFIELD_RX],
24870 + &avr32_ifield_table[AVR32_IFIELD_K16],
24871 + &avr32_ifield_table[AVR32_IFIELD_RY],
24875 + AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100,
24876 + &avr32_syntax_table[AVR32_SYNTAX_STC_D1],
24877 + BFD_RELOC_AVR32_10UW, 4, 2,
24879 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24880 + &avr32_ifield_table[AVR32_IFIELD_RY],
24881 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24882 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24886 + AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0,
24887 + &avr32_syntax_table[AVR32_SYNTAX_STC_D2],
24888 + BFD_RELOC_UNUSED, 3, -1,
24890 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24891 + &avr32_ifield_table[AVR32_IFIELD_RY],
24892 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24896 + AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0,
24897 + &avr32_syntax_table[AVR32_SYNTAX_STC_D3],
24898 + BFD_RELOC_UNUSED, 5, -1,
24900 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24901 + &avr32_ifield_table[AVR32_IFIELD_RY],
24902 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24903 + &avr32_ifield_table[AVR32_IFIELD_K2],
24904 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24908 + AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000,
24909 + &avr32_syntax_table[AVR32_SYNTAX_STC_W1],
24910 + BFD_RELOC_AVR32_10UW, 4, 2,
24912 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24913 + &avr32_ifield_table[AVR32_IFIELD_RY],
24914 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24915 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24919 + AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff,
24920 + &avr32_syntax_table[AVR32_SYNTAX_STC_W2],
24921 + BFD_RELOC_UNUSED, 3, -1,
24923 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24924 + &avr32_ifield_table[AVR32_IFIELD_RY],
24925 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24929 + AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0,
24930 + &avr32_syntax_table[AVR32_SYNTAX_STC_W3],
24931 + BFD_RELOC_UNUSED, 5, -1,
24933 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24934 + &avr32_ifield_table[AVR32_IFIELD_RY],
24935 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
24936 + &avr32_ifield_table[AVR32_IFIELD_K2],
24937 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24941 + AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100,
24942 + &avr32_syntax_table[AVR32_SYNTAX_STC0_D],
24943 + BFD_RELOC_AVR32_14UW, 3, 1,
24945 + &avr32_ifield_table[AVR32_IFIELD_RY],
24946 + &avr32_ifield_table[AVR32_IFIELD_K12CP],
24947 + &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24951 + AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000,
24952 + &avr32_syntax_table[AVR32_SYNTAX_STC0_W],
24953 + BFD_RELOC_AVR32_14UW, 3, 1,
24955 + &avr32_ifield_table[AVR32_IFIELD_RY],
24956 + &avr32_ifield_table[AVR32_IFIELD_K12CP],
24957 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24961 + AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00,
24962 + &avr32_syntax_table[AVR32_SYNTAX_STCM_D],
24963 + BFD_RELOC_UNUSED, 3, -1,
24965 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24966 + &avr32_ifield_table[AVR32_IFIELD_RY],
24967 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24971 + AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00,
24972 + &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU],
24973 + BFD_RELOC_UNUSED, 3, -1,
24975 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24976 + &avr32_ifield_table[AVR32_IFIELD_RY],
24977 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24981 + AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00,
24982 + &avr32_syntax_table[AVR32_SYNTAX_STCM_W],
24983 + BFD_RELOC_UNUSED, 4, -1,
24985 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24986 + &avr32_ifield_table[AVR32_IFIELD_RY],
24987 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24988 + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
24992 + AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00,
24993 + &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU],
24994 + BFD_RELOC_UNUSED, 4, -1,
24996 + &avr32_ifield_table[AVR32_IFIELD_CPNO],
24997 + &avr32_ifield_table[AVR32_IFIELD_RY],
24998 + &avr32_ifield_table[AVR32_IFIELD_K8E],
24999 + &avr32_ifield_table[AVR32_IFIELD_CM_HL],
25003 + AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000,
25004 + &avr32_syntax_table[AVR32_SYNTAX_STCOND],
25005 + BFD_RELOC_UNUSED, 3, -1,
25007 + &avr32_ifield_table[AVR32_IFIELD_RX],
25008 + &avr32_ifield_table[AVR32_IFIELD_K16],
25009 + &avr32_ifield_table[AVR32_IFIELD_RY],
25013 + AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000,
25014 + &avr32_syntax_table[AVR32_SYNTAX_STDSP],
25015 + BFD_RELOC_UNUSED, 2, -1,
25017 + &avr32_ifield_table[AVR32_IFIELD_K7C],
25018 + &avr32_ifield_table[AVR32_IFIELD_RY],
25022 + AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0,
25023 + &avr32_syntax_table[AVR32_SYNTAX_STHH_W2],
25024 + BFD_RELOC_UNUSED, 7, -1,
25026 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
25027 + &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
25028 + &avr32_ifield_table[AVR32_IFIELD_K2],
25029 + &avr32_ifield_table[AVR32_IFIELD_RX],
25030 + &avr32_ifield_table[AVR32_IFIELD_X2],
25031 + &avr32_ifield_table[AVR32_IFIELD_RY],
25032 + &avr32_ifield_table[AVR32_IFIELD_Y2],
25036 + AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000,
25037 + &avr32_syntax_table[AVR32_SYNTAX_STHH_W1],
25038 + BFD_RELOC_AVR32_STHH_W, 6, 1,
25040 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
25041 + &avr32_ifield_table[AVR32_IFIELD_K8E2],
25042 + &avr32_ifield_table[AVR32_IFIELD_RX],
25043 + &avr32_ifield_table[AVR32_IFIELD_X2],
25044 + &avr32_ifield_table[AVR32_IFIELD_RY],
25045 + &avr32_ifield_table[AVR32_IFIELD_Y2],
25049 + AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000,
25050 + &avr32_syntax_table[AVR32_SYNTAX_STM],
25051 + BFD_RELOC_UNUSED, 2, -1,
25053 + &avr32_ifield_table[AVR32_IFIELD_RY],
25054 + &avr32_ifield_table[AVR32_IFIELD_K16],
25058 + AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000,
25059 + &avr32_syntax_table[AVR32_SYNTAX_STM_PU],
25060 + BFD_RELOC_UNUSED, 2, -1,
25062 + &avr32_ifield_table[AVR32_IFIELD_RY],
25063 + &avr32_ifield_table[AVR32_IFIELD_K16],
25067 + AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000,
25068 + &avr32_syntax_table[AVR32_SYNTAX_STMTS],
25069 + BFD_RELOC_UNUSED, 2, -1,
25071 + &avr32_ifield_table[AVR32_IFIELD_RY],
25072 + &avr32_ifield_table[AVR32_IFIELD_K16],
25076 + AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000,
25077 + &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU],
25078 + BFD_RELOC_UNUSED, 2, -1,
25080 + &avr32_ifield_table[AVR32_IFIELD_RY],
25081 + &avr32_ifield_table[AVR32_IFIELD_K16],
25085 + AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000,
25086 + &avr32_syntax_table[AVR32_SYNTAX_STSWP_H],
25087 + BFD_RELOC_UNUSED, 3, -1,
25089 + &avr32_ifield_table[AVR32_IFIELD_RX],
25090 + &avr32_ifield_table[AVR32_IFIELD_K12],
25091 + &avr32_ifield_table[AVR32_IFIELD_RY],
25095 + AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000,
25096 + &avr32_syntax_table[AVR32_SYNTAX_STSWP_W],
25097 + BFD_RELOC_UNUSED, 3, -1,
25099 + &avr32_ifield_table[AVR32_IFIELD_RX],
25100 + &avr32_ifield_table[AVR32_IFIELD_K12],
25101 + &avr32_ifield_table[AVR32_IFIELD_RY],
25105 + AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000,
25106 + &avr32_syntax_table[AVR32_SYNTAX_SUB1],
25107 + BFD_RELOC_UNUSED, 2, -1,
25109 + &avr32_ifield_table[AVR32_IFIELD_RY],
25110 + &avr32_ifield_table[AVR32_IFIELD_RX],
25114 + AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0,
25115 + &avr32_syntax_table[AVR32_SYNTAX_SUB2],
25116 + BFD_RELOC_UNUSED, 4, -1,
25118 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
25119 + &avr32_ifield_table[AVR32_IFIELD_RX],
25120 + &avr32_ifield_table[AVR32_IFIELD_RY],
25121 + &avr32_ifield_table[AVR32_IFIELD_K2],
25125 + AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000,
25126 + &avr32_syntax_table[AVR32_SYNTAX_SUB5],
25127 + BFD_RELOC_AVR32_SUB5, 3, 2,
25129 + &avr32_ifield_table[AVR32_IFIELD_RY],
25130 + &avr32_ifield_table[AVR32_IFIELD_RX],
25131 + &avr32_ifield_table[AVR32_IFIELD_K16],
25135 + AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000,
25136 + &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP],
25137 + BFD_RELOC_AVR32_10SW, 2, 1,
25139 + &avr32_ifield_table[AVR32_IFIELD_RY],
25140 + &avr32_ifield_table[AVR32_IFIELD_K8C],
25144 + AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000,
25145 + &avr32_syntax_table[AVR32_SYNTAX_SUB3],
25146 + BFD_RELOC_AVR32_8S, 2, 1,
25148 + &avr32_ifield_table[AVR32_IFIELD_RY],
25149 + &avr32_ifield_table[AVR32_IFIELD_K8C],
25153 + AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000,
25154 + &avr32_syntax_table[AVR32_SYNTAX_SUB4],
25155 + BFD_RELOC_AVR32_21S, 2, 1,
25157 + &avr32_ifield_table[AVR32_IFIELD_RY],
25158 + &avr32_ifield_table[AVR32_IFIELD_K21],
25162 + AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00,
25163 + &avr32_syntax_table[AVR32_SYNTAX_SUBEQ],
25164 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25166 + &avr32_ifield_table[AVR32_IFIELD_RY],
25167 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25171 + AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00,
25172 + &avr32_syntax_table[AVR32_SYNTAX_SUBNE],
25173 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25175 + &avr32_ifield_table[AVR32_IFIELD_RY],
25176 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25180 + AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00,
25181 + &avr32_syntax_table[AVR32_SYNTAX_SUBHS],
25182 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25184 + &avr32_ifield_table[AVR32_IFIELD_RY],
25185 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25189 + AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00,
25190 + &avr32_syntax_table[AVR32_SYNTAX_SUBLO],
25191 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25193 + &avr32_ifield_table[AVR32_IFIELD_RY],
25194 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25198 + AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00,
25199 + &avr32_syntax_table[AVR32_SYNTAX_SUBGE],
25200 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25202 + &avr32_ifield_table[AVR32_IFIELD_RY],
25203 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25207 + AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00,
25208 + &avr32_syntax_table[AVR32_SYNTAX_SUBLT],
25209 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25211 + &avr32_ifield_table[AVR32_IFIELD_RY],
25212 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25216 + AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00,
25217 + &avr32_syntax_table[AVR32_SYNTAX_SUBMI],
25218 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25220 + &avr32_ifield_table[AVR32_IFIELD_RY],
25221 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25225 + AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00,
25226 + &avr32_syntax_table[AVR32_SYNTAX_SUBPL],
25227 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25229 + &avr32_ifield_table[AVR32_IFIELD_RY],
25230 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25234 + AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00,
25235 + &avr32_syntax_table[AVR32_SYNTAX_SUBLS],
25236 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25238 + &avr32_ifield_table[AVR32_IFIELD_RY],
25239 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25243 + AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00,
25244 + &avr32_syntax_table[AVR32_SYNTAX_SUBGT],
25245 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25247 + &avr32_ifield_table[AVR32_IFIELD_RY],
25248 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25252 + AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00,
25253 + &avr32_syntax_table[AVR32_SYNTAX_SUBLE],
25254 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25256 + &avr32_ifield_table[AVR32_IFIELD_RY],
25257 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25261 + AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00,
25262 + &avr32_syntax_table[AVR32_SYNTAX_SUBHI],
25263 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25265 + &avr32_ifield_table[AVR32_IFIELD_RY],
25266 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25270 + AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00,
25271 + &avr32_syntax_table[AVR32_SYNTAX_SUBVS],
25272 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25274 + &avr32_ifield_table[AVR32_IFIELD_RY],
25275 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25279 + AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00,
25280 + &avr32_syntax_table[AVR32_SYNTAX_SUBVC],
25281 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25283 + &avr32_ifield_table[AVR32_IFIELD_RY],
25284 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25288 + AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00,
25289 + &avr32_syntax_table[AVR32_SYNTAX_SUBQS],
25290 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25292 + &avr32_ifield_table[AVR32_IFIELD_RY],
25293 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25297 + AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00,
25298 + &avr32_syntax_table[AVR32_SYNTAX_SUBAL],
25299 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25301 + &avr32_ifield_table[AVR32_IFIELD_RY],
25302 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25306 + AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00,
25307 + &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ],
25308 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25310 + &avr32_ifield_table[AVR32_IFIELD_RY],
25311 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25315 + AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00,
25316 + &avr32_syntax_table[AVR32_SYNTAX_SUBFNE],
25317 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25319 + &avr32_ifield_table[AVR32_IFIELD_RY],
25320 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25324 + AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00,
25325 + &avr32_syntax_table[AVR32_SYNTAX_SUBFHS],
25326 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25328 + &avr32_ifield_table[AVR32_IFIELD_RY],
25329 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25333 + AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00,
25334 + &avr32_syntax_table[AVR32_SYNTAX_SUBFLO],
25335 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25337 + &avr32_ifield_table[AVR32_IFIELD_RY],
25338 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25342 + AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00,
25343 + &avr32_syntax_table[AVR32_SYNTAX_SUBFGE],
25344 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25346 + &avr32_ifield_table[AVR32_IFIELD_RY],
25347 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25351 + AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00,
25352 + &avr32_syntax_table[AVR32_SYNTAX_SUBFLT],
25353 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25355 + &avr32_ifield_table[AVR32_IFIELD_RY],
25356 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25360 + AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00,
25361 + &avr32_syntax_table[AVR32_SYNTAX_SUBFMI],
25362 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25364 + &avr32_ifield_table[AVR32_IFIELD_RY],
25365 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25369 + AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00,
25370 + &avr32_syntax_table[AVR32_SYNTAX_SUBFPL],
25371 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25373 + &avr32_ifield_table[AVR32_IFIELD_RY],
25374 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25378 + AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00,
25379 + &avr32_syntax_table[AVR32_SYNTAX_SUBFLS],
25380 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25382 + &avr32_ifield_table[AVR32_IFIELD_RY],
25383 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25387 + AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00,
25388 + &avr32_syntax_table[AVR32_SYNTAX_SUBFGT],
25389 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25391 + &avr32_ifield_table[AVR32_IFIELD_RY],
25392 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25396 + AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00,
25397 + &avr32_syntax_table[AVR32_SYNTAX_SUBFLE],
25398 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25400 + &avr32_ifield_table[AVR32_IFIELD_RY],
25401 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25405 + AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00,
25406 + &avr32_syntax_table[AVR32_SYNTAX_SUBFHI],
25407 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25409 + &avr32_ifield_table[AVR32_IFIELD_RY],
25410 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25414 + AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00,
25415 + &avr32_syntax_table[AVR32_SYNTAX_SUBFVS],
25416 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25418 + &avr32_ifield_table[AVR32_IFIELD_RY],
25419 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25423 + AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00,
25424 + &avr32_syntax_table[AVR32_SYNTAX_SUBFVC],
25425 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25427 + &avr32_ifield_table[AVR32_IFIELD_RY],
25428 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25432 + AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00,
25433 + &avr32_syntax_table[AVR32_SYNTAX_SUBFQS],
25434 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25436 + &avr32_ifield_table[AVR32_IFIELD_RY],
25437 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25441 + AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00,
25442 + &avr32_syntax_table[AVR32_SYNTAX_SUBFAL],
25443 + BFD_RELOC_AVR32_8S_EXT, 2, 1,
25445 + &avr32_ifield_table[AVR32_IFIELD_RY],
25446 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25450 + AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0,
25451 + &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W],
25452 + BFD_RELOC_UNUSED, 5, -1,
25454 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
25455 + &avr32_ifield_table[AVR32_IFIELD_RX],
25456 + &avr32_ifield_table[AVR32_IFIELD_X],
25457 + &avr32_ifield_table[AVR32_IFIELD_RY],
25458 + &avr32_ifield_table[AVR32_IFIELD_Y],
25462 + AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000,
25463 + &avr32_syntax_table[AVR32_SYNTAX_SWAP_B],
25464 + BFD_RELOC_UNUSED, 1, -1,
25466 + &avr32_ifield_table[AVR32_IFIELD_RY],
25470 + AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000,
25471 + &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH],
25472 + BFD_RELOC_UNUSED, 1, -1,
25474 + &avr32_ifield_table[AVR32_IFIELD_RY],
25478 + AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000,
25479 + &avr32_syntax_table[AVR32_SYNTAX_SWAP_H],
25480 + BFD_RELOC_UNUSED, 1, -1,
25482 + &avr32_ifield_table[AVR32_IFIELD_RY],
25486 + AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00,
25487 + &avr32_syntax_table[AVR32_SYNTAX_SYNC],
25488 + BFD_RELOC_AVR32_8S_EXT, 1, 0,
25490 + &avr32_ifield_table[AVR32_IFIELD_K8E],
25494 + AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000,
25495 + &avr32_syntax_table[AVR32_SYNTAX_TLBR],
25496 + BFD_RELOC_UNUSED, 0, -1, { NULL },
25499 + AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000,
25500 + &avr32_syntax_table[AVR32_SYNTAX_TLBS],
25501 + BFD_RELOC_UNUSED, 0, -1, { NULL },
25504 + AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000,
25505 + &avr32_syntax_table[AVR32_SYNTAX_TLBW],
25506 + BFD_RELOC_UNUSED, 0, -1, { NULL },
25509 + AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000,
25510 + &avr32_syntax_table[AVR32_SYNTAX_TNBZ],
25511 + BFD_RELOC_UNUSED, 1, -1,
25513 + &avr32_ifield_table[AVR32_IFIELD_RY],
25517 + AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000,
25518 + &avr32_syntax_table[AVR32_SYNTAX_TST],
25519 + BFD_RELOC_UNUSED, 2, -1,
25521 + &avr32_ifield_table[AVR32_IFIELD_RY],
25522 + &avr32_ifield_table[AVR32_IFIELD_RX],
25526 + AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0,
25527 + &avr32_syntax_table[AVR32_SYNTAX_XCHG],
25528 + BFD_RELOC_UNUSED, 3, -1,
25530 + &avr32_ifield_table[AVR32_IFIELD_RD_E],
25531 + &avr32_ifield_table[AVR32_IFIELD_RX],
25532 + &avr32_ifield_table[AVR32_IFIELD_RY],
25536 + AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000,
25537 + &avr32_syntax_table[AVR32_SYNTAX_MEMC],
25538 + BFD_RELOC_AVR32_15S, 2, 0,
25540 + &avr32_ifield_table[AVR32_IFIELD_MEM15],
25541 + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25545 + AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000,
25546 + &avr32_syntax_table[AVR32_SYNTAX_MEMS],
25547 + BFD_RELOC_AVR32_15S, 2, 0,
25549 + &avr32_ifield_table[AVR32_IFIELD_MEM15],
25550 + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25554 + AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000,
25555 + &avr32_syntax_table[AVR32_SYNTAX_MEMT],
25556 + BFD_RELOC_AVR32_15S, 2, 0,
25558 + &avr32_ifield_table[AVR32_IFIELD_MEM15],
25559 + &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25563 + AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00,
25564 + &avr32_syntax_table[AVR32_SYNTAX_BFEXTS],
25565 + BFD_RELOC_UNUSED, 4, -1,
25567 + &avr32_ifield_table[AVR32_IFIELD_RX],
25568 + &avr32_ifield_table[AVR32_IFIELD_RY],
25569 + &avr32_ifield_table[AVR32_IFIELD_S5],
25570 + &avr32_ifield_table[AVR32_IFIELD_K5E],
25574 + AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00,
25575 + &avr32_syntax_table[AVR32_SYNTAX_BFEXTU],
25576 + BFD_RELOC_UNUSED, 4, -1,
25578 + &avr32_ifield_table[AVR32_IFIELD_RX],
25579 + &avr32_ifield_table[AVR32_IFIELD_RY],
25580 + &avr32_ifield_table[AVR32_IFIELD_S5],
25581 + &avr32_ifield_table[AVR32_IFIELD_K5E],
25585 + AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00,
25586 + &avr32_syntax_table[AVR32_SYNTAX_BFINS],
25587 + BFD_RELOC_UNUSED, 4, -1,
25589 + &avr32_ifield_table[AVR32_IFIELD_RX],
25590 + &avr32_ifield_table[AVR32_IFIELD_RY],
25591 + &avr32_ifield_table[AVR32_IFIELD_S5],
25592 + &avr32_ifield_table[AVR32_IFIELD_K5E],
25595 +#define AVR32_OPCODE_RSUBCOND(cond_name, cond_field) \
25597 + AVR32_OPC_RSUB ## cond_name , 4, \
25598 + 0xfbb00000 | (cond_field << 8), 0xfff0ff00, \
25599 + &avr32_syntax_table[AVR32_SYNTAX_RSUB ## cond_name ], \
25600 + BFD_RELOC_AVR32_8S_EXT, 2, 1, \
25602 + &avr32_ifield_table[AVR32_IFIELD_RY], \
25603 + &avr32_ifield_table[AVR32_IFIELD_K8E], \
25607 + AVR32_OPCODE_RSUBCOND (EQ, 0)
25608 + AVR32_OPCODE_RSUBCOND (NE, 1)
25609 + AVR32_OPCODE_RSUBCOND (CC, 2)
25610 + AVR32_OPCODE_RSUBCOND (CS, 3)
25611 + AVR32_OPCODE_RSUBCOND (GE, 4)
25612 + AVR32_OPCODE_RSUBCOND (LT, 5)
25613 + AVR32_OPCODE_RSUBCOND (MI, 6)
25614 + AVR32_OPCODE_RSUBCOND (PL, 7)
25615 + AVR32_OPCODE_RSUBCOND (LS, 8)
25616 + AVR32_OPCODE_RSUBCOND (GT, 9)
25617 + AVR32_OPCODE_RSUBCOND (LE, 10)
25618 + AVR32_OPCODE_RSUBCOND (HI, 11)
25619 + AVR32_OPCODE_RSUBCOND (VS, 12)
25620 + AVR32_OPCODE_RSUBCOND (VC, 13)
25621 + AVR32_OPCODE_RSUBCOND (QS, 14)
25622 + AVR32_OPCODE_RSUBCOND (AL, 15)
25624 +#define AVR32_OPCODE_OP3_COND(op_name, op_field, cond_name, cond_field) \
25626 + AVR32_OPC_ ## op_name ## cond_name , 4, \
25627 + 0xe1d0e000 | (cond_field << 8) | (op_field << 4), 0xe1f0fff0, \
25628 + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
25629 + BFD_RELOC_UNUSED, 3, -1, \
25631 + &avr32_ifield_table[AVR32_IFIELD_RD_E], \
25632 + &avr32_ifield_table[AVR32_IFIELD_RX], \
25633 + &avr32_ifield_table[AVR32_IFIELD_RY], \
25637 + AVR32_OPCODE_OP3_COND (ADD, 0, EQ, 0)
25638 + AVR32_OPCODE_OP3_COND (ADD, 0, NE, 1)
25639 + AVR32_OPCODE_OP3_COND (ADD, 0, CC, 2)
25640 + AVR32_OPCODE_OP3_COND (ADD, 0, CS, 3)
25641 + AVR32_OPCODE_OP3_COND (ADD, 0, GE, 4)
25642 + AVR32_OPCODE_OP3_COND (ADD, 0, LT, 5)
25643 + AVR32_OPCODE_OP3_COND (ADD, 0, MI, 6)
25644 + AVR32_OPCODE_OP3_COND (ADD, 0, PL, 7)
25645 + AVR32_OPCODE_OP3_COND (ADD, 0, LS, 8)
25646 + AVR32_OPCODE_OP3_COND (ADD, 0, GT, 9)
25647 + AVR32_OPCODE_OP3_COND (ADD, 0, LE, 10)
25648 + AVR32_OPCODE_OP3_COND (ADD, 0, HI, 11)
25649 + AVR32_OPCODE_OP3_COND (ADD, 0, VS, 12)
25650 + AVR32_OPCODE_OP3_COND (ADD, 0, VC, 13)
25651 + AVR32_OPCODE_OP3_COND (ADD, 0, QS, 14)
25652 + AVR32_OPCODE_OP3_COND (ADD, 0, AL, 15)
25654 + AVR32_OPCODE_OP3_COND (SUB2, 1, EQ, 0)
25655 + AVR32_OPCODE_OP3_COND (SUB2, 1, NE, 1)
25656 + AVR32_OPCODE_OP3_COND (SUB2, 1, CC, 2)
25657 + AVR32_OPCODE_OP3_COND (SUB2, 1, CS, 3)
25658 + AVR32_OPCODE_OP3_COND (SUB2, 1, GE, 4)
25659 + AVR32_OPCODE_OP3_COND (SUB2, 1, LT, 5)
25660 + AVR32_OPCODE_OP3_COND (SUB2, 1, MI, 6)
25661 + AVR32_OPCODE_OP3_COND (SUB2, 1, PL, 7)
25662 + AVR32_OPCODE_OP3_COND (SUB2, 1, LS, 8)
25663 + AVR32_OPCODE_OP3_COND (SUB2, 1, GT, 9)
25664 + AVR32_OPCODE_OP3_COND (SUB2, 1, LE, 10)
25665 + AVR32_OPCODE_OP3_COND (SUB2, 1, HI, 11)
25666 + AVR32_OPCODE_OP3_COND (SUB2, 1, VS, 12)
25667 + AVR32_OPCODE_OP3_COND (SUB2, 1, VC, 13)
25668 + AVR32_OPCODE_OP3_COND (SUB2, 1, QS, 14)
25669 + AVR32_OPCODE_OP3_COND (SUB2, 1, AL, 15)
25671 + AVR32_OPCODE_OP3_COND (AND, 2, EQ, 0)
25672 + AVR32_OPCODE_OP3_COND (AND, 2, NE, 1)
25673 + AVR32_OPCODE_OP3_COND (AND, 2, CC, 2)
25674 + AVR32_OPCODE_OP3_COND (AND, 2, CS, 3)
25675 + AVR32_OPCODE_OP3_COND (AND, 2, GE, 4)
25676 + AVR32_OPCODE_OP3_COND (AND, 2, LT, 5)
25677 + AVR32_OPCODE_OP3_COND (AND, 2, MI, 6)
25678 + AVR32_OPCODE_OP3_COND (AND, 2, PL, 7)
25679 + AVR32_OPCODE_OP3_COND (AND, 2, LS, 8)
25680 + AVR32_OPCODE_OP3_COND (AND, 2, GT, 9)
25681 + AVR32_OPCODE_OP3_COND (AND, 2, LE, 10)
25682 + AVR32_OPCODE_OP3_COND (AND, 2, HI, 11)
25683 + AVR32_OPCODE_OP3_COND (AND, 2, VS, 12)
25684 + AVR32_OPCODE_OP3_COND (AND, 2, VC, 13)
25685 + AVR32_OPCODE_OP3_COND (AND, 2, QS, 14)
25686 + AVR32_OPCODE_OP3_COND (AND, 2, AL, 15)
25688 + AVR32_OPCODE_OP3_COND (OR, 3, EQ, 0)
25689 + AVR32_OPCODE_OP3_COND (OR, 3, NE, 1)
25690 + AVR32_OPCODE_OP3_COND (OR, 3, CC, 2)
25691 + AVR32_OPCODE_OP3_COND (OR, 3, CS, 3)
25692 + AVR32_OPCODE_OP3_COND (OR, 3, GE, 4)
25693 + AVR32_OPCODE_OP3_COND (OR, 3, LT, 5)
25694 + AVR32_OPCODE_OP3_COND (OR, 3, MI, 6)
25695 + AVR32_OPCODE_OP3_COND (OR, 3, PL, 7)
25696 + AVR32_OPCODE_OP3_COND (OR, 3, LS, 8)
25697 + AVR32_OPCODE_OP3_COND (OR, 3, GT, 9)
25698 + AVR32_OPCODE_OP3_COND (OR, 3, LE, 10)
25699 + AVR32_OPCODE_OP3_COND (OR, 3, HI, 11)
25700 + AVR32_OPCODE_OP3_COND (OR, 3, VS, 12)
25701 + AVR32_OPCODE_OP3_COND (OR, 3, VC, 13)
25702 + AVR32_OPCODE_OP3_COND (OR, 3, QS, 14)
25703 + AVR32_OPCODE_OP3_COND (OR, 3, AL, 15)
25705 + AVR32_OPCODE_OP3_COND (EOR, 4, EQ, 0)
25706 + AVR32_OPCODE_OP3_COND (EOR, 4, NE, 1)
25707 + AVR32_OPCODE_OP3_COND (EOR, 4, CC, 2)
25708 + AVR32_OPCODE_OP3_COND (EOR, 4, CS, 3)
25709 + AVR32_OPCODE_OP3_COND (EOR, 4, GE, 4)
25710 + AVR32_OPCODE_OP3_COND (EOR, 4, LT, 5)
25711 + AVR32_OPCODE_OP3_COND (EOR, 4, MI, 6)
25712 + AVR32_OPCODE_OP3_COND (EOR, 4, PL, 7)
25713 + AVR32_OPCODE_OP3_COND (EOR, 4, LS, 8)
25714 + AVR32_OPCODE_OP3_COND (EOR, 4, GT, 9)
25715 + AVR32_OPCODE_OP3_COND (EOR, 4, LE, 10)
25716 + AVR32_OPCODE_OP3_COND (EOR, 4, HI, 11)
25717 + AVR32_OPCODE_OP3_COND (EOR, 4, VS, 12)
25718 + AVR32_OPCODE_OP3_COND (EOR, 4, VC, 13)
25719 + AVR32_OPCODE_OP3_COND (EOR, 4, QS, 14)
25720 + AVR32_OPCODE_OP3_COND (EOR, 4, AL, 15)
25722 +#define AVR32_OPCODE_LD_COND(op_name, op_field, cond_name, cond_field) \
25724 + AVR32_OPC_ ## op_name ## cond_name , 4, \
25725 + 0xe1f00000 | (cond_field << 12) | (op_field << 9), 0xe1f0fe00, \
25726 + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
25727 + BFD_RELOC_UNUSED, 3, -1, \
25729 + &avr32_ifield_table[AVR32_IFIELD_RY], \
25730 + &avr32_ifield_table[AVR32_IFIELD_RX], \
25731 + &avr32_ifield_table[AVR32_IFIELD_K9E], \
25735 +#define AVR32_OPCODE_ST_COND(op_name, op_field, cond_name, cond_field) \
25737 + AVR32_OPC_ ## op_name ## cond_name , 4, \
25738 + 0xe1f00000 | (cond_field << 12) | (op_field << 9), 0xe1f0fe00, \
25739 + &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ], \
25740 + BFD_RELOC_UNUSED, 3, -1, \
25742 + &avr32_ifield_table[AVR32_IFIELD_RX], \
25743 + &avr32_ifield_table[AVR32_IFIELD_K9E], \
25744 + &avr32_ifield_table[AVR32_IFIELD_RY], \
25748 + AVR32_OPCODE_LD_COND (LD_W, 0, EQ, 0)
25749 + AVR32_OPCODE_LD_COND (LD_W, 0, NE, 1)
25750 + AVR32_OPCODE_LD_COND (LD_W, 0, CC, 2)
25751 + AVR32_OPCODE_LD_COND (LD_W, 0, CS, 3)
25752 + AVR32_OPCODE_LD_COND (LD_W, 0, GE, 4)
25753 + AVR32_OPCODE_LD_COND (LD_W, 0, LT, 5)
25754 + AVR32_OPCODE_LD_COND (LD_W, 0, MI, 6)
25755 + AVR32_OPCODE_LD_COND (LD_W, 0, PL, 7)
25756 + AVR32_OPCODE_LD_COND (LD_W, 0, LS, 8)
25757 + AVR32_OPCODE_LD_COND (LD_W, 0, GT, 9)
25758 + AVR32_OPCODE_LD_COND (LD_W, 0, LE, 10)
25759 + AVR32_OPCODE_LD_COND (LD_W, 0, HI, 11)
25760 + AVR32_OPCODE_LD_COND (LD_W, 0, VS, 12)
25761 + AVR32_OPCODE_LD_COND (LD_W, 0, VC, 13)
25762 + AVR32_OPCODE_LD_COND (LD_W, 0, QS, 14)
25763 + AVR32_OPCODE_LD_COND (LD_W, 0, AL, 15)
25765 + AVR32_OPCODE_LD_COND (LD_SH, 1, EQ, 0)
25766 + AVR32_OPCODE_LD_COND (LD_SH, 1, NE, 1)
25767 + AVR32_OPCODE_LD_COND (LD_SH, 1, CC, 2)
25768 + AVR32_OPCODE_LD_COND (LD_SH, 1, CS, 3)
25769 + AVR32_OPCODE_LD_COND (LD_SH, 1, GE, 4)
25770 + AVR32_OPCODE_LD_COND (LD_SH, 1, LT, 5)
25771 + AVR32_OPCODE_LD_COND (LD_SH, 1, MI, 6)
25772 + AVR32_OPCODE_LD_COND (LD_SH, 1, PL, 7)
25773 + AVR32_OPCODE_LD_COND (LD_SH, 1, LS, 8)
25774 + AVR32_OPCODE_LD_COND (LD_SH, 1, GT, 9)
25775 + AVR32_OPCODE_LD_COND (LD_SH, 1, LE, 10)
25776 + AVR32_OPCODE_LD_COND (LD_SH, 1, HI, 11)
25777 + AVR32_OPCODE_LD_COND (LD_SH, 1, VS, 12)
25778 + AVR32_OPCODE_LD_COND (LD_SH, 1, VC, 13)
25779 + AVR32_OPCODE_LD_COND (LD_SH, 1, QS, 14)
25780 + AVR32_OPCODE_LD_COND (LD_SH, 1, AL, 15)
25782 + AVR32_OPCODE_LD_COND (LD_UH, 2, EQ, 0)
25783 + AVR32_OPCODE_LD_COND (LD_UH, 2, NE, 1)
25784 + AVR32_OPCODE_LD_COND (LD_UH, 2, CC, 2)
25785 + AVR32_OPCODE_LD_COND (LD_UH, 2, CS, 3)
25786 + AVR32_OPCODE_LD_COND (LD_UH, 2, GE, 4)
25787 + AVR32_OPCODE_LD_COND (LD_UH, 2, LT, 5)
25788 + AVR32_OPCODE_LD_COND (LD_UH, 2, MI, 6)
25789 + AVR32_OPCODE_LD_COND (LD_UH, 2, PL, 7)
25790 + AVR32_OPCODE_LD_COND (LD_SH, 2, LS, 8)
25791 + AVR32_OPCODE_LD_COND (LD_SH, 2, GT, 9)
25792 + AVR32_OPCODE_LD_COND (LD_SH, 2, LE, 10)
25793 + AVR32_OPCODE_LD_COND (LD_SH, 2, HI, 11)
25794 + AVR32_OPCODE_LD_COND (LD_SH, 2, VS, 12)
25795 + AVR32_OPCODE_LD_COND (LD_SH, 2, VC, 13)
25796 + AVR32_OPCODE_LD_COND (LD_SH, 2, QS, 14)
25797 + AVR32_OPCODE_LD_COND (LD_SH, 2, AL, 15)
25799 + AVR32_OPCODE_LD_COND (LD_SB, 3, EQ, 0)
25800 + AVR32_OPCODE_LD_COND (LD_SB, 3, NE, 1)
25801 + AVR32_OPCODE_LD_COND (LD_SB, 3, CC, 2)
25802 + AVR32_OPCODE_LD_COND (LD_SB, 3, CS, 3)
25803 + AVR32_OPCODE_LD_COND (LD_SB, 3, GE, 4)
25804 + AVR32_OPCODE_LD_COND (LD_SB, 3, LT, 5)
25805 + AVR32_OPCODE_LD_COND (LD_SB, 3, MI, 6)
25806 + AVR32_OPCODE_LD_COND (LD_SB, 3, PL, 7)
25807 + AVR32_OPCODE_LD_COND (LD_SB, 3, LS, 8)
25808 + AVR32_OPCODE_LD_COND (LD_SB, 3, GT, 9)
25809 + AVR32_OPCODE_LD_COND (LD_SB, 3, LE, 10)
25810 + AVR32_OPCODE_LD_COND (LD_SB, 3, HI, 11)
25811 + AVR32_OPCODE_LD_COND (LD_SB, 3, VS, 12)
25812 + AVR32_OPCODE_LD_COND (LD_SB, 3, VC, 13)
25813 + AVR32_OPCODE_LD_COND (LD_SB, 3, QS, 14)
25814 + AVR32_OPCODE_LD_COND (LD_SB, 3, AL, 15)
25816 + AVR32_OPCODE_LD_COND (LD_UB, 4, EQ, 0)
25817 + AVR32_OPCODE_LD_COND (LD_UB, 4, NE, 1)
25818 + AVR32_OPCODE_LD_COND (LD_UB, 4, CC, 2)
25819 + AVR32_OPCODE_LD_COND (LD_UB, 4, CS, 3)
25820 + AVR32_OPCODE_LD_COND (LD_UB, 4, GE, 4)
25821 + AVR32_OPCODE_LD_COND (LD_UB, 4, LT, 5)
25822 + AVR32_OPCODE_LD_COND (LD_UB, 4, MI, 6)
25823 + AVR32_OPCODE_LD_COND (LD_UB, 4, PL, 7)
25824 + AVR32_OPCODE_LD_COND (LD_UB, 4, LS, 8)
25825 + AVR32_OPCODE_LD_COND (LD_UB, 4, GT, 9)
25826 + AVR32_OPCODE_LD_COND (LD_UB, 4, LE, 10)
25827 + AVR32_OPCODE_LD_COND (LD_UB, 4, HI, 11)
25828 + AVR32_OPCODE_LD_COND (LD_UB, 4, VS, 12)
25829 + AVR32_OPCODE_LD_COND (LD_UB, 4, VC, 13)
25830 + AVR32_OPCODE_LD_COND (LD_UB, 4, QS, 14)
25831 + AVR32_OPCODE_LD_COND (LD_UB, 4, AL, 15)
25833 + AVR32_OPCODE_ST_COND (ST_W, 5, EQ, 0)
25834 + AVR32_OPCODE_ST_COND (ST_W, 5, NE, 1)
25835 + AVR32_OPCODE_ST_COND (ST_W, 5, CC, 2)
25836 + AVR32_OPCODE_ST_COND (ST_W, 5, CS, 3)
25837 + AVR32_OPCODE_ST_COND (ST_W, 5, GE, 4)
25838 + AVR32_OPCODE_ST_COND (ST_W, 5, LT, 5)
25839 + AVR32_OPCODE_ST_COND (ST_W, 5, MI, 6)
25840 + AVR32_OPCODE_ST_COND (ST_W, 5, PL, 7)
25841 + AVR32_OPCODE_ST_COND (ST_W, 5, LS, 8)
25842 + AVR32_OPCODE_ST_COND (ST_W, 5, GT, 9)
25843 + AVR32_OPCODE_ST_COND (ST_W, 5, LE, 10)
25844 + AVR32_OPCODE_ST_COND (ST_W, 5, HI, 11)
25845 + AVR32_OPCODE_ST_COND (ST_W, 5, VS, 12)
25846 + AVR32_OPCODE_ST_COND (ST_W, 5, VC, 13)
25847 + AVR32_OPCODE_ST_COND (ST_W, 5, QS, 14)
25848 + AVR32_OPCODE_ST_COND (ST_W, 5, AL, 15)
25850 + AVR32_OPCODE_ST_COND (ST_H, 6, EQ, 0)
25851 + AVR32_OPCODE_ST_COND (ST_H, 6, NE, 1)
25852 + AVR32_OPCODE_ST_COND (ST_H, 6, CC, 2)
25853 + AVR32_OPCODE_ST_COND (ST_H, 6, CS, 3)
25854 + AVR32_OPCODE_ST_COND (ST_H, 6, GE, 4)
25855 + AVR32_OPCODE_ST_COND (ST_H, 6, LT, 5)
25856 + AVR32_OPCODE_ST_COND (ST_H, 6, MI, 6)
25857 + AVR32_OPCODE_ST_COND (ST_H, 6, PL, 7)
25858 + AVR32_OPCODE_ST_COND (ST_H, 6, LS, 8)
25859 + AVR32_OPCODE_ST_COND (ST_H, 6, GT, 9)
25860 + AVR32_OPCODE_ST_COND (ST_H, 6, LE, 10)
25861 + AVR32_OPCODE_ST_COND (ST_H, 6, HI, 11)
25862 + AVR32_OPCODE_ST_COND (ST_H, 6, VS, 12)
25863 + AVR32_OPCODE_ST_COND (ST_H, 6, VC, 13)
25864 + AVR32_OPCODE_ST_COND (ST_H, 6, QS, 14)
25865 + AVR32_OPCODE_ST_COND (ST_H, 6, AL, 15)
25867 + AVR32_OPCODE_ST_COND (ST_B, 7, EQ, 0)
25868 + AVR32_OPCODE_ST_COND (ST_B, 7, NE, 1)
25869 + AVR32_OPCODE_ST_COND (ST_B, 7, CC, 2)
25870 + AVR32_OPCODE_ST_COND (ST_B, 7, CS, 3)
25871 + AVR32_OPCODE_ST_COND (ST_B, 7, GE, 4)
25872 + AVR32_OPCODE_ST_COND (ST_B, 7, LT, 5)
25873 + AVR32_OPCODE_ST_COND (ST_B, 7, MI, 6)
25874 + AVR32_OPCODE_ST_COND (ST_B, 7, PL, 7)
25875 + AVR32_OPCODE_ST_COND (ST_B, 7, LS, 8)
25876 + AVR32_OPCODE_ST_COND (ST_B, 7, GT, 9)
25877 + AVR32_OPCODE_ST_COND (ST_B, 7, LE, 10)
25878 + AVR32_OPCODE_ST_COND (ST_B, 7, HI, 11)
25879 + AVR32_OPCODE_ST_COND (ST_B, 7, VS, 12)
25880 + AVR32_OPCODE_ST_COND (ST_B, 7, VC, 13)
25881 + AVR32_OPCODE_ST_COND (ST_B, 7, QS, 14)
25882 + AVR32_OPCODE_ST_COND (ST_B, 7, AL, 15)
25885 + AVR32_OPC_MOVH, 4, 0xfc100000, 0xfff00000,
25886 + &avr32_syntax_table[AVR32_SYNTAX_MOVH],
25887 + BFD_RELOC_AVR32_16U, 2, 1,
25889 + &avr32_ifield_table[AVR32_IFIELD_RY],
25890 + &avr32_ifield_table[AVR32_IFIELD_K16],
25894 + AVR32_OPC_SSCALL, 2, 0xd7530000, 0xffff0000,
25895 + &avr32_syntax_table[AVR32_SYNTAX_SSCALL],
25896 + BFD_RELOC_UNUSED, 0, -1, { NULL },
25899 + AVR32_OPC_RETSS, 2, 0xd7630000, 0xffff0000,
25900 + &avr32_syntax_table[AVR32_SYNTAX_RETSS],
25901 + BFD_RELOC_UNUSED, 0, -1, { NULL },
25905 + AVR32_OPC_FMAC_S, 4, 0xE1A00000, 0xFFF0F000,
25906 + &avr32_syntax_table[AVR32_SYNTAX_FMAC_S],
25907 + BFD_RELOC_UNUSED, 4, -1,
25909 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25910 + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25911 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25912 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25916 + AVR32_OPC_FNMAC_S, 4, 0xE1A01000, 0xFFF0F000,
25917 + &avr32_syntax_table[AVR32_SYNTAX_FNMAC_S],
25918 + BFD_RELOC_UNUSED, 4, -1,
25920 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25921 + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25922 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25923 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25927 + AVR32_OPC_FMSC_S, 4, 0xE3A00000, 0xFFF0F000,
25928 + &avr32_syntax_table[AVR32_SYNTAX_FMSC_S],
25929 + BFD_RELOC_UNUSED, 4, -1,
25931 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25932 + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25933 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25934 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25938 + AVR32_OPC_FNMSC_S, 4, 0xE3A01000, 0xFFF0F000,
25939 + &avr32_syntax_table[AVR32_SYNTAX_FNMSC_S],
25940 + BFD_RELOC_UNUSED, 4, -1,
25942 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25943 + &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25944 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25945 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25949 + AVR32_OPC_FMUL_S, 4, 0xE5A20000, 0xFFFFF000,
25950 + &avr32_syntax_table[AVR32_SYNTAX_FMUL_S],
25951 + BFD_RELOC_UNUSED, 3, -1,
25953 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25954 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25955 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25959 + AVR32_OPC_FNMUL_S, 4, 0xE5A30000, 0xFFFFF000,
25960 + &avr32_syntax_table[AVR32_SYNTAX_FNMUL_S],
25961 + BFD_RELOC_UNUSED, 3, -1,
25963 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25964 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25965 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25969 + AVR32_OPC_FADD_S, 4, 0xE5A00000, 0xFFFFF000,
25970 + &avr32_syntax_table[AVR32_SYNTAX_FADD_S],
25971 + BFD_RELOC_UNUSED, 3, -1,
25973 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25974 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25975 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25979 + AVR32_OPC_FSUB_S, 4, 0xE5A10000, 0xFFFFF000,
25980 + &avr32_syntax_table[AVR32_SYNTAX_FSUB_S],
25981 + BFD_RELOC_UNUSED, 3, -1,
25983 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25984 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25985 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25989 + AVR32_OPC_FCASTRS_SW, 4, 0xE5AB0000, 0xFFFFF0F0,
25990 + &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_SW],
25991 + BFD_RELOC_UNUSED, 2, -1,
25993 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25994 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25998 + AVR32_OPC_FCASTRS_UW, 4, 0xE5A90000, 0xFFFFF0F0,
25999 + &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_UW],
26000 + BFD_RELOC_UNUSED, 2, -1,
26002 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26003 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26007 + AVR32_OPC_FCASTSW_S, 4, 0xE5A60000, 0xFFFFF0F0,
26008 + &avr32_syntax_table[AVR32_SYNTAX_FCASTSW_S],
26009 + BFD_RELOC_UNUSED, 2, -1,
26011 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26012 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26016 + AVR32_OPC_FCASTUW_S, 4, 0xE5A40000, 0xFFFFF0F0,
26017 + &avr32_syntax_table[AVR32_SYNTAX_FCASTUW_S],
26018 + BFD_RELOC_UNUSED, 2, -1,
26020 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26021 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26025 + AVR32_OPC_FCMP_S, 4, 0xE5AC0000, 0xFFFFFF00,
26026 + &avr32_syntax_table[AVR32_SYNTAX_FCMP_S],
26027 + BFD_RELOC_UNUSED, 2, -1,
26029 + &avr32_ifield_table[AVR32_IFIELD_FP_RX],
26030 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26034 + AVR32_OPC_FCHK_S, 4, 0xE5AD0000, 0xFFFFFFF0,
26035 + &avr32_syntax_table[AVR32_SYNTAX_FCHK_S],
26036 + BFD_RELOC_UNUSED, 1, -1,
26038 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26042 + AVR32_OPC_FRCPA_S, 4, 0xE5AE0000, 0xFFFFF0F0,
26043 + &avr32_syntax_table[AVR32_SYNTAX_FRCPA_S],
26044 + BFD_RELOC_UNUSED, 2, -1,
26046 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26047 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26051 + AVR32_OPC_FRSQRTA_S, 4, 0xE5AF0000, 0xFFFFF0F0,
26052 + &avr32_syntax_table[AVR32_SYNTAX_FRSQRTA_S],
26053 + BFD_RELOC_UNUSED, 2, -1,
26055 + &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26056 + &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26063 +const struct avr32_alias avr32_alias_table[] =
26066 + AVR32_ALIAS_PICOSVMAC0,
26067 + &avr32_opc_table[AVR32_OPC_COP],
26069 + { 0, PICO_CPNO },
26070 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26075 + AVR32_ALIAS_PICOSVMAC1,
26076 + &avr32_opc_table[AVR32_OPC_COP],
26078 + { 0, PICO_CPNO },
26079 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26084 + AVR32_ALIAS_PICOSVMAC2,
26085 + &avr32_opc_table[AVR32_OPC_COP],
26087 + { 0, PICO_CPNO },
26088 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26093 + AVR32_ALIAS_PICOSVMAC3,
26094 + &avr32_opc_table[AVR32_OPC_COP],
26096 + { 0, PICO_CPNO },
26097 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26102 + AVR32_ALIAS_PICOSVMUL0,
26103 + &avr32_opc_table[AVR32_OPC_COP],
26105 + { 0, PICO_CPNO },
26106 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26111 + AVR32_ALIAS_PICOSVMUL1,
26112 + &avr32_opc_table[AVR32_OPC_COP],
26114 + { 0, PICO_CPNO },
26115 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26120 + AVR32_ALIAS_PICOSVMUL2,
26121 + &avr32_opc_table[AVR32_OPC_COP],
26123 + { 0, PICO_CPNO },
26124 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26129 + AVR32_ALIAS_PICOSVMUL3,
26130 + &avr32_opc_table[AVR32_OPC_COP],
26132 + { 0, PICO_CPNO },
26133 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26138 + AVR32_ALIAS_PICOVMAC0,
26139 + &avr32_opc_table[AVR32_OPC_COP],
26141 + { 0, PICO_CPNO },
26142 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26147 + AVR32_ALIAS_PICOVMAC1,
26148 + &avr32_opc_table[AVR32_OPC_COP],
26150 + { 0, PICO_CPNO },
26151 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26156 + AVR32_ALIAS_PICOVMAC2,
26157 + &avr32_opc_table[AVR32_OPC_COP],
26159 + { 0, PICO_CPNO },
26160 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26165 + AVR32_ALIAS_PICOVMAC3,
26166 + &avr32_opc_table[AVR32_OPC_COP],
26168 + { 0, PICO_CPNO },
26169 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26174 + AVR32_ALIAS_PICOVMUL0,
26175 + &avr32_opc_table[AVR32_OPC_COP],
26177 + { 0, PICO_CPNO },
26178 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26183 + AVR32_ALIAS_PICOVMUL1,
26184 + &avr32_opc_table[AVR32_OPC_COP],
26186 + { 0, PICO_CPNO },
26187 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26192 + AVR32_ALIAS_PICOVMUL2,
26193 + &avr32_opc_table[AVR32_OPC_COP],
26195 + { 0, PICO_CPNO },
26196 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26201 + AVR32_ALIAS_PICOVMUL3,
26202 + &avr32_opc_table[AVR32_OPC_COP],
26204 + { 0, PICO_CPNO },
26205 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26210 + AVR32_ALIAS_PICOLD_D1,
26211 + &avr32_opc_table[AVR32_OPC_LDC_D1],
26213 + { 0, PICO_CPNO },
26214 + { 1, 0 }, { 1, 1 },
26218 + AVR32_ALIAS_PICOLD_D2,
26219 + &avr32_opc_table[AVR32_OPC_LDC_D2],
26221 + { 0, PICO_CPNO },
26222 + { 1, 0 }, { 1, 1 },
26226 + AVR32_ALIAS_PICOLD_D3,
26227 + &avr32_opc_table[AVR32_OPC_LDC_D3],
26229 + { 0, PICO_CPNO },
26230 + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26234 + AVR32_ALIAS_PICOLD_W1,
26235 + &avr32_opc_table[AVR32_OPC_LDC_W1],
26237 + { 0, PICO_CPNO },
26238 + { 1, 0 }, { 1, 1 },
26242 + AVR32_ALIAS_PICOLD_W2,
26243 + &avr32_opc_table[AVR32_OPC_LDC_W2],
26245 + { 0, PICO_CPNO },
26246 + { 1, 0 }, { 1, 1 },
26250 + AVR32_ALIAS_PICOLD_W3,
26251 + &avr32_opc_table[AVR32_OPC_LDC_W3],
26253 + { 0, PICO_CPNO },
26254 + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26258 + AVR32_ALIAS_PICOLDM_D,
26259 + &avr32_opc_table[AVR32_OPC_LDCM_D],
26261 + { 0, PICO_CPNO },
26262 + { 1, 0 }, { 1, 1 },
26266 + AVR32_ALIAS_PICOLDM_D_PU,
26267 + &avr32_opc_table[AVR32_OPC_LDCM_D_PU],
26269 + { 0, PICO_CPNO },
26270 + { 1, 0 }, { 1, 1 },
26274 + AVR32_ALIAS_PICOLDM_W,
26275 + &avr32_opc_table[AVR32_OPC_LDCM_W],
26277 + { 0, PICO_CPNO },
26278 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26282 + AVR32_ALIAS_PICOLDM_W_PU,
26283 + &avr32_opc_table[AVR32_OPC_LDCM_W_PU],
26285 + { 0, PICO_CPNO },
26286 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26290 + AVR32_ALIAS_PICOMV_D1,
26291 + &avr32_opc_table[AVR32_OPC_MVCR_D],
26293 + { 0, PICO_CPNO },
26294 + { 1, 0 }, { 1, 1 },
26298 + AVR32_ALIAS_PICOMV_D2,
26299 + &avr32_opc_table[AVR32_OPC_MVRC_D],
26301 + { 0, PICO_CPNO },
26302 + { 1, 0 }, { 1, 1 },
26306 + AVR32_ALIAS_PICOMV_W1,
26307 + &avr32_opc_table[AVR32_OPC_MVCR_W],
26309 + { 0, PICO_CPNO },
26310 + { 1, 0 }, { 1, 1 },
26314 + AVR32_ALIAS_PICOMV_W2,
26315 + &avr32_opc_table[AVR32_OPC_MVRC_W],
26317 + { 0, PICO_CPNO },
26318 + { 1, 0 }, { 1, 1 },
26322 + AVR32_ALIAS_PICOST_D1,
26323 + &avr32_opc_table[AVR32_OPC_STC_D1],
26325 + { 0, PICO_CPNO },
26326 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26330 + AVR32_ALIAS_PICOST_D2,
26331 + &avr32_opc_table[AVR32_OPC_STC_D2],
26333 + { 0, PICO_CPNO },
26334 + { 1, 0 }, { 1, 1 },
26338 + AVR32_ALIAS_PICOST_D3,
26339 + &avr32_opc_table[AVR32_OPC_STC_D3],
26341 + { 0, PICO_CPNO },
26342 + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26346 + AVR32_ALIAS_PICOST_W1,
26347 + &avr32_opc_table[AVR32_OPC_STC_W1],
26349 + { 0, PICO_CPNO },
26350 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26354 + AVR32_ALIAS_PICOST_W2,
26355 + &avr32_opc_table[AVR32_OPC_STC_W2],
26357 + { 0, PICO_CPNO },
26358 + { 1, 0 }, { 1, 1 },
26362 + AVR32_ALIAS_PICOST_W3,
26363 + &avr32_opc_table[AVR32_OPC_STC_W3],
26365 + { 0, PICO_CPNO },
26366 + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26370 + AVR32_ALIAS_PICOSTM_D,
26371 + &avr32_opc_table[AVR32_OPC_STCM_D],
26373 + { 0, PICO_CPNO },
26374 + { 1, 0 }, { 1, 1 },
26378 + AVR32_ALIAS_PICOSTM_D_PU,
26379 + &avr32_opc_table[AVR32_OPC_STCM_D_PU],
26381 + { 0, PICO_CPNO },
26382 + { 1, 0 }, { 1, 1 },
26386 + AVR32_ALIAS_PICOSTM_W,
26387 + &avr32_opc_table[AVR32_OPC_STCM_W],
26389 + { 0, PICO_CPNO },
26390 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26394 + AVR32_ALIAS_PICOSTM_W_PU,
26395 + &avr32_opc_table[AVR32_OPC_STCM_W_PU],
26397 + { 0, PICO_CPNO },
26398 + { 1, 0 }, { 1, 1 }, { 1, 2 },
26404 +#define SYNTAX_NORMAL0(id, mne, opc, arch) \
26406 + AVR32_SYNTAX_##id, arch, \
26407 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26408 + AVR32_PARSER_NORMAL, \
26409 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26412 +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch) \
26414 + AVR32_SYNTAX_##id, arch, \
26415 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26416 + AVR32_PARSER_NORMAL, \
26417 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26420 + AVR32_OPERAND_##op0, \
26423 +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch) \
26425 + AVR32_SYNTAX_##id, arch, \
26426 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26427 + AVR32_PARSER_NORMAL, \
26428 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26431 + AVR32_OPERAND_##op0, \
26434 +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch) \
26436 + AVR32_SYNTAX_##id, arch, \
26437 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26438 + AVR32_PARSER_NORMAL, \
26439 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26442 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26445 +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch) \
26447 + AVR32_SYNTAX_##id, arch, \
26448 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26449 + AVR32_PARSER_NORMAL, \
26450 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26453 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26456 +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch) \
26458 + AVR32_SYNTAX_##id, arch, \
26459 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26460 + AVR32_PARSER_NORMAL, \
26461 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26464 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26465 + AVR32_OPERAND_##op2, \
26468 +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch) \
26470 + AVR32_SYNTAX_##id, arch, \
26471 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26472 + AVR32_PARSER_NORMAL, \
26473 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26476 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26477 + AVR32_OPERAND_##op2, \
26480 +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\
26482 + AVR32_SYNTAX_##id, arch, \
26483 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26484 + AVR32_PARSER_NORMAL, \
26485 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26488 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26489 + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \
26492 +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch) \
26494 + AVR32_SYNTAX_##id, arch, \
26495 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26496 + AVR32_PARSER_NORMAL, \
26497 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26500 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26501 + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \
26502 + AVR32_OPERAND_##op4, \
26506 +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \
26508 + AVR32_SYNTAX_##id, arch, \
26509 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26510 + AVR32_PARSER_NORMAL, \
26511 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26512 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1, \
26514 + AVR32_OPERAND_##op0, \
26517 +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch) \
26519 + AVR32_SYNTAX_##id, arch, \
26520 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26521 + AVR32_PARSER_NORMAL, \
26522 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26523 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1, \
26525 + AVR32_OPERAND_##op0, \
26528 +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch) \
26530 + AVR32_SYNTAX_##id, arch, \
26531 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26532 + AVR32_PARSER_NORMAL, \
26533 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26534 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2, \
26536 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26539 +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch) \
26541 + AVR32_SYNTAX_##id, arch, \
26542 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26543 + AVR32_PARSER_NORMAL, \
26544 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26545 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2, \
26547 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26550 +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch) \
26552 + AVR32_SYNTAX_##id, arch, \
26553 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26554 + AVR32_PARSER_NORMAL, \
26555 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26556 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3, \
26558 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26559 + AVR32_OPERAND_##op2, \
26562 +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch) \
26564 + AVR32_SYNTAX_##id, arch, \
26565 + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \
26566 + AVR32_PARSER_NORMAL, \
26567 + { &avr32_opc_table[AVR32_OPC_##opc], }, \
26568 + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3, \
26570 + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \
26571 + AVR32_OPERAND_##op2, \
26576 +const struct avr32_syntax avr32_syntax_table[] =
26578 + SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1),
26579 + SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1),
26580 + SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1),
26581 + SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1),
26582 + SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1),
26583 + SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26584 + SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1),
26585 + SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26586 + SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1),
26587 + SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26588 + SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26589 + SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26590 + SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26591 + SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26592 + SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26593 + SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1),
26594 + SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1),
26595 + SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26596 + SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26597 + SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26598 + SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26599 + SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26600 + SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26601 + SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1),
26602 + SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1),
26603 + SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1),
26604 + SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1),
26605 + SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1),
26606 + SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1),
26607 + SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1),
26608 + SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1),
26609 + SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1),
26610 + SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1),
26611 + SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1),
26612 + SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1),
26613 + SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1),
26614 + SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1),
26615 + SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1),
26616 + SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1),
26617 + SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1),
26618 + SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1),
26619 + SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1),
26620 + SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1),
26621 + SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1),
26622 + SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1),
26623 + SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1),
26624 + SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1),
26625 + SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1),
26626 + SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1),
26627 + SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1),
26628 + SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1),
26629 + SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1),
26630 + SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1),
26631 + SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26632 + SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1),
26633 + SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1),
26634 + SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1),
26635 + SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1),
26636 + SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1),
26637 + SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26638 + SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1),
26639 + SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1),
26640 + SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1),
26641 + SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1),
26642 + SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1),
26643 + SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1),
26644 + SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26645 + SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26646 + SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1),
26647 + SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1),
26648 + SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1),
26649 + SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1),
26650 + SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1),
26651 + SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1),
26652 + SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1),
26653 + SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26654 + SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26655 + SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26656 + SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26657 + SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1),
26658 + SYNTAX_NORMAL0(SSCALL, SSCALL, SSCALL, AVR32_V3),
26659 + SYNTAX_NORMAL0(RETSS, RETSS, RETSS, AVR32_V3),
26660 + SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1),
26661 + SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1),
26662 + SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1),
26663 + SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1),
26664 + SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1),
26665 + SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1),
26666 + SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1),
26667 + SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1),
26668 + SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1),
26669 + SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1),
26670 + SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1),
26671 + SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1),
26672 + SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1),
26673 + SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1),
26674 + SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1),
26675 + SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1),
26676 + SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1),
26677 + SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26678 + SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1),
26679 + SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1),
26680 + SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1),
26681 + SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1),
26682 + SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26683 + SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1),
26684 + SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1),
26685 + SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1),
26686 + SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1),
26687 + SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1),
26688 + SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1),
26689 + SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1),
26690 + SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26691 + SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1),
26692 + SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1),
26693 + SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1),
26694 + SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1),
26695 + SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1),
26696 + SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26697 + SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1),
26698 + SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26699 + SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1),
26700 + SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26701 + SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1),
26702 + SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1),
26703 + SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1),
26704 + SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1),
26705 + SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1),
26706 + SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1),
26707 + SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1),
26708 + SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1),
26709 + SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1),
26710 + SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1),
26711 + SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1),
26712 + SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1),
26713 + SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1),
26714 + SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26715 + SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26716 + SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1),
26717 + SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26718 + SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26719 + SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1),
26720 + SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26721 + SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26722 + SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1),
26723 + SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26724 + SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1),
26725 + SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26726 + SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1),
26727 + SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1),
26728 + SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26729 + SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26730 + SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1),
26731 + SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1),
26732 + SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1),
26733 + SYNTAX_NORMAL2(MOV2, MOV, MOV2,INTREG, SIGNED_CONST, AVR32_V1),
26734 + SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1),
26735 + SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1),
26736 + SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1),
26737 + SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1),
26738 + SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1),
26739 + SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1),
26740 + SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1),
26741 + SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1),
26742 + SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1),
26743 + SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1),
26744 + SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1),
26745 + SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1),
26746 + SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1),
26747 + SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1),
26748 + SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1),
26749 + SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1),
26750 + SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1),
26751 + SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1),
26752 + SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1),
26753 + SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1),
26754 + SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26755 + SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26756 + SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1),
26757 + SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1),
26758 + SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1),
26759 + SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1),
26760 + SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1),
26761 + SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1),
26762 + SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1),
26763 + SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1),
26764 + SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1),
26765 + SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1),
26766 + SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1),
26767 + SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1),
26768 + SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26769 + SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26770 + SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26771 + SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26772 + SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1),
26773 + SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1),
26774 + SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26775 + SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26776 + SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26777 + SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26778 + SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1),
26779 + SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26780 + SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26781 + SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26782 + SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26783 + SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26784 + SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1),
26785 + SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26786 + SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1),
26787 + SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1),
26788 + SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1),
26789 + SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1),
26790 + SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1),
26791 + SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1),
26792 + SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1),
26793 + SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1),
26794 + SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1),
26795 + SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26796 + SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26797 + SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26798 + SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26799 + SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD),
26800 + SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD),
26801 + SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26802 + SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26803 + SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26804 + SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26805 + SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26806 + SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26807 + SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26808 + SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26809 + SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26810 + SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26811 + SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26812 + SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26813 + SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26814 + SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26815 + SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26816 + SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26817 + SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26818 + SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26819 + SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26820 + SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26821 + SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26822 + SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26823 + SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26824 + SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26825 + SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26826 + SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26827 + SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26828 + SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26829 + SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26830 + SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26831 + SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26832 + SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1),
26833 + SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1),
26834 + SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1),
26835 + SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1),
26836 + SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD),
26837 + SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26838 + SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26839 + SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26840 + SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26841 + SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26842 + SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26843 + SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26844 + SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26845 + SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26846 + SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26847 + SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26848 + SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26849 + SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26850 + SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26851 + SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26852 + SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26853 + SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26854 + SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26855 + SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1),
26856 + SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1),
26857 + SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1),
26858 + SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1),
26859 + SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1),
26860 + SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1),
26861 + SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1),
26862 + SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1),
26863 + SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1),
26864 + SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1),
26865 + SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1),
26866 + SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1),
26867 + SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1),
26868 + SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1),
26869 + SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1),
26870 + SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1),
26871 + SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1),
26872 + SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1),
26873 + SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1),
26874 + SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1),
26875 + SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1),
26876 + SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1),
26877 + SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1),
26878 + SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1),
26879 + SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1),
26880 + SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1),
26881 + SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1),
26882 + SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1),
26883 + SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1),
26884 + SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1),
26885 + SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1),
26886 + SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26887 + SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG, AVR32_DSP),
26888 + SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP),
26889 + SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26890 + SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26891 + SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26892 + SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP),
26893 + SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP),
26894 + SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP),
26895 + SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1),
26896 + SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1),
26897 + SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26898 + SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1),
26899 + SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1),
26900 + SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1),
26901 + SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1),
26902 + SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1),
26903 + SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1),
26904 + SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1),
26905 + SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1),
26906 + SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1),
26907 + SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1),
26908 + SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1),
26909 + SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1),
26910 + SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1),
26911 + SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1),
26912 + SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1),
26913 + SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1),
26914 + SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1),
26915 + SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1),
26916 + SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1),
26917 + SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1),
26918 + SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1),
26919 + SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1),
26920 + SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1),
26921 + SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1),
26922 + SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1),
26923 + SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1),
26924 + SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1),
26925 + SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1),
26926 + SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1),
26927 + SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1),
26928 + SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1),
26929 + SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1),
26930 + SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1),
26931 + SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1),
26932 + SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1),
26933 + SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1),
26934 + SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1),
26935 + SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1),
26936 + SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1),
26937 + SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1),
26938 + SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1),
26939 + SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1),
26940 + SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26941 + SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1),
26942 + SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1),
26943 + SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1),
26944 + SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1),
26945 + SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1),
26946 + SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26947 + SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1),
26948 + SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26949 + SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1),
26950 + SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26951 + SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1),
26952 + SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1),
26953 + SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1),
26954 + SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26955 + SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26956 + SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1),
26957 + SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26958 + SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1),
26959 + SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26960 + SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1),
26961 + SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1),
26962 + SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1),
26963 + SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26964 + SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26965 + SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1),
26966 + SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26967 + SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
26968 + SYNTAX_NORMAL_C2(SUBEQ, SUBEQ, SUBEQ, SUB2EQ, INTREG, SIGNED_CONST, AVR32_V1),
26969 + SYNTAX_NORMAL_C2(SUBNE, SUBNE, SUBNE, SUB2NE, INTREG, SIGNED_CONST, AVR32_V1),
26970 + SYNTAX_NORMAL_C2(SUBCC, SUBCC, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26971 + SYNTAX_NORMAL_C2(SUBCS, SUBCS, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26972 + SYNTAX_NORMAL_C2(SUBGE, SUBGE, SUBGE, SUB2GE, INTREG, SIGNED_CONST, AVR32_V1),
26973 + SYNTAX_NORMAL_C2(SUBLT, SUBLT, SUBLT, SUB2LT, INTREG, SIGNED_CONST, AVR32_V1),
26974 + SYNTAX_NORMAL_C2(SUBMI, SUBMI, SUBMI, SUB2MI, INTREG, SIGNED_CONST, AVR32_V1),
26975 + SYNTAX_NORMAL_C2(SUBPL, SUBPL, SUBPL, SUB2PL, INTREG, SIGNED_CONST, AVR32_V1),
26976 + SYNTAX_NORMAL_C2(SUBLS, SUBLS, SUBLS, SUB2LS, INTREG, SIGNED_CONST, AVR32_V1),
26977 + SYNTAX_NORMAL_C2(SUBGT, SUBGT, SUBGT, SUB2GT, INTREG, SIGNED_CONST, AVR32_V1),
26978 + SYNTAX_NORMAL_C2(SUBLE, SUBLE, SUBLE, SUB2LE, INTREG, SIGNED_CONST, AVR32_V1),
26979 + SYNTAX_NORMAL_C2(SUBHI, SUBHI, SUBHI, SUB2HI, INTREG, SIGNED_CONST, AVR32_V1),
26980 + SYNTAX_NORMAL_C2(SUBVS, SUBVS, SUBVS, SUB2VS, INTREG, SIGNED_CONST, AVR32_V1),
26981 + SYNTAX_NORMAL_C2(SUBVC, SUBVC, SUBVC, SUB2VC, INTREG, SIGNED_CONST, AVR32_V1),
26982 + SYNTAX_NORMAL_C2(SUBQS, SUBQS, SUBQS, SUB2QS, INTREG, SIGNED_CONST, AVR32_V1),
26983 + SYNTAX_NORMAL_C2(SUBAL, SUBAL, SUBAL, SUB2AL, INTREG, SIGNED_CONST, AVR32_V1),
26984 + SYNTAX_NORMAL_C2(SUBHS, SUBHS, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
26985 + SYNTAX_NORMAL_C2(SUBLO, SUBLO, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
26986 + SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1),
26987 + SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1),
26988 + SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
26989 + SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
26990 + SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1),
26991 + SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1),
26992 + SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1),
26993 + SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1),
26994 + SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1),
26995 + SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1),
26996 + SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1),
26997 + SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1),
26998 + SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1),
26999 + SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1),
27000 + SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1),
27001 + SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1),
27002 + SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
27003 + SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
27004 + SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
27005 + SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1),
27006 + SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1),
27007 + SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1),
27008 + SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1),
27009 + SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1),
27010 + SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1),
27011 + SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1),
27012 + SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1),
27013 + SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1),
27014 + SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1),
27015 + SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27016 + SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27017 + SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27018 + SYNTAX_NORMAL4 (FMAC_S, FMAC_S, FMAC_S, INTREG, INTREG, INTREG, INTREG,
27020 + SYNTAX_NORMAL4 (FNMAC_S, FNMAC_S, FNMAC_S, INTREG, INTREG, INTREG, INTREG,
27022 + SYNTAX_NORMAL4 (FMSC_S, FMSC_S, FMSC_S, INTREG, INTREG, INTREG, INTREG,
27024 + SYNTAX_NORMAL4 (FNMSC_S, FNMSC_S, FNMSC_S, INTREG, INTREG, INTREG, INTREG,
27026 + SYNTAX_NORMAL3 (FMUL_S, FMUL_S, FMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
27027 + SYNTAX_NORMAL3 (FNMUL_S, FNMUL_S, FNMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
27028 + SYNTAX_NORMAL3 (FADD_S, FADD_S, FADD_S, INTREG, INTREG, INTREG, AVR32_V3FP),
27029 + SYNTAX_NORMAL3 (FSUB_S, FSUB_S, FSUB_S, INTREG, INTREG, INTREG, AVR32_V3FP),
27030 + SYNTAX_NORMAL2 (FCASTRS_SW, FCASTRS_SW, FCASTRS_SW, INTREG, INTREG, AVR32_V3FP),
27031 + SYNTAX_NORMAL2 (FCASTRS_UW, FCASTRS_UW, FCASTRS_UW, INTREG, INTREG, AVR32_V3FP),
27032 + SYNTAX_NORMAL2 (FCASTSW_S, FCASTSW_S, FCASTSW_S, INTREG, INTREG, AVR32_V3FP),
27033 + SYNTAX_NORMAL2 (FCASTUW_S, FCASTUW_S, FCASTUW_S, INTREG, INTREG, AVR32_V3FP),
27034 + SYNTAX_NORMAL2 (FCMP_S, FCMP_S, FCMP_S, INTREG, INTREG, AVR32_V3FP),
27035 + SYNTAX_NORMAL1 (FCHK_S, FCHK_S, FCHK_S, INTREG, AVR32_V3FP),
27036 + SYNTAX_NORMAL2 (FRCPA_S, FRCPA_S, FRCPA_S, INTREG, INTREG, AVR32_V3FP),
27037 + SYNTAX_NORMAL2 (FRSQRTA_S, FRSQRTA_S, FRSQRTA_S, INTREG, INTREG, AVR32_V3FP),
27039 + AVR32_SYNTAX_LDA_W,
27040 + AVR32_V1, NULL, AVR32_PARSER_LDA,
27044 + AVR32_OPERAND_INTREG,
27045 + AVR32_OPERAND_SIGNED_CONST,
27049 + AVR32_SYNTAX_CALL,
27050 + AVR32_V1, NULL, AVR32_PARSER_CALL,
27054 + AVR32_OPERAND_JMPLABEL,
27058 + AVR32_SYNTAX_PICOSVMAC0,
27059 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27060 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC0] },
27061 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC1], 4,
27063 + AVR32_OPERAND_PICO_OUT0,
27064 + AVR32_OPERAND_PICO_IN,
27065 + AVR32_OPERAND_PICO_IN,
27066 + AVR32_OPERAND_PICO_IN,
27070 + AVR32_SYNTAX_PICOSVMAC1,
27071 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27072 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC1] },
27073 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC2], 4,
27075 + AVR32_OPERAND_PICO_OUT1,
27076 + AVR32_OPERAND_PICO_IN,
27077 + AVR32_OPERAND_PICO_IN,
27078 + AVR32_OPERAND_PICO_IN,
27082 + AVR32_SYNTAX_PICOSVMAC2,
27083 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27084 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC2] },
27085 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC3], 4,
27087 + AVR32_OPERAND_PICO_OUT2,
27088 + AVR32_OPERAND_PICO_IN,
27089 + AVR32_OPERAND_PICO_IN,
27090 + AVR32_OPERAND_PICO_IN,
27094 + AVR32_SYNTAX_PICOSVMAC3,
27095 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27096 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC3] },
27099 + AVR32_OPERAND_PICO_OUT3,
27100 + AVR32_OPERAND_PICO_IN,
27101 + AVR32_OPERAND_PICO_IN,
27102 + AVR32_OPERAND_PICO_IN,
27106 + AVR32_SYNTAX_PICOSVMUL0,
27107 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27108 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL0] },
27109 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL1], 4,
27111 + AVR32_OPERAND_PICO_OUT0,
27112 + AVR32_OPERAND_PICO_IN,
27113 + AVR32_OPERAND_PICO_IN,
27114 + AVR32_OPERAND_PICO_IN,
27118 + AVR32_SYNTAX_PICOSVMUL1,
27119 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27120 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL1] },
27121 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL2], 4,
27123 + AVR32_OPERAND_PICO_OUT1,
27124 + AVR32_OPERAND_PICO_IN,
27125 + AVR32_OPERAND_PICO_IN,
27126 + AVR32_OPERAND_PICO_IN,
27130 + AVR32_SYNTAX_PICOSVMUL2,
27131 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27132 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL2] },
27133 + &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL3], 4,
27135 + AVR32_OPERAND_PICO_OUT2,
27136 + AVR32_OPERAND_PICO_IN,
27137 + AVR32_OPERAND_PICO_IN,
27138 + AVR32_OPERAND_PICO_IN,
27142 + AVR32_SYNTAX_PICOSVMUL3,
27143 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27144 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL3] },
27147 + AVR32_OPERAND_PICO_OUT3,
27148 + AVR32_OPERAND_PICO_IN,
27149 + AVR32_OPERAND_PICO_IN,
27150 + AVR32_OPERAND_PICO_IN,
27154 + AVR32_SYNTAX_PICOVMAC0,
27155 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27156 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC0] },
27157 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC1], 4,
27159 + AVR32_OPERAND_PICO_OUT0,
27160 + AVR32_OPERAND_PICO_IN,
27161 + AVR32_OPERAND_PICO_IN,
27162 + AVR32_OPERAND_PICO_IN,
27166 + AVR32_SYNTAX_PICOVMAC1,
27167 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27168 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC1] },
27169 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC2], 4,
27171 + AVR32_OPERAND_PICO_OUT1,
27172 + AVR32_OPERAND_PICO_IN,
27173 + AVR32_OPERAND_PICO_IN,
27174 + AVR32_OPERAND_PICO_IN,
27178 + AVR32_SYNTAX_PICOVMAC2,
27179 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27180 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC2] },
27181 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC3], 4,
27183 + AVR32_OPERAND_PICO_OUT2,
27184 + AVR32_OPERAND_PICO_IN,
27185 + AVR32_OPERAND_PICO_IN,
27186 + AVR32_OPERAND_PICO_IN,
27190 + AVR32_SYNTAX_PICOVMAC3,
27191 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27192 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC3] },
27195 + AVR32_OPERAND_PICO_OUT3,
27196 + AVR32_OPERAND_PICO_IN,
27197 + AVR32_OPERAND_PICO_IN,
27198 + AVR32_OPERAND_PICO_IN,
27202 + AVR32_SYNTAX_PICOVMUL0,
27203 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27204 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL0] },
27205 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL1], 4,
27207 + AVR32_OPERAND_PICO_OUT0,
27208 + AVR32_OPERAND_PICO_IN,
27209 + AVR32_OPERAND_PICO_IN,
27210 + AVR32_OPERAND_PICO_IN,
27214 + AVR32_SYNTAX_PICOVMUL1,
27215 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27216 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL1] },
27217 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL2], 4,
27219 + AVR32_OPERAND_PICO_OUT1,
27220 + AVR32_OPERAND_PICO_IN,
27221 + AVR32_OPERAND_PICO_IN,
27222 + AVR32_OPERAND_PICO_IN,
27226 + AVR32_SYNTAX_PICOVMUL2,
27227 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27228 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL2] },
27229 + &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL3], 4,
27231 + AVR32_OPERAND_PICO_OUT2,
27232 + AVR32_OPERAND_PICO_IN,
27233 + AVR32_OPERAND_PICO_IN,
27234 + AVR32_OPERAND_PICO_IN,
27238 + AVR32_SYNTAX_PICOVMUL3,
27239 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27240 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL3] },
27243 + AVR32_OPERAND_PICO_OUT3,
27244 + AVR32_OPERAND_PICO_IN,
27245 + AVR32_OPERAND_PICO_IN,
27246 + AVR32_OPERAND_PICO_IN,
27250 + AVR32_SYNTAX_PICOLD_D2,
27251 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27252 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D2] },
27253 + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D3], 2,
27255 + AVR32_OPERAND_PICO_REG_D,
27256 + AVR32_OPERAND_INTREG_PREDEC,
27260 + AVR32_SYNTAX_PICOLD_D3,
27261 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27262 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D3] },
27263 + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D1], 2,
27265 + AVR32_OPERAND_PICO_REG_D,
27266 + AVR32_OPERAND_INTREG_INDEX,
27270 + AVR32_SYNTAX_PICOLD_D1,
27271 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27272 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D1] },
27275 + AVR32_OPERAND_PICO_REG_D,
27276 + AVR32_OPERAND_INTREG_UDISP_W,
27280 + AVR32_SYNTAX_PICOLD_W2,
27281 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27282 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W2] },
27283 + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W3], 2,
27285 + AVR32_OPERAND_PICO_REG_W,
27286 + AVR32_OPERAND_INTREG_PREDEC,
27290 + AVR32_SYNTAX_PICOLD_W3,
27291 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27292 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W3] },
27293 + &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W1], 2,
27295 + AVR32_OPERAND_PICO_REG_W,
27296 + AVR32_OPERAND_INTREG_INDEX,
27300 + AVR32_SYNTAX_PICOLD_W1,
27301 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27302 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W1] },
27305 + AVR32_OPERAND_PICO_REG_W,
27306 + AVR32_OPERAND_INTREG_UDISP_W,
27310 + AVR32_SYNTAX_PICOLDM_D,
27311 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27312 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D] },
27313 + &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_D_PU], -2,
27315 + AVR32_OPERAND_INTREG,
27316 + AVR32_OPERAND_PICO_REGLIST_D,
27320 + AVR32_SYNTAX_PICOLDM_D_PU,
27321 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27322 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D_PU] },
27325 + AVR32_OPERAND_INTREG_POSTINC,
27326 + AVR32_OPERAND_PICO_REGLIST_D,
27330 + AVR32_SYNTAX_PICOLDM_W,
27331 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27332 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W] },
27333 + &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_W_PU], -2,
27335 + AVR32_OPERAND_INTREG,
27336 + AVR32_OPERAND_PICO_REGLIST_W,
27340 + AVR32_SYNTAX_PICOLDM_W_PU,
27341 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27342 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W_PU] },
27345 + AVR32_OPERAND_INTREG_POSTINC,
27346 + AVR32_OPERAND_PICO_REGLIST_W,
27350 + AVR32_SYNTAX_PICOMV_D1,
27351 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27352 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D1] },
27353 + &avr32_syntax_table[AVR32_SYNTAX_PICOMV_D2], 2,
27355 + AVR32_OPERAND_DWREG,
27356 + AVR32_OPERAND_PICO_REG_D,
27360 + AVR32_SYNTAX_PICOMV_D2,
27361 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27362 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D2] },
27365 + AVR32_OPERAND_PICO_REG_D,
27366 + AVR32_OPERAND_DWREG,
27370 + AVR32_SYNTAX_PICOMV_W1,
27371 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27372 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W1] },
27373 + &avr32_syntax_table[AVR32_SYNTAX_PICOMV_W2], 2,
27375 + AVR32_OPERAND_INTREG,
27376 + AVR32_OPERAND_PICO_REG_W,
27380 + AVR32_SYNTAX_PICOMV_W2,
27381 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27382 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W2] },
27385 + AVR32_OPERAND_PICO_REG_W,
27386 + AVR32_OPERAND_INTREG,
27390 + AVR32_SYNTAX_PICOST_D2,
27391 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27392 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D2] },
27393 + &avr32_syntax_table[AVR32_SYNTAX_PICOST_D3], 2,
27395 + AVR32_OPERAND_INTREG_POSTINC,
27396 + AVR32_OPERAND_PICO_REG_D,
27400 + AVR32_SYNTAX_PICOST_D3,
27401 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27402 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D3] },
27403 + &avr32_syntax_table[AVR32_SYNTAX_PICOST_D1], 2,
27405 + AVR32_OPERAND_INTREG_INDEX,
27406 + AVR32_OPERAND_PICO_REG_D,
27410 + AVR32_SYNTAX_PICOST_D1,
27411 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27412 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D1] },
27415 + AVR32_OPERAND_INTREG_UDISP_W,
27416 + AVR32_OPERAND_PICO_REG_D,
27420 + AVR32_SYNTAX_PICOST_W2,
27421 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27422 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W2] },
27423 + &avr32_syntax_table[AVR32_SYNTAX_PICOST_W3], 2,
27425 + AVR32_OPERAND_INTREG_POSTINC,
27426 + AVR32_OPERAND_PICO_REG_W,
27430 + AVR32_SYNTAX_PICOST_W3,
27431 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27432 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W3] },
27433 + &avr32_syntax_table[AVR32_SYNTAX_PICOST_W1], 2,
27435 + AVR32_OPERAND_INTREG_INDEX,
27436 + AVR32_OPERAND_PICO_REG_W,
27440 + AVR32_SYNTAX_PICOST_W1,
27441 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27442 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W1] },
27445 + AVR32_OPERAND_INTREG_UDISP_W,
27446 + AVR32_OPERAND_PICO_REG_W,
27450 + AVR32_SYNTAX_PICOSTM_D,
27451 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27452 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D] },
27453 + &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_D_PU], -2,
27455 + AVR32_OPERAND_INTREG,
27456 + AVR32_OPERAND_PICO_REGLIST_D,
27460 + AVR32_SYNTAX_PICOSTM_D_PU,
27461 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27462 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D_PU] },
27465 + AVR32_OPERAND_INTREG_PREDEC,
27466 + AVR32_OPERAND_PICO_REGLIST_D,
27470 + AVR32_SYNTAX_PICOSTM_W,
27471 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27472 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W] },
27473 + &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_W_PU], -2,
27475 + AVR32_OPERAND_INTREG,
27476 + AVR32_OPERAND_PICO_REGLIST_W,
27480 + AVR32_SYNTAX_PICOSTM_W_PU,
27481 + AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27482 + { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W_PU] },
27485 + AVR32_OPERAND_INTREG_PREDEC,
27486 + AVR32_OPERAND_PICO_REGLIST_W,
27489 + SYNTAX_NORMAL2(RSUBEQ, RSUBEQ, RSUBEQ, INTREG, SIGNED_CONST, AVR32_V1),
27490 + SYNTAX_NORMAL2(RSUBNE, RSUBNE, RSUBNE, INTREG, SIGNED_CONST, AVR32_V2),
27491 + SYNTAX_NORMAL2(RSUBCC, RSUBCC, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27492 + SYNTAX_NORMAL2(RSUBCS, RSUBCS, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27493 + SYNTAX_NORMAL2(RSUBGE, RSUBGE, RSUBGE, INTREG, SIGNED_CONST, AVR32_V2),
27494 + SYNTAX_NORMAL2(RSUBLT, RSUBLT, RSUBLT, INTREG, SIGNED_CONST, AVR32_V2),
27495 + SYNTAX_NORMAL2(RSUBMI, RSUBMI, RSUBMI, INTREG, SIGNED_CONST, AVR32_V2),
27496 + SYNTAX_NORMAL2(RSUBPL, RSUBPL, RSUBPL, INTREG, SIGNED_CONST, AVR32_V2),
27497 + SYNTAX_NORMAL2(RSUBLS, RSUBLS, RSUBLS, INTREG, SIGNED_CONST, AVR32_V2),
27498 + SYNTAX_NORMAL2(RSUBGT, RSUBGT, RSUBGT, INTREG, SIGNED_CONST, AVR32_V2),
27499 + SYNTAX_NORMAL2(RSUBLE, RSUBLE, RSUBLE, INTREG, SIGNED_CONST, AVR32_V2),
27500 + SYNTAX_NORMAL2(RSUBHI, RSUBHI, RSUBHI, INTREG, SIGNED_CONST, AVR32_V2),
27501 + SYNTAX_NORMAL2(RSUBVS, RSUBVS, RSUBVS, INTREG, SIGNED_CONST, AVR32_V2),
27502 + SYNTAX_NORMAL2(RSUBVC, RSUBVC, RSUBVC, INTREG, SIGNED_CONST, AVR32_V2),
27503 + SYNTAX_NORMAL2(RSUBQS, RSUBQS, RSUBQS, INTREG, SIGNED_CONST, AVR32_V2),
27504 + SYNTAX_NORMAL2(RSUBAL, RSUBAL, RSUBAL, INTREG, SIGNED_CONST, AVR32_V2),
27505 + SYNTAX_NORMAL2(RSUBHS, RSUBHS, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27506 + SYNTAX_NORMAL2(RSUBLO, RSUBLO, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27507 + SYNTAX_NORMAL3(ADDEQ, ADDEQ, ADDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27508 + SYNTAX_NORMAL3(ADDNE, ADDNE, ADDNE, INTREG, INTREG, INTREG, AVR32_V2),
27509 + SYNTAX_NORMAL3(ADDCC, ADDCC, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27510 + SYNTAX_NORMAL3(ADDCS, ADDCS, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27511 + SYNTAX_NORMAL3(ADDGE, ADDGE, ADDGE, INTREG, INTREG, INTREG, AVR32_V2),
27512 + SYNTAX_NORMAL3(ADDLT, ADDLT, ADDLT, INTREG, INTREG, INTREG, AVR32_V2),
27513 + SYNTAX_NORMAL3(ADDMI, ADDMI, ADDMI, INTREG, INTREG, INTREG, AVR32_V2),
27514 + SYNTAX_NORMAL3(ADDPL, ADDPL, ADDPL, INTREG, INTREG, INTREG, AVR32_V2),
27515 + SYNTAX_NORMAL3(ADDLS, ADDLS, ADDLS, INTREG, INTREG, INTREG, AVR32_V2),
27516 + SYNTAX_NORMAL3(ADDGT, ADDGT, ADDGT, INTREG, INTREG, INTREG, AVR32_V2),
27517 + SYNTAX_NORMAL3(ADDLE, ADDLE, ADDLE, INTREG, INTREG, INTREG, AVR32_V2),
27518 + SYNTAX_NORMAL3(ADDHI, ADDHI, ADDHI, INTREG, INTREG, INTREG, AVR32_V2),
27519 + SYNTAX_NORMAL3(ADDVS, ADDVS, ADDVS, INTREG, INTREG, INTREG, AVR32_V2),
27520 + SYNTAX_NORMAL3(ADDVC, ADDVC, ADDVC, INTREG, INTREG, INTREG, AVR32_V2),
27521 + SYNTAX_NORMAL3(ADDQS, ADDQS, ADDQS, INTREG, INTREG, INTREG, AVR32_V2),
27522 + SYNTAX_NORMAL3(ADDAL, ADDAL, ADDAL, INTREG, INTREG, INTREG, AVR32_V2),
27523 + SYNTAX_NORMAL3(ADDHS, ADDHS, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27524 + SYNTAX_NORMAL3(ADDLO, ADDLO, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27525 + SYNTAX_NORMAL3(SUB2EQ, SUBEQ, SUB2EQ, INTREG, INTREG, INTREG, AVR32_V2),
27526 + SYNTAX_NORMAL3(SUB2NE, SUBNE, SUB2NE, INTREG, INTREG, INTREG, AVR32_V2),
27527 + SYNTAX_NORMAL3(SUB2CC, SUBCC, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27528 + SYNTAX_NORMAL3(SUB2CS, SUBCS, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27529 + SYNTAX_NORMAL3(SUB2GE, SUBGE, SUB2GE, INTREG, INTREG, INTREG, AVR32_V2),
27530 + SYNTAX_NORMAL3(SUB2LT, SUBLT, SUB2LT, INTREG, INTREG, INTREG, AVR32_V2),
27531 + SYNTAX_NORMAL3(SUB2MI, SUBMI, SUB2MI, INTREG, INTREG, INTREG, AVR32_V2),
27532 + SYNTAX_NORMAL3(SUB2PL, SUBPL, SUB2PL, INTREG, INTREG, INTREG, AVR32_V2),
27533 + SYNTAX_NORMAL3(SUB2LS, SUBLS, SUB2LS, INTREG, INTREG, INTREG, AVR32_V2),
27534 + SYNTAX_NORMAL3(SUB2GT, SUBGT, SUB2GT, INTREG, INTREG, INTREG, AVR32_V2),
27535 + SYNTAX_NORMAL3(SUB2LE, SUBLE, SUB2LE, INTREG, INTREG, INTREG, AVR32_V2),
27536 + SYNTAX_NORMAL3(SUB2HI, SUBHI, SUB2HI, INTREG, INTREG, INTREG, AVR32_V2),
27537 + SYNTAX_NORMAL3(SUB2VS, SUBVS, SUB2VS, INTREG, INTREG, INTREG, AVR32_V2),
27538 + SYNTAX_NORMAL3(SUB2VC, SUBVC, SUB2VC, INTREG, INTREG, INTREG, AVR32_V2),
27539 + SYNTAX_NORMAL3(SUB2QS, SUBQS, SUB2QS, INTREG, INTREG, INTREG, AVR32_V2),
27540 + SYNTAX_NORMAL3(SUB2AL, SUBAL, SUB2AL, INTREG, INTREG, INTREG, AVR32_V2),
27541 + SYNTAX_NORMAL3(SUB2HS, SUBHS, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27542 + SYNTAX_NORMAL3(SUB2LO, SUBLO, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27543 + SYNTAX_NORMAL3(ANDEQ, ANDEQ, ANDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27544 + SYNTAX_NORMAL3(ANDNE, ANDNE, ANDNE, INTREG, INTREG, INTREG, AVR32_V2),
27545 + SYNTAX_NORMAL3(ANDCC, ANDCC, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27546 + SYNTAX_NORMAL3(ANDCS, ANDCS, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27547 + SYNTAX_NORMAL3(ANDGE, ANDGE, ANDGE, INTREG, INTREG, INTREG, AVR32_V2),
27548 + SYNTAX_NORMAL3(ANDLT, ANDLT, ANDLT, INTREG, INTREG, INTREG, AVR32_V2),
27549 + SYNTAX_NORMAL3(ANDMI, ANDMI, ANDMI, INTREG, INTREG, INTREG, AVR32_V2),
27550 + SYNTAX_NORMAL3(ANDPL, ANDPL, ANDPL, INTREG, INTREG, INTREG, AVR32_V2),
27551 + SYNTAX_NORMAL3(ANDLS, ANDLS, ANDLS, INTREG, INTREG, INTREG, AVR32_V2),
27552 + SYNTAX_NORMAL3(ANDGT, ANDGT, ANDGT, INTREG, INTREG, INTREG, AVR32_V2),
27553 + SYNTAX_NORMAL3(ANDLE, ANDLE, ANDLE, INTREG, INTREG, INTREG, AVR32_V2),
27554 + SYNTAX_NORMAL3(ANDHI, ANDHI, ANDHI, INTREG, INTREG, INTREG, AVR32_V2),
27555 + SYNTAX_NORMAL3(ANDVS, ANDVS, ANDVS, INTREG, INTREG, INTREG, AVR32_V2),
27556 + SYNTAX_NORMAL3(ANDVC, ANDVC, ANDVC, INTREG, INTREG, INTREG, AVR32_V2),
27557 + SYNTAX_NORMAL3(ANDQS, ANDQS, ANDQS, INTREG, INTREG, INTREG, AVR32_V2),
27558 + SYNTAX_NORMAL3(ANDAL, ANDAL, ANDAL, INTREG, INTREG, INTREG, AVR32_V2),
27559 + SYNTAX_NORMAL3(ANDHS, ANDHS, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27560 + SYNTAX_NORMAL3(ANDLO, ANDLO, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27561 + SYNTAX_NORMAL3(OREQ, OREQ, OREQ, INTREG, INTREG, INTREG, AVR32_V2),
27562 + SYNTAX_NORMAL3(ORNE, ORNE, ORNE, INTREG, INTREG, INTREG, AVR32_V2),
27563 + SYNTAX_NORMAL3(ORCC, ORCC, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27564 + SYNTAX_NORMAL3(ORCS, ORCS, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27565 + SYNTAX_NORMAL3(ORGE, ORGE, ORGE, INTREG, INTREG, INTREG, AVR32_V2),
27566 + SYNTAX_NORMAL3(ORLT, ORLT, ORLT, INTREG, INTREG, INTREG, AVR32_V2),
27567 + SYNTAX_NORMAL3(ORMI, ORMI, ORMI, INTREG, INTREG, INTREG, AVR32_V2),
27568 + SYNTAX_NORMAL3(ORPL, ORPL, ORPL, INTREG, INTREG, INTREG, AVR32_V2),
27569 + SYNTAX_NORMAL3(ORLS, ORLS, ORLS, INTREG, INTREG, INTREG, AVR32_V2),
27570 + SYNTAX_NORMAL3(ORGT, ORGT, ORGT, INTREG, INTREG, INTREG, AVR32_V2),
27571 + SYNTAX_NORMAL3(ORLE, ORLE, ORLE, INTREG, INTREG, INTREG, AVR32_V2),
27572 + SYNTAX_NORMAL3(ORHI, ORHI, ORHI, INTREG, INTREG, INTREG, AVR32_V2),
27573 + SYNTAX_NORMAL3(ORVS, ORVS, ORVS, INTREG, INTREG, INTREG, AVR32_V2),
27574 + SYNTAX_NORMAL3(ORVC, ORVC, ORVC, INTREG, INTREG, INTREG, AVR32_V2),
27575 + SYNTAX_NORMAL3(ORQS, ORQS, ORQS, INTREG, INTREG, INTREG, AVR32_V2),
27576 + SYNTAX_NORMAL3(ORAL, ORAL, ORAL, INTREG, INTREG, INTREG, AVR32_V2),
27577 + SYNTAX_NORMAL3(ORHS, ORHS, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27578 + SYNTAX_NORMAL3(ORLO, ORLO, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27579 + SYNTAX_NORMAL3(EOREQ, EOREQ, EOREQ, INTREG, INTREG, INTREG, AVR32_V2),
27580 + SYNTAX_NORMAL3(EORNE, EORNE, EORNE, INTREG, INTREG, INTREG, AVR32_V2),
27581 + SYNTAX_NORMAL3(EORCC, EORCC, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27582 + SYNTAX_NORMAL3(EORCS, EORCS, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27583 + SYNTAX_NORMAL3(EORGE, EORGE, EORGE, INTREG, INTREG, INTREG, AVR32_V2),
27584 + SYNTAX_NORMAL3(EORLT, EORLT, EORLT, INTREG, INTREG, INTREG, AVR32_V2),
27585 + SYNTAX_NORMAL3(EORMI, EORMI, EORMI, INTREG, INTREG, INTREG, AVR32_V2),
27586 + SYNTAX_NORMAL3(EORPL, EORPL, EORPL, INTREG, INTREG, INTREG, AVR32_V2),
27587 + SYNTAX_NORMAL3(EORLS, EORLS, EORLS, INTREG, INTREG, INTREG, AVR32_V2),
27588 + SYNTAX_NORMAL3(EORGT, EORGT, EORGT, INTREG, INTREG, INTREG, AVR32_V2),
27589 + SYNTAX_NORMAL3(EORLE, EORLE, EORLE, INTREG, INTREG, INTREG, AVR32_V2),
27590 + SYNTAX_NORMAL3(EORHI, EORHI, EORHI, INTREG, INTREG, INTREG, AVR32_V2),
27591 + SYNTAX_NORMAL3(EORVS, EORVS, EORVS, INTREG, INTREG, INTREG, AVR32_V2),
27592 + SYNTAX_NORMAL3(EORVC, EORVC, EORVC, INTREG, INTREG, INTREG, AVR32_V2),
27593 + SYNTAX_NORMAL3(EORQS, EORQS, EORQS, INTREG, INTREG, INTREG, AVR32_V2),
27594 + SYNTAX_NORMAL3(EORAL, EORAL, EORAL, INTREG, INTREG, INTREG, AVR32_V2),
27595 + SYNTAX_NORMAL3(EORHS, EORHS, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27596 + SYNTAX_NORMAL3(EORLO, EORLO, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27597 + SYNTAX_NORMAL2(LD_WEQ, LD_WEQ, LD_WEQ, INTREG, INTREG_UDISP_W, AVR32_V2),
27598 + SYNTAX_NORMAL2(LD_WNE, LD_WNE, LD_WNE, INTREG, INTREG_UDISP_W, AVR32_V2),
27599 + SYNTAX_NORMAL2(LD_WCC, LD_WCC, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27600 + SYNTAX_NORMAL2(LD_WCS, LD_WCS, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27601 + SYNTAX_NORMAL2(LD_WGE, LD_WGE, LD_WGE, INTREG, INTREG_UDISP_W, AVR32_V2),
27602 + SYNTAX_NORMAL2(LD_WLT, LD_WLT, LD_WLT, INTREG, INTREG_UDISP_W, AVR32_V2),
27603 + SYNTAX_NORMAL2(LD_WMI, LD_WMI, LD_WMI, INTREG, INTREG_UDISP_W, AVR32_V2),
27604 + SYNTAX_NORMAL2(LD_WPL, LD_WPL, LD_WPL, INTREG, INTREG_UDISP_W, AVR32_V2),
27605 + SYNTAX_NORMAL2(LD_WLS, LD_WLS, LD_WLS, INTREG, INTREG_UDISP_W, AVR32_V2),
27606 + SYNTAX_NORMAL2(LD_WGT, LD_WGT, LD_WGT, INTREG, INTREG_UDISP_W, AVR32_V2),
27607 + SYNTAX_NORMAL2(LD_WLE, LD_WLE, LD_WLE, INTREG, INTREG_UDISP_W, AVR32_V2),
27608 + SYNTAX_NORMAL2(LD_WHI, LD_WHI, LD_WHI, INTREG, INTREG_UDISP_W, AVR32_V2),
27609 + SYNTAX_NORMAL2(LD_WVS, LD_WVS, LD_WVS, INTREG, INTREG_UDISP_W, AVR32_V2),
27610 + SYNTAX_NORMAL2(LD_WVC, LD_WVC, LD_WVC, INTREG, INTREG_UDISP_W, AVR32_V2),
27611 + SYNTAX_NORMAL2(LD_WQS, LD_WQS, LD_WQS, INTREG, INTREG_UDISP_W, AVR32_V2),
27612 + SYNTAX_NORMAL2(LD_WAL, LD_WAL, LD_WAL, INTREG, INTREG_UDISP_W, AVR32_V2),
27613 + SYNTAX_NORMAL2(LD_WHS, LD_WHS, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27614 + SYNTAX_NORMAL2(LD_WLO, LD_WLO, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27615 + SYNTAX_NORMAL2(LD_SHEQ, LD_SHEQ, LD_SHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27616 + SYNTAX_NORMAL2(LD_SHNE, LD_SHNE, LD_SHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27617 + SYNTAX_NORMAL2(LD_SHCC, LD_SHCC, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27618 + SYNTAX_NORMAL2(LD_SHCS, LD_SHCS, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27619 + SYNTAX_NORMAL2(LD_SHGE, LD_SHGE, LD_SHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27620 + SYNTAX_NORMAL2(LD_SHLT, LD_SHLT, LD_SHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27621 + SYNTAX_NORMAL2(LD_SHMI, LD_SHMI, LD_SHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27622 + SYNTAX_NORMAL2(LD_SHPL, LD_SHPL, LD_SHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27623 + SYNTAX_NORMAL2(LD_SHLS, LD_SHLS, LD_SHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27624 + SYNTAX_NORMAL2(LD_SHGT, LD_SHGT, LD_SHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27625 + SYNTAX_NORMAL2(LD_SHLE, LD_SHLE, LD_SHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27626 + SYNTAX_NORMAL2(LD_SHHI, LD_SHHI, LD_SHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27627 + SYNTAX_NORMAL2(LD_SHVS, LD_SHVS, LD_SHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27628 + SYNTAX_NORMAL2(LD_SHVC, LD_SHVC, LD_SHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27629 + SYNTAX_NORMAL2(LD_SHQS, LD_SHQS, LD_SHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27630 + SYNTAX_NORMAL2(LD_SHAL, LD_SHAL, LD_SHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27631 + SYNTAX_NORMAL2(LD_SHHS, LD_SHHS, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27632 + SYNTAX_NORMAL2(LD_SHLO, LD_SHLO, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27633 + SYNTAX_NORMAL2(LD_UHEQ, LD_UHEQ, LD_UHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27634 + SYNTAX_NORMAL2(LD_UHNE, LD_UHNE, LD_UHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27635 + SYNTAX_NORMAL2(LD_UHCC, LD_UHCC, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27636 + SYNTAX_NORMAL2(LD_UHCS, LD_UHCS, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27637 + SYNTAX_NORMAL2(LD_UHGE, LD_UHGE, LD_UHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27638 + SYNTAX_NORMAL2(LD_UHLT, LD_UHLT, LD_UHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27639 + SYNTAX_NORMAL2(LD_UHMI, LD_UHMI, LD_UHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27640 + SYNTAX_NORMAL2(LD_UHPL, LD_UHPL, LD_UHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27641 + SYNTAX_NORMAL2(LD_UHLS, LD_UHLS, LD_UHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27642 + SYNTAX_NORMAL2(LD_UHGT, LD_UHGT, LD_UHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27643 + SYNTAX_NORMAL2(LD_UHLE, LD_UHLE, LD_UHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27644 + SYNTAX_NORMAL2(LD_UHHI, LD_UHHI, LD_UHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27645 + SYNTAX_NORMAL2(LD_UHVS, LD_UHVS, LD_UHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27646 + SYNTAX_NORMAL2(LD_UHVC, LD_UHVC, LD_UHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27647 + SYNTAX_NORMAL2(LD_UHQS, LD_UHQS, LD_UHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27648 + SYNTAX_NORMAL2(LD_UHAL, LD_UHAL, LD_UHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27649 + SYNTAX_NORMAL2(LD_UHHS, LD_UHHS, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27650 + SYNTAX_NORMAL2(LD_UHLO, LD_UHLO, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27651 + SYNTAX_NORMAL2(LD_SBEQ, LD_SBEQ, LD_SBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27652 + SYNTAX_NORMAL2(LD_SBNE, LD_SBNE, LD_SBNE, INTREG, INTREG_UDISP, AVR32_V2),
27653 + SYNTAX_NORMAL2(LD_SBCC, LD_SBCC, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27654 + SYNTAX_NORMAL2(LD_SBCS, LD_SBCS, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27655 + SYNTAX_NORMAL2(LD_SBGE, LD_SBGE, LD_SBGE, INTREG, INTREG_UDISP, AVR32_V2),
27656 + SYNTAX_NORMAL2(LD_SBLT, LD_SBLT, LD_SBLT, INTREG, INTREG_UDISP, AVR32_V2),
27657 + SYNTAX_NORMAL2(LD_SBMI, LD_SBMI, LD_SBMI, INTREG, INTREG_UDISP, AVR32_V2),
27658 + SYNTAX_NORMAL2(LD_SBPL, LD_SBPL, LD_SBPL, INTREG, INTREG_UDISP, AVR32_V2),
27659 + SYNTAX_NORMAL2(LD_SBLS, LD_SBLS, LD_SBLS, INTREG, INTREG_UDISP, AVR32_V2),
27660 + SYNTAX_NORMAL2(LD_SBGT, LD_SBGT, LD_SBGT, INTREG, INTREG_UDISP, AVR32_V2),
27661 + SYNTAX_NORMAL2(LD_SBLE, LD_SBLE, LD_SBLE, INTREG, INTREG_UDISP, AVR32_V2),
27662 + SYNTAX_NORMAL2(LD_SBHI, LD_SBHI, LD_SBHI, INTREG, INTREG_UDISP, AVR32_V2),
27663 + SYNTAX_NORMAL2(LD_SBVS, LD_SBVS, LD_SBVS, INTREG, INTREG_UDISP, AVR32_V2),
27664 + SYNTAX_NORMAL2(LD_SBVC, LD_SBVC, LD_SBVC, INTREG, INTREG_UDISP, AVR32_V2),
27665 + SYNTAX_NORMAL2(LD_SBQS, LD_SBQS, LD_SBQS, INTREG, INTREG_UDISP, AVR32_V2),
27666 + SYNTAX_NORMAL2(LD_SBAL, LD_SBAL, LD_SBAL, INTREG, INTREG_UDISP, AVR32_V2),
27667 + SYNTAX_NORMAL2(LD_SBHS, LD_SBHS, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27668 + SYNTAX_NORMAL2(LD_SBLO, LD_SBLO, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27669 + SYNTAX_NORMAL2(LD_UBEQ, LD_UBEQ, LD_UBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27670 + SYNTAX_NORMAL2(LD_UBNE, LD_UBNE, LD_UBNE, INTREG, INTREG_UDISP, AVR32_V2),
27671 + SYNTAX_NORMAL2(LD_UBCC, LD_UBCC, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27672 + SYNTAX_NORMAL2(LD_UBCS, LD_UBCS, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27673 + SYNTAX_NORMAL2(LD_UBGE, LD_UBGE, LD_UBGE, INTREG, INTREG_UDISP, AVR32_V2),
27674 + SYNTAX_NORMAL2(LD_UBLT, LD_UBLT, LD_UBLT, INTREG, INTREG_UDISP, AVR32_V2),
27675 + SYNTAX_NORMAL2(LD_UBMI, LD_UBMI, LD_UBMI, INTREG, INTREG_UDISP, AVR32_V2),
27676 + SYNTAX_NORMAL2(LD_UBPL, LD_UBPL, LD_UBPL, INTREG, INTREG_UDISP, AVR32_V2),
27677 + SYNTAX_NORMAL2(LD_UBLS, LD_UBLS, LD_UBLS, INTREG, INTREG_UDISP, AVR32_V2),
27678 + SYNTAX_NORMAL2(LD_UBGT, LD_UBGT, LD_UBGT, INTREG, INTREG_UDISP, AVR32_V2),
27679 + SYNTAX_NORMAL2(LD_UBLE, LD_UBLE, LD_UBLE, INTREG, INTREG_UDISP, AVR32_V2),
27680 + SYNTAX_NORMAL2(LD_UBHI, LD_UBHI, LD_UBHI, INTREG, INTREG_UDISP, AVR32_V2),
27681 + SYNTAX_NORMAL2(LD_UBVS, LD_UBVS, LD_UBVS, INTREG, INTREG_UDISP, AVR32_V2),
27682 + SYNTAX_NORMAL2(LD_UBVC, LD_UBVC, LD_UBVC, INTREG, INTREG_UDISP, AVR32_V2),
27683 + SYNTAX_NORMAL2(LD_UBQS, LD_UBQS, LD_UBQS, INTREG, INTREG_UDISP, AVR32_V2),
27684 + SYNTAX_NORMAL2(LD_UBAL, LD_UBAL, LD_UBAL, INTREG, INTREG_UDISP, AVR32_V2),
27685 + SYNTAX_NORMAL2(LD_UBHS, LD_UBHS, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27686 + SYNTAX_NORMAL2(LD_UBLO, LD_UBLO, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27687 + SYNTAX_NORMAL2(ST_WEQ, ST_WEQ, ST_WEQ, INTREG_UDISP_W, INTREG, AVR32_V2),
27688 + SYNTAX_NORMAL2(ST_WNE, ST_WNE, ST_WNE, INTREG_UDISP_W, INTREG, AVR32_V2),
27689 + SYNTAX_NORMAL2(ST_WCC, ST_WCC, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27690 + SYNTAX_NORMAL2(ST_WCS, ST_WCS, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27691 + SYNTAX_NORMAL2(ST_WGE, ST_WGE, ST_WGE, INTREG_UDISP_W, INTREG, AVR32_V2),
27692 + SYNTAX_NORMAL2(ST_WLT, ST_WLT, ST_WLT, INTREG_UDISP_W, INTREG, AVR32_V2),
27693 + SYNTAX_NORMAL2(ST_WMI, ST_WMI, ST_WMI, INTREG_UDISP_W, INTREG, AVR32_V2),
27694 + SYNTAX_NORMAL2(ST_WPL, ST_WPL, ST_WPL, INTREG_UDISP_W, INTREG, AVR32_V2),
27695 + SYNTAX_NORMAL2(ST_WLS, ST_WLS, ST_WLS, INTREG_UDISP_W, INTREG, AVR32_V2),
27696 + SYNTAX_NORMAL2(ST_WGT, ST_WGT, ST_WGT, INTREG_UDISP_W, INTREG, AVR32_V2),
27697 + SYNTAX_NORMAL2(ST_WLE, ST_WLE, ST_WLE, INTREG_UDISP_W, INTREG, AVR32_V2),
27698 + SYNTAX_NORMAL2(ST_WHI, ST_WHI, ST_WHI, INTREG_UDISP_W, INTREG, AVR32_V2),
27699 + SYNTAX_NORMAL2(ST_WVS, ST_WVS, ST_WVS, INTREG_UDISP_W, INTREG, AVR32_V2),
27700 + SYNTAX_NORMAL2(ST_WVC, ST_WVC, ST_WVC, INTREG_UDISP_W, INTREG, AVR32_V2),
27701 + SYNTAX_NORMAL2(ST_WQS, ST_WQS, ST_WQS, INTREG_UDISP_W, INTREG, AVR32_V2),
27702 + SYNTAX_NORMAL2(ST_WAL, ST_WAL, ST_WAL, INTREG_UDISP_W, INTREG, AVR32_V2),
27703 + SYNTAX_NORMAL2(ST_WHS, ST_WHS, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27704 + SYNTAX_NORMAL2(ST_WLO, ST_WLO, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27705 + SYNTAX_NORMAL2(ST_HEQ, ST_HEQ, ST_HEQ, INTREG_UDISP_H, INTREG, AVR32_V2),
27706 + SYNTAX_NORMAL2(ST_HNE, ST_HNE, ST_HNE, INTREG_UDISP_H, INTREG, AVR32_V2),
27707 + SYNTAX_NORMAL2(ST_HCC, ST_HCC, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27708 + SYNTAX_NORMAL2(ST_HCS, ST_HCS, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27709 + SYNTAX_NORMAL2(ST_HGE, ST_HGE, ST_HGE, INTREG_UDISP_H, INTREG, AVR32_V2),
27710 + SYNTAX_NORMAL2(ST_HLT, ST_HLT, ST_HLT, INTREG_UDISP_H, INTREG, AVR32_V2),
27711 + SYNTAX_NORMAL2(ST_HMI, ST_HMI, ST_HMI, INTREG_UDISP_H, INTREG, AVR32_V2),
27712 + SYNTAX_NORMAL2(ST_HPL, ST_HPL, ST_HPL, INTREG_UDISP_H, INTREG, AVR32_V2),
27713 + SYNTAX_NORMAL2(ST_HLS, ST_HLS, ST_HLS, INTREG_UDISP_H, INTREG, AVR32_V2),
27714 + SYNTAX_NORMAL2(ST_HGT, ST_HGT, ST_HGT, INTREG_UDISP_H, INTREG, AVR32_V2),
27715 + SYNTAX_NORMAL2(ST_HLE, ST_HLE, ST_HLE, INTREG_UDISP_H, INTREG, AVR32_V2),
27716 + SYNTAX_NORMAL2(ST_HHI, ST_HHI, ST_HHI, INTREG_UDISP_H, INTREG, AVR32_V2),
27717 + SYNTAX_NORMAL2(ST_HVS, ST_HVS, ST_HVS, INTREG_UDISP_H, INTREG, AVR32_V2),
27718 + SYNTAX_NORMAL2(ST_HVC, ST_HVC, ST_HVC, INTREG_UDISP_H, INTREG, AVR32_V2),
27719 + SYNTAX_NORMAL2(ST_HQS, ST_HQS, ST_HQS, INTREG_UDISP_H, INTREG, AVR32_V2),
27720 + SYNTAX_NORMAL2(ST_HAL, ST_HAL, ST_HAL, INTREG_UDISP_H, INTREG, AVR32_V2),
27721 + SYNTAX_NORMAL2(ST_HHS, ST_HHS, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27722 + SYNTAX_NORMAL2(ST_HLO, ST_HLO, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27723 + SYNTAX_NORMAL2(ST_BEQ, ST_BEQ, ST_BEQ, INTREG_UDISP, INTREG, AVR32_V2),
27724 + SYNTAX_NORMAL2(ST_BNE, ST_BNE, ST_BNE, INTREG_UDISP, INTREG, AVR32_V2),
27725 + SYNTAX_NORMAL2(ST_BCC, ST_BCC, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27726 + SYNTAX_NORMAL2(ST_BCS, ST_BCS, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27727 + SYNTAX_NORMAL2(ST_BGE, ST_BGE, ST_BGE, INTREG_UDISP, INTREG, AVR32_V2),
27728 + SYNTAX_NORMAL2(ST_BLT, ST_BLT, ST_BLT, INTREG_UDISP, INTREG, AVR32_V2),
27729 + SYNTAX_NORMAL2(ST_BMI, ST_BMI, ST_BMI, INTREG_UDISP, INTREG, AVR32_V2),
27730 + SYNTAX_NORMAL2(ST_BPL, ST_BPL, ST_BPL, INTREG_UDISP, INTREG, AVR32_V2),
27731 + SYNTAX_NORMAL2(ST_BLS, ST_BLS, ST_BLS, INTREG_UDISP, INTREG, AVR32_V2),
27732 + SYNTAX_NORMAL2(ST_BGT, ST_BGT, ST_BGT, INTREG_UDISP, INTREG, AVR32_V2),
27733 + SYNTAX_NORMAL2(ST_BLE, ST_BLE, ST_BLE, INTREG_UDISP, INTREG, AVR32_V2),
27734 + SYNTAX_NORMAL2(ST_BHI, ST_BHI, ST_BHI, INTREG_UDISP, INTREG, AVR32_V2),
27735 + SYNTAX_NORMAL2(ST_BVS, ST_BVS, ST_BVS, INTREG_UDISP, INTREG, AVR32_V2),
27736 + SYNTAX_NORMAL2(ST_BVC, ST_BVC, ST_BVC, INTREG_UDISP, INTREG, AVR32_V2),
27737 + SYNTAX_NORMAL2(ST_BQS, ST_BQS, ST_BQS, INTREG_UDISP, INTREG, AVR32_V2),
27738 + SYNTAX_NORMAL2(ST_BAL, ST_BAL, ST_BAL, INTREG_UDISP, INTREG, AVR32_V2),
27739 + SYNTAX_NORMAL2(ST_BHS, ST_BHS, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27740 + SYNTAX_NORMAL2(ST_BLO, ST_BLO, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27741 + SYNTAX_NORMAL2(MOVH, MOVH, MOVH, INTREG, UNSIGNED_CONST, AVR32_V2),
27745 +#define NORMAL_MNEMONIC(name, syntax, str) \
27747 + AVR32_MNEMONIC_##name, str, \
27748 + &avr32_syntax_table[AVR32_SYNTAX_##syntax], \
27750 +#define FP_MNEMONIC(name, syntax, str) \
27751 + NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"), \
27752 + NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d")
27754 +const struct avr32_mnemonic avr32_mnemonic_table[] =
27756 + NORMAL_MNEMONIC(ABS, ABS, "abs"),
27757 + NORMAL_MNEMONIC(ACALL, ACALL, "acall"),
27758 + NORMAL_MNEMONIC(ACR, ACR, "acr"),
27759 + NORMAL_MNEMONIC(ADC, ADC, "adc"),
27760 + NORMAL_MNEMONIC(ADD, ADD1, "add"),
27761 + NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"),
27762 + NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"),
27763 + NORMAL_MNEMONIC(AND, AND1, "and"),
27764 + NORMAL_MNEMONIC(ANDH, ANDH, "andh"),
27765 + NORMAL_MNEMONIC(ANDL, ANDL, "andl"),
27766 + NORMAL_MNEMONIC(ANDN, ANDN, "andn"),
27767 + NORMAL_MNEMONIC(ASR, ASR1, "asr"),
27768 + NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"),
27769 + NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"),
27770 + NORMAL_MNEMONIC(BFINS, BFINS, "bfins"),
27771 + NORMAL_MNEMONIC(BLD, BLD, "bld"),
27772 + NORMAL_MNEMONIC(BREQ, BREQ1, "breq"),
27773 + NORMAL_MNEMONIC(BRNE, BRNE1, "brne"),
27774 + NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"),
27775 + NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"),
27776 + NORMAL_MNEMONIC(BRGE, BRGE1, "brge"),
27777 + NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"),
27778 + NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"),
27779 + NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"),
27780 + NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"),
27781 + NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"),
27782 + NORMAL_MNEMONIC(BRLS, BRLS, "brls"),
27783 + NORMAL_MNEMONIC(BRGT, BRGT, "brgt"),
27784 + NORMAL_MNEMONIC(BRLE, BRLE, "brle"),
27785 + NORMAL_MNEMONIC(BRHI, BRHI, "brhi"),
27786 + NORMAL_MNEMONIC(BRVS, BRVS, "brvs"),
27787 + NORMAL_MNEMONIC(BRVC, BRVC, "brvc"),
27788 + NORMAL_MNEMONIC(BRQS, BRQS, "brqs"),
27789 + NORMAL_MNEMONIC(BRAL, BRAL, "bral"),
27790 + NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"),
27791 + NORMAL_MNEMONIC(BREV, BREV, "brev"),
27792 + NORMAL_MNEMONIC(BST, BST, "bst"),
27793 + NORMAL_MNEMONIC(CACHE, CACHE, "cache"),
27794 + NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"),
27795 + NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"),
27796 + NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"),
27797 + NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"),
27798 + NORMAL_MNEMONIC(CBR, CBR, "cbr"),
27799 + NORMAL_MNEMONIC(CLZ, CLZ, "clz"),
27800 + NORMAL_MNEMONIC(COM, COM, "com"),
27801 + NORMAL_MNEMONIC(COP, COP, "cop"),
27802 + NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"),
27803 + NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"),
27804 + NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"),
27805 + NORMAL_MNEMONIC(CP, CP_W1, "cp"),
27806 + NORMAL_MNEMONIC(CPC, CPC1, "cpc"),
27807 + NORMAL_MNEMONIC(CSRF, CSRF, "csrf"),
27808 + NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"),
27809 + NORMAL_MNEMONIC(DIVS, DIVS, "divs"),
27810 + NORMAL_MNEMONIC(DIVU, DIVU, "divu"),
27811 + NORMAL_MNEMONIC(EOR, EOR1, "eor"),
27812 + NORMAL_MNEMONIC(EORL, EORL, "eorl"),
27813 + NORMAL_MNEMONIC(EORH, EORH, "eorh"),
27814 + NORMAL_MNEMONIC(FRS, FRS, "frs"),
27815 + NORMAL_MNEMONIC(SSCALL, SSCALL, "sscall"),
27816 + NORMAL_MNEMONIC(RETSS, RETSS, "retss"),
27817 + NORMAL_MNEMONIC(ICALL, ICALL, "icall"),
27818 + NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"),
27819 + NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"),
27820 + NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"),
27821 + NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"),
27822 + NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"),
27823 + NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"),
27824 + NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"),
27825 + NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"),
27826 + NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"),
27827 + NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"),
27828 + NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"),
27829 + NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"),
27830 + NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"),
27831 + NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"),
27832 + NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"),
27833 + NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"),
27834 + NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"),
27835 + NORMAL_MNEMONIC(LDM, LDM, "ldm"),
27836 + NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"),
27837 + NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"),
27838 + NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"),
27839 + NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"),
27840 + NORMAL_MNEMONIC(LSL, LSL1, "lsl"),
27841 + NORMAL_MNEMONIC(LSR, LSR1, "lsr"),
27842 + NORMAL_MNEMONIC(MAC, MAC, "mac"),
27843 + NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"),
27844 + NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"),
27845 + NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"),
27846 + NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"),
27847 + NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"),
27848 + NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"),
27849 + NORMAL_MNEMONIC(MAX, MAX, "max"),
27850 + NORMAL_MNEMONIC(MCALL, MCALL, "mcall"),
27851 + NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"),
27852 + NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"),
27853 + NORMAL_MNEMONIC(MIN, MIN, "min"),
27854 + NORMAL_MNEMONIC(MOV, MOV3, "mov"),
27855 + NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"),
27856 + NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"),
27857 + NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"),
27858 + NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"),
27859 + NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"),
27860 + NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"),
27861 + NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"),
27862 + NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"),
27863 + NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"),
27864 + NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"),
27865 + NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"),
27866 + NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"),
27867 + NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"),
27868 + NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"),
27869 + NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"),
27870 + NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"),
27871 + NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"),
27872 + NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"),
27873 + NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"),
27874 + NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"),
27875 + NORMAL_MNEMONIC(MUL, MUL1, "mul"),
27876 + NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"),
27877 + NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"),
27878 + NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"),
27879 + NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"),
27880 + NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"),
27881 + NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"),
27882 + NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"),
27883 + NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"),
27884 + NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"),
27885 + NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"),
27886 + NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"),
27887 + NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"),
27888 + NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"),
27889 + NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"),
27890 + NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"),
27891 + NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"),
27892 + NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"),
27893 + NORMAL_MNEMONIC(NEG, NEG, "neg"),
27894 + NORMAL_MNEMONIC(NOP, NOP, "nop"),
27895 + NORMAL_MNEMONIC(OR, OR1, "or"),
27896 + NORMAL_MNEMONIC(ORH, ORH, "orh"),
27897 + NORMAL_MNEMONIC(ORL, ORL, "orl"),
27898 + NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"),
27899 + NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"),
27900 + NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"),
27901 + NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"),
27902 + NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"),
27903 + NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"),
27904 + NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"),
27905 + NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"),
27906 + NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"),
27907 + NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"),
27908 + NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"),
27909 + NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"),
27910 + NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"),
27911 + NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"),
27912 + NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"),
27913 + NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"),
27914 + NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"),
27915 + NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"),
27916 + NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"),
27917 + NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"),
27918 + NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"),
27919 + NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"),
27920 + NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"),
27921 + NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"),
27922 + NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"),
27923 + NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"),
27924 + NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"),
27925 + NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"),
27926 + NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"),
27927 + NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"),
27928 + NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"),
27929 + NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"),
27930 + NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"),
27931 + NORMAL_MNEMONIC(POPJC, POPJC, "popjc"),
27932 + NORMAL_MNEMONIC(POPM, POPM, "popm"),
27933 + NORMAL_MNEMONIC(PREF, PREF, "pref"),
27934 + NORMAL_MNEMONIC(PSAD, PSAD, "psad"),
27935 + NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"),
27936 + NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"),
27937 + NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"),
27938 + NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"),
27939 + NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"),
27940 + NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"),
27941 + NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"),
27942 + NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"),
27943 + NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"),
27944 + NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"),
27945 + NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"),
27946 + NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"),
27947 + NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"),
27948 + NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"),
27949 + NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"),
27950 + NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"),
27951 + NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"),
27952 + NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"),
27953 + NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"),
27954 + NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"),
27955 + NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"),
27956 + NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"),
27957 + NORMAL_MNEMONIC(RETNE, RETNE, "retne"),
27958 + NORMAL_MNEMONIC(RETCC, RETCC, "retcc"),
27959 + NORMAL_MNEMONIC(RETCS, RETCS, "retcs"),
27960 + NORMAL_MNEMONIC(RETGE, RETGE, "retge"),
27961 + NORMAL_MNEMONIC(RETLT, RETLT, "retlt"),
27962 + NORMAL_MNEMONIC(RETMI, RETMI, "retmi"),
27963 + NORMAL_MNEMONIC(RETPL, RETPL, "retpl"),
27964 + NORMAL_MNEMONIC(RETLS, RETLS, "retls"),
27965 + NORMAL_MNEMONIC(RETGT, RETGT, "retgt"),
27966 + NORMAL_MNEMONIC(RETLE, RETLE, "retle"),
27967 + NORMAL_MNEMONIC(RETHI, RETHI, "rethi"),
27968 + NORMAL_MNEMONIC(RETVS, RETVS, "retvs"),
27969 + NORMAL_MNEMONIC(RETVC, RETVC, "retvc"),
27970 + NORMAL_MNEMONIC(RETQS, RETQS, "retqs"),
27971 + NORMAL_MNEMONIC(RETAL, RETAL, "retal"),
27972 + NORMAL_MNEMONIC(RETHS, RETHS, "reths"),
27973 + NORMAL_MNEMONIC(RETLO, RETLO, "retlo"),
27974 + NORMAL_MNEMONIC(RET, RETAL, "ret"),
27975 + NORMAL_MNEMONIC(RETD, RETD, "retd"),
27976 + NORMAL_MNEMONIC(RETE, RETE, "rete"),
27977 + NORMAL_MNEMONIC(RETJ, RETJ, "retj"),
27978 + NORMAL_MNEMONIC(RETS, RETS, "rets"),
27979 + NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"),
27980 + NORMAL_MNEMONIC(ROL, ROL, "rol"),
27981 + NORMAL_MNEMONIC(ROR, ROR, "ror"),
27982 + NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"),
27983 + NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"),
27984 + NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"),
27985 + NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"),
27986 + NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"),
27987 + NORMAL_MNEMONIC(SATS, SATS, "sats"),
27988 + NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"),
27989 + NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"),
27990 + NORMAL_MNEMONIC(SATU, SATU, "satu"),
27991 + NORMAL_MNEMONIC(SBC, SBC, "sbc"),
27992 + NORMAL_MNEMONIC(SBR, SBR, "sbr"),
27993 + NORMAL_MNEMONIC(SCALL, SCALL, "scall"),
27994 + NORMAL_MNEMONIC(SCR, SCR, "scr"),
27995 + NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"),
27996 + NORMAL_MNEMONIC(SREQ, SREQ, "sreq"),
27997 + NORMAL_MNEMONIC(SRNE, SRNE, "srne"),
27998 + NORMAL_MNEMONIC(SRCC, SRCC, "srcc"),
27999 + NORMAL_MNEMONIC(SRCS, SRCS, "srcs"),
28000 + NORMAL_MNEMONIC(SRGE, SRGE, "srge"),
28001 + NORMAL_MNEMONIC(SRLT, SRLT, "srlt"),
28002 + NORMAL_MNEMONIC(SRMI, SRMI, "srmi"),
28003 + NORMAL_MNEMONIC(SRPL, SRPL, "srpl"),
28004 + NORMAL_MNEMONIC(SRLS, SRLS, "srls"),
28005 + NORMAL_MNEMONIC(SRGT, SRGT, "srgt"),
28006 + NORMAL_MNEMONIC(SRLE, SRLE, "srle"),
28007 + NORMAL_MNEMONIC(SRHI, SRHI, "srhi"),
28008 + NORMAL_MNEMONIC(SRVS, SRVS, "srvs"),
28009 + NORMAL_MNEMONIC(SRVC, SRVC, "srvc"),
28010 + NORMAL_MNEMONIC(SRQS, SRQS, "srqs"),
28011 + NORMAL_MNEMONIC(SRAL, SRAL, "sral"),
28012 + NORMAL_MNEMONIC(SRHS, SRHS, "srhs"),
28013 + NORMAL_MNEMONIC(SRLO, SRLO, "srlo"),
28014 + NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"),
28015 + NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"),
28016 + NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"),
28017 + NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"),
28018 + NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"),
28019 + NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"),
28020 + NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"),
28021 + NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"),
28022 + NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"),
28023 + NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"),
28024 + NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"),
28025 + NORMAL_MNEMONIC(STCOND, STCOND, "stcond"),
28026 + NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"),
28027 + NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"),
28028 + NORMAL_MNEMONIC(STM, STM, "stm"),
28029 + NORMAL_MNEMONIC(STMTS, STMTS, "stmts"),
28030 + NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"),
28031 + NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"),
28032 + NORMAL_MNEMONIC(SUB, SUB1, "sub"),
28033 + NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"),
28034 + NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"),
28035 + NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"),
28036 + NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"),
28037 + NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"),
28038 + NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"),
28039 + NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"),
28040 + NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"),
28041 + NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"),
28042 + NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"),
28043 + NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"),
28044 + NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"),
28045 + NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"),
28046 + NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"),
28047 + NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"),
28048 + NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"),
28049 + NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"),
28050 + NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"),
28051 + NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"),
28052 + NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"),
28053 + NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"),
28054 + NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"),
28055 + NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"),
28056 + NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"),
28057 + NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"),
28058 + NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"),
28059 + NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"),
28060 + NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"),
28061 + NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"),
28062 + NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"),
28063 + NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"),
28064 + NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"),
28065 + NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"),
28066 + NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"),
28067 + NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"),
28068 + NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"),
28069 + NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"),
28070 + NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"),
28071 + NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"),
28072 + NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"),
28073 + NORMAL_MNEMONIC(SYNC, SYNC, "sync"),
28074 + NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"),
28075 + NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"),
28076 + NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"),
28077 + NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"),
28078 + NORMAL_MNEMONIC(TST, TST, "tst"),
28079 + NORMAL_MNEMONIC(XCHG, XCHG, "xchg"),
28080 + NORMAL_MNEMONIC(MEMC, MEMC, "memc"),
28081 + NORMAL_MNEMONIC(MEMS, MEMS, "mems"),
28082 + NORMAL_MNEMONIC(MEMT, MEMT, "memt"),
28083 + NORMAL_MNEMONIC (FMAC_S, FMAC_S, "fmac.s"),
28084 + NORMAL_MNEMONIC (FNMAC_S, FNMAC_S, "fnmac.s"),
28085 + NORMAL_MNEMONIC (FMSC_S, FMSC_S, "fmsc.s"),
28086 + NORMAL_MNEMONIC (FNMSC_S, FNMSC_S, "fnmsc.s"),
28087 + NORMAL_MNEMONIC (FMUL_S, FMUL_S, "fmul.s"),
28088 + NORMAL_MNEMONIC (FNMUL_S, FNMUL_S, "fnmul.s"),
28089 + NORMAL_MNEMONIC (FADD_S, FADD_S, "fadd.s"),
28090 + NORMAL_MNEMONIC (FSUB_S, FSUB_S, "fsub.s"),
28091 + NORMAL_MNEMONIC (FCASTRS_SW, FCASTRS_SW, "fcastrs.sw"),
28092 + NORMAL_MNEMONIC (FCASTRS_UW, FCASTRS_UW, "fcastrs.uw"),
28093 + NORMAL_MNEMONIC (FCASTSW_S, FCASTSW_S, "fcastsw.s"),
28094 + NORMAL_MNEMONIC (FCASTUW_S, FCASTUW_S, "fcastuw.s"),
28095 + NORMAL_MNEMONIC (FCMP_S, FCMP_S, "fcmp.s"),
28096 + NORMAL_MNEMONIC (FCHK_S, FCHK_S, "fchk.s"),
28097 + NORMAL_MNEMONIC (FRCPA_S, FRCPA_S, "frcpa.s"),
28098 + NORMAL_MNEMONIC (FRSQRTA_S, FRSQRTA_S, "frsqrta.s"),
28099 + NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"),
28100 + NORMAL_MNEMONIC(CALL, CALL, "call"),
28101 + NORMAL_MNEMONIC(PICOSVMAC, PICOSVMAC0, "picosvmac"),
28102 + NORMAL_MNEMONIC(PICOSVMUL, PICOSVMUL0, "picosvmul"),
28103 + NORMAL_MNEMONIC(PICOVMAC, PICOVMAC0, "picovmac"),
28104 + NORMAL_MNEMONIC(PICOVMUL, PICOVMUL0, "picovmul"),
28105 + NORMAL_MNEMONIC(PICOLD_D, PICOLD_D2, "picold.d"),
28106 + NORMAL_MNEMONIC(PICOLD_W, PICOLD_W2, "picold.w"),
28107 + NORMAL_MNEMONIC(PICOLDM_D, PICOLDM_D, "picoldm.d"),
28108 + NORMAL_MNEMONIC(PICOLDM_W, PICOLDM_W, "picoldm.w"),
28109 + NORMAL_MNEMONIC(PICOMV_D, PICOMV_D1, "picomv.d"),
28110 + NORMAL_MNEMONIC(PICOMV_W, PICOMV_W1, "picomv.w"),
28111 + NORMAL_MNEMONIC(PICOST_D, PICOST_D2, "picost.d"),
28112 + NORMAL_MNEMONIC(PICOST_W, PICOST_W2, "picost.w"),
28113 + NORMAL_MNEMONIC(PICOSTM_D, PICOSTM_D, "picostm.d"),
28114 + NORMAL_MNEMONIC(PICOSTM_W, PICOSTM_W, "picostm.w"),
28115 + NORMAL_MNEMONIC(RSUBEQ, RSUBEQ, "rsubeq"),
28116 + NORMAL_MNEMONIC(RSUBNE, RSUBNE, "rsubne"),
28117 + NORMAL_MNEMONIC(RSUBCC, RSUBCC, "rsubcc"),
28118 + NORMAL_MNEMONIC(RSUBCS, RSUBCS, "rsubcs"),
28119 + NORMAL_MNEMONIC(RSUBGE, RSUBGE, "rsubge"),
28120 + NORMAL_MNEMONIC(RSUBLT, RSUBLT, "rsublt"),
28121 + NORMAL_MNEMONIC(RSUBMI, RSUBMI, "rsubmi"),
28122 + NORMAL_MNEMONIC(RSUBPL, RSUBPL, "rsubpl"),
28123 + NORMAL_MNEMONIC(RSUBLS, RSUBLS, "rsubls"),
28124 + NORMAL_MNEMONIC(RSUBGT, RSUBGT, "rsubgt"),
28125 + NORMAL_MNEMONIC(RSUBLE, RSUBLE, "rsuble"),
28126 + NORMAL_MNEMONIC(RSUBHI, RSUBHI, "rsubhi"),
28127 + NORMAL_MNEMONIC(RSUBVS, RSUBVS, "rsubvs"),
28128 + NORMAL_MNEMONIC(RSUBVC, RSUBVC, "rsubvc"),
28129 + NORMAL_MNEMONIC(RSUBQS, RSUBQS, "rsubqs"),
28130 + NORMAL_MNEMONIC(RSUBAL, RSUBAL, "rsubal"),
28131 + NORMAL_MNEMONIC(RSUBHS, RSUBHS, "rsubhs"),
28132 + NORMAL_MNEMONIC(RSUBLO, RSUBLO, "rsublo"),
28133 + NORMAL_MNEMONIC(ADDEQ, ADDEQ, "addeq"),
28134 + NORMAL_MNEMONIC(ADDNE, ADDNE, "addne"),
28135 + NORMAL_MNEMONIC(ADDCC, ADDCC, "addcc"),
28136 + NORMAL_MNEMONIC(ADDCS, ADDCS, "addcs"),
28137 + NORMAL_MNEMONIC(ADDGE, ADDGE, "addge"),
28138 + NORMAL_MNEMONIC(ADDLT, ADDLT, "addlt"),
28139 + NORMAL_MNEMONIC(ADDMI, ADDMI, "addmi"),
28140 + NORMAL_MNEMONIC(ADDPL, ADDPL, "addpl"),
28141 + NORMAL_MNEMONIC(ADDLS, ADDLS, "addls"),
28142 + NORMAL_MNEMONIC(ADDGT, ADDGT, "addgt"),
28143 + NORMAL_MNEMONIC(ADDLE, ADDLE, "addle"),
28144 + NORMAL_MNEMONIC(ADDHI, ADDHI, "addhi"),
28145 + NORMAL_MNEMONIC(ADDVS, ADDVS, "addvs"),
28146 + NORMAL_MNEMONIC(ADDVC, ADDVC, "addvc"),
28147 + NORMAL_MNEMONIC(ADDQS, ADDQS, "addqs"),
28148 + NORMAL_MNEMONIC(ADDAL, ADDAL, "addal"),
28149 + NORMAL_MNEMONIC(ADDHS, ADDHS, "addhs"),
28150 + NORMAL_MNEMONIC(ADDLO, ADDLO, "addlo"),
28151 + NORMAL_MNEMONIC(ANDEQ, ANDEQ, "andeq"),
28152 + NORMAL_MNEMONIC(ANDNE, ANDNE, "andne"),
28153 + NORMAL_MNEMONIC(ANDCC, ANDCC, "andcc"),
28154 + NORMAL_MNEMONIC(ANDCS, ANDCS, "andcs"),
28155 + NORMAL_MNEMONIC(ANDGE, ANDGE, "andge"),
28156 + NORMAL_MNEMONIC(ANDLT, ANDLT, "andlt"),
28157 + NORMAL_MNEMONIC(ANDMI, ANDMI, "andmi"),
28158 + NORMAL_MNEMONIC(ANDPL, ANDPL, "andpl"),
28159 + NORMAL_MNEMONIC(ANDLS, ANDLS, "andls"),
28160 + NORMAL_MNEMONIC(ANDGT, ANDGT, "andgt"),
28161 + NORMAL_MNEMONIC(ANDLE, ANDLE, "andle"),
28162 + NORMAL_MNEMONIC(ANDHI, ANDHI, "andhi"),
28163 + NORMAL_MNEMONIC(ANDVS, ANDVS, "andvs"),
28164 + NORMAL_MNEMONIC(ANDVC, ANDVC, "andvc"),
28165 + NORMAL_MNEMONIC(ANDQS, ANDQS, "andqs"),
28166 + NORMAL_MNEMONIC(ANDAL, ANDAL, "andal"),
28167 + NORMAL_MNEMONIC(ANDHS, ANDHS, "andhs"),
28168 + NORMAL_MNEMONIC(ANDLO, ANDLO, "andlo"),
28169 + NORMAL_MNEMONIC(OREQ, OREQ, "oreq"),
28170 + NORMAL_MNEMONIC(ORNE, ORNE, "orne"),
28171 + NORMAL_MNEMONIC(ORCC, ORCC, "orcc"),
28172 + NORMAL_MNEMONIC(ORCS, ORCS, "orcs"),
28173 + NORMAL_MNEMONIC(ORGE, ORGE, "orge"),
28174 + NORMAL_MNEMONIC(ORLT, ORLT, "orlt"),
28175 + NORMAL_MNEMONIC(ORMI, ORMI, "ormi"),
28176 + NORMAL_MNEMONIC(ORPL, ORPL, "orpl"),
28177 + NORMAL_MNEMONIC(ORLS, ORLS, "orls"),
28178 + NORMAL_MNEMONIC(ORGT, ORGT, "orgt"),
28179 + NORMAL_MNEMONIC(ORLE, ORLE, "orle"),
28180 + NORMAL_MNEMONIC(ORHI, ORHI, "orhi"),
28181 + NORMAL_MNEMONIC(ORVS, ORVS, "orvs"),
28182 + NORMAL_MNEMONIC(ORVC, ORVC, "orvc"),
28183 + NORMAL_MNEMONIC(ORQS, ORQS, "orqs"),
28184 + NORMAL_MNEMONIC(ORAL, ORAL, "oral"),
28185 + NORMAL_MNEMONIC(ORHS, ORHS, "orhs"),
28186 + NORMAL_MNEMONIC(ORLO, ORLO, "orlo"),
28187 + NORMAL_MNEMONIC(EOREQ, EOREQ, "eoreq"),
28188 + NORMAL_MNEMONIC(EORNE, EORNE, "eorne"),
28189 + NORMAL_MNEMONIC(EORCC, EORCC, "eorcc"),
28190 + NORMAL_MNEMONIC(EORCS, EORCS, "eorcs"),
28191 + NORMAL_MNEMONIC(EORGE, EORGE, "eorge"),
28192 + NORMAL_MNEMONIC(EORLT, EORLT, "eorlt"),
28193 + NORMAL_MNEMONIC(EORMI, EORMI, "eormi"),
28194 + NORMAL_MNEMONIC(EORPL, EORPL, "eorpl"),
28195 + NORMAL_MNEMONIC(EORLS, EORLS, "eorls"),
28196 + NORMAL_MNEMONIC(EORGT, EORGT, "eorgt"),
28197 + NORMAL_MNEMONIC(EORLE, EORLE, "eorle"),
28198 + NORMAL_MNEMONIC(EORHI, EORHI, "eorhi"),
28199 + NORMAL_MNEMONIC(EORVS, EORVS, "eorvs"),
28200 + NORMAL_MNEMONIC(EORVC, EORVC, "eorvc"),
28201 + NORMAL_MNEMONIC(EORQS, EORQS, "eorqs"),
28202 + NORMAL_MNEMONIC(EORAL, EORAL, "eoral"),
28203 + NORMAL_MNEMONIC(EORHS, EORHS, "eorhs"),
28204 + NORMAL_MNEMONIC(EORLO, EORLO, "eorlo"),
28205 + NORMAL_MNEMONIC(LD_WEQ, LD_WEQ, "ld.weq"),
28206 + NORMAL_MNEMONIC(LD_WNE, LD_WNE, "ld.wne"),
28207 + NORMAL_MNEMONIC(LD_WCC, LD_WCC, "ld.wcc"),
28208 + NORMAL_MNEMONIC(LD_WCS, LD_WCS, "ld.wcs"),
28209 + NORMAL_MNEMONIC(LD_WGE, LD_WGE, "ld.wge"),
28210 + NORMAL_MNEMONIC(LD_WLT, LD_WLT, "ld.wlt"),
28211 + NORMAL_MNEMONIC(LD_WMI, LD_WMI, "ld.wmi"),
28212 + NORMAL_MNEMONIC(LD_WPL, LD_WPL, "ld.wpl"),
28213 + NORMAL_MNEMONIC(LD_WLS, LD_WLS, "ld.wls"),
28214 + NORMAL_MNEMONIC(LD_WGT, LD_WGT, "ld.wgt"),
28215 + NORMAL_MNEMONIC(LD_WLE, LD_WLE, "ld.wle"),
28216 + NORMAL_MNEMONIC(LD_WHI, LD_WHI, "ld.whi"),
28217 + NORMAL_MNEMONIC(LD_WVS, LD_WVS, "ld.wvs"),
28218 + NORMAL_MNEMONIC(LD_WVC, LD_WVC, "ld.wvc"),
28219 + NORMAL_MNEMONIC(LD_WQS, LD_WQS, "ld.wqs"),
28220 + NORMAL_MNEMONIC(LD_WAL, LD_WAL, "ld.wal"),
28221 + NORMAL_MNEMONIC(LD_WHS, LD_WHS, "ld.whs"),
28222 + NORMAL_MNEMONIC(LD_WLO, LD_WLO, "ld.wlo"),
28223 + NORMAL_MNEMONIC(LD_SHEQ, LD_SHEQ, "ld.sheq"),
28224 + NORMAL_MNEMONIC(LD_SHNE, LD_SHNE, "ld.shne"),
28225 + NORMAL_MNEMONIC(LD_SHCC, LD_SHCC, "ld.shcc"),
28226 + NORMAL_MNEMONIC(LD_SHCS, LD_SHCS, "ld.shcs"),
28227 + NORMAL_MNEMONIC(LD_SHGE, LD_SHGE, "ld.shge"),
28228 + NORMAL_MNEMONIC(LD_SHLT, LD_SHLT, "ld.shlt"),
28229 + NORMAL_MNEMONIC(LD_SHMI, LD_SHMI, "ld.shmi"),
28230 + NORMAL_MNEMONIC(LD_SHPL, LD_SHPL, "ld.shpl"),
28231 + NORMAL_MNEMONIC(LD_SHLS, LD_SHLS, "ld.shls"),
28232 + NORMAL_MNEMONIC(LD_SHGT, LD_SHGT, "ld.shgt"),
28233 + NORMAL_MNEMONIC(LD_SHLE, LD_SHLE, "ld.shle"),
28234 + NORMAL_MNEMONIC(LD_SHHI, LD_SHHI, "ld.shhi"),
28235 + NORMAL_MNEMONIC(LD_SHVS, LD_SHVS, "ld.shvs"),
28236 + NORMAL_MNEMONIC(LD_SHVC, LD_SHVC, "ld.shvc"),
28237 + NORMAL_MNEMONIC(LD_SHQS, LD_SHQS, "ld.shqs"),
28238 + NORMAL_MNEMONIC(LD_SHAL, LD_SHAL, "ld.shal"),
28239 + NORMAL_MNEMONIC(LD_SHHS, LD_SHHS, "ld.shhs"),
28240 + NORMAL_MNEMONIC(LD_SHLO, LD_SHLO, "ld.shlo"),
28241 + NORMAL_MNEMONIC(LD_UHEQ, LD_UHEQ, "ld.uheq"),
28242 + NORMAL_MNEMONIC(LD_UHNE, LD_UHNE, "ld.uhne"),
28243 + NORMAL_MNEMONIC(LD_UHCC, LD_UHCC, "ld.uhcc"),
28244 + NORMAL_MNEMONIC(LD_UHCS, LD_UHCS, "ld.uhcs"),
28245 + NORMAL_MNEMONIC(LD_UHGE, LD_UHGE, "ld.uhge"),
28246 + NORMAL_MNEMONIC(LD_UHLT, LD_UHLT, "ld.uhlt"),
28247 + NORMAL_MNEMONIC(LD_UHMI, LD_UHMI, "ld.uhmi"),
28248 + NORMAL_MNEMONIC(LD_UHPL, LD_UHPL, "ld.uhpl"),
28249 + NORMAL_MNEMONIC(LD_UHLS, LD_UHLS, "ld.uhls"),
28250 + NORMAL_MNEMONIC(LD_UHGT, LD_UHGT, "ld.uhgt"),
28251 + NORMAL_MNEMONIC(LD_UHLE, LD_UHLE, "ld.uhle"),
28252 + NORMAL_MNEMONIC(LD_UHHI, LD_UHHI, "ld.uhhi"),
28253 + NORMAL_MNEMONIC(LD_UHVS, LD_UHVS, "ld.uhvs"),
28254 + NORMAL_MNEMONIC(LD_UHVC, LD_UHVC, "ld.uhvc"),
28255 + NORMAL_MNEMONIC(LD_UHQS, LD_UHQS, "ld.uhqs"),
28256 + NORMAL_MNEMONIC(LD_UHAL, LD_UHAL, "ld.uhal"),
28257 + NORMAL_MNEMONIC(LD_UHHS, LD_UHHS, "ld.uhhs"),
28258 + NORMAL_MNEMONIC(LD_UHLO, LD_UHLO, "ld.uhlo"),
28259 + NORMAL_MNEMONIC(LD_SBEQ, LD_SBEQ, "ld.sbeq"),
28260 + NORMAL_MNEMONIC(LD_SBNE, LD_SBNE, "ld.sbne"),
28261 + NORMAL_MNEMONIC(LD_SBCC, LD_SBCC, "ld.sbcc"),
28262 + NORMAL_MNEMONIC(LD_SBCS, LD_SBCS, "ld.sbcs"),
28263 + NORMAL_MNEMONIC(LD_SBGE, LD_SBGE, "ld.sbge"),
28264 + NORMAL_MNEMONIC(LD_SBLT, LD_SBLT, "ld.sblt"),
28265 + NORMAL_MNEMONIC(LD_SBMI, LD_SBMI, "ld.sbmi"),
28266 + NORMAL_MNEMONIC(LD_SBPL, LD_SBPL, "ld.sbpl"),
28267 + NORMAL_MNEMONIC(LD_SBLS, LD_SBLS, "ld.sbls"),
28268 + NORMAL_MNEMONIC(LD_SBGT, LD_SBGT, "ld.sbgt"),
28269 + NORMAL_MNEMONIC(LD_SBLE, LD_SBLE, "ld.sble"),
28270 + NORMAL_MNEMONIC(LD_SBHI, LD_SBHI, "ld.sbhi"),
28271 + NORMAL_MNEMONIC(LD_SBVS, LD_SBVS, "ld.sbvs"),
28272 + NORMAL_MNEMONIC(LD_SBVC, LD_SBVC, "ld.sbvc"),
28273 + NORMAL_MNEMONIC(LD_SBQS, LD_SBQS, "ld.sbqs"),
28274 + NORMAL_MNEMONIC(LD_SBAL, LD_SBAL, "ld.sbal"),
28275 + NORMAL_MNEMONIC(LD_SBHS, LD_SBHS, "ld.sbhs"),
28276 + NORMAL_MNEMONIC(LD_SBLO, LD_SBLO, "ld.sblo"),
28277 + NORMAL_MNEMONIC(LD_UBEQ, LD_UBEQ, "ld.ubeq"),
28278 + NORMAL_MNEMONIC(LD_UBNE, LD_UBNE, "ld.ubne"),
28279 + NORMAL_MNEMONIC(LD_UBCC, LD_UBCC, "ld.ubcc"),
28280 + NORMAL_MNEMONIC(LD_UBCS, LD_UBCS, "ld.ubcs"),
28281 + NORMAL_MNEMONIC(LD_UBGE, LD_UBGE, "ld.ubge"),
28282 + NORMAL_MNEMONIC(LD_UBLT, LD_UBLT, "ld.ublt"),
28283 + NORMAL_MNEMONIC(LD_UBMI, LD_UBMI, "ld.ubmi"),
28284 + NORMAL_MNEMONIC(LD_UBPL, LD_UBPL, "ld.ubpl"),
28285 + NORMAL_MNEMONIC(LD_UBLS, LD_UBLS, "ld.ubls"),
28286 + NORMAL_MNEMONIC(LD_UBGT, LD_UBGT, "ld.ubgt"),
28287 + NORMAL_MNEMONIC(LD_UBLE, LD_UBLE, "ld.uble"),
28288 + NORMAL_MNEMONIC(LD_UBHI, LD_UBHI, "ld.ubhi"),
28289 + NORMAL_MNEMONIC(LD_UBVS, LD_UBVS, "ld.ubvs"),
28290 + NORMAL_MNEMONIC(LD_UBVC, LD_UBVC, "ld.ubvc"),
28291 + NORMAL_MNEMONIC(LD_UBQS, LD_UBQS, "ld.ubqs"),
28292 + NORMAL_MNEMONIC(LD_UBAL, LD_UBAL, "ld.ubal"),
28293 + NORMAL_MNEMONIC(LD_UBHS, LD_UBHS, "ld.ubhs"),
28294 + NORMAL_MNEMONIC(LD_UBLO, LD_UBLO, "ld.ublo"),
28295 + NORMAL_MNEMONIC(ST_WEQ, ST_WEQ, "st.weq"),
28296 + NORMAL_MNEMONIC(ST_WNE, ST_WNE, "st.wne"),
28297 + NORMAL_MNEMONIC(ST_WCC, ST_WCC, "st.wcc"),
28298 + NORMAL_MNEMONIC(ST_WCS, ST_WCS, "st.wcs"),
28299 + NORMAL_MNEMONIC(ST_WGE, ST_WGE, "st.wge"),
28300 + NORMAL_MNEMONIC(ST_WLT, ST_WLT, "st.wlt"),
28301 + NORMAL_MNEMONIC(ST_WMI, ST_WMI, "st.wmi"),
28302 + NORMAL_MNEMONIC(ST_WPL, ST_WPL, "st.wpl"),
28303 + NORMAL_MNEMONIC(ST_WLS, ST_WLS, "st.wls"),
28304 + NORMAL_MNEMONIC(ST_WGT, ST_WGT, "st.wgt"),
28305 + NORMAL_MNEMONIC(ST_WLE, ST_WLE, "st.wle"),
28306 + NORMAL_MNEMONIC(ST_WHI, ST_WHI, "st.whi"),
28307 + NORMAL_MNEMONIC(ST_WVS, ST_WVS, "st.wvs"),
28308 + NORMAL_MNEMONIC(ST_WVC, ST_WVC, "st.wvc"),
28309 + NORMAL_MNEMONIC(ST_WQS, ST_WQS, "st.wqs"),
28310 + NORMAL_MNEMONIC(ST_WAL, ST_WAL, "st.wal"),
28311 + NORMAL_MNEMONIC(ST_WHS, ST_WHS, "st.whs"),
28312 + NORMAL_MNEMONIC(ST_WLO, ST_WLO, "st.wlo"),
28313 + NORMAL_MNEMONIC(ST_HEQ, ST_HEQ, "st.heq"),
28314 + NORMAL_MNEMONIC(ST_HNE, ST_HNE, "st.hne"),
28315 + NORMAL_MNEMONIC(ST_HCC, ST_HCC, "st.hcc"),
28316 + NORMAL_MNEMONIC(ST_HCS, ST_HCS, "st.hcs"),
28317 + NORMAL_MNEMONIC(ST_HGE, ST_HGE, "st.hge"),
28318 + NORMAL_MNEMONIC(ST_HLT, ST_HLT, "st.hlt"),
28319 + NORMAL_MNEMONIC(ST_HMI, ST_HMI, "st.hmi"),
28320 + NORMAL_MNEMONIC(ST_HPL, ST_HPL, "st.hpl"),
28321 + NORMAL_MNEMONIC(ST_HLS, ST_HLS, "st.hls"),
28322 + NORMAL_MNEMONIC(ST_HGT, ST_HGT, "st.hgt"),
28323 + NORMAL_MNEMONIC(ST_HLE, ST_HLE, "st.hle"),
28324 + NORMAL_MNEMONIC(ST_HHI, ST_HHI, "st.hhi"),
28325 + NORMAL_MNEMONIC(ST_HVS, ST_HVS, "st.hvs"),
28326 + NORMAL_MNEMONIC(ST_HVC, ST_HVC, "st.hvc"),
28327 + NORMAL_MNEMONIC(ST_HQS, ST_HQS, "st.hqs"),
28328 + NORMAL_MNEMONIC(ST_HAL, ST_HAL, "st.hal"),
28329 + NORMAL_MNEMONIC(ST_HHS, ST_HHS, "st.hhs"),
28330 + NORMAL_MNEMONIC(ST_HLO, ST_HLO, "st.hlo"),
28331 + NORMAL_MNEMONIC(ST_BEQ, ST_BEQ, "st.beq"),
28332 + NORMAL_MNEMONIC(ST_BNE, ST_BNE, "st.bne"),
28333 + NORMAL_MNEMONIC(ST_BCC, ST_BCC, "st.bcc"),
28334 + NORMAL_MNEMONIC(ST_BCS, ST_BCS, "st.bcs"),
28335 + NORMAL_MNEMONIC(ST_BGE, ST_BGE, "st.bge"),
28336 + NORMAL_MNEMONIC(ST_BLT, ST_BLT, "st.blt"),
28337 + NORMAL_MNEMONIC(ST_BMI, ST_BMI, "st.bmi"),
28338 + NORMAL_MNEMONIC(ST_BPL, ST_BPL, "st.bpl"),
28339 + NORMAL_MNEMONIC(ST_BLS, ST_BLS, "st.bls"),
28340 + NORMAL_MNEMONIC(ST_BGT, ST_BGT, "st.bgt"),
28341 + NORMAL_MNEMONIC(ST_BLE, ST_BLE, "st.ble"),
28342 + NORMAL_MNEMONIC(ST_BHI, ST_BHI, "st.bhi"),
28343 + NORMAL_MNEMONIC(ST_BVS, ST_BVS, "st.bvs"),
28344 + NORMAL_MNEMONIC(ST_BVC, ST_BVC, "st.bvc"),
28345 + NORMAL_MNEMONIC(ST_BQS, ST_BQS, "st.bqs"),
28346 + NORMAL_MNEMONIC(ST_BAL, ST_BAL, "st.bal"),
28347 + NORMAL_MNEMONIC(ST_BHS, ST_BHS, "st.bhs"),
28348 + NORMAL_MNEMONIC(ST_BLO, ST_BLO, "st.blo"),
28349 + NORMAL_MNEMONIC(MOVH, MOVH, "movh"),
28352 +#undef NORMAL_MNEMONIC
28353 +#undef ALIAS_MNEMONIC
28354 +#undef FP_MNEMONIC
28356 +++ b/opcodes/avr32-opc.h
28358 +/* Opcode tables for AVR32.
28359 + Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
28361 + Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
28363 + This file is part of libopcodes.
28365 + This program is free software; you can redistribute it and/or
28366 + modify it under the terms of the GNU General Public License as
28367 + published by the Free Software Foundation; either version 2 of the
28368 + License, or (at your option) any later version.
28370 + This program is distributed in the hope that it will be useful, but
28371 + WITHOUT ANY WARRANTY; without even the implied warranty of
28372 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
28373 + General Public License for more details.
28375 + You should have received a copy of the GNU General Public License
28376 + along with this program; if not, write to the Free Software
28377 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
28378 + 02111-1307, USA. */
28382 +#define AVR32_MAX_OPERANDS 8
28383 +#define AVR32_MAX_FIELDS 8
28385 +#define AVR32_V1 (1 << 1)
28386 +#define AVR32_SIMD (1 << 2)
28387 +#define AVR32_DSP (1 << 3)
28388 +#define AVR32_RMW (1 << 4)
28389 +#define AVR32_V2 (1 << 5)
28390 +#define AVR32_V3 (1 << 6)
28391 +#define AVR32_V3FP (1 << 7)
28392 +#define AVR32_PICO (1 << 17)
28394 +/* Registers we commonly refer to */
28395 +#define AVR32_REG_R12 12
28396 +#define AVR32_REG_SP 13
28397 +#define AVR32_REG_LR 14
28398 +#define AVR32_REG_PC 15
28400 +struct avr32_ifield
28403 + unsigned short bitsize;
28404 + unsigned short shift;
28405 + unsigned long mask;
28407 + /* If the value doesn't fit, it will be truncated with no warning */
28408 + void (*insert)(const struct avr32_ifield *, void *, unsigned long);
28409 + void (*extract)(const struct avr32_ifield *, void *, unsigned long *);
28412 +struct avr32_opcode
28416 + unsigned long value;
28417 + unsigned long mask;
28418 + const struct avr32_syntax *syntax;
28419 + bfd_reloc_code_real_type reloc_type;
28420 + unsigned int nr_fields;
28421 + /* if relaxable, which field is variable, otherwise -1 */
28423 + const struct avr32_ifield *fields[AVR32_MAX_FIELDS];
28426 +struct avr32_alias
28429 + const struct avr32_opcode *opc;
28432 + unsigned long value;
28433 + } operand_map[AVR32_MAX_OPERANDS];
28436 +struct avr32_syntax
28439 + unsigned long isa_flags;
28440 + const struct avr32_mnemonic *mnemonic;
28443 + const struct avr32_opcode *opc;
28444 + const struct avr32_alias *alias;
28446 + const struct avr32_syntax *next;
28447 + /* negative means "vararg" */
28449 + int operand[AVR32_MAX_OPERANDS];
28453 +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL)
28454 +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0)
28455 +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL)
28458 +struct avr32_mnemonic
28461 + const char *name;
28462 + const struct avr32_syntax *syntax;
28465 +extern const struct avr32_ifield avr32_ifield_table[];
28466 +extern struct avr32_opcode avr32_opc_table[];
28467 +extern const struct avr32_syntax avr32_syntax_table[];
28468 +extern const struct avr32_alias avr32_alias_table[];
28469 +extern const struct avr32_mnemonic avr32_mnemonic_table[];
28471 +extern void avr32_insert_simple(const struct avr32_ifield *field,
28472 + void *buf, unsigned long value);
28473 +extern void avr32_insert_bit5c(const struct avr32_ifield *field,
28474 + void *buf, unsigned long value);
28475 +extern void avr32_insert_k10(const struct avr32_ifield *field,
28476 + void *buf, unsigned long value);
28477 +extern void avr32_insert_k21(const struct avr32_ifield *field,
28478 + void *buf, unsigned long value);
28479 +extern void avr32_insert_cpop(const struct avr32_ifield *field,
28480 + void *buf, unsigned long value);
28481 +extern void avr32_insert_k12cp(const struct avr32_ifield *field,
28482 + void *buf, unsigned long value);
28484 +extern void avr32_extract_simple(const struct avr32_ifield *field,
28485 + void *buf, unsigned long *value);
28486 +extern void avr32_extract_bit5c(const struct avr32_ifield *field,
28487 + void *buf, unsigned long *value);
28488 +extern void avr32_extract_k10(const struct avr32_ifield *field,
28489 + void *buf, unsigned long *value);
28490 +extern void avr32_extract_k21(const struct avr32_ifield *field,
28491 + void *buf, unsigned long *value);
28492 +extern void avr32_extract_cpop(const struct avr32_ifield *field,
28493 + void *buf, unsigned long *value);
28494 +extern void avr32_extract_k12cp(const struct avr32_ifield *field,
28495 + void *buf, unsigned long *value);
28497 +enum avr32_operand_type
28499 + AVR32_OPERAND_INTREG, /* just a register */
28500 + AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */
28501 + AVR32_OPERAND_INTREG_POSTINC, /* register with post-increment */
28502 + AVR32_OPERAND_INTREG_LSL, /* register with left shift */
28503 + AVR32_OPERAND_INTREG_LSR, /* register with right shift */
28504 + AVR32_OPERAND_INTREG_BSEL, /* register with byte selector */
28505 + AVR32_OPERAND_INTREG_HSEL, /* register with halfword selector */
28506 + AVR32_OPERAND_INTREG_SDISP, /* Rp[signed disp] */
28507 + AVR32_OPERAND_INTREG_SDISP_H, /* Rp[signed hword-aligned disp] */
28508 + AVR32_OPERAND_INTREG_SDISP_W, /* Rp[signed word-aligned disp] */
28509 + AVR32_OPERAND_INTREG_UDISP, /* Rp[unsigned disp] */
28510 + AVR32_OPERAND_INTREG_UDISP_H, /* Rp[unsigned hword-aligned disp] */
28511 + AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */
28512 + AVR32_OPERAND_INTREG_INDEX, /* Rp[Ri << sa] */
28513 + AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */
28514 + AVR32_OPERAND_DWREG, /* Even-numbered register */
28515 + AVR32_OPERAND_PC_UDISP_W, /* PC[unsigned word-aligned disp] or label */
28516 + AVR32_OPERAND_SP, /* Just SP */
28517 + AVR32_OPERAND_SP_UDISP_W, /* SP[unsigned word-aligned disp] */
28518 + AVR32_OPERAND_CPNO,
28519 + AVR32_OPERAND_CPREG,
28520 + AVR32_OPERAND_CPREG_D,
28521 + AVR32_OPERAND_UNSIGNED_CONST,
28522 + AVR32_OPERAND_UNSIGNED_CONST_W,
28523 + AVR32_OPERAND_SIGNED_CONST,
28524 + AVR32_OPERAND_SIGNED_CONST_W,
28525 + AVR32_OPERAND_JMPLABEL,
28526 + AVR32_OPERAND_UNSIGNED_NUMBER,
28527 + AVR32_OPERAND_UNSIGNED_NUMBER_W,
28528 + AVR32_OPERAND_REGLIST8,
28529 + AVR32_OPERAND_REGLIST9,
28530 + AVR32_OPERAND_REGLIST16,
28531 + AVR32_OPERAND_REGLIST_LDM,
28532 + AVR32_OPERAND_REGLIST_CP8,
28533 + AVR32_OPERAND_REGLIST_CPD8,
28534 + AVR32_OPERAND_RETVAL,
28535 + AVR32_OPERAND_MCALL,
28536 + AVR32_OPERAND_JOSPINC,
28537 + AVR32_OPERAND_COH,
28538 + AVR32_OPERAND_PICO_REG_W,
28539 + AVR32_OPERAND_PICO_REG_D,
28540 + AVR32_OPERAND_PICO_REGLIST_W,
28541 + AVR32_OPERAND_PICO_REGLIST_D,
28542 + AVR32_OPERAND_PICO_IN,
28543 + AVR32_OPERAND_PICO_OUT0,
28544 + AVR32_OPERAND_PICO_OUT1,
28545 + AVR32_OPERAND_PICO_OUT2,
28546 + AVR32_OPERAND_PICO_OUT3,
28547 + AVR32_OPERAND__END_
28549 +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_
28550 +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_
28552 +enum avr32_ifield_type
28556 + AVR32_IFIELD_COND4C,
28557 + AVR32_IFIELD_K8C,
28558 + AVR32_IFIELD_K7C,
28559 + AVR32_IFIELD_K5C,
28561 + AVR32_IFIELD_RY_DW,
28562 + AVR32_IFIELD_COND4E,
28563 + AVR32_IFIELD_K8E,
28564 + AVR32_IFIELD_BIT5C,
28565 + AVR32_IFIELD_COND3,
28566 + AVR32_IFIELD_K10,
28567 + AVR32_IFIELD_POPM,
28569 + AVR32_IFIELD_RD_E,
28570 + AVR32_IFIELD_RD_DW,
28575 + AVR32_IFIELD_K5E,
28576 + AVR32_IFIELD_PART2,
28577 + AVR32_IFIELD_PART1,
28578 + AVR32_IFIELD_K16,
28579 + AVR32_IFIELD_CACHEOP,
28580 + AVR32_IFIELD_K11,
28581 + AVR32_IFIELD_K21,
28582 + AVR32_IFIELD_CPOP,
28583 + AVR32_IFIELD_CPNO,
28584 + AVR32_IFIELD_CRD_RI,
28585 + AVR32_IFIELD_CRX,
28586 + AVR32_IFIELD_CRY,
28587 + AVR32_IFIELD_K7E,
28588 + AVR32_IFIELD_CRD_DW,
28589 + AVR32_IFIELD_PART1_K12,
28590 + AVR32_IFIELD_PART2_K12,
28591 + AVR32_IFIELD_K12,
28593 + AVR32_IFIELD_K5E2,
28595 + AVR32_IFIELD_COND4E2,
28596 + AVR32_IFIELD_K8E2,
28598 + AVR32_IFIELD_MEM15,
28599 + AVR32_IFIELD_MEMB5,
28601 + AVR32_IFIELD_CM_HL,
28602 + AVR32_IFIELD_K12CP,
28603 + AVR32_IFIELD_K9E,
28604 + AVR32_IFIELD_FP_RX,
28605 + AVR32_IFIELD_FP_RY,
28606 + AVR32_IFIELD_FP_RD,
28607 + AVR32_IFIELD_FP_RA,
28608 + AVR32_IFIELD__END_,
28610 +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_
28612 +enum avr32_opc_type
28620 + AVR32_OPC_ADDABS,
28621 + AVR32_OPC_ADDHH_W,
28626 + AVR32_OPC_ANDH_COH,
28628 + AVR32_OPC_ANDL_COH,
28658 + AVR32_OPC_BREAKPOINT,
28662 + AVR32_OPC_CASTS_B,
28663 + AVR32_OPC_CASTS_H,
28664 + AVR32_OPC_CASTU_B,
28665 + AVR32_OPC_CASTU_H,
28678 + AVR32_OPC_CSRFCZ,
28688 + AVR32_OPC_INCJOSP,
28694 + AVR32_OPC_LD_SB2,
28695 + AVR32_OPC_LD_SB1,
28696 + AVR32_OPC_LD_UB1,
28697 + AVR32_OPC_LD_UB2,
28698 + AVR32_OPC_LD_UB5,
28699 + AVR32_OPC_LD_UB3,
28700 + AVR32_OPC_LD_UB4,
28701 + AVR32_OPC_LD_SH1,
28702 + AVR32_OPC_LD_SH2,
28703 + AVR32_OPC_LD_SH5,
28704 + AVR32_OPC_LD_SH3,
28705 + AVR32_OPC_LD_SH4,
28706 + AVR32_OPC_LD_UH1,
28707 + AVR32_OPC_LD_UH2,
28708 + AVR32_OPC_LD_UH5,
28709 + AVR32_OPC_LD_UH3,
28710 + AVR32_OPC_LD_UH4,
28717 + AVR32_OPC_LDC_D1,
28718 + AVR32_OPC_LDC_D2,
28719 + AVR32_OPC_LDC_D3,
28720 + AVR32_OPC_LDC_W1,
28721 + AVR32_OPC_LDC_W2,
28722 + AVR32_OPC_LDC_W3,
28723 + AVR32_OPC_LDC0_D,
28724 + AVR32_OPC_LDC0_W,
28725 + AVR32_OPC_LDCM_D,
28726 + AVR32_OPC_LDCM_D_PU,
28727 + AVR32_OPC_LDCM_W,
28728 + AVR32_OPC_LDCM_W_PU,
28730 + AVR32_OPC_LDDPC_EXT,
28732 + AVR32_OPC_LDINS_B,
28733 + AVR32_OPC_LDINS_H,
28736 + AVR32_OPC_LDMTS_PU,
28737 + AVR32_OPC_LDSWP_SH,
28738 + AVR32_OPC_LDSWP_UH,
28739 + AVR32_OPC_LDSWP_W,
28747 + AVR32_OPC_MACHH_D,
28748 + AVR32_OPC_MACHH_W,
28749 + AVR32_OPC_MACS_D,
28750 + AVR32_OPC_MACSATHH_W,
28752 + AVR32_OPC_MACWH_D,
28761 + AVR32_OPC_MOVEQ1,
28762 + AVR32_OPC_MOVNE1,
28763 + AVR32_OPC_MOVCC1,
28764 + AVR32_OPC_MOVCS1,
28765 + AVR32_OPC_MOVGE1,
28766 + AVR32_OPC_MOVLT1,
28767 + AVR32_OPC_MOVMI1,
28768 + AVR32_OPC_MOVPL1,
28769 + AVR32_OPC_MOVLS1,
28770 + AVR32_OPC_MOVGT1,
28771 + AVR32_OPC_MOVLE1,
28772 + AVR32_OPC_MOVHI1,
28773 + AVR32_OPC_MOVVS1,
28774 + AVR32_OPC_MOVVC1,
28775 + AVR32_OPC_MOVQS1,
28776 + AVR32_OPC_MOVAL1,
28777 + AVR32_OPC_MOVEQ2,
28778 + AVR32_OPC_MOVNE2,
28779 + AVR32_OPC_MOVCC2,
28780 + AVR32_OPC_MOVCS2,
28781 + AVR32_OPC_MOVGE2,
28782 + AVR32_OPC_MOVLT2,
28783 + AVR32_OPC_MOVMI2,
28784 + AVR32_OPC_MOVPL2,
28785 + AVR32_OPC_MOVLS2,
28786 + AVR32_OPC_MOVGT2,
28787 + AVR32_OPC_MOVLE2,
28788 + AVR32_OPC_MOVHI2,
28789 + AVR32_OPC_MOVVS2,
28790 + AVR32_OPC_MOVVC2,
28791 + AVR32_OPC_MOVQS2,
28792 + AVR32_OPC_MOVAL2,
28798 + AVR32_OPC_MULHH_W,
28799 + AVR32_OPC_MULNHH_W,
28800 + AVR32_OPC_MULNWH_D,
28802 + AVR32_OPC_MULSATHH_H,
28803 + AVR32_OPC_MULSATHH_W,
28804 + AVR32_OPC_MULSATRNDHH_H,
28805 + AVR32_OPC_MULSATRNDWH_W,
28806 + AVR32_OPC_MULSATWH_W,
28807 + AVR32_OPC_MULU_D,
28808 + AVR32_OPC_MULWH_D,
28811 + AVR32_OPC_MVCR_D,
28812 + AVR32_OPC_MVCR_W,
28813 + AVR32_OPC_MVRC_D,
28814 + AVR32_OPC_MVRC_W,
28822 + AVR32_OPC_PABS_SB,
28823 + AVR32_OPC_PABS_SH,
28824 + AVR32_OPC_PACKSH_SB,
28825 + AVR32_OPC_PACKSH_UB,
28826 + AVR32_OPC_PACKW_SH,
28827 + AVR32_OPC_PADD_B,
28828 + AVR32_OPC_PADD_H,
28829 + AVR32_OPC_PADDH_SH,
28830 + AVR32_OPC_PADDH_UB,
28831 + AVR32_OPC_PADDS_SB,
28832 + AVR32_OPC_PADDS_SH,
28833 + AVR32_OPC_PADDS_UB,
28834 + AVR32_OPC_PADDS_UH,
28835 + AVR32_OPC_PADDSUB_H,
28836 + AVR32_OPC_PADDSUBH_SH,
28837 + AVR32_OPC_PADDSUBS_SH,
28838 + AVR32_OPC_PADDSUBS_UH,
28839 + AVR32_OPC_PADDX_H,
28840 + AVR32_OPC_PADDXH_SH,
28841 + AVR32_OPC_PADDXS_SH,
28842 + AVR32_OPC_PADDXS_UH,
28843 + AVR32_OPC_PASR_B,
28844 + AVR32_OPC_PASR_H,
28845 + AVR32_OPC_PAVG_SH,
28846 + AVR32_OPC_PAVG_UB,
28847 + AVR32_OPC_PLSL_B,
28848 + AVR32_OPC_PLSL_H,
28849 + AVR32_OPC_PLSR_B,
28850 + AVR32_OPC_PLSR_H,
28851 + AVR32_OPC_PMAX_SH,
28852 + AVR32_OPC_PMAX_UB,
28853 + AVR32_OPC_PMIN_SH,
28854 + AVR32_OPC_PMIN_UB,
28857 + AVR32_OPC_POPM_E,
28860 + AVR32_OPC_PSUB_B,
28861 + AVR32_OPC_PSUB_H,
28862 + AVR32_OPC_PSUBADD_H,
28863 + AVR32_OPC_PSUBADDH_SH,
28864 + AVR32_OPC_PSUBADDS_SH,
28865 + AVR32_OPC_PSUBADDS_UH,
28866 + AVR32_OPC_PSUBH_SH,
28867 + AVR32_OPC_PSUBH_UB,
28868 + AVR32_OPC_PSUBS_SB,
28869 + AVR32_OPC_PSUBS_SH,
28870 + AVR32_OPC_PSUBS_UB,
28871 + AVR32_OPC_PSUBS_UH,
28872 + AVR32_OPC_PSUBX_H,
28873 + AVR32_OPC_PSUBXH_SH,
28874 + AVR32_OPC_PSUBXS_SH,
28875 + AVR32_OPC_PSUBXS_UH,
28876 + AVR32_OPC_PUNPCKSB_H,
28877 + AVR32_OPC_PUNPCKUB_H,
28878 + AVR32_OPC_PUSHJC,
28880 + AVR32_OPC_PUSHM_E,
28881 + AVR32_OPC_RCALL1,
28882 + AVR32_OPC_RCALL2,
28908 + AVR32_OPC_SATADD_H,
28909 + AVR32_OPC_SATADD_W,
28910 + AVR32_OPC_SATRNDS,
28911 + AVR32_OPC_SATRNDU,
28913 + AVR32_OPC_SATSUB_H,
28914 + AVR32_OPC_SATSUB_W1,
28915 + AVR32_OPC_SATSUB_W2,
28959 + AVR32_OPC_STC_D1,
28960 + AVR32_OPC_STC_D2,
28961 + AVR32_OPC_STC_D3,
28962 + AVR32_OPC_STC_W1,
28963 + AVR32_OPC_STC_W2,
28964 + AVR32_OPC_STC_W3,
28965 + AVR32_OPC_STC0_D,
28966 + AVR32_OPC_STC0_W,
28967 + AVR32_OPC_STCM_D,
28968 + AVR32_OPC_STCM_D_PU,
28969 + AVR32_OPC_STCM_W,
28970 + AVR32_OPC_STCM_W_PU,
28971 + AVR32_OPC_STCOND,
28973 + AVR32_OPC_STHH_W2,
28974 + AVR32_OPC_STHH_W1,
28976 + AVR32_OPC_STM_PU,
28978 + AVR32_OPC_STMTS_PU,
28979 + AVR32_OPC_STSWP_H,
28980 + AVR32_OPC_STSWP_W,
28984 + AVR32_OPC_SUB3_SP,
29003 + AVR32_OPC_SUBFEQ,
29004 + AVR32_OPC_SUBFNE,
29005 + AVR32_OPC_SUBFCC,
29006 + AVR32_OPC_SUBFCS,
29007 + AVR32_OPC_SUBFGE,
29008 + AVR32_OPC_SUBFLT,
29009 + AVR32_OPC_SUBFMI,
29010 + AVR32_OPC_SUBFPL,
29011 + AVR32_OPC_SUBFLS,
29012 + AVR32_OPC_SUBFGT,
29013 + AVR32_OPC_SUBFLE,
29014 + AVR32_OPC_SUBFHI,
29015 + AVR32_OPC_SUBFVS,
29016 + AVR32_OPC_SUBFVC,
29017 + AVR32_OPC_SUBFQS,
29018 + AVR32_OPC_SUBFAL,
29019 + AVR32_OPC_SUBHH_W,
29020 + AVR32_OPC_SWAP_B,
29021 + AVR32_OPC_SWAP_BH,
29022 + AVR32_OPC_SWAP_H,
29033 + AVR32_OPC_BFEXTS,
29034 + AVR32_OPC_BFEXTU,
29036 + AVR32_OPC_RSUBEQ,
29037 + AVR32_OPC_RSUBNE,
29038 + AVR32_OPC_RSUBCC,
29039 + AVR32_OPC_RSUBCS,
29040 + AVR32_OPC_RSUBGE,
29041 + AVR32_OPC_RSUBLT,
29042 + AVR32_OPC_RSUBMI,
29043 + AVR32_OPC_RSUBPL,
29044 + AVR32_OPC_RSUBLS,
29045 + AVR32_OPC_RSUBGT,
29046 + AVR32_OPC_RSUBLE,
29047 + AVR32_OPC_RSUBHI,
29048 + AVR32_OPC_RSUBVS,
29049 + AVR32_OPC_RSUBVC,
29050 + AVR32_OPC_RSUBQS,
29051 + AVR32_OPC_RSUBAL,
29068 + AVR32_OPC_SUB2EQ,
29069 + AVR32_OPC_SUB2NE,
29070 + AVR32_OPC_SUB2CC,
29071 + AVR32_OPC_SUB2CS,
29072 + AVR32_OPC_SUB2GE,
29073 + AVR32_OPC_SUB2LT,
29074 + AVR32_OPC_SUB2MI,
29075 + AVR32_OPC_SUB2PL,
29076 + AVR32_OPC_SUB2LS,
29077 + AVR32_OPC_SUB2GT,
29078 + AVR32_OPC_SUB2LE,
29079 + AVR32_OPC_SUB2HI,
29080 + AVR32_OPC_SUB2VS,
29081 + AVR32_OPC_SUB2VC,
29082 + AVR32_OPC_SUB2QS,
29083 + AVR32_OPC_SUB2AL,
29132 + AVR32_OPC_LD_WEQ,
29133 + AVR32_OPC_LD_WNE,
29134 + AVR32_OPC_LD_WCC,
29135 + AVR32_OPC_LD_WCS,
29136 + AVR32_OPC_LD_WGE,
29137 + AVR32_OPC_LD_WLT,
29138 + AVR32_OPC_LD_WMI,
29139 + AVR32_OPC_LD_WPL,
29140 + AVR32_OPC_LD_WLS,
29141 + AVR32_OPC_LD_WGT,
29142 + AVR32_OPC_LD_WLE,
29143 + AVR32_OPC_LD_WHI,
29144 + AVR32_OPC_LD_WVS,
29145 + AVR32_OPC_LD_WVC,
29146 + AVR32_OPC_LD_WQS,
29147 + AVR32_OPC_LD_WAL,
29148 + AVR32_OPC_LD_SHEQ,
29149 + AVR32_OPC_LD_SHNE,
29150 + AVR32_OPC_LD_SHCC,
29151 + AVR32_OPC_LD_SHCS,
29152 + AVR32_OPC_LD_SHGE,
29153 + AVR32_OPC_LD_SHLT,
29154 + AVR32_OPC_LD_SHMI,
29155 + AVR32_OPC_LD_SHPL,
29156 + AVR32_OPC_LD_SHLS,
29157 + AVR32_OPC_LD_SHGT,
29158 + AVR32_OPC_LD_SHLE,
29159 + AVR32_OPC_LD_SHHI,
29160 + AVR32_OPC_LD_SHVS,
29161 + AVR32_OPC_LD_SHVC,
29162 + AVR32_OPC_LD_SHQS,
29163 + AVR32_OPC_LD_SHAL,
29164 + AVR32_OPC_LD_UHEQ,
29165 + AVR32_OPC_LD_UHNE,
29166 + AVR32_OPC_LD_UHCC,
29167 + AVR32_OPC_LD_UHCS,
29168 + AVR32_OPC_LD_UHGE,
29169 + AVR32_OPC_LD_UHLT,
29170 + AVR32_OPC_LD_UHMI,
29171 + AVR32_OPC_LD_UHPL,
29172 + AVR32_OPC_LD_UHLS,
29173 + AVR32_OPC_LD_UHGT,
29174 + AVR32_OPC_LD_UHLE,
29175 + AVR32_OPC_LD_UHHI,
29176 + AVR32_OPC_LD_UHVS,
29177 + AVR32_OPC_LD_UHVC,
29178 + AVR32_OPC_LD_UHQS,
29179 + AVR32_OPC_LD_UHAL,
29180 + AVR32_OPC_LD_SBEQ,
29181 + AVR32_OPC_LD_SBNE,
29182 + AVR32_OPC_LD_SBCC,
29183 + AVR32_OPC_LD_SBCS,
29184 + AVR32_OPC_LD_SBGE,
29185 + AVR32_OPC_LD_SBLT,
29186 + AVR32_OPC_LD_SBMI,
29187 + AVR32_OPC_LD_SBPL,
29188 + AVR32_OPC_LD_SBLS,
29189 + AVR32_OPC_LD_SBGT,
29190 + AVR32_OPC_LD_SBLE,
29191 + AVR32_OPC_LD_SBHI,
29192 + AVR32_OPC_LD_SBVS,
29193 + AVR32_OPC_LD_SBVC,
29194 + AVR32_OPC_LD_SBQS,
29195 + AVR32_OPC_LD_SBAL,
29196 + AVR32_OPC_LD_UBEQ,
29197 + AVR32_OPC_LD_UBNE,
29198 + AVR32_OPC_LD_UBCC,
29199 + AVR32_OPC_LD_UBCS,
29200 + AVR32_OPC_LD_UBGE,
29201 + AVR32_OPC_LD_UBLT,
29202 + AVR32_OPC_LD_UBMI,
29203 + AVR32_OPC_LD_UBPL,
29204 + AVR32_OPC_LD_UBLS,
29205 + AVR32_OPC_LD_UBGT,
29206 + AVR32_OPC_LD_UBLE,
29207 + AVR32_OPC_LD_UBHI,
29208 + AVR32_OPC_LD_UBVS,
29209 + AVR32_OPC_LD_UBVC,
29210 + AVR32_OPC_LD_UBQS,
29211 + AVR32_OPC_LD_UBAL,
29212 + AVR32_OPC_ST_WEQ,
29213 + AVR32_OPC_ST_WNE,
29214 + AVR32_OPC_ST_WCC,
29215 + AVR32_OPC_ST_WCS,
29216 + AVR32_OPC_ST_WGE,
29217 + AVR32_OPC_ST_WLT,
29218 + AVR32_OPC_ST_WMI,
29219 + AVR32_OPC_ST_WPL,
29220 + AVR32_OPC_ST_WLS,
29221 + AVR32_OPC_ST_WGT,
29222 + AVR32_OPC_ST_WLE,
29223 + AVR32_OPC_ST_WHI,
29224 + AVR32_OPC_ST_WVS,
29225 + AVR32_OPC_ST_WVC,
29226 + AVR32_OPC_ST_WQS,
29227 + AVR32_OPC_ST_WAL,
29228 + AVR32_OPC_ST_HEQ,
29229 + AVR32_OPC_ST_HNE,
29230 + AVR32_OPC_ST_HCC,
29231 + AVR32_OPC_ST_HCS,
29232 + AVR32_OPC_ST_HGE,
29233 + AVR32_OPC_ST_HLT,
29234 + AVR32_OPC_ST_HMI,
29235 + AVR32_OPC_ST_HPL,
29236 + AVR32_OPC_ST_HLS,
29237 + AVR32_OPC_ST_HGT,
29238 + AVR32_OPC_ST_HLE,
29239 + AVR32_OPC_ST_HHI,
29240 + AVR32_OPC_ST_HVS,
29241 + AVR32_OPC_ST_HVC,
29242 + AVR32_OPC_ST_HQS,
29243 + AVR32_OPC_ST_HAL,
29244 + AVR32_OPC_ST_BEQ,
29245 + AVR32_OPC_ST_BNE,
29246 + AVR32_OPC_ST_BCC,
29247 + AVR32_OPC_ST_BCS,
29248 + AVR32_OPC_ST_BGE,
29249 + AVR32_OPC_ST_BLT,
29250 + AVR32_OPC_ST_BMI,
29251 + AVR32_OPC_ST_BPL,
29252 + AVR32_OPC_ST_BLS,
29253 + AVR32_OPC_ST_BGT,
29254 + AVR32_OPC_ST_BLE,
29255 + AVR32_OPC_ST_BHI,
29256 + AVR32_OPC_ST_BVS,
29257 + AVR32_OPC_ST_BVC,
29258 + AVR32_OPC_ST_BQS,
29259 + AVR32_OPC_ST_BAL,
29261 + AVR32_OPC_SSCALL,
29263 + AVR32_OPC_FMAC_S,
29264 + AVR32_OPC_FNMAC_S,
29265 + AVR32_OPC_FMSC_S,
29266 + AVR32_OPC_FNMSC_S,
29267 + AVR32_OPC_FMUL_S,
29268 + AVR32_OPC_FNMUL_S,
29269 + AVR32_OPC_FADD_S,
29270 + AVR32_OPC_FSUB_S,
29271 + AVR32_OPC_FCASTRS_SW,
29272 + AVR32_OPC_FCASTRS_UW,
29273 + AVR32_OPC_FCASTSW_S,
29274 + AVR32_OPC_FCASTUW_S,
29275 + AVR32_OPC_FCMP_S,
29276 + AVR32_OPC_FCHK_S,
29277 + AVR32_OPC_FRCPA_S,
29278 + AVR32_OPC_FRSQRTA_S,
29281 +#define AVR32_NR_OPCODES AVR32_OPC__END_
29283 +enum avr32_syntax_type
29285 + AVR32_SYNTAX_ABS,
29286 + AVR32_SYNTAX_ACALL,
29287 + AVR32_SYNTAX_ACR,
29288 + AVR32_SYNTAX_ADC,
29289 + AVR32_SYNTAX_ADD1,
29290 + AVR32_SYNTAX_ADD2,
29291 + AVR32_SYNTAX_ADDABS,
29292 + AVR32_SYNTAX_ADDHH_W,
29293 + AVR32_SYNTAX_AND1,
29294 + AVR32_SYNTAX_AND2,
29295 + AVR32_SYNTAX_AND3,
29296 + AVR32_SYNTAX_ANDH,
29297 + AVR32_SYNTAX_ANDH_COH,
29298 + AVR32_SYNTAX_ANDL,
29299 + AVR32_SYNTAX_ANDL_COH,
29300 + AVR32_SYNTAX_ANDN,
29301 + AVR32_SYNTAX_ASR1,
29302 + AVR32_SYNTAX_ASR3,
29303 + AVR32_SYNTAX_ASR2,
29304 + AVR32_SYNTAX_BFEXTS,
29305 + AVR32_SYNTAX_BFEXTU,
29306 + AVR32_SYNTAX_BFINS,
29307 + AVR32_SYNTAX_BLD,
29308 + AVR32_SYNTAX_BREQ1,
29309 + AVR32_SYNTAX_BRNE1,
29310 + AVR32_SYNTAX_BRCC1,
29311 + AVR32_SYNTAX_BRCS1,
29312 + AVR32_SYNTAX_BRGE1,
29313 + AVR32_SYNTAX_BRLT1,
29314 + AVR32_SYNTAX_BRMI1,
29315 + AVR32_SYNTAX_BRPL1,
29316 + AVR32_SYNTAX_BRHS1,
29317 + AVR32_SYNTAX_BRLO1,
29318 + AVR32_SYNTAX_BREQ2,
29319 + AVR32_SYNTAX_BRNE2,
29320 + AVR32_SYNTAX_BRCC2,
29321 + AVR32_SYNTAX_BRCS2,
29322 + AVR32_SYNTAX_BRGE2,
29323 + AVR32_SYNTAX_BRLT2,
29324 + AVR32_SYNTAX_BRMI2,
29325 + AVR32_SYNTAX_BRPL2,
29326 + AVR32_SYNTAX_BRLS,
29327 + AVR32_SYNTAX_BRGT,
29328 + AVR32_SYNTAX_BRLE,
29329 + AVR32_SYNTAX_BRHI,
29330 + AVR32_SYNTAX_BRVS,
29331 + AVR32_SYNTAX_BRVC,
29332 + AVR32_SYNTAX_BRQS,
29333 + AVR32_SYNTAX_BRAL,
29334 + AVR32_SYNTAX_BRHS2,
29335 + AVR32_SYNTAX_BRLO2,
29336 + AVR32_SYNTAX_BREAKPOINT,
29337 + AVR32_SYNTAX_BREV,
29338 + AVR32_SYNTAX_BST,
29339 + AVR32_SYNTAX_CACHE,
29340 + AVR32_SYNTAX_CASTS_B,
29341 + AVR32_SYNTAX_CASTS_H,
29342 + AVR32_SYNTAX_CASTU_B,
29343 + AVR32_SYNTAX_CASTU_H,
29344 + AVR32_SYNTAX_CBR,
29345 + AVR32_SYNTAX_CLZ,
29346 + AVR32_SYNTAX_COM,
29347 + AVR32_SYNTAX_COP,
29348 + AVR32_SYNTAX_CP_B,
29349 + AVR32_SYNTAX_CP_H,
29350 + AVR32_SYNTAX_CP_W1,
29351 + AVR32_SYNTAX_CP_W2,
29352 + AVR32_SYNTAX_CP_W3,
29353 + AVR32_SYNTAX_CPC1,
29354 + AVR32_SYNTAX_CPC2,
29355 + AVR32_SYNTAX_CSRF,
29356 + AVR32_SYNTAX_CSRFCZ,
29357 + AVR32_SYNTAX_DIVS,
29358 + AVR32_SYNTAX_DIVU,
29359 + AVR32_SYNTAX_EOR1,
29360 + AVR32_SYNTAX_EOR2,
29361 + AVR32_SYNTAX_EOR3,
29362 + AVR32_SYNTAX_EORL,
29363 + AVR32_SYNTAX_EORH,
29364 + AVR32_SYNTAX_FRS,
29365 + AVR32_SYNTAX_SSCALL,
29366 + AVR32_SYNTAX_RETSS,
29367 + AVR32_SYNTAX_ICALL,
29368 + AVR32_SYNTAX_INCJOSP,
29369 + AVR32_SYNTAX_LD_D1,
29370 + AVR32_SYNTAX_LD_D2,
29371 + AVR32_SYNTAX_LD_D3,
29372 + AVR32_SYNTAX_LD_D5,
29373 + AVR32_SYNTAX_LD_D4,
29374 + AVR32_SYNTAX_LD_SB2,
29375 + AVR32_SYNTAX_LD_SB1,
29376 + AVR32_SYNTAX_LD_UB1,
29377 + AVR32_SYNTAX_LD_UB2,
29378 + AVR32_SYNTAX_LD_UB5,
29379 + AVR32_SYNTAX_LD_UB3,
29380 + AVR32_SYNTAX_LD_UB4,
29381 + AVR32_SYNTAX_LD_SH1,
29382 + AVR32_SYNTAX_LD_SH2,
29383 + AVR32_SYNTAX_LD_SH5,
29384 + AVR32_SYNTAX_LD_SH3,
29385 + AVR32_SYNTAX_LD_SH4,
29386 + AVR32_SYNTAX_LD_UH1,
29387 + AVR32_SYNTAX_LD_UH2,
29388 + AVR32_SYNTAX_LD_UH5,
29389 + AVR32_SYNTAX_LD_UH3,
29390 + AVR32_SYNTAX_LD_UH4,
29391 + AVR32_SYNTAX_LD_W1,
29392 + AVR32_SYNTAX_LD_W2,
29393 + AVR32_SYNTAX_LD_W5,
29394 + AVR32_SYNTAX_LD_W6,
29395 + AVR32_SYNTAX_LD_W3,
29396 + AVR32_SYNTAX_LD_W4,
29397 + AVR32_SYNTAX_LDC_D1,
29398 + AVR32_SYNTAX_LDC_D2,
29399 + AVR32_SYNTAX_LDC_D3,
29400 + AVR32_SYNTAX_LDC_W1,
29401 + AVR32_SYNTAX_LDC_W2,
29402 + AVR32_SYNTAX_LDC_W3,
29403 + AVR32_SYNTAX_LDC0_D,
29404 + AVR32_SYNTAX_LDC0_W,
29405 + AVR32_SYNTAX_LDCM_D,
29406 + AVR32_SYNTAX_LDCM_D_PU,
29407 + AVR32_SYNTAX_LDCM_W,
29408 + AVR32_SYNTAX_LDCM_W_PU,
29409 + AVR32_SYNTAX_LDDPC,
29410 + AVR32_SYNTAX_LDDPC_EXT,
29411 + AVR32_SYNTAX_LDDSP,
29412 + AVR32_SYNTAX_LDINS_B,
29413 + AVR32_SYNTAX_LDINS_H,
29414 + AVR32_SYNTAX_LDM,
29415 + AVR32_SYNTAX_LDMTS,
29416 + AVR32_SYNTAX_LDMTS_PU,
29417 + AVR32_SYNTAX_LDSWP_SH,
29418 + AVR32_SYNTAX_LDSWP_UH,
29419 + AVR32_SYNTAX_LDSWP_W,
29420 + AVR32_SYNTAX_LSL1,
29421 + AVR32_SYNTAX_LSL3,
29422 + AVR32_SYNTAX_LSL2,
29423 + AVR32_SYNTAX_LSR1,
29424 + AVR32_SYNTAX_LSR3,
29425 + AVR32_SYNTAX_LSR2,
29426 + AVR32_SYNTAX_MAC,
29427 + AVR32_SYNTAX_MACHH_D,
29428 + AVR32_SYNTAX_MACHH_W,
29429 + AVR32_SYNTAX_MACS_D,
29430 + AVR32_SYNTAX_MACSATHH_W,
29431 + AVR32_SYNTAX_MACUD,
29432 + AVR32_SYNTAX_MACWH_D,
29433 + AVR32_SYNTAX_MAX,
29434 + AVR32_SYNTAX_MCALL,
29435 + AVR32_SYNTAX_MFDR,
29436 + AVR32_SYNTAX_MFSR,
29437 + AVR32_SYNTAX_MIN,
29438 + AVR32_SYNTAX_MOV3,
29439 + AVR32_SYNTAX_MOV1,
29440 + AVR32_SYNTAX_MOV2,
29441 + AVR32_SYNTAX_MOVEQ1,
29442 + AVR32_SYNTAX_MOVNE1,
29443 + AVR32_SYNTAX_MOVCC1,
29444 + AVR32_SYNTAX_MOVCS1,
29445 + AVR32_SYNTAX_MOVGE1,
29446 + AVR32_SYNTAX_MOVLT1,
29447 + AVR32_SYNTAX_MOVMI1,
29448 + AVR32_SYNTAX_MOVPL1,
29449 + AVR32_SYNTAX_MOVLS1,
29450 + AVR32_SYNTAX_MOVGT1,
29451 + AVR32_SYNTAX_MOVLE1,
29452 + AVR32_SYNTAX_MOVHI1,
29453 + AVR32_SYNTAX_MOVVS1,
29454 + AVR32_SYNTAX_MOVVC1,
29455 + AVR32_SYNTAX_MOVQS1,
29456 + AVR32_SYNTAX_MOVAL1,
29457 + AVR32_SYNTAX_MOVHS1,
29458 + AVR32_SYNTAX_MOVLO1,
29459 + AVR32_SYNTAX_MOVEQ2,
29460 + AVR32_SYNTAX_MOVNE2,
29461 + AVR32_SYNTAX_MOVCC2,
29462 + AVR32_SYNTAX_MOVCS2,
29463 + AVR32_SYNTAX_MOVGE2,
29464 + AVR32_SYNTAX_MOVLT2,
29465 + AVR32_SYNTAX_MOVMI2,
29466 + AVR32_SYNTAX_MOVPL2,
29467 + AVR32_SYNTAX_MOVLS2,
29468 + AVR32_SYNTAX_MOVGT2,
29469 + AVR32_SYNTAX_MOVLE2,
29470 + AVR32_SYNTAX_MOVHI2,
29471 + AVR32_SYNTAX_MOVVS2,
29472 + AVR32_SYNTAX_MOVVC2,
29473 + AVR32_SYNTAX_MOVQS2,
29474 + AVR32_SYNTAX_MOVAL2,
29475 + AVR32_SYNTAX_MOVHS2,
29476 + AVR32_SYNTAX_MOVLO2,
29477 + AVR32_SYNTAX_MTDR,
29478 + AVR32_SYNTAX_MTSR,
29479 + AVR32_SYNTAX_MUL1,
29480 + AVR32_SYNTAX_MUL2,
29481 + AVR32_SYNTAX_MUL3,
29482 + AVR32_SYNTAX_MULHH_W,
29483 + AVR32_SYNTAX_MULNHH_W,
29484 + AVR32_SYNTAX_MULNWH_D,
29485 + AVR32_SYNTAX_MULSD,
29486 + AVR32_SYNTAX_MULSATHH_H,
29487 + AVR32_SYNTAX_MULSATHH_W,
29488 + AVR32_SYNTAX_MULSATRNDHH_H,
29489 + AVR32_SYNTAX_MULSATRNDWH_W,
29490 + AVR32_SYNTAX_MULSATWH_W,
29491 + AVR32_SYNTAX_MULU_D,
29492 + AVR32_SYNTAX_MULWH_D,
29493 + AVR32_SYNTAX_MUSFR,
29494 + AVR32_SYNTAX_MUSTR,
29495 + AVR32_SYNTAX_MVCR_D,
29496 + AVR32_SYNTAX_MVCR_W,
29497 + AVR32_SYNTAX_MVRC_D,
29498 + AVR32_SYNTAX_MVRC_W,
29499 + AVR32_SYNTAX_NEG,
29500 + AVR32_SYNTAX_NOP,
29501 + AVR32_SYNTAX_OR1,
29502 + AVR32_SYNTAX_OR2,
29503 + AVR32_SYNTAX_OR3,
29504 + AVR32_SYNTAX_ORH,
29505 + AVR32_SYNTAX_ORL,
29506 + AVR32_SYNTAX_PABS_SB,
29507 + AVR32_SYNTAX_PABS_SH,
29508 + AVR32_SYNTAX_PACKSH_SB,
29509 + AVR32_SYNTAX_PACKSH_UB,
29510 + AVR32_SYNTAX_PACKW_SH,
29511 + AVR32_SYNTAX_PADD_B,
29512 + AVR32_SYNTAX_PADD_H,
29513 + AVR32_SYNTAX_PADDH_SH,
29514 + AVR32_SYNTAX_PADDH_UB,
29515 + AVR32_SYNTAX_PADDS_SB,
29516 + AVR32_SYNTAX_PADDS_SH,
29517 + AVR32_SYNTAX_PADDS_UB,
29518 + AVR32_SYNTAX_PADDS_UH,
29519 + AVR32_SYNTAX_PADDSUB_H,
29520 + AVR32_SYNTAX_PADDSUBH_SH,
29521 + AVR32_SYNTAX_PADDSUBS_SH,
29522 + AVR32_SYNTAX_PADDSUBS_UH,
29523 + AVR32_SYNTAX_PADDX_H,
29524 + AVR32_SYNTAX_PADDXH_SH,
29525 + AVR32_SYNTAX_PADDXS_SH,
29526 + AVR32_SYNTAX_PADDXS_UH,
29527 + AVR32_SYNTAX_PASR_B,
29528 + AVR32_SYNTAX_PASR_H,
29529 + AVR32_SYNTAX_PAVG_SH,
29530 + AVR32_SYNTAX_PAVG_UB,
29531 + AVR32_SYNTAX_PLSL_B,
29532 + AVR32_SYNTAX_PLSL_H,
29533 + AVR32_SYNTAX_PLSR_B,
29534 + AVR32_SYNTAX_PLSR_H,
29535 + AVR32_SYNTAX_PMAX_SH,
29536 + AVR32_SYNTAX_PMAX_UB,
29537 + AVR32_SYNTAX_PMIN_SH,
29538 + AVR32_SYNTAX_PMIN_UB,
29539 + AVR32_SYNTAX_POPJC,
29540 + AVR32_SYNTAX_POPM,
29541 + AVR32_SYNTAX_POPM_E,
29542 + AVR32_SYNTAX_PREF,
29543 + AVR32_SYNTAX_PSAD,
29544 + AVR32_SYNTAX_PSUB_B,
29545 + AVR32_SYNTAX_PSUB_H,
29546 + AVR32_SYNTAX_PSUBADD_H,
29547 + AVR32_SYNTAX_PSUBADDH_SH,
29548 + AVR32_SYNTAX_PSUBADDS_SH,
29549 + AVR32_SYNTAX_PSUBADDS_UH,
29550 + AVR32_SYNTAX_PSUBH_SH,
29551 + AVR32_SYNTAX_PSUBH_UB,
29552 + AVR32_SYNTAX_PSUBS_SB,
29553 + AVR32_SYNTAX_PSUBS_SH,
29554 + AVR32_SYNTAX_PSUBS_UB,
29555 + AVR32_SYNTAX_PSUBS_UH,
29556 + AVR32_SYNTAX_PSUBX_H,
29557 + AVR32_SYNTAX_PSUBXH_SH,
29558 + AVR32_SYNTAX_PSUBXS_SH,
29559 + AVR32_SYNTAX_PSUBXS_UH,
29560 + AVR32_SYNTAX_PUNPCKSB_H,
29561 + AVR32_SYNTAX_PUNPCKUB_H,
29562 + AVR32_SYNTAX_PUSHJC,
29563 + AVR32_SYNTAX_PUSHM,
29564 + AVR32_SYNTAX_PUSHM_E,
29565 + AVR32_SYNTAX_RCALL1,
29566 + AVR32_SYNTAX_RCALL2,
29567 + AVR32_SYNTAX_RETEQ,
29568 + AVR32_SYNTAX_RETNE,
29569 + AVR32_SYNTAX_RETCC,
29570 + AVR32_SYNTAX_RETCS,
29571 + AVR32_SYNTAX_RETGE,
29572 + AVR32_SYNTAX_RETLT,
29573 + AVR32_SYNTAX_RETMI,
29574 + AVR32_SYNTAX_RETPL,
29575 + AVR32_SYNTAX_RETLS,
29576 + AVR32_SYNTAX_RETGT,
29577 + AVR32_SYNTAX_RETLE,
29578 + AVR32_SYNTAX_RETHI,
29579 + AVR32_SYNTAX_RETVS,
29580 + AVR32_SYNTAX_RETVC,
29581 + AVR32_SYNTAX_RETQS,
29582 + AVR32_SYNTAX_RETAL,
29583 + AVR32_SYNTAX_RETHS,
29584 + AVR32_SYNTAX_RETLO,
29585 + AVR32_SYNTAX_RETD,
29586 + AVR32_SYNTAX_RETE,
29587 + AVR32_SYNTAX_RETJ,
29588 + AVR32_SYNTAX_RETS,
29589 + AVR32_SYNTAX_RJMP,
29590 + AVR32_SYNTAX_ROL,
29591 + AVR32_SYNTAX_ROR,
29592 + AVR32_SYNTAX_RSUB1,
29593 + AVR32_SYNTAX_RSUB2,
29594 + AVR32_SYNTAX_SATADD_H,
29595 + AVR32_SYNTAX_SATADD_W,
29596 + AVR32_SYNTAX_SATRNDS,
29597 + AVR32_SYNTAX_SATRNDU,
29598 + AVR32_SYNTAX_SATS,
29599 + AVR32_SYNTAX_SATSUB_H,
29600 + AVR32_SYNTAX_SATSUB_W1,
29601 + AVR32_SYNTAX_SATSUB_W2,
29602 + AVR32_SYNTAX_SATU,
29603 + AVR32_SYNTAX_SBC,
29604 + AVR32_SYNTAX_SBR,
29605 + AVR32_SYNTAX_SCALL,
29606 + AVR32_SYNTAX_SCR,
29607 + AVR32_SYNTAX_SLEEP,
29608 + AVR32_SYNTAX_SREQ,
29609 + AVR32_SYNTAX_SRNE,
29610 + AVR32_SYNTAX_SRCC,
29611 + AVR32_SYNTAX_SRCS,
29612 + AVR32_SYNTAX_SRGE,
29613 + AVR32_SYNTAX_SRLT,
29614 + AVR32_SYNTAX_SRMI,
29615 + AVR32_SYNTAX_SRPL,
29616 + AVR32_SYNTAX_SRLS,
29617 + AVR32_SYNTAX_SRGT,
29618 + AVR32_SYNTAX_SRLE,
29619 + AVR32_SYNTAX_SRHI,
29620 + AVR32_SYNTAX_SRVS,
29621 + AVR32_SYNTAX_SRVC,
29622 + AVR32_SYNTAX_SRQS,
29623 + AVR32_SYNTAX_SRAL,
29624 + AVR32_SYNTAX_SRHS,
29625 + AVR32_SYNTAX_SRLO,
29626 + AVR32_SYNTAX_SSRF,
29627 + AVR32_SYNTAX_ST_B1,
29628 + AVR32_SYNTAX_ST_B2,
29629 + AVR32_SYNTAX_ST_B5,
29630 + AVR32_SYNTAX_ST_B3,
29631 + AVR32_SYNTAX_ST_B4,
29632 + AVR32_SYNTAX_ST_D1,
29633 + AVR32_SYNTAX_ST_D2,
29634 + AVR32_SYNTAX_ST_D3,
29635 + AVR32_SYNTAX_ST_D5,
29636 + AVR32_SYNTAX_ST_D4,
29637 + AVR32_SYNTAX_ST_H1,
29638 + AVR32_SYNTAX_ST_H2,
29639 + AVR32_SYNTAX_ST_H5,
29640 + AVR32_SYNTAX_ST_H3,
29641 + AVR32_SYNTAX_ST_H4,
29642 + AVR32_SYNTAX_ST_W1,
29643 + AVR32_SYNTAX_ST_W2,
29644 + AVR32_SYNTAX_ST_W5,
29645 + AVR32_SYNTAX_ST_W3,
29646 + AVR32_SYNTAX_ST_W4,
29647 + AVR32_SYNTAX_STC_D1,
29648 + AVR32_SYNTAX_STC_D2,
29649 + AVR32_SYNTAX_STC_D3,
29650 + AVR32_SYNTAX_STC_W1,
29651 + AVR32_SYNTAX_STC_W2,
29652 + AVR32_SYNTAX_STC_W3,
29653 + AVR32_SYNTAX_STC0_D,
29654 + AVR32_SYNTAX_STC0_W,
29655 + AVR32_SYNTAX_STCM_D,
29656 + AVR32_SYNTAX_STCM_D_PU,
29657 + AVR32_SYNTAX_STCM_W,
29658 + AVR32_SYNTAX_STCM_W_PU,
29659 + AVR32_SYNTAX_STCOND,
29660 + AVR32_SYNTAX_STDSP,
29661 + AVR32_SYNTAX_STHH_W2,
29662 + AVR32_SYNTAX_STHH_W1,
29663 + AVR32_SYNTAX_STM,
29664 + AVR32_SYNTAX_STM_PU,
29665 + AVR32_SYNTAX_STMTS,
29666 + AVR32_SYNTAX_STMTS_PU,
29667 + AVR32_SYNTAX_STSWP_H,
29668 + AVR32_SYNTAX_STSWP_W,
29669 + AVR32_SYNTAX_SUB1,
29670 + AVR32_SYNTAX_SUB2,
29671 + AVR32_SYNTAX_SUB5,
29672 + AVR32_SYNTAX_SUB3_SP,
29673 + AVR32_SYNTAX_SUB3,
29674 + AVR32_SYNTAX_SUB4,
29675 + AVR32_SYNTAX_SUBEQ,
29676 + AVR32_SYNTAX_SUBNE,
29677 + AVR32_SYNTAX_SUBCC,
29678 + AVR32_SYNTAX_SUBCS,
29679 + AVR32_SYNTAX_SUBGE,
29680 + AVR32_SYNTAX_SUBLT,
29681 + AVR32_SYNTAX_SUBMI,
29682 + AVR32_SYNTAX_SUBPL,
29683 + AVR32_SYNTAX_SUBLS,
29684 + AVR32_SYNTAX_SUBGT,
29685 + AVR32_SYNTAX_SUBLE,
29686 + AVR32_SYNTAX_SUBHI,
29687 + AVR32_SYNTAX_SUBVS,
29688 + AVR32_SYNTAX_SUBVC,
29689 + AVR32_SYNTAX_SUBQS,
29690 + AVR32_SYNTAX_SUBAL,
29691 + AVR32_SYNTAX_SUBHS,
29692 + AVR32_SYNTAX_SUBLO,
29693 + AVR32_SYNTAX_SUBFEQ,
29694 + AVR32_SYNTAX_SUBFNE,
29695 + AVR32_SYNTAX_SUBFCC,
29696 + AVR32_SYNTAX_SUBFCS,
29697 + AVR32_SYNTAX_SUBFGE,
29698 + AVR32_SYNTAX_SUBFLT,
29699 + AVR32_SYNTAX_SUBFMI,
29700 + AVR32_SYNTAX_SUBFPL,
29701 + AVR32_SYNTAX_SUBFLS,
29702 + AVR32_SYNTAX_SUBFGT,
29703 + AVR32_SYNTAX_SUBFLE,
29704 + AVR32_SYNTAX_SUBFHI,
29705 + AVR32_SYNTAX_SUBFVS,
29706 + AVR32_SYNTAX_SUBFVC,
29707 + AVR32_SYNTAX_SUBFQS,
29708 + AVR32_SYNTAX_SUBFAL,
29709 + AVR32_SYNTAX_SUBFHS,
29710 + AVR32_SYNTAX_SUBFLO,
29711 + AVR32_SYNTAX_SUBHH_W,
29712 + AVR32_SYNTAX_SWAP_B,
29713 + AVR32_SYNTAX_SWAP_BH,
29714 + AVR32_SYNTAX_SWAP_H,
29715 + AVR32_SYNTAX_SYNC,
29716 + AVR32_SYNTAX_TLBR,
29717 + AVR32_SYNTAX_TLBS,
29718 + AVR32_SYNTAX_TLBW,
29719 + AVR32_SYNTAX_TNBZ,
29720 + AVR32_SYNTAX_TST,
29721 + AVR32_SYNTAX_XCHG,
29722 + AVR32_SYNTAX_MEMC,
29723 + AVR32_SYNTAX_MEMS,
29724 + AVR32_SYNTAX_MEMT,
29725 + AVR32_SYNTAX_FMAC_S,
29726 + AVR32_SYNTAX_FNMAC_S,
29727 + AVR32_SYNTAX_FMSC_S,
29728 + AVR32_SYNTAX_FNMSC_S,
29729 + AVR32_SYNTAX_FMUL_S,
29730 + AVR32_SYNTAX_FNMUL_S,
29731 + AVR32_SYNTAX_FADD_S,
29732 + AVR32_SYNTAX_FSUB_S,
29733 + AVR32_SYNTAX_FCASTRS_SW,
29734 + AVR32_SYNTAX_FCASTRS_UW,
29735 + AVR32_SYNTAX_FCASTSW_S,
29736 + AVR32_SYNTAX_FCASTUW_S,
29737 + AVR32_SYNTAX_FCMP_S,
29738 + AVR32_SYNTAX_FCHK_S,
29739 + AVR32_SYNTAX_FRCPA_S,
29740 + AVR32_SYNTAX_FRSQRTA_S,
29741 + AVR32_SYNTAX_LDA_W,
29742 + AVR32_SYNTAX_CALL,
29743 + AVR32_SYNTAX_PICOSVMAC0,
29744 + AVR32_SYNTAX_PICOSVMAC1,
29745 + AVR32_SYNTAX_PICOSVMAC2,
29746 + AVR32_SYNTAX_PICOSVMAC3,
29747 + AVR32_SYNTAX_PICOSVMUL0,
29748 + AVR32_SYNTAX_PICOSVMUL1,
29749 + AVR32_SYNTAX_PICOSVMUL2,
29750 + AVR32_SYNTAX_PICOSVMUL3,
29751 + AVR32_SYNTAX_PICOVMAC0,
29752 + AVR32_SYNTAX_PICOVMAC1,
29753 + AVR32_SYNTAX_PICOVMAC2,
29754 + AVR32_SYNTAX_PICOVMAC3,
29755 + AVR32_SYNTAX_PICOVMUL0,
29756 + AVR32_SYNTAX_PICOVMUL1,
29757 + AVR32_SYNTAX_PICOVMUL2,
29758 + AVR32_SYNTAX_PICOVMUL3,
29759 + AVR32_SYNTAX_PICOLD_D2,
29760 + AVR32_SYNTAX_PICOLD_D3,
29761 + AVR32_SYNTAX_PICOLD_D1,
29762 + AVR32_SYNTAX_PICOLD_W2,
29763 + AVR32_SYNTAX_PICOLD_W3,
29764 + AVR32_SYNTAX_PICOLD_W1,
29765 + AVR32_SYNTAX_PICOLDM_D,
29766 + AVR32_SYNTAX_PICOLDM_D_PU,
29767 + AVR32_SYNTAX_PICOLDM_W,
29768 + AVR32_SYNTAX_PICOLDM_W_PU,
29769 + AVR32_SYNTAX_PICOMV_D1,
29770 + AVR32_SYNTAX_PICOMV_D2,
29771 + AVR32_SYNTAX_PICOMV_W1,
29772 + AVR32_SYNTAX_PICOMV_W2,
29773 + AVR32_SYNTAX_PICOST_D2,
29774 + AVR32_SYNTAX_PICOST_D3,
29775 + AVR32_SYNTAX_PICOST_D1,
29776 + AVR32_SYNTAX_PICOST_W2,
29777 + AVR32_SYNTAX_PICOST_W3,
29778 + AVR32_SYNTAX_PICOST_W1,
29779 + AVR32_SYNTAX_PICOSTM_D,
29780 + AVR32_SYNTAX_PICOSTM_D_PU,
29781 + AVR32_SYNTAX_PICOSTM_W,
29782 + AVR32_SYNTAX_PICOSTM_W_PU,
29783 + AVR32_SYNTAX_RSUBEQ,
29784 + AVR32_SYNTAX_RSUBNE,
29785 + AVR32_SYNTAX_RSUBCC,
29786 + AVR32_SYNTAX_RSUBCS,
29787 + AVR32_SYNTAX_RSUBGE,
29788 + AVR32_SYNTAX_RSUBLT,
29789 + AVR32_SYNTAX_RSUBMI,
29790 + AVR32_SYNTAX_RSUBPL,
29791 + AVR32_SYNTAX_RSUBLS,
29792 + AVR32_SYNTAX_RSUBGT,
29793 + AVR32_SYNTAX_RSUBLE,
29794 + AVR32_SYNTAX_RSUBHI,
29795 + AVR32_SYNTAX_RSUBVS,
29796 + AVR32_SYNTAX_RSUBVC,
29797 + AVR32_SYNTAX_RSUBQS,
29798 + AVR32_SYNTAX_RSUBAL,
29799 + AVR32_SYNTAX_RSUBHS,
29800 + AVR32_SYNTAX_RSUBLO,
29801 + AVR32_SYNTAX_ADDEQ,
29802 + AVR32_SYNTAX_ADDNE,
29803 + AVR32_SYNTAX_ADDCC,
29804 + AVR32_SYNTAX_ADDCS,
29805 + AVR32_SYNTAX_ADDGE,
29806 + AVR32_SYNTAX_ADDLT,
29807 + AVR32_SYNTAX_ADDMI,
29808 + AVR32_SYNTAX_ADDPL,
29809 + AVR32_SYNTAX_ADDLS,
29810 + AVR32_SYNTAX_ADDGT,
29811 + AVR32_SYNTAX_ADDLE,
29812 + AVR32_SYNTAX_ADDHI,
29813 + AVR32_SYNTAX_ADDVS,
29814 + AVR32_SYNTAX_ADDVC,
29815 + AVR32_SYNTAX_ADDQS,
29816 + AVR32_SYNTAX_ADDAL,
29817 + AVR32_SYNTAX_ADDHS,
29818 + AVR32_SYNTAX_ADDLO,
29819 + AVR32_SYNTAX_SUB2EQ,
29820 + AVR32_SYNTAX_SUB2NE,
29821 + AVR32_SYNTAX_SUB2CC,
29822 + AVR32_SYNTAX_SUB2CS,
29823 + AVR32_SYNTAX_SUB2GE,
29824 + AVR32_SYNTAX_SUB2LT,
29825 + AVR32_SYNTAX_SUB2MI,
29826 + AVR32_SYNTAX_SUB2PL,
29827 + AVR32_SYNTAX_SUB2LS,
29828 + AVR32_SYNTAX_SUB2GT,
29829 + AVR32_SYNTAX_SUB2LE,
29830 + AVR32_SYNTAX_SUB2HI,
29831 + AVR32_SYNTAX_SUB2VS,
29832 + AVR32_SYNTAX_SUB2VC,
29833 + AVR32_SYNTAX_SUB2QS,
29834 + AVR32_SYNTAX_SUB2AL,
29835 + AVR32_SYNTAX_SUB2HS,
29836 + AVR32_SYNTAX_SUB2LO,
29837 + AVR32_SYNTAX_ANDEQ,
29838 + AVR32_SYNTAX_ANDNE,
29839 + AVR32_SYNTAX_ANDCC,
29840 + AVR32_SYNTAX_ANDCS,
29841 + AVR32_SYNTAX_ANDGE,
29842 + AVR32_SYNTAX_ANDLT,
29843 + AVR32_SYNTAX_ANDMI,
29844 + AVR32_SYNTAX_ANDPL,
29845 + AVR32_SYNTAX_ANDLS,
29846 + AVR32_SYNTAX_ANDGT,
29847 + AVR32_SYNTAX_ANDLE,
29848 + AVR32_SYNTAX_ANDHI,
29849 + AVR32_SYNTAX_ANDVS,
29850 + AVR32_SYNTAX_ANDVC,
29851 + AVR32_SYNTAX_ANDQS,
29852 + AVR32_SYNTAX_ANDAL,
29853 + AVR32_SYNTAX_ANDHS,
29854 + AVR32_SYNTAX_ANDLO,
29855 + AVR32_SYNTAX_OREQ,
29856 + AVR32_SYNTAX_ORNE,
29857 + AVR32_SYNTAX_ORCC,
29858 + AVR32_SYNTAX_ORCS,
29859 + AVR32_SYNTAX_ORGE,
29860 + AVR32_SYNTAX_ORLT,
29861 + AVR32_SYNTAX_ORMI,
29862 + AVR32_SYNTAX_ORPL,
29863 + AVR32_SYNTAX_ORLS,
29864 + AVR32_SYNTAX_ORGT,
29865 + AVR32_SYNTAX_ORLE,
29866 + AVR32_SYNTAX_ORHI,
29867 + AVR32_SYNTAX_ORVS,
29868 + AVR32_SYNTAX_ORVC,
29869 + AVR32_SYNTAX_ORQS,
29870 + AVR32_SYNTAX_ORAL,
29871 + AVR32_SYNTAX_ORHS,
29872 + AVR32_SYNTAX_ORLO,
29873 + AVR32_SYNTAX_EOREQ,
29874 + AVR32_SYNTAX_EORNE,
29875 + AVR32_SYNTAX_EORCC,
29876 + AVR32_SYNTAX_EORCS,
29877 + AVR32_SYNTAX_EORGE,
29878 + AVR32_SYNTAX_EORLT,
29879 + AVR32_SYNTAX_EORMI,
29880 + AVR32_SYNTAX_EORPL,
29881 + AVR32_SYNTAX_EORLS,
29882 + AVR32_SYNTAX_EORGT,
29883 + AVR32_SYNTAX_EORLE,
29884 + AVR32_SYNTAX_EORHI,
29885 + AVR32_SYNTAX_EORVS,
29886 + AVR32_SYNTAX_EORVC,
29887 + AVR32_SYNTAX_EORQS,
29888 + AVR32_SYNTAX_EORAL,
29889 + AVR32_SYNTAX_EORHS,
29890 + AVR32_SYNTAX_EORLO,
29891 + AVR32_SYNTAX_LD_WEQ,
29892 + AVR32_SYNTAX_LD_WNE,
29893 + AVR32_SYNTAX_LD_WCC,
29894 + AVR32_SYNTAX_LD_WCS,
29895 + AVR32_SYNTAX_LD_WGE,
29896 + AVR32_SYNTAX_LD_WLT,
29897 + AVR32_SYNTAX_LD_WMI,
29898 + AVR32_SYNTAX_LD_WPL,
29899 + AVR32_SYNTAX_LD_WLS,
29900 + AVR32_SYNTAX_LD_WGT,
29901 + AVR32_SYNTAX_LD_WLE,
29902 + AVR32_SYNTAX_LD_WHI,
29903 + AVR32_SYNTAX_LD_WVS,
29904 + AVR32_SYNTAX_LD_WVC,
29905 + AVR32_SYNTAX_LD_WQS,
29906 + AVR32_SYNTAX_LD_WAL,
29907 + AVR32_SYNTAX_LD_WHS,
29908 + AVR32_SYNTAX_LD_WLO,
29909 + AVR32_SYNTAX_LD_SHEQ,
29910 + AVR32_SYNTAX_LD_SHNE,
29911 + AVR32_SYNTAX_LD_SHCC,
29912 + AVR32_SYNTAX_LD_SHCS,
29913 + AVR32_SYNTAX_LD_SHGE,
29914 + AVR32_SYNTAX_LD_SHLT,
29915 + AVR32_SYNTAX_LD_SHMI,
29916 + AVR32_SYNTAX_LD_SHPL,
29917 + AVR32_SYNTAX_LD_SHLS,
29918 + AVR32_SYNTAX_LD_SHGT,
29919 + AVR32_SYNTAX_LD_SHLE,
29920 + AVR32_SYNTAX_LD_SHHI,
29921 + AVR32_SYNTAX_LD_SHVS,
29922 + AVR32_SYNTAX_LD_SHVC,
29923 + AVR32_SYNTAX_LD_SHQS,
29924 + AVR32_SYNTAX_LD_SHAL,
29925 + AVR32_SYNTAX_LD_SHHS,
29926 + AVR32_SYNTAX_LD_SHLO,
29927 + AVR32_SYNTAX_LD_UHEQ,
29928 + AVR32_SYNTAX_LD_UHNE,
29929 + AVR32_SYNTAX_LD_UHCC,
29930 + AVR32_SYNTAX_LD_UHCS,
29931 + AVR32_SYNTAX_LD_UHGE,
29932 + AVR32_SYNTAX_LD_UHLT,
29933 + AVR32_SYNTAX_LD_UHMI,
29934 + AVR32_SYNTAX_LD_UHPL,
29935 + AVR32_SYNTAX_LD_UHLS,
29936 + AVR32_SYNTAX_LD_UHGT,
29937 + AVR32_SYNTAX_LD_UHLE,
29938 + AVR32_SYNTAX_LD_UHHI,
29939 + AVR32_SYNTAX_LD_UHVS,
29940 + AVR32_SYNTAX_LD_UHVC,
29941 + AVR32_SYNTAX_LD_UHQS,
29942 + AVR32_SYNTAX_LD_UHAL,
29943 + AVR32_SYNTAX_LD_UHHS,
29944 + AVR32_SYNTAX_LD_UHLO,
29945 + AVR32_SYNTAX_LD_SBEQ,
29946 + AVR32_SYNTAX_LD_SBNE,
29947 + AVR32_SYNTAX_LD_SBCC,
29948 + AVR32_SYNTAX_LD_SBCS,
29949 + AVR32_SYNTAX_LD_SBGE,
29950 + AVR32_SYNTAX_LD_SBLT,
29951 + AVR32_SYNTAX_LD_SBMI,
29952 + AVR32_SYNTAX_LD_SBPL,
29953 + AVR32_SYNTAX_LD_SBLS,
29954 + AVR32_SYNTAX_LD_SBGT,
29955 + AVR32_SYNTAX_LD_SBLE,
29956 + AVR32_SYNTAX_LD_SBHI,
29957 + AVR32_SYNTAX_LD_SBVS,
29958 + AVR32_SYNTAX_LD_SBVC,
29959 + AVR32_SYNTAX_LD_SBQS,
29960 + AVR32_SYNTAX_LD_SBAL,
29961 + AVR32_SYNTAX_LD_SBHS,
29962 + AVR32_SYNTAX_LD_SBLO,
29963 + AVR32_SYNTAX_LD_UBEQ,
29964 + AVR32_SYNTAX_LD_UBNE,
29965 + AVR32_SYNTAX_LD_UBCC,
29966 + AVR32_SYNTAX_LD_UBCS,
29967 + AVR32_SYNTAX_LD_UBGE,
29968 + AVR32_SYNTAX_LD_UBLT,
29969 + AVR32_SYNTAX_LD_UBMI,
29970 + AVR32_SYNTAX_LD_UBPL,
29971 + AVR32_SYNTAX_LD_UBLS,
29972 + AVR32_SYNTAX_LD_UBGT,
29973 + AVR32_SYNTAX_LD_UBLE,
29974 + AVR32_SYNTAX_LD_UBHI,
29975 + AVR32_SYNTAX_LD_UBVS,
29976 + AVR32_SYNTAX_LD_UBVC,
29977 + AVR32_SYNTAX_LD_UBQS,
29978 + AVR32_SYNTAX_LD_UBAL,
29979 + AVR32_SYNTAX_LD_UBHS,
29980 + AVR32_SYNTAX_LD_UBLO,
29981 + AVR32_SYNTAX_ST_WEQ,
29982 + AVR32_SYNTAX_ST_WNE,
29983 + AVR32_SYNTAX_ST_WCC,
29984 + AVR32_SYNTAX_ST_WCS,
29985 + AVR32_SYNTAX_ST_WGE,
29986 + AVR32_SYNTAX_ST_WLT,
29987 + AVR32_SYNTAX_ST_WMI,
29988 + AVR32_SYNTAX_ST_WPL,
29989 + AVR32_SYNTAX_ST_WLS,
29990 + AVR32_SYNTAX_ST_WGT,
29991 + AVR32_SYNTAX_ST_WLE,
29992 + AVR32_SYNTAX_ST_WHI,
29993 + AVR32_SYNTAX_ST_WVS,
29994 + AVR32_SYNTAX_ST_WVC,
29995 + AVR32_SYNTAX_ST_WQS,
29996 + AVR32_SYNTAX_ST_WAL,
29997 + AVR32_SYNTAX_ST_WHS,
29998 + AVR32_SYNTAX_ST_WLO,
29999 + AVR32_SYNTAX_ST_HEQ,
30000 + AVR32_SYNTAX_ST_HNE,
30001 + AVR32_SYNTAX_ST_HCC,
30002 + AVR32_SYNTAX_ST_HCS,
30003 + AVR32_SYNTAX_ST_HGE,
30004 + AVR32_SYNTAX_ST_HLT,
30005 + AVR32_SYNTAX_ST_HMI,
30006 + AVR32_SYNTAX_ST_HPL,
30007 + AVR32_SYNTAX_ST_HLS,
30008 + AVR32_SYNTAX_ST_HGT,
30009 + AVR32_SYNTAX_ST_HLE,
30010 + AVR32_SYNTAX_ST_HHI,
30011 + AVR32_SYNTAX_ST_HVS,
30012 + AVR32_SYNTAX_ST_HVC,
30013 + AVR32_SYNTAX_ST_HQS,
30014 + AVR32_SYNTAX_ST_HAL,
30015 + AVR32_SYNTAX_ST_HHS,
30016 + AVR32_SYNTAX_ST_HLO,
30017 + AVR32_SYNTAX_ST_BEQ,
30018 + AVR32_SYNTAX_ST_BNE,
30019 + AVR32_SYNTAX_ST_BCC,
30020 + AVR32_SYNTAX_ST_BCS,
30021 + AVR32_SYNTAX_ST_BGE,
30022 + AVR32_SYNTAX_ST_BLT,
30023 + AVR32_SYNTAX_ST_BMI,
30024 + AVR32_SYNTAX_ST_BPL,
30025 + AVR32_SYNTAX_ST_BLS,
30026 + AVR32_SYNTAX_ST_BGT,
30027 + AVR32_SYNTAX_ST_BLE,
30028 + AVR32_SYNTAX_ST_BHI,
30029 + AVR32_SYNTAX_ST_BVS,
30030 + AVR32_SYNTAX_ST_BVC,
30031 + AVR32_SYNTAX_ST_BQS,
30032 + AVR32_SYNTAX_ST_BAL,
30033 + AVR32_SYNTAX_ST_BHS,
30034 + AVR32_SYNTAX_ST_BLO,
30035 + AVR32_SYNTAX_MOVH,
30036 + AVR32_SYNTAX__END_
30038 +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_
30040 +enum avr32_alias_type
30042 + AVR32_ALIAS_PICOSVMAC0,
30043 + AVR32_ALIAS_PICOSVMAC1,
30044 + AVR32_ALIAS_PICOSVMAC2,
30045 + AVR32_ALIAS_PICOSVMAC3,
30046 + AVR32_ALIAS_PICOSVMUL0,
30047 + AVR32_ALIAS_PICOSVMUL1,
30048 + AVR32_ALIAS_PICOSVMUL2,
30049 + AVR32_ALIAS_PICOSVMUL3,
30050 + AVR32_ALIAS_PICOVMAC0,
30051 + AVR32_ALIAS_PICOVMAC1,
30052 + AVR32_ALIAS_PICOVMAC2,
30053 + AVR32_ALIAS_PICOVMAC3,
30054 + AVR32_ALIAS_PICOVMUL0,
30055 + AVR32_ALIAS_PICOVMUL1,
30056 + AVR32_ALIAS_PICOVMUL2,
30057 + AVR32_ALIAS_PICOVMUL3,
30058 + AVR32_ALIAS_PICOLD_D1,
30059 + AVR32_ALIAS_PICOLD_D2,
30060 + AVR32_ALIAS_PICOLD_D3,
30061 + AVR32_ALIAS_PICOLD_W1,
30062 + AVR32_ALIAS_PICOLD_W2,
30063 + AVR32_ALIAS_PICOLD_W3,
30064 + AVR32_ALIAS_PICOLDM_D,
30065 + AVR32_ALIAS_PICOLDM_D_PU,
30066 + AVR32_ALIAS_PICOLDM_W,
30067 + AVR32_ALIAS_PICOLDM_W_PU,
30068 + AVR32_ALIAS_PICOMV_D1,
30069 + AVR32_ALIAS_PICOMV_D2,
30070 + AVR32_ALIAS_PICOMV_W1,
30071 + AVR32_ALIAS_PICOMV_W2,
30072 + AVR32_ALIAS_PICOST_D1,
30073 + AVR32_ALIAS_PICOST_D2,
30074 + AVR32_ALIAS_PICOST_D3,
30075 + AVR32_ALIAS_PICOST_W1,
30076 + AVR32_ALIAS_PICOST_W2,
30077 + AVR32_ALIAS_PICOST_W3,
30078 + AVR32_ALIAS_PICOSTM_D,
30079 + AVR32_ALIAS_PICOSTM_D_PU,
30080 + AVR32_ALIAS_PICOSTM_W,
30081 + AVR32_ALIAS_PICOSTM_W_PU,
30082 + AVR32_ALIAS__END_
30084 +#define AVR32_NR_ALIAS AVR32_ALIAS__END_
30086 +enum avr32_mnemonic_type
30088 + AVR32_MNEMONIC_ABS,
30089 + AVR32_MNEMONIC_ACALL,
30090 + AVR32_MNEMONIC_ACR,
30091 + AVR32_MNEMONIC_ADC,
30092 + AVR32_MNEMONIC_ADD,
30093 + AVR32_MNEMONIC_ADDABS,
30094 + AVR32_MNEMONIC_ADDHH_W,
30095 + AVR32_MNEMONIC_AND,
30096 + AVR32_MNEMONIC_ANDH,
30097 + AVR32_MNEMONIC_ANDL,
30098 + AVR32_MNEMONIC_ANDN,
30099 + AVR32_MNEMONIC_ASR,
30100 + AVR32_MNEMONIC_BFEXTS,
30101 + AVR32_MNEMONIC_BFEXTU,
30102 + AVR32_MNEMONIC_BFINS,
30103 + AVR32_MNEMONIC_BLD,
30104 + AVR32_MNEMONIC_BREQ,
30105 + AVR32_MNEMONIC_BRNE,
30106 + AVR32_MNEMONIC_BRCC,
30107 + AVR32_MNEMONIC_BRCS,
30108 + AVR32_MNEMONIC_BRGE,
30109 + AVR32_MNEMONIC_BRLT,
30110 + AVR32_MNEMONIC_BRMI,
30111 + AVR32_MNEMONIC_BRPL,
30112 + AVR32_MNEMONIC_BRHS,
30113 + AVR32_MNEMONIC_BRLO,
30114 + AVR32_MNEMONIC_BRLS,
30115 + AVR32_MNEMONIC_BRGT,
30116 + AVR32_MNEMONIC_BRLE,
30117 + AVR32_MNEMONIC_BRHI,
30118 + AVR32_MNEMONIC_BRVS,
30119 + AVR32_MNEMONIC_BRVC,
30120 + AVR32_MNEMONIC_BRQS,
30121 + AVR32_MNEMONIC_BRAL,
30122 + AVR32_MNEMONIC_BREAKPOINT,
30123 + AVR32_MNEMONIC_BREV,
30124 + AVR32_MNEMONIC_BST,
30125 + AVR32_MNEMONIC_CACHE,
30126 + AVR32_MNEMONIC_CASTS_B,
30127 + AVR32_MNEMONIC_CASTS_H,
30128 + AVR32_MNEMONIC_CASTU_B,
30129 + AVR32_MNEMONIC_CASTU_H,
30130 + AVR32_MNEMONIC_CBR,
30131 + AVR32_MNEMONIC_CLZ,
30132 + AVR32_MNEMONIC_COM,
30133 + AVR32_MNEMONIC_COP,
30134 + AVR32_MNEMONIC_CP_B,
30135 + AVR32_MNEMONIC_CP_H,
30136 + AVR32_MNEMONIC_CP_W,
30137 + AVR32_MNEMONIC_CP,
30138 + AVR32_MNEMONIC_CPC,
30139 + AVR32_MNEMONIC_CSRF,
30140 + AVR32_MNEMONIC_CSRFCZ,
30141 + AVR32_MNEMONIC_DIVS,
30142 + AVR32_MNEMONIC_DIVU,
30143 + AVR32_MNEMONIC_EOR,
30144 + AVR32_MNEMONIC_EORL,
30145 + AVR32_MNEMONIC_EORH,
30146 + AVR32_MNEMONIC_FRS,
30147 + AVR32_MNEMONIC_SSCALL,
30148 + AVR32_MNEMONIC_RETSS,
30149 + AVR32_MNEMONIC_ICALL,
30150 + AVR32_MNEMONIC_INCJOSP,
30151 + AVR32_MNEMONIC_LD_D,
30152 + AVR32_MNEMONIC_LD_SB,
30153 + AVR32_MNEMONIC_LD_UB,
30154 + AVR32_MNEMONIC_LD_SH,
30155 + AVR32_MNEMONIC_LD_UH,
30156 + AVR32_MNEMONIC_LD_W,
30157 + AVR32_MNEMONIC_LDC_D,
30158 + AVR32_MNEMONIC_LDC_W,
30159 + AVR32_MNEMONIC_LDC0_D,
30160 + AVR32_MNEMONIC_LDC0_W,
30161 + AVR32_MNEMONIC_LDCM_D,
30162 + AVR32_MNEMONIC_LDCM_W,
30163 + AVR32_MNEMONIC_LDDPC,
30164 + AVR32_MNEMONIC_LDDSP,
30165 + AVR32_MNEMONIC_LDINS_B,
30166 + AVR32_MNEMONIC_LDINS_H,
30167 + AVR32_MNEMONIC_LDM,
30168 + AVR32_MNEMONIC_LDMTS,
30169 + AVR32_MNEMONIC_LDSWP_SH,
30170 + AVR32_MNEMONIC_LDSWP_UH,
30171 + AVR32_MNEMONIC_LDSWP_W,
30172 + AVR32_MNEMONIC_LSL,
30173 + AVR32_MNEMONIC_LSR,
30174 + AVR32_MNEMONIC_MAC,
30175 + AVR32_MNEMONIC_MACHH_D,
30176 + AVR32_MNEMONIC_MACHH_W,
30177 + AVR32_MNEMONIC_MACS_D,
30178 + AVR32_MNEMONIC_MACSATHH_W,
30179 + AVR32_MNEMONIC_MACU_D,
30180 + AVR32_MNEMONIC_MACWH_D,
30181 + AVR32_MNEMONIC_MAX,
30182 + AVR32_MNEMONIC_MCALL,
30183 + AVR32_MNEMONIC_MFDR,
30184 + AVR32_MNEMONIC_MFSR,
30185 + AVR32_MNEMONIC_MIN,
30186 + AVR32_MNEMONIC_MOV,
30187 + AVR32_MNEMONIC_MOVEQ,
30188 + AVR32_MNEMONIC_MOVNE,
30189 + AVR32_MNEMONIC_MOVCC,
30190 + AVR32_MNEMONIC_MOVCS,
30191 + AVR32_MNEMONIC_MOVGE,
30192 + AVR32_MNEMONIC_MOVLT,
30193 + AVR32_MNEMONIC_MOVMI,
30194 + AVR32_MNEMONIC_MOVPL,
30195 + AVR32_MNEMONIC_MOVLS,
30196 + AVR32_MNEMONIC_MOVGT,
30197 + AVR32_MNEMONIC_MOVLE,
30198 + AVR32_MNEMONIC_MOVHI,
30199 + AVR32_MNEMONIC_MOVVS,
30200 + AVR32_MNEMONIC_MOVVC,
30201 + AVR32_MNEMONIC_MOVQS,
30202 + AVR32_MNEMONIC_MOVAL,
30203 + AVR32_MNEMONIC_MOVHS,
30204 + AVR32_MNEMONIC_MOVLO,
30205 + AVR32_MNEMONIC_MTDR,
30206 + AVR32_MNEMONIC_MTSR,
30207 + AVR32_MNEMONIC_MUL,
30208 + AVR32_MNEMONIC_MULHH_W,
30209 + AVR32_MNEMONIC_MULNHH_W,
30210 + AVR32_MNEMONIC_MULNWH_D,
30211 + AVR32_MNEMONIC_MULS_D,
30212 + AVR32_MNEMONIC_MULSATHH_H,
30213 + AVR32_MNEMONIC_MULSATHH_W,
30214 + AVR32_MNEMONIC_MULSATRNDHH_H,
30215 + AVR32_MNEMONIC_MULSATRNDWH_W,
30216 + AVR32_MNEMONIC_MULSATWH_W,
30217 + AVR32_MNEMONIC_MULU_D,
30218 + AVR32_MNEMONIC_MULWH_D,
30219 + AVR32_MNEMONIC_MUSFR,
30220 + AVR32_MNEMONIC_MUSTR,
30221 + AVR32_MNEMONIC_MVCR_D,
30222 + AVR32_MNEMONIC_MVCR_W,
30223 + AVR32_MNEMONIC_MVRC_D,
30224 + AVR32_MNEMONIC_MVRC_W,
30225 + AVR32_MNEMONIC_NEG,
30226 + AVR32_MNEMONIC_NOP,
30227 + AVR32_MNEMONIC_OR,
30228 + AVR32_MNEMONIC_ORH,
30229 + AVR32_MNEMONIC_ORL,
30230 + AVR32_MNEMONIC_PABS_SB,
30231 + AVR32_MNEMONIC_PABS_SH,
30232 + AVR32_MNEMONIC_PACKSH_SB,
30233 + AVR32_MNEMONIC_PACKSH_UB,
30234 + AVR32_MNEMONIC_PACKW_SH,
30235 + AVR32_MNEMONIC_PADD_B,
30236 + AVR32_MNEMONIC_PADD_H,
30237 + AVR32_MNEMONIC_PADDH_SH,
30238 + AVR32_MNEMONIC_PADDH_UB,
30239 + AVR32_MNEMONIC_PADDS_SB,
30240 + AVR32_MNEMONIC_PADDS_SH,
30241 + AVR32_MNEMONIC_PADDS_UB,
30242 + AVR32_MNEMONIC_PADDS_UH,
30243 + AVR32_MNEMONIC_PADDSUB_H,
30244 + AVR32_MNEMONIC_PADDSUBH_SH,
30245 + AVR32_MNEMONIC_PADDSUBS_SH,
30246 + AVR32_MNEMONIC_PADDSUBS_UH,
30247 + AVR32_MNEMONIC_PADDX_H,
30248 + AVR32_MNEMONIC_PADDXH_SH,
30249 + AVR32_MNEMONIC_PADDXS_SH,
30250 + AVR32_MNEMONIC_PADDXS_UH,
30251 + AVR32_MNEMONIC_PASR_B,
30252 + AVR32_MNEMONIC_PASR_H,
30253 + AVR32_MNEMONIC_PAVG_SH,
30254 + AVR32_MNEMONIC_PAVG_UB,
30255 + AVR32_MNEMONIC_PLSL_B,
30256 + AVR32_MNEMONIC_PLSL_H,
30257 + AVR32_MNEMONIC_PLSR_B,
30258 + AVR32_MNEMONIC_PLSR_H,
30259 + AVR32_MNEMONIC_PMAX_SH,
30260 + AVR32_MNEMONIC_PMAX_UB,
30261 + AVR32_MNEMONIC_PMIN_SH,
30262 + AVR32_MNEMONIC_PMIN_UB,
30263 + AVR32_MNEMONIC_POPJC,
30264 + AVR32_MNEMONIC_POPM,
30265 + AVR32_MNEMONIC_PREF,
30266 + AVR32_MNEMONIC_PSAD,
30267 + AVR32_MNEMONIC_PSUB_B,
30268 + AVR32_MNEMONIC_PSUB_H,
30269 + AVR32_MNEMONIC_PSUBADD_H,
30270 + AVR32_MNEMONIC_PSUBADDH_SH,
30271 + AVR32_MNEMONIC_PSUBADDS_SH,
30272 + AVR32_MNEMONIC_PSUBADDS_UH,
30273 + AVR32_MNEMONIC_PSUBH_SH,
30274 + AVR32_MNEMONIC_PSUBH_UB,
30275 + AVR32_MNEMONIC_PSUBS_SB,
30276 + AVR32_MNEMONIC_PSUBS_SH,
30277 + AVR32_MNEMONIC_PSUBS_UB,
30278 + AVR32_MNEMONIC_PSUBS_UH,
30279 + AVR32_MNEMONIC_PSUBX_H,
30280 + AVR32_MNEMONIC_PSUBXH_SH,
30281 + AVR32_MNEMONIC_PSUBXS_SH,
30282 + AVR32_MNEMONIC_PSUBXS_UH,
30283 + AVR32_MNEMONIC_PUNPCKSB_H,
30284 + AVR32_MNEMONIC_PUNPCKUB_H,
30285 + AVR32_MNEMONIC_PUSHJC,
30286 + AVR32_MNEMONIC_PUSHM,
30287 + AVR32_MNEMONIC_RCALL,
30288 + AVR32_MNEMONIC_RETEQ,
30289 + AVR32_MNEMONIC_RETNE,
30290 + AVR32_MNEMONIC_RETCC,
30291 + AVR32_MNEMONIC_RETCS,
30292 + AVR32_MNEMONIC_RETGE,
30293 + AVR32_MNEMONIC_RETLT,
30294 + AVR32_MNEMONIC_RETMI,
30295 + AVR32_MNEMONIC_RETPL,
30296 + AVR32_MNEMONIC_RETLS,
30297 + AVR32_MNEMONIC_RETGT,
30298 + AVR32_MNEMONIC_RETLE,
30299 + AVR32_MNEMONIC_RETHI,
30300 + AVR32_MNEMONIC_RETVS,
30301 + AVR32_MNEMONIC_RETVC,
30302 + AVR32_MNEMONIC_RETQS,
30303 + AVR32_MNEMONIC_RETAL,
30304 + AVR32_MNEMONIC_RETHS,
30305 + AVR32_MNEMONIC_RETLO,
30306 + AVR32_MNEMONIC_RET,
30307 + AVR32_MNEMONIC_RETD,
30308 + AVR32_MNEMONIC_RETE,
30309 + AVR32_MNEMONIC_RETJ,
30310 + AVR32_MNEMONIC_RETS,
30311 + AVR32_MNEMONIC_RJMP,
30312 + AVR32_MNEMONIC_ROL,
30313 + AVR32_MNEMONIC_ROR,
30314 + AVR32_MNEMONIC_RSUB,
30315 + AVR32_MNEMONIC_SATADD_H,
30316 + AVR32_MNEMONIC_SATADD_W,
30317 + AVR32_MNEMONIC_SATRNDS,
30318 + AVR32_MNEMONIC_SATRNDU,
30319 + AVR32_MNEMONIC_SATS,
30320 + AVR32_MNEMONIC_SATSUB_H,
30321 + AVR32_MNEMONIC_SATSUB_W,
30322 + AVR32_MNEMONIC_SATU,
30323 + AVR32_MNEMONIC_SBC,
30324 + AVR32_MNEMONIC_SBR,
30325 + AVR32_MNEMONIC_SCALL,
30326 + AVR32_MNEMONIC_SCR,
30327 + AVR32_MNEMONIC_SLEEP,
30328 + AVR32_MNEMONIC_SREQ,
30329 + AVR32_MNEMONIC_SRNE,
30330 + AVR32_MNEMONIC_SRCC,
30331 + AVR32_MNEMONIC_SRCS,
30332 + AVR32_MNEMONIC_SRGE,
30333 + AVR32_MNEMONIC_SRLT,
30334 + AVR32_MNEMONIC_SRMI,
30335 + AVR32_MNEMONIC_SRPL,
30336 + AVR32_MNEMONIC_SRLS,
30337 + AVR32_MNEMONIC_SRGT,
30338 + AVR32_MNEMONIC_SRLE,
30339 + AVR32_MNEMONIC_SRHI,
30340 + AVR32_MNEMONIC_SRVS,
30341 + AVR32_MNEMONIC_SRVC,
30342 + AVR32_MNEMONIC_SRQS,
30343 + AVR32_MNEMONIC_SRAL,
30344 + AVR32_MNEMONIC_SRHS,
30345 + AVR32_MNEMONIC_SRLO,
30346 + AVR32_MNEMONIC_SSRF,
30347 + AVR32_MNEMONIC_ST_B,
30348 + AVR32_MNEMONIC_ST_D,
30349 + AVR32_MNEMONIC_ST_H,
30350 + AVR32_MNEMONIC_ST_W,
30351 + AVR32_MNEMONIC_STC_D,
30352 + AVR32_MNEMONIC_STC_W,
30353 + AVR32_MNEMONIC_STC0_D,
30354 + AVR32_MNEMONIC_STC0_W,
30355 + AVR32_MNEMONIC_STCM_D,
30356 + AVR32_MNEMONIC_STCM_W,
30357 + AVR32_MNEMONIC_STCOND,
30358 + AVR32_MNEMONIC_STDSP,
30359 + AVR32_MNEMONIC_STHH_W,
30360 + AVR32_MNEMONIC_STM,
30361 + AVR32_MNEMONIC_STMTS,
30362 + AVR32_MNEMONIC_STSWP_H,
30363 + AVR32_MNEMONIC_STSWP_W,
30364 + AVR32_MNEMONIC_SUB,
30365 + AVR32_MNEMONIC_SUBEQ,
30366 + AVR32_MNEMONIC_SUBNE,
30367 + AVR32_MNEMONIC_SUBCC,
30368 + AVR32_MNEMONIC_SUBCS,
30369 + AVR32_MNEMONIC_SUBGE,
30370 + AVR32_MNEMONIC_SUBLT,
30371 + AVR32_MNEMONIC_SUBMI,
30372 + AVR32_MNEMONIC_SUBPL,
30373 + AVR32_MNEMONIC_SUBLS,
30374 + AVR32_MNEMONIC_SUBGT,
30375 + AVR32_MNEMONIC_SUBLE,
30376 + AVR32_MNEMONIC_SUBHI,
30377 + AVR32_MNEMONIC_SUBVS,
30378 + AVR32_MNEMONIC_SUBVC,
30379 + AVR32_MNEMONIC_SUBQS,
30380 + AVR32_MNEMONIC_SUBAL,
30381 + AVR32_MNEMONIC_SUBHS,
30382 + AVR32_MNEMONIC_SUBLO,
30383 + AVR32_MNEMONIC_SUBFEQ,
30384 + AVR32_MNEMONIC_SUBFNE,
30385 + AVR32_MNEMONIC_SUBFCC,
30386 + AVR32_MNEMONIC_SUBFCS,
30387 + AVR32_MNEMONIC_SUBFGE,
30388 + AVR32_MNEMONIC_SUBFLT,
30389 + AVR32_MNEMONIC_SUBFMI,
30390 + AVR32_MNEMONIC_SUBFPL,
30391 + AVR32_MNEMONIC_SUBFLS,
30392 + AVR32_MNEMONIC_SUBFGT,
30393 + AVR32_MNEMONIC_SUBFLE,
30394 + AVR32_MNEMONIC_SUBFHI,
30395 + AVR32_MNEMONIC_SUBFVS,
30396 + AVR32_MNEMONIC_SUBFVC,
30397 + AVR32_MNEMONIC_SUBFQS,
30398 + AVR32_MNEMONIC_SUBFAL,
30399 + AVR32_MNEMONIC_SUBFHS,
30400 + AVR32_MNEMONIC_SUBFLO,
30401 + AVR32_MNEMONIC_SUBHH_W,
30402 + AVR32_MNEMONIC_SWAP_B,
30403 + AVR32_MNEMONIC_SWAP_BH,
30404 + AVR32_MNEMONIC_SWAP_H,
30405 + AVR32_MNEMONIC_SYNC,
30406 + AVR32_MNEMONIC_TLBR,
30407 + AVR32_MNEMONIC_TLBS,
30408 + AVR32_MNEMONIC_TLBW,
30409 + AVR32_MNEMONIC_TNBZ,
30410 + AVR32_MNEMONIC_TST,
30411 + AVR32_MNEMONIC_XCHG,
30412 + AVR32_MNEMONIC_MEMC,
30413 + AVR32_MNEMONIC_MEMS,
30414 + AVR32_MNEMONIC_MEMT,
30415 + AVR32_MNEMONIC_FMAC_S,
30416 + AVR32_MNEMONIC_FNMAC_S,
30417 + AVR32_MNEMONIC_FMSC_S,
30418 + AVR32_MNEMONIC_FNMSC_S,
30419 + AVR32_MNEMONIC_FMUL_S,
30420 + AVR32_MNEMONIC_FNMUL_S,
30421 + AVR32_MNEMONIC_FADD_S,
30422 + AVR32_MNEMONIC_FSUB_S,
30423 + AVR32_MNEMONIC_FCASTRS_SW,
30424 + AVR32_MNEMONIC_FCASTRS_UW,
30425 + AVR32_MNEMONIC_FCASTSW_S,
30426 + AVR32_MNEMONIC_FCASTUW_S,
30427 + AVR32_MNEMONIC_FCMP_S,
30428 + AVR32_MNEMONIC_FCHK_S,
30429 + AVR32_MNEMONIC_FRCPA_S,
30430 + AVR32_MNEMONIC_FRSQRTA_S,
30431 + /* AVR32_MNEMONIC_FLD_S,
30432 + AVR32_MNEMONIC_FLD_D,
30433 + AVR32_MNEMONIC_FST_S,
30434 + AVR32_MNEMONIC_FST_D, */
30435 + AVR32_MNEMONIC_LDA_W,
30436 + AVR32_MNEMONIC_CALL,
30437 + AVR32_MNEMONIC_PICOSVMAC,
30438 + AVR32_MNEMONIC_PICOSVMUL,
30439 + AVR32_MNEMONIC_PICOVMAC,
30440 + AVR32_MNEMONIC_PICOVMUL,
30441 + AVR32_MNEMONIC_PICOLD_D,
30442 + AVR32_MNEMONIC_PICOLD_W,
30443 + AVR32_MNEMONIC_PICOLDM_D,
30444 + AVR32_MNEMONIC_PICOLDM_W,
30445 + AVR32_MNEMONIC_PICOMV_D,
30446 + AVR32_MNEMONIC_PICOMV_W,
30447 + AVR32_MNEMONIC_PICOST_D,
30448 + AVR32_MNEMONIC_PICOST_W,
30449 + AVR32_MNEMONIC_PICOSTM_D,
30450 + AVR32_MNEMONIC_PICOSTM_W,
30451 + AVR32_MNEMONIC_RSUBEQ,
30452 + AVR32_MNEMONIC_RSUBNE,
30453 + AVR32_MNEMONIC_RSUBCC,
30454 + AVR32_MNEMONIC_RSUBCS,
30455 + AVR32_MNEMONIC_RSUBGE,
30456 + AVR32_MNEMONIC_RSUBLT,
30457 + AVR32_MNEMONIC_RSUBMI,
30458 + AVR32_MNEMONIC_RSUBPL,
30459 + AVR32_MNEMONIC_RSUBLS,
30460 + AVR32_MNEMONIC_RSUBGT,
30461 + AVR32_MNEMONIC_RSUBLE,
30462 + AVR32_MNEMONIC_RSUBHI,
30463 + AVR32_MNEMONIC_RSUBVS,
30464 + AVR32_MNEMONIC_RSUBVC,
30465 + AVR32_MNEMONIC_RSUBQS,
30466 + AVR32_MNEMONIC_RSUBAL,
30467 + AVR32_MNEMONIC_RSUBHS,
30468 + AVR32_MNEMONIC_RSUBLO,
30469 + AVR32_MNEMONIC_ADDEQ,
30470 + AVR32_MNEMONIC_ADDNE,
30471 + AVR32_MNEMONIC_ADDCC,
30472 + AVR32_MNEMONIC_ADDCS,
30473 + AVR32_MNEMONIC_ADDGE,
30474 + AVR32_MNEMONIC_ADDLT,
30475 + AVR32_MNEMONIC_ADDMI,
30476 + AVR32_MNEMONIC_ADDPL,
30477 + AVR32_MNEMONIC_ADDLS,
30478 + AVR32_MNEMONIC_ADDGT,
30479 + AVR32_MNEMONIC_ADDLE,
30480 + AVR32_MNEMONIC_ADDHI,
30481 + AVR32_MNEMONIC_ADDVS,
30482 + AVR32_MNEMONIC_ADDVC,
30483 + AVR32_MNEMONIC_ADDQS,
30484 + AVR32_MNEMONIC_ADDAL,
30485 + AVR32_MNEMONIC_ADDHS,
30486 + AVR32_MNEMONIC_ADDLO,
30487 + AVR32_MNEMONIC_ANDEQ,
30488 + AVR32_MNEMONIC_ANDNE,
30489 + AVR32_MNEMONIC_ANDCC,
30490 + AVR32_MNEMONIC_ANDCS,
30491 + AVR32_MNEMONIC_ANDGE,
30492 + AVR32_MNEMONIC_ANDLT,
30493 + AVR32_MNEMONIC_ANDMI,
30494 + AVR32_MNEMONIC_ANDPL,
30495 + AVR32_MNEMONIC_ANDLS,
30496 + AVR32_MNEMONIC_ANDGT,
30497 + AVR32_MNEMONIC_ANDLE,
30498 + AVR32_MNEMONIC_ANDHI,
30499 + AVR32_MNEMONIC_ANDVS,
30500 + AVR32_MNEMONIC_ANDVC,
30501 + AVR32_MNEMONIC_ANDQS,
30502 + AVR32_MNEMONIC_ANDAL,
30503 + AVR32_MNEMONIC_ANDHS,
30504 + AVR32_MNEMONIC_ANDLO,
30505 + AVR32_MNEMONIC_OREQ,
30506 + AVR32_MNEMONIC_ORNE,
30507 + AVR32_MNEMONIC_ORCC,
30508 + AVR32_MNEMONIC_ORCS,
30509 + AVR32_MNEMONIC_ORGE,
30510 + AVR32_MNEMONIC_ORLT,
30511 + AVR32_MNEMONIC_ORMI,
30512 + AVR32_MNEMONIC_ORPL,
30513 + AVR32_MNEMONIC_ORLS,
30514 + AVR32_MNEMONIC_ORGT,
30515 + AVR32_MNEMONIC_ORLE,
30516 + AVR32_MNEMONIC_ORHI,
30517 + AVR32_MNEMONIC_ORVS,
30518 + AVR32_MNEMONIC_ORVC,
30519 + AVR32_MNEMONIC_ORQS,
30520 + AVR32_MNEMONIC_ORAL,
30521 + AVR32_MNEMONIC_ORHS,
30522 + AVR32_MNEMONIC_ORLO,
30523 + AVR32_MNEMONIC_EOREQ,
30524 + AVR32_MNEMONIC_EORNE,
30525 + AVR32_MNEMONIC_EORCC,
30526 + AVR32_MNEMONIC_EORCS,
30527 + AVR32_MNEMONIC_EORGE,
30528 + AVR32_MNEMONIC_EORLT,
30529 + AVR32_MNEMONIC_EORMI,
30530 + AVR32_MNEMONIC_EORPL,
30531 + AVR32_MNEMONIC_EORLS,
30532 + AVR32_MNEMONIC_EORGT,
30533 + AVR32_MNEMONIC_EORLE,
30534 + AVR32_MNEMONIC_EORHI,
30535 + AVR32_MNEMONIC_EORVS,
30536 + AVR32_MNEMONIC_EORVC,
30537 + AVR32_MNEMONIC_EORQS,
30538 + AVR32_MNEMONIC_EORAL,
30539 + AVR32_MNEMONIC_EORHS,
30540 + AVR32_MNEMONIC_EORLO,
30541 + AVR32_MNEMONIC_LD_WEQ,
30542 + AVR32_MNEMONIC_LD_WNE,
30543 + AVR32_MNEMONIC_LD_WCC,
30544 + AVR32_MNEMONIC_LD_WCS,
30545 + AVR32_MNEMONIC_LD_WGE,
30546 + AVR32_MNEMONIC_LD_WLT,
30547 + AVR32_MNEMONIC_LD_WMI,
30548 + AVR32_MNEMONIC_LD_WPL,
30549 + AVR32_MNEMONIC_LD_WLS,
30550 + AVR32_MNEMONIC_LD_WGT,
30551 + AVR32_MNEMONIC_LD_WLE,
30552 + AVR32_MNEMONIC_LD_WHI,
30553 + AVR32_MNEMONIC_LD_WVS,
30554 + AVR32_MNEMONIC_LD_WVC,
30555 + AVR32_MNEMONIC_LD_WQS,
30556 + AVR32_MNEMONIC_LD_WAL,
30557 + AVR32_MNEMONIC_LD_WHS,
30558 + AVR32_MNEMONIC_LD_WLO,
30559 + AVR32_MNEMONIC_LD_SHEQ,
30560 + AVR32_MNEMONIC_LD_SHNE,
30561 + AVR32_MNEMONIC_LD_SHCC,
30562 + AVR32_MNEMONIC_LD_SHCS,
30563 + AVR32_MNEMONIC_LD_SHGE,
30564 + AVR32_MNEMONIC_LD_SHLT,
30565 + AVR32_MNEMONIC_LD_SHMI,
30566 + AVR32_MNEMONIC_LD_SHPL,
30567 + AVR32_MNEMONIC_LD_SHLS,
30568 + AVR32_MNEMONIC_LD_SHGT,
30569 + AVR32_MNEMONIC_LD_SHLE,
30570 + AVR32_MNEMONIC_LD_SHHI,
30571 + AVR32_MNEMONIC_LD_SHVS,
30572 + AVR32_MNEMONIC_LD_SHVC,
30573 + AVR32_MNEMONIC_LD_SHQS,
30574 + AVR32_MNEMONIC_LD_SHAL,
30575 + AVR32_MNEMONIC_LD_SHHS,
30576 + AVR32_MNEMONIC_LD_SHLO,
30577 + AVR32_MNEMONIC_LD_UHEQ,
30578 + AVR32_MNEMONIC_LD_UHNE,
30579 + AVR32_MNEMONIC_LD_UHCC,
30580 + AVR32_MNEMONIC_LD_UHCS,
30581 + AVR32_MNEMONIC_LD_UHGE,
30582 + AVR32_MNEMONIC_LD_UHLT,
30583 + AVR32_MNEMONIC_LD_UHMI,
30584 + AVR32_MNEMONIC_LD_UHPL,
30585 + AVR32_MNEMONIC_LD_UHLS,
30586 + AVR32_MNEMONIC_LD_UHGT,
30587 + AVR32_MNEMONIC_LD_UHLE,
30588 + AVR32_MNEMONIC_LD_UHHI,
30589 + AVR32_MNEMONIC_LD_UHVS,
30590 + AVR32_MNEMONIC_LD_UHVC,
30591 + AVR32_MNEMONIC_LD_UHQS,
30592 + AVR32_MNEMONIC_LD_UHAL,
30593 + AVR32_MNEMONIC_LD_UHHS,
30594 + AVR32_MNEMONIC_LD_UHLO,
30595 + AVR32_MNEMONIC_LD_SBEQ,
30596 + AVR32_MNEMONIC_LD_SBNE,
30597 + AVR32_MNEMONIC_LD_SBCC,
30598 + AVR32_MNEMONIC_LD_SBCS,
30599 + AVR32_MNEMONIC_LD_SBGE,
30600 + AVR32_MNEMONIC_LD_SBLT,
30601 + AVR32_MNEMONIC_LD_SBMI,
30602 + AVR32_MNEMONIC_LD_SBPL,
30603 + AVR32_MNEMONIC_LD_SBLS,
30604 + AVR32_MNEMONIC_LD_SBGT,
30605 + AVR32_MNEMONIC_LD_SBLE,
30606 + AVR32_MNEMONIC_LD_SBHI,
30607 + AVR32_MNEMONIC_LD_SBVS,
30608 + AVR32_MNEMONIC_LD_SBVC,
30609 + AVR32_MNEMONIC_LD_SBQS,
30610 + AVR32_MNEMONIC_LD_SBAL,
30611 + AVR32_MNEMONIC_LD_SBHS,
30612 + AVR32_MNEMONIC_LD_SBLO,
30613 + AVR32_MNEMONIC_LD_UBEQ,
30614 + AVR32_MNEMONIC_LD_UBNE,
30615 + AVR32_MNEMONIC_LD_UBCC,
30616 + AVR32_MNEMONIC_LD_UBCS,
30617 + AVR32_MNEMONIC_LD_UBGE,
30618 + AVR32_MNEMONIC_LD_UBLT,
30619 + AVR32_MNEMONIC_LD_UBMI,
30620 + AVR32_MNEMONIC_LD_UBPL,
30621 + AVR32_MNEMONIC_LD_UBLS,
30622 + AVR32_MNEMONIC_LD_UBGT,
30623 + AVR32_MNEMONIC_LD_UBLE,
30624 + AVR32_MNEMONIC_LD_UBHI,
30625 + AVR32_MNEMONIC_LD_UBVS,
30626 + AVR32_MNEMONIC_LD_UBVC,
30627 + AVR32_MNEMONIC_LD_UBQS,
30628 + AVR32_MNEMONIC_LD_UBAL,
30629 + AVR32_MNEMONIC_LD_UBHS,
30630 + AVR32_MNEMONIC_LD_UBLO,
30631 + AVR32_MNEMONIC_ST_WEQ,
30632 + AVR32_MNEMONIC_ST_WNE,
30633 + AVR32_MNEMONIC_ST_WCC,
30634 + AVR32_MNEMONIC_ST_WCS,
30635 + AVR32_MNEMONIC_ST_WGE,
30636 + AVR32_MNEMONIC_ST_WLT,
30637 + AVR32_MNEMONIC_ST_WMI,
30638 + AVR32_MNEMONIC_ST_WPL,
30639 + AVR32_MNEMONIC_ST_WLS,
30640 + AVR32_MNEMONIC_ST_WGT,
30641 + AVR32_MNEMONIC_ST_WLE,
30642 + AVR32_MNEMONIC_ST_WHI,
30643 + AVR32_MNEMONIC_ST_WVS,
30644 + AVR32_MNEMONIC_ST_WVC,
30645 + AVR32_MNEMONIC_ST_WQS,
30646 + AVR32_MNEMONIC_ST_WAL,
30647 + AVR32_MNEMONIC_ST_WHS,
30648 + AVR32_MNEMONIC_ST_WLO,
30649 + AVR32_MNEMONIC_ST_HEQ,
30650 + AVR32_MNEMONIC_ST_HNE,
30651 + AVR32_MNEMONIC_ST_HCC,
30652 + AVR32_MNEMONIC_ST_HCS,
30653 + AVR32_MNEMONIC_ST_HGE,
30654 + AVR32_MNEMONIC_ST_HLT,
30655 + AVR32_MNEMONIC_ST_HMI,
30656 + AVR32_MNEMONIC_ST_HPL,
30657 + AVR32_MNEMONIC_ST_HLS,
30658 + AVR32_MNEMONIC_ST_HGT,
30659 + AVR32_MNEMONIC_ST_HLE,
30660 + AVR32_MNEMONIC_ST_HHI,
30661 + AVR32_MNEMONIC_ST_HVS,
30662 + AVR32_MNEMONIC_ST_HVC,
30663 + AVR32_MNEMONIC_ST_HQS,
30664 + AVR32_MNEMONIC_ST_HAL,
30665 + AVR32_MNEMONIC_ST_HHS,
30666 + AVR32_MNEMONIC_ST_HLO,
30667 + AVR32_MNEMONIC_ST_BEQ,
30668 + AVR32_MNEMONIC_ST_BNE,
30669 + AVR32_MNEMONIC_ST_BCC,
30670 + AVR32_MNEMONIC_ST_BCS,
30671 + AVR32_MNEMONIC_ST_BGE,
30672 + AVR32_MNEMONIC_ST_BLT,
30673 + AVR32_MNEMONIC_ST_BMI,
30674 + AVR32_MNEMONIC_ST_BPL,
30675 + AVR32_MNEMONIC_ST_BLS,
30676 + AVR32_MNEMONIC_ST_BGT,
30677 + AVR32_MNEMONIC_ST_BLE,
30678 + AVR32_MNEMONIC_ST_BHI,
30679 + AVR32_MNEMONIC_ST_BVS,
30680 + AVR32_MNEMONIC_ST_BVC,
30681 + AVR32_MNEMONIC_ST_BQS,
30682 + AVR32_MNEMONIC_ST_BAL,
30683 + AVR32_MNEMONIC_ST_BHS,
30684 + AVR32_MNEMONIC_ST_BLO,
30685 + AVR32_MNEMONIC_MOVH,
30686 + AVR32_MNEMONIC__END_
30688 +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_
30690 +enum avr32_syntax_parser
30692 + AVR32_PARSER_NORMAL,
30693 + AVR32_PARSER_ALIAS,
30694 + AVR32_PARSER_LDA,
30695 + AVR32_PARSER_CALL,
30696 + AVR32_PARSER__END_
30698 +#define AVR32_NR_PARSERS AVR32_PARSER__END_
30699 --- a/opcodes/configure
30700 +++ b/opcodes/configure
30701 @@ -12417,6 +12417,7 @@ if test x${all_targets} = xfalse ; then
30702 bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30703 bfd_arm_arch) ta="$ta arm-dis.lo" ;;
30704 bfd_avr_arch) ta="$ta avr-dis.lo" ;;
30705 + bfd_avr32_arch) ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30706 bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
30707 bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30708 bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30709 --- a/opcodes/configure.in
30710 +++ b/opcodes/configure.in
30711 @@ -223,6 +223,7 @@ if test x${all_targets} = xfalse ; then
30712 bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30713 bfd_arm_arch) ta="$ta arm-dis.lo" ;;
30714 bfd_avr_arch) ta="$ta avr-dis.lo" ;;
30715 + bfd_avr32_arch) ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30716 bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
30717 bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30718 bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30719 @@ -285,7 +286,7 @@ if test x${all_targets} = xfalse ; then
30720 ta="$ta sh64-dis.lo sh64-opc.lo"
30721 archdefs="$archdefs -DINCLUDE_SHMEDIA"
30726 ta="$ta sh-dis.lo cgen-bitset.lo" ;;
30727 bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
30728 --- a/opcodes/disassemble.c
30729 +++ b/opcodes/disassemble.c
30734 +#define ARCH_avr32
30738 @@ -130,6 +131,11 @@ disassembler (abfd)
30739 disassemble = print_insn_avr;
30743 + case bfd_arch_avr32:
30744 + disassemble = print_insn_avr32;
30748 case bfd_arch_bfin:
30749 disassemble = print_insn_bfin;
30750 @@ -489,6 +495,9 @@ disassembler_usage (stream)
30752 print_i386_disassembler_options (stream);
30755 + print_avr32_disassembler_options (stream);
30758 print_s390_disassembler_options (stream);