add usb controller definition

[openwrt/svn-archive/archive.git] / target / linux / ar7 / files / include / asm-mips / ar7 / ar7.h

diff --git a/target/linux/ar7/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
index ae1d4192bfe36449c41253b3ad62caed1e3e57d1..9592f63bf565db6885198b38092cf847e8b89e62 100644 (file)
--- a/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
+++ b/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
@@ -1,18 +1,16 @@
 /*
- * $Id$
- * 
  * Copyright (C) 2006, 2007 OpenWrt.org
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
@@ -23,53 +21,55 @@
 
 #include <linux/delay.h>
 #include <asm/addrspace.h>
-#include <asm/io.h>
-
-#define AR7_REGS_BASE 0x08610000
-
-#define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
-#define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
-#define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
-#define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
-#define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
-#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
-#define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1A00)
-#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
-#define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1E00)
-#define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
-#define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
-
-#define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
-#define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
-#define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
-
-#define  AR7_RESET_PEREPHERIAL 0x0
-#define  AR7_RESET_SOFTWARE    0x4
-#define  AR7_RESET_STATUS      0x8
-
-#define AR7_RESET_BIT_CPMAC_LO 17
-#define AR7_RESET_BIT_CPMAC_HI 21
-#define AR7_RESET_BIT_MDIO     22
-#define AR7_RESET_BIT_EPHY     26
+#include <linux/io.h>
+
+#define AR7_REGS_BASE  0x08610000
+
+#define AR7_REGS_MAC0  (AR7_REGS_BASE + 0x0000)
+#define AR7_REGS_GPIO  (AR7_REGS_BASE + 0x0900)
+/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
+#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
+#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
+#define AR7_REGS_USB   (AR7_REGS_BASE + 0x1200)
+#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_VLYNQ0        (AR7_REGS_BASE + 0x1800)
+#define AR7_REGS_DCL   (AR7_REGS_BASE + 0x1a00)
+#define AR7_REGS_VLYNQ1        (AR7_REGS_BASE + 0x1c00)
+#define AR7_REGS_MDIO  (AR7_REGS_BASE + 0x1e00)
+#define AR7_REGS_IRQ   (AR7_REGS_BASE + 0x2400)
+#define AR7_REGS_MAC1  (AR7_REGS_BASE + 0x2800)
+
+#define AR7_REGS_WDT   (AR7_REGS_BASE + 0x1f00)
+#define UR8_REGS_WDT   (AR7_REGS_BASE + 0x0b00)
+#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
+
+#define AR7_RESET_PEREPHERIAL  0x0
+#define AR7_RESET_SOFTWARE     0x4
+#define AR7_RESET_STATUS       0x8
+
+#define AR7_RESET_BIT_CPMAC_LO 17
+#define AR7_RESET_BIT_CPMAC_HI 21
+#define AR7_RESET_BIT_MDIO     22
+#define AR7_RESET_BIT_EPHY     26
 
 /* GPIO control registers */
-#define  AR7_GPIO_INPUT  0x0
-#define  AR7_GPIO_OUTPUT 0x4
-#define  AR7_GPIO_DIR    0x8
-#define  AR7_GPIO_ENABLE 0xC
+#define AR7_GPIO_INPUT 0x0
+#define AR7_GPIO_OUTPUT        0x4
+#define AR7_GPIO_DIR   0x8
+#define AR7_GPIO_ENABLE        0xc
 
-#define AR7_CHIP_7100 0x18
-#define AR7_CHIP_7200 0x2b
-#define AR7_CHIP_7300 0x05
+#define AR7_CHIP_7100  0x18
+#define AR7_CHIP_7200  0x2b
+#define AR7_CHIP_7300  0x05
 
 /* Interrupts */
-#define AR7_IRQ_UART0  15
-#define AR7_IRQ_UART1  16
+#define AR7_IRQ_UART0  15
+#define AR7_IRQ_UART1  16
 
 /* Clocks */
-#define AR7_AFE_CLOCK  35328000
-#define AR7_REF_CLOCK  25000000
-#define AR7_XTAL_CLOCK 24000000
+#define AR7_AFE_CLOCK  35328000
+#define AR7_REF_CLOCK  25000000
+#define AR7_XTAL_CLOCK 24000000
 
 struct plat_cpmac_data {
        int reset_bit;
@@ -132,14 +132,16 @@ static inline int ar7_has_high_cpmac(void)
 
 static inline void ar7_device_enable(u32 bit)
 {
-       void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
+       void *reset_reg =
+               (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
        writel(readl(reset_reg) | (1 << bit), reset_reg);
        mdelay(20);
 }
 
 static inline void ar7_device_disable(u32 bit)
 {
-       void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
+       void *reset_reg =
+               (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
        writel(readl(reset_reg) & ~(1 << bit), reset_reg);
        mdelay(20);
 }