-static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
-
-#ifdef CONFIG_PCI
-static void ar71xx_pci_irq_dispatch(void)
-{
- u32 pending;
-
- pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- if (pending & PCI_INT_DEV0)
- do_IRQ(AR71XX_PCI_IRQ_DEV0);
-
- else if (pending & PCI_INT_DEV1)
- do_IRQ(AR71XX_PCI_IRQ_DEV1);
-
- else if (pending & PCI_INT_DEV2)
- do_IRQ(AR71XX_PCI_IRQ_DEV2);
-
- else if (pending & PCI_INT_CORE)
- do_IRQ(AR71XX_PCI_IRQ_CORE);
-
- else
- spurious_interrupt();
-}
-
-static void ar71xx_pci_irq_unmask(unsigned int irq)
-{
- irq -= AR71XX_PCI_IRQ_BASE;
- ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
-
- /* flush write */
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static void ar71xx_pci_irq_mask(unsigned int irq)
-{
- irq -= AR71XX_PCI_IRQ_BASE;
- ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
-
- /* flush write */
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static struct irq_chip ar71xx_pci_irq_chip = {
- .name = "AR71XX PCI ",
- .mask = ar71xx_pci_irq_mask,
- .unmask = ar71xx_pci_irq_unmask,
- .mask_ack = ar71xx_pci_irq_mask,
-};
-
-static struct irqaction ar71xx_pci_irqaction = {
- .handler = no_action,
- .name = "cascade [AR71XX PCI]",
-};
-
-static void __init ar71xx_pci_irq_init(void)
-{
- int i;
-
- ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
-
- ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
- ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
-
- for (i = AR71XX_PCI_IRQ_BASE;
- i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
- handle_level_irq);
- }
-
- setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
-}
-
-static void ar724x_pci_irq_dispatch(void)
-{
- u32 pending;
-
- pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
- ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
-
- if (pending & AR724X_PCI_INT_DEV0)
- do_IRQ(AR71XX_PCI_IRQ_DEV0);
-
- else
- spurious_interrupt();
-}
-
-static void ar724x_pci_irq_unmask(unsigned int irq)
-{
- switch (irq) {
- case AR71XX_PCI_IRQ_DEV0:
- irq -= AR71XX_PCI_IRQ_BASE;
- ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
- ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
- AR724X_PCI_INT_DEV0);
- /* flush write */
- ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
- }
-}
-
-static void ar724x_pci_irq_mask(unsigned int irq)
-{
- switch (irq) {
- case AR71XX_PCI_IRQ_DEV0:
- irq -= AR71XX_PCI_IRQ_BASE;
- ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
- ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
- ~AR724X_PCI_INT_DEV0);
- /* flush write */
- ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
-
- ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
- ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
- AR724X_PCI_INT_DEV0);
- /* flush write */
- ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
- }
-}
-
-static struct irq_chip ar724x_pci_irq_chip = {
- .name = "AR724X PCI ",
- .mask = ar724x_pci_irq_mask,
- .unmask = ar724x_pci_irq_unmask,
- .mask_ack = ar724x_pci_irq_mask,
-};
-
-static struct irqaction ar724x_pci_irqaction = {
- .handler = no_action,
- .name = "cascade [AR724X PCI]",
-};
-
-static void __init ar724x_pci_irq_init(void)
-{
- int i;
-
- ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
-
- ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
- ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
-
- for (i = AR71XX_PCI_IRQ_BASE;
- i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
- handle_level_irq);
- }
-
- setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
-}
-#else
-static inline void ar71xx_pci_irq_init(void) {};
-static inline void ar724x_pci_irq_init(void) {};
-#endif /* CONFIG_PCI */