/*
* Atheros AR71xx SoC specific interrupt handling
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
u32 pending;
pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
+ ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
if (pending & PCI_INT_DEV0)
do_IRQ(AR71XX_PCI_IRQ_DEV0);
else if (pending & PCI_INT_DEV2)
do_IRQ(AR71XX_PCI_IRQ_DEV2);
+ else if (pending & PCI_INT_CORE)
+ do_IRQ(AR71XX_PCI_IRQ_CORE);
+
else
spurious_interrupt();
}
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
+
+ /* flush write */
+ ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
}
static void ar71xx_pci_irq_mask(unsigned int irq)
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
+
+ /* flush write */
+ ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
}
static struct irq_chip ar71xx_pci_irq_chip = {