[ar71xx] use enum for the machine type

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / setup.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
index 758f5414235e1d71b24c5fda7f10f509f746a7e3..2e1a7f6a56104e471fc1dea4690130858bcf0b47 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx SoC specific setup
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
@@ -23,17 +23,18 @@
 #include <asm/traps.h>
 #include <asm/time.h>          /* for mips_hpt_frequency */
 #include <asm/reboot.h>                /* for _machine_{restart,halt} */
+#include <asm/mips_machine.h>
 
 #include <asm/mach-ar71xx/ar71xx.h>
 #include <asm/mach-ar71xx/pci.h>
-#include <asm/mach-ar71xx/platform.h>
+
+#include "devices.h"
 
 #define AR71XX_SYS_TYPE_LEN    64
 #define AR71XX_BASE_FREQ       40000000
 #define AR91XX_BASE_FREQ       5000000
 
-#define AR71XX_MEM_SIZE_MIN    0x0200000
-#define AR71XX_MEM_SIZE_MAX    0x8000000
+enum ar71xx_mach_type ar71xx_mach;
 
 u32 ar71xx_cpu_freq;
 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
@@ -106,7 +107,7 @@ static void __init ar71xx_detect_sys_type(void)
        u32 id;
        u32 rev;
 
-       id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
+       id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
        rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 
        switch (id & REV_ID_CHIP_MASK) {
@@ -149,7 +150,7 @@ static void __init ar91xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
-       pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
+       pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
        freq = div * AR91XX_BASE_FREQ;
@@ -169,7 +170,7 @@ static void __init ar71xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
-       pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
+       pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
        freq = div * AR71XX_BASE_FREQ;
@@ -255,6 +256,13 @@ void __init plat_mem_setup(void)
        ar71xx_detect_sys_type();
        detect_sys_frequency();
 
+       printk(KERN_INFO
+               "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
+               ar71xx_sys_type,
+               ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
+               ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
+               ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
+
        _machine_restart = ar71xx_restart;
        _machine_halt = ar71xx_halt;
        pm_power_off = ar71xx_halt;
@@ -268,3 +276,16 @@ void __init plat_time_init(void)
 {
        mips_hpt_frequency = ar71xx_cpu_freq / 2;
 }
+
+static int __init ar71xx_machine_setup(void)
+{
+       ar71xx_gpio_init();
+
+       ar71xx_add_device_uart();
+       ar71xx_add_device_wdt();
+
+       mips_machine_setup(ar71xx_mach);
+       return 0;
+}
+
+arch_initcall(ar71xx_machine_setup);