ar71xx: rename ath79_parse_mac_addr to ath79_parse_ascii_mac

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 7975464333a930c0ad73f36c35873307e4a5c8ec..4a2b1db7fb13ba2145eaf1bad8b9771466f3e7da 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -181,6 +181,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        if (ath79_soc == ATH79_SOC_AR9341 ||
            ath79_soc == ATH79_SOC_AR9342 ||
            ath79_soc == ATH79_SOC_AR9344 ||
+           ath79_soc == ATH79_SOC_QCA9556 ||
            ath79_soc == ATH79_SOC_QCA9558)
                max_id = 1;
        else
@@ -202,6 +203,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
                if (id == 0) {
                        mdio_dev = &ath79_mdio0_device;
@@ -250,12 +252,17 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
                }
                mdio_data->is_ar934x = 1;
                break;
+
        case ATH79_SOC_QCA9558:
                if (id == 1)
                        mdio_data->builtin_switch = 1;
                mdio_data->is_ar934x = 1;
                break;
 
+       case ATH79_SOC_QCA9556:
+               mdio_data->is_ar934x = 1;
+               break;
+
        default:
                break;
        }
@@ -355,6 +362,26 @@ static void ar934x_set_speed_ge0(int speed)
        iounmap(base);
 }
 
+static void qca955x_set_speed_xmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(0, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
+       iounmap(base);
+}
+
+static void qca955x_set_speed_sgmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(1, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
+       iounmap(base);
+}
+
 static void ath79_set_speed_dummy(int speed)
 {
 }
@@ -412,8 +439,8 @@ static struct resource ath79_eth0_resources[] = {
        }, {
                .name   = "mac_irq",
                .flags  = IORESOURCE_IRQ,
-               .start  = ATH79_CPU_IRQ_GE0,
-               .end    = ATH79_CPU_IRQ_GE0,
+               .start  = ATH79_CPU_IRQ(4),
+               .end    = ATH79_CPU_IRQ(4),
        },
 };
 
@@ -440,8 +467,8 @@ static struct resource ath79_eth1_resources[] = {
        }, {
                .name   = "mac_irq",
                .flags  = IORESOURCE_IRQ,
-               .start  = ATH79_CPU_IRQ_GE1,
-               .end    = ATH79_CPU_IRQ_GE1,
+               .start  = ATH79_CPU_IRQ(5),
+               .end    = ATH79_CPU_IRQ(5),
        },
 };
 
@@ -540,6 +567,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
                pll_10 = AR934X_PLL_VAL_10;
                pll_100 = AR934X_PLL_VAL_100;
@@ -616,6 +644,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                        }
                        break;
 
+               case ATH79_SOC_QCA9556:
                case ATH79_SOC_QCA9558:
                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
@@ -673,6 +702,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                        }
                        break;
 
+               case ATH79_SOC_QCA9556:
                case ATH79_SOC_QCA9558:
                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
@@ -905,7 +935,6 @@ void __init ath79_register_eth(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
-       case ATH79_SOC_QCA9558:
                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;
@@ -934,6 +963,30 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 
+       case ATH79_SOC_QCA9556:
+       case ATH79_SOC_QCA9558:
+               if (id == 0) {
+                       pdata->reset_bit = QCA955X_RESET_GE0_MAC |
+                                          QCA955X_RESET_GE0_MDIO;
+                       pdata->set_speed = qca955x_set_speed_xmii;
+               } else {
+                       pdata->reset_bit = QCA955X_RESET_GE1_MAC |
+                                          QCA955X_RESET_GE1_MDIO;
+                       pdata->set_speed = qca955x_set_speed_sgmii;
+               }
+
+               pdata->ddr_flush = ath79_ddr_no_flush;
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
        default:
                BUG();
        }
@@ -976,6 +1029,7 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->mii_bus_dev = &ath79_mdio1_device.dev;
                        break;
 
+               case ATH79_SOC_QCA9556:
                case ATH79_SOC_QCA9558:
                        /* don't assign any MDIO device by default */
                        break;
@@ -1002,35 +1056,42 @@ void __init ath79_set_mac_base(unsigned char *mac)
        memcpy(ath79_mac_base, mac, ETH_ALEN);
 }
 
-void __init ath79_parse_mac_addr(char *mac_str)
+void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
 {
-       u8 tmp[ETH_ALEN];
        int t;
 
        t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
-                       &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+                  &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
 
        if (t != ETH_ALEN)
                t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
-                       &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+                       &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
 
-       if (t == ETH_ALEN)
-               ath79_set_mac_base(tmp);
-       else
-               printk(KERN_DEBUG "ar71xx: failed to parse mac address "
-                               "\"%s\"\n", mac_str);
+       if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
+               memset(mac, 0, ETH_ALEN);
+               printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
+                      mac_str);
+       }
+}
+
+static void __init ath79_set_mac_base_ascii(char *str)
+{
+       u8 mac[ETH_ALEN];
+
+       ath79_parse_ascii_mac(str, mac);
+       ath79_set_mac_base(mac);
 }
 
 static int __init ath79_ethaddr_setup(char *str)
 {
-       ath79_parse_mac_addr(str);
+       ath79_set_mac_base_ascii(str);
        return 1;
 }
 __setup("ethaddr=", ath79_ethaddr_setup);
 
 static int __init ath79_kmac_setup(char *str)
 {
-       ath79_parse_mac_addr(str);
+       ath79_set_mac_base_ascii(str);
        return 1;
 }
 __setup("kmac=", ath79_kmac_setup);