#define AR71XX_PCI_IRQ_BASE 48
#define AR71XX_PCI_IRQ_COUNT 8
-#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
-#define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
__raw_writel(val, base + reg);
+ (void) __raw_readl(base + reg);
iounmap(base);
}
void __iomem *base;
base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
iounmap(base);
}