[ar71xx] ag71xx driver: NAPI poll cleanup

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index d8851160f7fef6ba5b81d5de66d45748a02282fe..80c8e18ab1079d4d3d39d33ebe33e431d863003d 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
 
 #include <linux/bitops.h>
 
@@ -37,9 +38,7 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
-#define AG71XX_DRV_VERSION     "0.5.1"
-
-#define AG71XX_NAPI_TX         1
+#define AG71XX_DRV_VERSION     "0.5.12"
 
 #define AG71XX_NAPI_WEIGHT     64
 
@@ -47,13 +46,8 @@
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 
-#ifdef AG71XX_NAPI_TX
 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
-#else
-#define AG71XX_INT_POLL        (AG71XX_INT_RX)
-#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif
 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536
@@ -131,6 +125,8 @@ struct ag71xx {
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;
+
+       struct work_struct      restart_work;
 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
@@ -198,12 +194,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define AG71XX_REG_INT_ENABLE  0x0198
 #define AG71XX_REG_INT_STATUS  0x019c
 
-#define MAC_CFG1_TXE           BIT(0)
-#define MAC_CFG1_STX           BIT(1)
-#define MAC_CFG1_RXE           BIT(2)
-#define MAC_CFG1_SRX           BIT(3)
-#define MAC_CFG1_LB            BIT(8)
-#define MAC_CFG1_SR            BIT(31)
+#define MAC_CFG1_TXE           BIT(0)  /* Tx Enable */
+#define MAC_CFG1_STX           BIT(1)  /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE           BIT(2)  /* Rx Enable */
+#define MAC_CFG1_SRX           BIT(3)  /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC           BIT(4)  /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC           BIT(5)  /* Rx Flow Control Enable */
+#define MAC_CFG1_LB            BIT(8)  /* Loopback mode */
+#define MAC_CFG1_SR            BIT(31) /* Soft Reset */
 
 #define MAC_CFG2_FDX           BIT(0)
 #define MAC_CFG2_CRC_EN                BIT(1)
@@ -285,17 +283,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 
-#define TX_CTRL_TXE            BIT(0)
+#define TX_CTRL_TXE            BIT(0)  /* Tx Enable */
 
-#define TX_STATUS_PS           BIT(0)
-#define TX_STATUS_UR           BIT(1)
-#define TX_STATUS_BE           BIT(3)
+#define TX_STATUS_PS           BIT(0)  /* Packet Sent */
+#define TX_STATUS_UR           BIT(1)  /* Tx Underrun */
+#define TX_STATUS_BE           BIT(3)  /* Bus Error */
 
-#define RX_CTRL_RXE            BIT(0)
+#define RX_CTRL_RXE            BIT(0)  /* Rx Enable */
 
-#define RX_STATUS_PR           BIT(0)
-#define RX_STATUS_OF           BIT(1)
-#define RX_STATUS_BE           BIT(3)
+#define RX_STATUS_PR           BIT(0)  /* Packet Received */
+#define RX_STATUS_OF           BIT(2)  /* Rx Overflow */
+#define RX_STATUS_BE           BIT(3)  /* Bus Error */
 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4
@@ -306,13 +304,18 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 {
+       void __iomem *r;
+
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-               __raw_writel(value, ag->mac_base + reg);
+               r = ag->mac_base + reg;
+               __raw_writel(value, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-               reg -= AG71XX_REG_MAC_IFCTL;
-               __raw_writel(value, ag->mac_base2 + reg);
+               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               __raw_writel(value, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -321,15 +324,17 @@ static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 
 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 {
+       void __iomem *r;
        u32 ret;
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-               ret = __raw_readl(ag->mac_base + reg);
+               r = ag->mac_base + reg;
+               ret = __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-               reg -= AG71XX_REG_MAC_IFCTL;
-               ret = __raw_readl(ag->mac_base2 + reg);
+               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               ret = __raw_readl(r);
                break;
        default:
                BUG();
@@ -346,10 +351,12 @@ static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
                r = ag->mac_base + reg;
                __raw_writel(__raw_readl(r) | mask, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
                r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
                __raw_writel(__raw_readl(r) | mask, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -364,10 +371,12 @@ static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
                r = ag->mac_base + reg;
                __raw_writel(__raw_readl(r) & ~mask, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
                r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
                __raw_writel(__raw_readl(r) & ~mask, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -387,6 +396,7 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {
        __raw_writel(value, ag->mii_ctrl);
+       __raw_readl(ag->mii_ctrl);
 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)