[ar71xx] ag71xx driver: fix a kernel crash caused by r14496

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index 05adeabbbb4e3e7cb641d760f493266a4c32a7bb..96bfd21b50754a5ebbfca14b7012a894241d57b3 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx built-in ethernet mac driver
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Based on Atheros' AG7100 driver
@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
 
 #include <linux/bitops.h>
 
@@ -37,23 +38,17 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
-#define AG71XX_DRV_VERSION     "0.5.2"
-
-#define AG71XX_NAPI_TX         1
+#define AG71XX_DRV_VERSION     "0.5.20"
 
 #define AG71XX_NAPI_WEIGHT     64
+#define AG71XX_OOM_REFILL      (1 + HZ/10)
 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 
-#ifdef AG71XX_NAPI_TX
 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
-#else
-#define AG71XX_INT_POLL        (AG71XX_INT_RX)
-#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif
 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536
@@ -90,6 +85,7 @@ struct ag71xx_desc {
 #define DESC_MORE      BIT(24)
 #define DESC_PKTLEN_M  0x1fff
        u32     next;
+       u32     pad;
 };
 
 struct ag71xx_buf {
@@ -131,6 +127,9 @@ struct ag71xx {
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;
+
+       struct work_struct      restart_work;
+       struct timer_list       oom_timer;
 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
@@ -229,7 +228,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
 #define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
 #define FIFO_CFG4_CE           BIT(3)  /* Code Error */
-#define FIFO_CFG4_CRC          BIT(4)  /* CRC error */
+#define FIFO_CFG4_CR           BIT(4)  /* CRC error */
 #define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
 #define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
 #define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
@@ -260,6 +259,8 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
 #define FIFO_CFG5_LE           BIT(14) /* Long Event */
 #define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16           BIT(16) /* unknown */
+#define FIFO_CFG5_17           BIT(17) /* unknown */
 #define FIFO_CFG5_SF           BIT(18) /* Short Frame */
 #define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
 
@@ -287,17 +288,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MII_IND_BUSY           BIT(0)
 #define MII_IND_INVALID                BIT(2)
 
-#define TX_CTRL_TXE            BIT(0)
+#define TX_CTRL_TXE            BIT(0)  /* Tx Enable */
 
-#define TX_STATUS_PS           BIT(0)
-#define TX_STATUS_UR           BIT(1)
-#define TX_STATUS_BE           BIT(3)
+#define TX_STATUS_PS           BIT(0)  /* Packet Sent */
+#define TX_STATUS_UR           BIT(1)  /* Tx Underrun */
+#define TX_STATUS_BE           BIT(3)  /* Bus Error */
 
-#define RX_CTRL_RXE            BIT(0)
+#define RX_CTRL_RXE            BIT(0)  /* Rx Enable */
 
-#define RX_STATUS_PR           BIT(0)
-#define RX_STATUS_OF           BIT(1)
-#define RX_STATUS_BE           BIT(3)
+#define RX_STATUS_PR           BIT(0)  /* Packet Received */
+#define RX_STATUS_OF           BIT(2)  /* Rx Overflow */
+#define RX_STATUS_BE           BIT(3)  /* Bus Error */
 
 #define MII_CTRL_IF_MASK       3
 #define MII_CTRL_SPEED_SHIFT   4
@@ -308,13 +309,18 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 {
+       void __iomem *r;
+
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-               __raw_writel(value, ag->mac_base + reg);
+               r = ag->mac_base + reg;
+               __raw_writel(value, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-               reg -= AG71XX_REG_MAC_IFCTL;
-               __raw_writel(value, ag->mac_base2 + reg);
+               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               __raw_writel(value, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -323,15 +329,17 @@ static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 
 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 {
+       void __iomem *r;
        u32 ret;
 
        switch (reg) {
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-               ret = __raw_readl(ag->mac_base + reg);
+               r = ag->mac_base + reg;
+               ret = __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-               reg -= AG71XX_REG_MAC_IFCTL;
-               ret = __raw_readl(ag->mac_base2 + reg);
+               r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+               ret = __raw_readl(r);
                break;
        default:
                BUG();
@@ -348,10 +356,12 @@ static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
                r = ag->mac_base + reg;
                __raw_writel(__raw_readl(r) | mask, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
                r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
                __raw_writel(__raw_readl(r) | mask, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -366,10 +376,12 @@ static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
        case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
                r = ag->mac_base + reg;
                __raw_writel(__raw_readl(r) & ~mask, r);
+               __raw_readl(r);
                break;
        case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
                r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
                __raw_writel(__raw_readl(r) & ~mask, r);
+               __raw_readl(r);
                break;
        default:
                BUG();
@@ -389,6 +401,7 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {
        __raw_writel(value, ag->mii_ctrl);
+       __raw_readl(ag->mii_ctrl);
 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)