/*
* Atheros AR71xx built-in ethernet mac driver
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
#include <linux/phy.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
#include <linux/bitops.h>
#define ETH_FCS_LEN 4
#define AG71XX_DRV_NAME "ag71xx"
-#define AG71XX_DRV_VERSION "0.4.0"
-
-#define AG71XX_NAPI_TX 1
+#define AG71XX_DRV_VERSION "0.5.20"
#define AG71XX_NAPI_WEIGHT 64
+#define AG71XX_OOM_REFILL (1 + HZ/10)
#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
-#ifdef AG71XX_NAPI_TX
#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
-#else
-#define AG71XX_INT_POLL (AG71XX_INT_RX)
-#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif
#define AG71XX_TX_FIFO_LEN 2048
#define AG71XX_TX_MTU_LEN 1536
#define DESC_MORE BIT(24)
#define DESC_PKTLEN_M 0x1fff
u32 next;
+ u32 pad;
};
struct ag71xx_buf {
struct platform_device *pdev;
struct net_device *dev;
struct napi_struct napi;
+ u32 msg_enable;
struct ag71xx_ring rx_ring;
struct ag71xx_ring tx_ring;
unsigned int link;
unsigned int speed;
int duplex;
+
+ struct work_struct restart_work;
+ struct timer_list oom_timer;
};
extern struct ethtool_ops ag71xx_ethtool_ops;
#define AG71XX_REG_INT_ENABLE 0x0198
#define AG71XX_REG_INT_STATUS 0x019c
-#define MAC_CFG1_TXE BIT(0)
-#define MAC_CFG1_STX BIT(1)
-#define MAC_CFG1_RXE BIT(2)
-#define MAC_CFG1_SRX BIT(3)
-#define MAC_CFG1_LB BIT(8)
-#define MAC_CFG1_SR BIT(31)
+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
+#define MAC_CFG1_LB BIT(8) /* Loopback mode */
+#define MAC_CFG1_SR BIT(31) /* Soft Reset */
#define MAC_CFG2_FDX BIT(0)
#define MAC_CFG2_CRC_EN BIT(1)
#define MAC_CFG2_IF_1000 BIT(9)
#define MAC_CFG2_IF_10_100 BIT(8)
+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE BIT(0) /* Drop Event */
+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG4_FC BIT(2) /* False Carrier */
+#define FIFO_CFG4_CE BIT(3) /* Code Error */
+#define FIFO_CFG4_CR BIT(4) /* CRC error */
+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
+#define FIFO_CFG4_LO BIT(6) /* Length out of range */
+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
+#define FIFO_CFG4_DR BIT(10) /* Dribble */
+#define FIFO_CFG4_LE BIT(11) /* Long Event */
+#define FIFO_CFG4_CF BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE BIT(0) /* Drop Event */
+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG5_FC BIT(2) /* False Carrier */
+#define FIFO_CFG5_CE BIT(3) /* Code Error */
+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
+#define FIFO_CFG5_DR BIT(9) /* Dribble */
+#define FIFO_CFG5_CF BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE BIT(14) /* Long Event */
+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16 BIT(16) /* unknown */
+#define FIFO_CFG5_17 BIT(17) /* unknown */
+#define FIFO_CFG5_SF BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
+
#define AG71XX_INT_TX_PS BIT(0)
#define AG71XX_INT_TX_UR BIT(1)
#define AG71XX_INT_TX_BE BIT(3)
#define MII_CMD_WRITE 0x0
#define MII_CMD_READ 0x1
-#define MII_ADDR_S 8
+#define MII_ADDR_SHIFT 8
#define MII_IND_BUSY BIT(0)
#define MII_IND_INVALID BIT(2)
-#define TX_CTRL_TXE BIT(0)
-
-#define TX_STATUS_PS BIT(0)
-#define TX_STATUS_UR BIT(1)
-#define TX_STATUS_BE BIT(3)
+#define TX_CTRL_TXE BIT(0) /* Tx Enable */
-#define RX_CTRL_RXE BIT(0)
+#define TX_STATUS_PS BIT(0) /* Packet Sent */
+#define TX_STATUS_UR BIT(1) /* Tx Underrun */
+#define TX_STATUS_BE BIT(3) /* Bus Error */
-#define RX_STATUS_PR BIT(0)
-#define RX_STATUS_OF BIT(1)
-#define RX_STATUS_BE BIT(3)
+#define RX_CTRL_RXE BIT(0) /* Rx Enable */
-#define FIFO_CFG5_BYTE_PER_CLK BIT(19)
+#define RX_STATUS_PR BIT(0) /* Packet Received */
+#define RX_STATUS_OF BIT(2) /* Rx Overflow */
+#define RX_STATUS_BE BIT(3) /* Bus Error */
#define MII_CTRL_IF_MASK 3
#define MII_CTRL_SPEED_SHIFT 4
static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
{
+ void __iomem *r;
+
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- __raw_writel(value, ag->mac_base + reg);
+ r = ag->mac_base + reg;
+ __raw_writel(value, r);
+ __raw_readl(r);
break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- reg -= AG71XX_REG_MAC_IFCTL;
- __raw_writel(value, ag->mac_base2 + reg);
+ r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ __raw_writel(value, r);
+ __raw_readl(r);
break;
default:
BUG();
static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
{
+ void __iomem *r;
u32 ret;
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- ret = __raw_readl(ag->mac_base + reg);
+ r = ag->mac_base + reg;
+ ret = __raw_readl(r);
break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- reg -= AG71XX_REG_MAC_IFCTL;
- ret = __raw_readl(ag->mac_base2 + reg);
+ r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ ret = __raw_readl(r);
break;
+ default:
+ BUG();
}
return ret;
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) | mask, r);
+ __raw_readl(r);
break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
__raw_writel(__raw_readl(r) | mask, r);
+ __raw_readl(r);
break;
default:
BUG();
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) & ~mask, r);
+ __raw_readl(r);
break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
__raw_writel(__raw_readl(r) & ~mask, r);
+ __raw_readl(r);
break;
default:
BUG();
static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
{
__raw_writel(value, ag->mii_ctrl);
+ __raw_readl(ag->mii_ctrl);
}
static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
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