#include "ag71xx.h"
+#define AG71XX_DEFAULT_MSG_ENABLE \
+ ( NETIF_MSG_DRV \
+ | NETIF_MSG_PROBE \
+ | NETIF_MSG_LINK \
+ | NETIF_MSG_TIMER \
+ | NETIF_MSG_IFDOWN \
+ | NETIF_MSG_IFUP \
+ | NETIF_MSG_RX_ERR \
+ | NETIF_MSG_TX_ERR )
+
+static int ag71xx_debug = -1;
+
+module_param(ag71xx_debug, int, 0);
+MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
+
+static void ag71xx_dump_dma_regs(struct ag71xx *ag)
+{
+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_TX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
+
+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_RX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
+}
+
static void ag71xx_dump_regs(struct ag71xx *ag)
{
DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
- DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_MII_CFG),
- ag71xx_rr(ag, AG71XX_REG_MII_CMD),
- ag71xx_rr(ag, AG71XX_REG_MII_ADDR));
- DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_MII_CTRL),
- ag71xx_rr(ag, AG71XX_REG_MII_STATUS),
- ag71xx_rr(ag, AG71XX_REG_MII_IND));
DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
- DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
ag->dev->name,
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
}
+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
+{
+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
+ ag->dev->name, label, intr,
+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
+}
+
static void ag71xx_ring_free(struct ag71xx_ring *ring)
{
kfree(ring->buf);
return 0;
-err:
+ err:
return err;
}
break;
}
+ dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+
skb->dev = ag->dev;
skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
break;
}
+ dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+
skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
skb->dev = ag->dev;
+
ring->buf[i].skb = skb;
ring->descs[i].data = virt_to_phys(skb->data);
}
u32 t;
t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
- | (((u32) mac[2]) << 8) | ((u32) mac[2]);
+ | (((u32) mac[2]) << 8) | ((u32) mac[3]);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
}
-#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
- | MAC_CFG1_STX)
+#define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX)
+#define AR71XX_FIFO_CFG5_INIT 0x0007ffef
+
+#define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX | \
+ MAC_CFG1_TFC | MAC_CFG1_RFC)
+#define AR91XX_FIFO_CFG5_INIT 0x0007efef
+
+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
+static void ag71xx_dma_reset(struct ag71xx *ag)
+{
+ int i;
+
+ ag71xx_dump_dma_regs(ag);
+
+ /* stop RX and TX */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+
+ /* clear descriptor addresses */
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
+
+ /* clear pending RX/TX interrupts */
+ for (i = 0; i < 256; i++) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+ }
+
+ /* clear pending errors */
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
+
+ if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
+ ag->dev->name);
+
+ if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
+ ag->dev->name);
+
+ ag71xx_dump_dma_regs(ag);
+}
static void ag71xx_hw_init(struct ag71xx *ag)
{
ar71xx_device_start(pdata->reset_bit);
mdelay(100);
- ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
-
- /* TODO: set max packet size */
-
+ /* setup MAC configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
+ pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00);
+ /* setup max frame length */
+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+ /* setup MII interface type */
ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
- ag71xx_wr(ag, AG71XX_REG_MII_CFG, MII_CFG_CLK_DIV_28);
-
+ /* setup FIFO configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
+ pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
+ : AR71XX_FIFO_CFG5_INIT);
+
+ ag71xx_dma_reset(ag);
}
static void ag71xx_hw_start(struct ag71xx *ag)
static void ag71xx_hw_stop(struct ag71xx *ag)
{
- /* stop RX and TX */
- ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
- ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
-
/* disable all interrupts */
ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
+
+ ag71xx_dma_reset(ag);
}
static int ag71xx_open(struct net_device *dev)
napi_enable(&ag->napi);
netif_carrier_off(dev);
- if (ag->phy_dev) {
- phy_start(ag->phy_dev);
- } else {
- ag->duplex = DUPLEX_FULL;
- ag->speed = SPEED_100;
- ag->link = 1;
- ag71xx_link_update(ag);
- }
+ ag71xx_phy_start(ag);
ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
return 0;
-err:
+ err:
ag71xx_rings_cleanup(ag);
return ret;
}
ag71xx_hw_stop(ag);
netif_carrier_off(dev);
- if (ag->phy_dev) {
- phy_stop(ag->phy_dev);
- } else {
- ag->duplex = -1;
- ag->link = 0;
- ag->speed = 0;
- ag71xx_link_update(ag);
- }
+ ag71xx_phy_stop(ag);
napi_disable(&ag->napi);
desc = &ring->descs[i];
spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
spin_unlock_irqrestore(&ag->lock, flags);
if (!ag71xx_desc_empty(desc))
goto err_drop;
}
- dma_cache_wback_inv((unsigned long)skb->data, skb->len);
+ dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
ring->buf[i].skb = skb;
return 0;
-err_drop:
+ err_drop:
dev->stats.tx_dropped++;
dev_kfree_skb(skb);
static void ag71xx_tx_packets(struct ag71xx *ag)
{
- struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct ag71xx_ring *ring = &ag->tx_ring;
unsigned int sent;
DBG("%s: processing TX ring\n", ag->dev->name);
-#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
-#endif
-
sent = 0;
while (ring->dirty != ring->curr) {
unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
{
struct net_device *dev = ag->dev;
struct ag71xx_ring *ring = &ag->rx_ring;
-#ifndef AG71XX_NAPI_TX
- struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
- unsigned long flags;
-#endif
int done = 0;
-#ifndef AG71XX_NAPI_TX
- spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
- spin_unlock_irqrestore(&ag->lock, flags);
-#endif
-
DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
dev->name, limit, ring->curr, ring->dirty);
break;
}
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+
skb = ring->buf[i].skb;
pktlen = ag71xx_desc_pktlen(desc);
pktlen -= ETH_FCS_LEN;
- /* TODO: move it into the refill function */
- dma_cache_wback_inv((unsigned long)skb->data, pktlen);
skb_put(skb, pktlen);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
- skb->ip_summed = CHECKSUM_UNNECESSARY;
+ skb->ip_summed = CHECKSUM_NONE;
netif_receive_skb(skb);
ring->buf[i].skb = NULL;
done++;
- ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
-
ring->curr++;
if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
ag71xx_ring_rx_refill(ag);
static int ag71xx_poll(struct napi_struct *napi, int limit)
{
struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
-#ifdef AG71XX_NAPI_TX
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
-#endif
struct net_device *dev = ag->dev;
unsigned long flags;
u32 status;
int done;
-#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
ag71xx_tx_packets(ag);
-#endif
DBG("%s: processing RX ring\n", dev->name);
done = ag71xx_rx_packets(ag, limit);
/* TODO: add OOM handler */
- status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
- status &= AG71XX_INT_POLL;
+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+ if (unlikely(status & RX_STATUS_OF)) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
+ dev->stats.rx_fifo_errors++;
+
+ /* restart RX */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+ }
- if ((done < limit) && (!status)) {
+ if ((done < limit) && ((status & RX_STATUS_PR) == 0)) {
DBG("%s: disable polling mode, done=%d, status=%x\n",
dev->name, done, status);
return 0;
}
- if (status & AG71XX_INT_RX_OF) {
- printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
- dev->name);
-
- /* ack interrupt */
- ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
- /* restart RX */
- ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
- }
-
DBG("%s: stay in polling mode, done=%d, status=%x\n",
dev->name, done, status);
return 1;
u32 status;
status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+ ag71xx_dump_intr(ag, "raw", status);
status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
+ ag71xx_dump_intr(ag, "masked", status);
if (unlikely(!status))
return IRQ_NONE;
}
#endif
-#ifndef AG71XX_NAPI_TX
- if (likely(status & AG71XX_INT_TX_PS))
- ag71xx_tx_packets(ag);
-#endif
-
if (likely(status & AG71XX_INT_POLL)) {
ag71xx_int_disable(ag, AG71XX_INT_POLL);
DBG("%s: enable polling mode\n", dev->name);
static int __init ag71xx_probe(struct platform_device *pdev)
{
- static u8 default_mac[ETH_ALEN] = {0x00, 0xba, 0xdb, 0xad, 0xba, 0xd0};
struct net_device *dev;
struct resource *res;
struct ag71xx *ag;
+ struct ag71xx_platform_data *pdata;
int err;
- if (!pdev->dev.platform_data) {
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
dev_err(&pdev->dev, "no platform data specified\n");
err = -ENXIO;
goto err_out;
ag = netdev_priv(dev);
ag->pdev = pdev;
ag->dev = dev;
+ ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
+ ag->msg_enable = netif_msg_init(ag71xx_debug,
+ AG71XX_DEFAULT_MSG_ENABLE);
spin_lock_init(&ag->lock);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
goto err_free_dev;
}
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
+ if (!res) {
+ dev_err(&pdev->dev, "no mac_base2 resource found\n");
+ err = -ENXIO;
+ goto err_unmap_base1;
+ }
+
+ ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
+ if (!ag->mac_base) {
+ dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
+ err = -ENOMEM;
+ goto err_unmap_base1;
+ }
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
if (!res) {
dev_err(&pdev->dev, "no mii_ctrl resource found\n");
err = -ENXIO;
- goto err_unmap_base;
+ goto err_unmap_base2;
}
ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
if (!ag->mii_ctrl) {
dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
err = -ENOMEM;
- goto err_unmap_base;
+ goto err_unmap_base2;
}
dev->irq = platform_get_irq(pdev, 0);
netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
- memcpy(dev->dev_addr, default_mac, ETH_ALEN);
- dev->dev_addr[5] += pdev->id & 0xff;
+ if (is_valid_ether_addr(pdata->mac_addr))
+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
+ else {
+ dev->dev_addr[0] = 0xde;
+ dev->dev_addr[1] = 0xad;
+ get_random_bytes(&dev->dev_addr[2], 3);
+ dev->dev_addr[5] = pdev->id & 0xff;
+ }
err = register_netdev(dev);
if (err) {
ag71xx_dump_regs(ag);
- err = ag71xx_mdio_init(ag, pdev->id);
+ /* Reset the mdio bus explicitly */
+ if (ag->mii_bus) {
+ mutex_lock(&ag->mii_bus->mdio_lock);
+ ag->mii_bus->reset(ag->mii_bus);
+ mutex_unlock(&ag->mii_bus->mdio_lock);
+ }
+
+ err = ag71xx_phy_connect(ag);
if (err)
goto err_unregister_netdev;
return 0;
-err_unregister_netdev:
+ err_unregister_netdev:
unregister_netdev(dev);
-err_free_irq:
+ err_free_irq:
free_irq(dev->irq, dev);
-err_unmap_mii_ctrl:
+ err_unmap_mii_ctrl:
iounmap(ag->mii_ctrl);
-err_unmap_base:
+ err_unmap_base2:
+ iounmap(ag->mac_base2);
+ err_unmap_base1:
iounmap(ag->mac_base);
-err_free_dev:
+ err_free_dev:
kfree(dev);
-err_out:
+ err_out:
platform_set_drvdata(pdev, NULL);
return err;
}
if (dev) {
struct ag71xx *ag = netdev_priv(dev);
- if (ag->phy_dev)
- phy_disconnect(ag->phy_dev);
- ag71xx_mdio_cleanup(ag);
+ ag71xx_phy_disconnect(ag);
unregister_netdev(dev);
free_irq(dev->irq, dev);
iounmap(ag->mii_ctrl);
+ iounmap(ag->mac_base2);
iounmap(ag->mac_base);
kfree(dev);
platform_set_drvdata(pdev, NULL);
static int __init ag71xx_module_init(void)
{
- return platform_driver_register(&ag71xx_driver);
+ int ret;
+
+ ret = ag71xx_mdio_driver_init();
+ if (ret)
+ goto err_out;
+
+ ret = platform_driver_register(&ag71xx_driver);
+ if (ret)
+ goto err_mdio_exit;
+
+ return 0;
+
+ err_mdio_exit:
+ ag71xx_mdio_driver_exit();
+ err_out:
+ return ret;
}
static void __exit ag71xx_module_exit(void)
{
platform_driver_unregister(&ag71xx_driver);
+ ag71xx_mdio_driver_exit();
}
module_init(ag71xx_module_init);
projects / openwrt / svn-archive / archive.git / blobdiff