[ar71xx] add preliminary support for the Ubiquiti LS-SR71 board (thanks to Xianghua...

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / include / asm-mips / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 78cf1ca24437ea1a8119a47868fc00fe01066bbd..c0f3e7bc995d18e716b87fa34369476fa74a3b20 100644 (file)
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx SoC specific definitions
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
@@ -56,6 +56,11 @@
 #define AR71XX_DMA_SIZE                0x10000
 #define AR71XX_STEREO_BASE     (AR71XX_APB_BASE + 0x000B0000)
 #define AR71XX_STEREO_SIZE     0x10000
+#define AR91XX_WMAC_BASE       (AR71XX_APB_BASE + 0x000C0000)
+#define AR91XX_WMAC_SIZE       0x30000
+
+#define AR71XX_MEM_SIZE_MIN    0x0200000
+#define AR71XX_MEM_SIZE_MAX    0x8000000
 
 #define AR71XX_CPU_IRQ_BASE    0
 #define AR71XX_MISC_IRQ_BASE   8
@@ -66,6 +71,7 @@
 #define AR71XX_PCI_IRQ_COUNT   4
 
 #define AR71XX_CPU_IRQ_PCI     (AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_WMAC    (AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_USB     (AR71XX_CPU_IRQ_BASE + 3)
 #define AR71XX_CPU_IRQ_GE0     (AR71XX_CPU_IRQ_BASE + 4)
 #define AR71XX_CPU_IRQ_GE1     (AR71XX_CPU_IRQ_BASE + 5)
@@ -113,6 +119,14 @@ extern unsigned long ar71xx_mach_type;
 #define AR71XX_MACH_RB_493     5       /* Mikrotik RouterBOARD 493/493AH */
 #define AR71XX_MACH_AW_NR580   6       /* AzureWave AW-NR580 */
 #define AR71XX_MACH_AP83       7       /* Atheros AP83 */
+#define AR71XX_MACH_TEW_632BRP 8       /* TRENDnet TEW-632BRP */
+#define AR71XX_MACH_UBNT_RS    9       /* Ubiquiti RouterStation */
+#define AR71XX_MACH_UBNT_LSX   10      /* Ubiquiti LSX */
+#define AR71XX_MACH_WNR2000    11      /* NETGEAR WNR2000 */
+#define AR71XX_MACH_PB42       12      /* Atheros PB42 */
+#define AR71XX_MACH_MZK_W300NH 13      /* Planex MZK-W300NH */
+#define AR71XX_MACH_MZK_W04NU  14      /* Planex MZK-W04NU */
+#define AR71XX_MACH_UBNT_LSSR71        15      /* Ubiquiti LS-SR71 */
 
 /*
  * PLL block
@@ -198,14 +212,14 @@ extern void ar71xx_add_device_usb(void) __init;
 
 #define GPIO_FUNC_STEREO_EN    BIT(17)
 #define GPIO_FUNC_SLIC_EN      BIT(16)
-#define GPIO_FUNC_SPI_CS1_EN   BIT(15)
-#define GPIO_FUNC_SPI_CS0_EN   BIT(14)
-#define GPIO_FUNC_SPI_EN       BIT(13)
+#define GPIO_FUNC_SPI_CS2_EN   BIT(13)
+#define GPIO_FUNC_SPI_CS1_EN   BIT(12)
 #define GPIO_FUNC_UART_EN      BIT(8)
 #define GPIO_FUNC_USB_OC_EN    BIT(4)
 #define GPIO_FUNC_USB_CLK_EN   BIT(0)
 
 #define AR71XX_GPIO_COUNT      16
+#define AR91XX_GPIO_COUNT      22
 
 extern void __iomem *ar71xx_gpio_base;
 
@@ -295,20 +309,26 @@ extern void ar71xx_ddr_flush(u32 reg);
 /*
  * RESET block
  */
-#define RESET_REG_TIMER                        0x00
-#define RESET_REG_TIMER_RELOAD         0x04
-#define RESET_REG_WDOG_CTRL            0x08
-#define RESET_REG_WDOG                 0x0c
-#define RESET_REG_MISC_INT_STATUS      0x10
-#define RESET_REG_MISC_INT_ENABLE      0x14
-#define RESET_REG_PCI_INT_STATUS       0x18
-#define RESET_REG_PCI_INT_ENABLE       0x1c
-#define RESET_REG_GLOBAL_INT_STATUS    0x20
-#define RESET_REG_RESET_MODULE         0x24
-#define RESET_REG_PERFC_CTRL           0x2c
-#define RESET_REG_PERFC0               0x30
-#define RESET_REG_PERFC1               0x34
-#define RESET_REG_REV_ID               0x90
+#define AR71XX_RESET_REG_TIMER                 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD          0x04
+#define AR71XX_RESET_REG_WDOG_CTRL             0x08
+#define AR71XX_RESET_REG_WDOG                  0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS       0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE       0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS                0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE                0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS     0x20
+#define AR71XX_RESET_REG_RESET_MODULE          0x24
+#define AR71XX_RESET_REG_PERFC_CTRL            0x2c
+#define AR71XX_RESET_REG_PERFC0                        0x30
+#define AR71XX_RESET_REG_PERFC1                        0x34
+#define AR71XX_RESET_REG_REV_ID                        0x90
+
+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS     0x18
+#define AR91XX_RESET_REG_RESET_MODULE          0x1c
+#define AR91XX_RESET_REG_PERF_CTRL             0x20
+#define AR91XX_RESET_REG_PERFC0                        0x24
+#define AR91XX_RESET_REG_PERFC1                        0x28
 
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
@@ -333,6 +353,7 @@ extern void ar71xx_ddr_flush(u32 reg);
 
 #define RESET_MODULE_EXTERNAL          BIT(28)
 #define RESET_MODULE_FULL_CHIP         BIT(24)
+#define RESET_MODULE_AMBA2WMAC         BIT(22)
 #define RESET_MODULE_CPU_NMI           BIT(21)
 #define RESET_MODULE_CPU_COLD          BIT(20)
 #define RESET_MODULE_DMA               BIT(19)