[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / include / asm-mips / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 322f3c2ec7682f5ae115084e74d869f39a518b75..e9a69cd56b24ff85be9f3bec77b88e2f29a2ead6 100644 (file)
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -106,13 +106,10 @@ extern enum ar71xx_soc_type ar71xx_soc;
 /*
  * PLL block
  */
-#define PLL_REG_CPU_PLL_CFG    0x00
-#define PLL_REG_SEC_PLL_CFG    0x04
-#define PLL_REG_CPU_CLK_CTRL   0x08
-#define PLL_REG_ETH_INT0_CLK   0x10
-#define PLL_REG_ETH_INT1_CLK   0x14
-#define PLL_REG_ETH_EXT_CLK    0x18
-#define PLL_REG_PCI_CLK                0x1c
+#define AR71XX_PLL_REG_CPU_CONFIG      0x00
+#define AR71XX_PLL_REG_SEC_CONFIG      0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK  0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK  0x14
 
 #define AR71XX_PLL_DIV_SHIFT           3
 #define AR71XX_PLL_DIV_MASK            0x1f
@@ -123,6 +120,14 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR71XX_AHB_DIV_SHIFT           20
 #define AR71XX_AHB_DIV_MASK            0x7
 
+#define AR71XX_ETH0_PLL_SHIFT          17
+#define AR71XX_ETH1_PLL_SHIFT          19
+
+#define AR91XX_PLL_REG_CPU_CONFIG      0x00
+#define AR91XX_PLL_REG_ETH_CONFIG      0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK  0x18
+
 #define AR91XX_PLL_DIV_SHIFT           0
 #define AR91XX_PLL_DIV_MASK            0x3ff
 #define AR91XX_DDR_DIV_SHIFT           22
@@ -130,6 +135,9 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR91XX_AHB_DIV_SHIFT           19
 #define AR91XX_AHB_DIV_MASK            0x1
 
+#define AR91XX_ETH0_PLL_SHIFT          20
+#define AR91XX_ETH1_PLL_SHIFT          22
+
 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
@@ -207,19 +215,24 @@ extern void ar71xx_gpio_function_disable(u32 mask);
 /*
  * DDR_CTRL block
  */
-#define AR71XX_DDR_REG_PCI_WIN0        0x7c
-#define AR71XX_DDR_REG_PCI_WIN1        0x80
-#define AR71XX_DDR_REG_PCI_WIN2        0x84
-#define AR71XX_DDR_REG_PCI_WIN3        0x88
-#define AR71XX_DDR_REG_PCI_WIN4        0x8c
-#define AR71XX_DDR_REG_PCI_WIN5        0x90
-#define AR71XX_DDR_REG_PCI_WIN6        0x94
-#define AR71XX_DDR_REG_PCI_WIN7        0x98
+#define AR71XX_DDR_REG_PCI_WIN0                0x7c
+#define AR71XX_DDR_REG_PCI_WIN1                0x80
+#define AR71XX_DDR_REG_PCI_WIN2                0x84
+#define AR71XX_DDR_REG_PCI_WIN3                0x88
+#define AR71XX_DDR_REG_PCI_WIN4                0x8c
+#define AR71XX_DDR_REG_PCI_WIN5                0x90
+#define AR71XX_DDR_REG_PCI_WIN6                0x94
+#define AR71XX_DDR_REG_PCI_WIN7                0x98
 #define AR71XX_DDR_REG_FLUSH_GE0       0x9c
 #define AR71XX_DDR_REG_FLUSH_GE1       0xa0
 #define AR71XX_DDR_REG_FLUSH_USB       0xa4
 #define AR71XX_DDR_REG_FLUSH_PCI       0xa8
 
+#define AR91XX_DDR_REG_FLUSH_GE0       0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1       0x80
+#define AR91XX_DDR_REG_FLUSH_USB       0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC      0x88
+
 #define PCI_WIN0_OFFS  0x10000000
 #define PCI_WIN1_OFFS  0x11000000
 #define PCI_WIN2_OFFS  0x12000000