extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
+enum ar71xx_soc_type {
+ AR71XX_SOC_UNKNOWN,
+ AR71XX_SOC_AR7130,
+ AR71XX_SOC_AR7141,
+ AR71XX_SOC_AR7161,
+ AR71XX_SOC_AR9130,
+ AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
+extern unsigned long ar71xx_mach_type;
+
+#define AR71XX_MACH_GENERIC 0
+#define AR71XX_MACH_WP543 1 /* Compex WP543 */
+#define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
+#define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
+#define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */
+#define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
+#define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */
+#define AR71XX_MACH_AP83 7 /* Atheros AP83 */
+#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
+#define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */
+#define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */
+
/*
* PLL block
*/
-#define PLL_REG_CPU_PLL_CFG 0x00
-#define PLL_REG_SEC_PLL_CFG 0x04
-#define PLL_REG_CPU_CLK_CTRL 0x08
-#define PLL_REG_ETH_INT0_CLK 0x10
-#define PLL_REG_ETH_INT1_CLK 0x14
-#define PLL_REG_ETH_EXT_CLK 0x18
-#define PLL_REG_PCI_CLK 0x1c
-
-#define PLL_DIV_SHIFT 3
-#define PLL_DIV_MASK 0x1f
-#define CPU_DIV_SHIFT 16
-#define CPU_DIV_MASK 0x3
-#define DDR_DIV_SHIFT 18
-#define DDR_DIV_MASK 0x3
-#define AHB_DIV_SHIFT 20
-#define AHB_DIV_MASK 0x7
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
+
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
+#define AR91XX_PLL_REG_CPU_CONFIG 0x00
+#define AR91XX_PLL_REG_ETH_CONFIG 0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
+
+#define AR91XX_PLL_DIV_SHIFT 0
+#define AR91XX_PLL_DIV_MASK 0x3ff
+#define AR91XX_DDR_DIV_SHIFT 22
+#define AR91XX_DDR_DIV_MASK 0x3
+#define AR91XX_AHB_DIV_SHIFT 19
+#define AR91XX_AHB_DIV_MASK 0x1
+
+#define AR91XX_ETH0_PLL_SHIFT 20
+#define AR91XX_ETH1_PLL_SHIFT 22
extern void __iomem *ar71xx_pll_base;
#define GPIO_FUNC_STEREO_EN BIT(17)
#define GPIO_FUNC_SLIC_EN BIT(16)
-#define GPIO_FUNC_SPI_CS1_EN BIT(15)
-#define GPIO_FUNC_SPI_CS0_EN BIT(14)
-#define GPIO_FUNC_SPI_EN BIT(13)
+#define GPIO_FUNC_SPI_CS2_EN BIT(13)
+#define GPIO_FUNC_SPI_CS1_EN BIT(12)
#define GPIO_FUNC_UART_EN BIT(8)
#define GPIO_FUNC_USB_OC_EN BIT(4)
#define GPIO_FUNC_USB_CLK_EN BIT(0)
#define AR71XX_GPIO_COUNT 16
+#define AR91XX_GPIO_COUNT 22
extern void __iomem *ar71xx_gpio_base;
/*
* DDR_CTRL block
*/
-#define DDR_REG_PCI_WIN0 0x7c
-#define DDR_REG_PCI_WIN1 0x80
-#define DDR_REG_PCI_WIN2 0x84
-#define DDR_REG_PCI_WIN3 0x88
-#define DDR_REG_PCI_WIN4 0x8c
-#define DDR_REG_PCI_WIN5 0x90
-#define DDR_REG_PCI_WIN6 0x94
-#define DDR_REG_PCI_WIN7 0x98
-#define DDR_REG_FLUSH_GE0 0x9c
-#define DDR_REG_FLUSH_GE1 0xa0
-#define DDR_REG_FLUSH_USB 0xa4
-#define DDR_REG_FLUSH_PCI 0xa8
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
+
+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1 0x80
+#define AR91XX_DDR_REG_FLUSH_USB 0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
#define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000
/*
* RESET block
*/
-#define RESET_REG_TIMER 0x00
-#define RESET_REG_TIMER_RELOAD 0x04
-#define RESET_REG_WDOG_CTRL 0x08
-#define RESET_REG_WDOG 0x0c
-#define RESET_REG_MISC_INT_STATUS 0x10
-#define RESET_REG_MISC_INT_ENABLE 0x14
-#define RESET_REG_PCI_INT_STATUS 0x18
-#define RESET_REG_PCI_INT_ENABLE 0x1c
-#define RESET_REG_GLOBAL_INT_STATUS 0x20
-#define RESET_REG_RESET_MODULE 0x24
-#define RESET_REG_PERFC_CTRL 0x2c
-#define RESET_REG_PERFC0 0x30
-#define RESET_REG_PERFC1 0x34
-#define RESET_REG_REV_ID 0x90
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
+
+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
+#define AR91XX_RESET_REG_RESET_MODULE 0x1c
+#define AR91XX_RESET_REG_PERF_CTRL 0x20
+#define AR91XX_RESET_REG_PERFC0 0x24
+#define AR91XX_RESET_REG_PERFC1 0x28
+
+#define WDOG_CTRL_LAST_RESET BIT(31)
+#define WDOG_CTRL_ACTION_MASK 3
+#define WDOG_CTRL_ACTION_NONE 0 /* no action */
+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define REV_ID_CHIP_AR7130 0xa0
#define REV_ID_CHIP_AR7141 0xa1
#define REV_ID_CHIP_AR7161 0xa2
+#define REV_ID_CHIP_AR9130 0xb0
+#define REV_ID_CHIP_AR9132 0xb1
#define REV_ID_REVISION_MASK 0x3
#define REV_ID_REVISION_SHIFT 2
#define MII1_CTRL_IF_RGMII 0
#define MII1_CTRL_IF_RMII 1
-#include <asm/bootinfo.h>
-#include <linux/init.h>
-
-#define ar71xx_print_cmdline() do { \
- printk(KERN_DEBUG "%s:%d arcs_cmdline:'%s'\n", \
- __FUNCTION__, __LINE__, arcs_cmdline); \
- printk(KERN_DEBUG "%s:%d boot_command_line:'%s'\n", \
- __FUNCTION__, __LINE__, boot_command_line); \
- } while (0)
-
#endif /* __ASSEMBLER__ */
#endif /* __ASM_MACH_AR71XX_H */
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