ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch

diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
index e4e2c30d94bf32add41bee42d517a7171f1af4ac..8d24c742d37c5f7a5ad8d12e09aa2ff34f9a4f7a 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
+++ b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
@@ -165,7 +165,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  }
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -298,6 +298,7 @@
+@@ -300,6 +300,7 @@
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
@@ -173,7 +173,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  
  #define MISC_INT_ETHSW                        BIT(12)
  #define MISC_INT_TIMER4                       BIT(10)
-@@ -396,6 +397,37 @@
+@@ -398,6 +399,37 @@
         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
         AR934X_PCIE_WMAC_INT_PCIE_RC3)