ar71xx: update 3.3 patches

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 601-MIPS-ath79-add-more-register-defines.patch

diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 74b3c831f133a67a78f6bcffca7bc6a3507139ec..a5394add91a9cbc9970054dd2fba91acad54fe1e 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -76,7 +76,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -285,7 +306,11 @@
+@@ -285,16 +306,50 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
@@ -88,16 +88,46 @@
  #define AR933X_RESET_USB_HOST         BIT(5)
  #define AR933X_RESET_USB_PHY          BIT(4)
  #define AR933X_RESET_USBSUS_OVERRIDE  BIT(3)
-@@ -323,6 +348,8 @@
- #define AR934X_RESET_MBOX             BIT(1)
- #define AR934X_RESET_I2S              BIT(0)
+ 
++#define AR934X_RESET_HOST             BIT(31)
++#define AR934X_RESET_SLIC             BIT(30)
++#define AR934X_RESET_HDMA             BIT(29)
++#define AR934X_RESET_EXTERNAL         BIT(28)
++#define AR934X_RESET_RTC              BIT(27)
++#define AR934X_RESET_PCIE_EP_INT      BIT(26)
++#define AR934X_RESET_CHKSUM_ACC               BIT(25)
++#define AR934X_RESET_FULL_CHIP                BIT(24)
++#define AR934X_RESET_GE1_MDIO         BIT(23)
++#define AR934X_RESET_GE0_MDIO         BIT(22)
++#define AR934X_RESET_CPU_NMI          BIT(21)
++#define AR934X_RESET_CPU_COLD         BIT(20)
++#define AR934X_RESET_HOST_RESET_INT   BIT(19)
++#define AR934X_RESET_PCIE_EP          BIT(18)
++#define AR934X_RESET_UART1            BIT(17)
++#define AR934X_RESET_DDR              BIT(16)
++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define AR934X_RESET_NANDF            BIT(14)
++#define AR934X_RESET_GE1_MAC          BIT(13)
++#define AR934X_RESET_ETH_SWITCH_ANALOG        BIT(12)
+ #define AR934X_RESET_USB_PHY_ANALOG   BIT(11)
++#define AR934X_RESET_HOST_DMA_INT     BIT(10)
++#define AR934X_RESET_GE0_MAC          BIT(9)
++#define AR934X_RESET_ETH_SWITCH               BIT(8)
++#define AR934X_RESET_PCIE_PHY         BIT(7)
++#define AR934X_RESET_PCIE             BIT(6)
+ #define AR934X_RESET_USB_HOST         BIT(5)
+ #define AR934X_RESET_USB_PHY          BIT(4)
+ #define AR934X_RESET_USBSUS_OVERRIDE  BIT(3)
++#define AR934X_RESET_LUT              BIT(2)
++#define AR934X_RESET_MBOX             BIT(1)
++#define AR934X_RESET_I2S              BIT(0)
  
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -427,6 +454,14 @@
+@@ -399,10 +454,138 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
@@ -110,9 +140,8 @@
 +#define AR934X_GPIO_REG_FUNC          0x6c
 +
  #define AR71XX_GPIO_COUNT             16
- #define AR7240_GPIO_COUNT             18
- #define AR7241_GPIO_COUNT             20
-@@ -434,4 +469,124 @@
+ #define AR724X_GPIO_COUNT             18
+ #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23