+ ar231x_board.radio = addr + 0x10000;
+
+ if (ar231x_board.radio) {
-+ /* broken board data detected, use radio data to find the offset,
-+ * user will fix this */
++ /* broken board data detected, use radio data to find the
++ * offset, user will fix this */
+ return 1;
+ }
+ return 0;
+ * Platform device information for the Ethernet MAC
+ */
+struct ar231x_eth {
-+ u32 reset_base;
++ void (*reset_set)(u32);
++ void (*reset_clear)(u32);
+ u32 reset_mac;
+ u32 reset_phy;
-+ u32 phy_base;
+ struct ar231x_board_config *config;
+ char *macaddr;
+};
+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
-@@ -0,0 +1,76 @@
+@@ -0,0 +1,79 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ return 0;
+}
+
-+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
++static inline dma_addr_t
++plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
+ return virt_to_phys(addr) + ar231x_dev_offset(dev);
+}
+
-+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
++static inline dma_addr_t
++plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+ return page_to_phys(page) + ar231x_dev_offset(dev);
+}
+
-+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
-+ dma_addr_t dma_addr)
++static inline unsigned long
++plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+ return dma_addr - ar231x_dev_offset(dev);
+}
+
-+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
-+ size_t size, enum dma_data_direction direction)
++static inline void
++plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
++ enum dma_data_direction direction)
+{
+}
+
+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
-@@ -0,0 +1,580 @@
+@@ -0,0 +1,617 @@
+/*
+ * Register definitions for AR2315+
+ *
+#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
+#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
++
++/*
++ * Miscellaneous interrupts, which share IP2.
++ */
++#define AR2315_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
++#define AR2315_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+1)
++#define AR2315_MISC_IRQ_I2C_RSVD (AR531X_MISC_IRQ_BASE+2)
++#define AR2315_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+3)
++#define AR2315_MISC_IRQ_AHB (AR531X_MISC_IRQ_BASE+4)
++#define AR2315_MISC_IRQ_APB (AR531X_MISC_IRQ_BASE+5)
++#define AR2315_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+6)
++#define AR2315_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+7)
++#define AR2315_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+8)
++#define AR2315_MISC_IRQ_IR_RSVD (AR531X_MISC_IRQ_BASE+9)
++#define AR2315_MISC_IRQ_COUNT 10
++
++
+/*
+ * Address map
+ */
+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
-+#define AR2315_UART0 0x11100003 /* UART MMR */
-+#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
++#define AR2315_UART0 0x11100000 /* UART MMR */
++#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
+#define AR2315_PCIEXT 0x80000000 /* pci external */
+
++/* MII registers offset inside Ethernet MMR region */
++#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
++
+/*
+ * Reset Register
+ */
+#define AR2315_RESET_COLD_APB 0x00000002
+#define AR2315_RESET_COLD_CPU 0x00000004
+#define AR2315_RESET_COLD_CPUWARM 0x00000008
-+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
++#define AR2315_RESET_SYSTEM \
++ (RESET_COLD_CPU |\
++ RESET_COLD_APB |\
++ RESET_COLD_AHB) /* full system */
+#define AR2317_RESET_SYSTEM 0x00000010
+
+
+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
+
-+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
-+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
-+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
-+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
-+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
-+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
-+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
-+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
-+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
-+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
-+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
-+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
++/* warm reset WLAN0 MAC */
++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
++/* warm reset WLAN0 BaseBand */
++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
++/* warm reset MPEG-TS */
++#define AR2315_RESET_MPEGTS_RSVD 0x00000004
++/* warm reset PCI ahb/dma */
++#define AR2315_RESET_PCIDMA 0x00000008
++/* warm reset memory controller */
++#define AR2315_RESET_MEMCTL 0x00000010
++/* warm reset local bus */
++#define AR2315_RESET_LOCAL 0x00000020
++/* warm reset I2C bus */
++#define AR2315_RESET_I2C_RSVD 0x00000040
++/* warm reset SPI interface */
++#define AR2315_RESET_SPI 0x00000080
++/* warm reset UART0 */
++#define AR2315_RESET_UART0 0x00000100
++/* warm reset IR interface */
++#define AR2315_RESET_IR_RSVD 0x00000200
++/* cold reset ENET0 phy */
++#define AR2315_RESET_EPHY0 0x00000400
++/* cold reset ENET0 mac */
++#define AR2315_RESET_ENET0 0x00000800
+
+/*
+ * AHB master arbitration control
+ */
+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
+
-+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
-+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
-+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
-+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
-+#define AR2315_ARB_PCI 0x00000010 /* PCI */
-+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
-+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
++/* CPU, default */
++#define AR2315_ARB_CPU 0x00000001
++/* WLAN */
++#define AR2315_ARB_WLAN 0x00000002
++/* MPEG-TS */
++#define AR2315_ARB_MPEGTS_RSVD 0x00000004
++/* LOCAL */
++#define AR2315_ARB_LOCAL 0x00000008
++/* PCI */
++#define AR2315_ARB_PCI 0x00000010
++/* Ethernet */
++#define AR2315_ARB_ETHERNET 0x00000020
++/* retry policy, debug only */
++#define AR2315_ARB_RETRY 0x00000100
+
+/*
+ * Config Register
+ */
+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
+
-+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
-+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
-+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
-+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
-+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
-+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
-+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
-+
-+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
-+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
++/* EC - AHB bridge endianess */
++#define AR2315_CONFIG_AHB 0x00000001
++/* WLAN byteswap */
++#define AR2315_CONFIG_WLAN 0x00000002
++/* MPEG-TS byteswap */
++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
++/* PCI byteswap */
++#define AR2315_CONFIG_PCI 0x00000008
++/* Memory controller endianess */
++#define AR2315_CONFIG_MEMCTL 0x00000010
++/* Local bus byteswap */
++#define AR2315_CONFIG_LOCAL 0x00000020
++/* Ethernet byteswap */
++#define AR2315_CONFIG_ETHERNET 0x00000040
++
++/* CPU write buffer merge */
++#define AR2315_CONFIG_MERGE 0x00000200
++/* CPU big endian */
++#define AR2315_CONFIG_CPU 0x00000400
+#define AR2315_CONFIG_PCIAHB 0x00000800
+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
-+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
++/* SPI byteswap */
++#define AR2315_CONFIG_SPI 0x00008000
+#define AR2315_CONFIG_CPU_DRAM 0x00010000
+#define AR2315_CONFIG_CPU_PCI 0x00020000
+#define AR2315_CONFIG_CPU_MMR 0x00040000
+#define AR2315_IF_DISABLED 0
+#define AR2315_IF_PCI 1
+#define AR2315_IF_TS_LOCAL 2
-+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
++/* only for emulation with separate pins */
++#define AR2315_IF_ALL 3
+#define AR2315_IF_LOCAL_HOST 0x00000008
+#define AR2315_IF_PCI_HOST 0x00000010
+#define AR2315_IF_PCI_INTR 0x00000020
+#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
+#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
+
-+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
-+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
-+#define AR2315_ISR_SPI 0x0004 /* SPI bus */
-+#define AR2315_ISR_AHB 0x0008 /* AHB error */
-+#define AR2315_ISR_APB 0x0010 /* APB error */
-+#define AR2315_ISR_TIMER 0x0020 /* timer */
-+#define AR2315_ISR_GPIO 0x0040 /* GPIO */
-+#define AR2315_ISR_WD 0x0080 /* watchdog */
-+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
-+
-+#define AR2315_GISR_MISC 0x0001
-+#define AR2315_GISR_WLAN0 0x0002
-+#define AR2315_GISR_MPEGTS_RSVD 0x0004
-+#define AR2315_GISR_LOCALPCI 0x0008
-+#define AR2315_GISR_WMACPOLL 0x0010
-+#define AR2315_GISR_TIMER 0x0020
-+#define AR2315_GISR_ETHERNET 0x0040
++#define AR2315_ISR_UART0 0x0001 /* high speed UART */
++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
++#define AR2315_ISR_SPI 0x0004 /* SPI bus */
++#define AR2315_ISR_AHB 0x0008 /* AHB error */
++#define AR2315_ISR_APB 0x0010 /* APB error */
++#define AR2315_ISR_TIMER 0x0020 /* timer */
++#define AR2315_ISR_GPIO 0x0040 /* GPIO */
++#define AR2315_ISR_WD 0x0080 /* watchdog */
++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
++
++#define AR2315_GISR_MISC 0x0001
++#define AR2315_GISR_WLAN0 0x0002
++#define AR2315_GISR_MPEGTS_RSVD 0x0004
++#define AR2315_GISR_LOCALPCI 0x0008
++#define AR2315_GISR_WMACPOLL 0x0010
++#define AR2315_GISR_TIMER 0x0020
++#define AR2315_GISR_ETHERNET 0x0040
+
+/*
+ * Interrupt routing from IO to the processor IP bits
+#define AR2315_WD (AR2315_DSLBASE + 0x0038)
+#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
+
-+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
-+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
-+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
+
+/*
+ * CPU Performance Counters
+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
+
-+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
-+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
-+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
-+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
-+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
-+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
-+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
-+
-+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
-+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
-+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
-+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
-+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
-+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
-+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
++
++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
+
+/*
+ * AHB Error Reporting.
+ */
+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
-+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
++#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
+
-+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
-+#define AR2315_GPIO_CR_I(x) (0) /* input */
++#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
++#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
++#define AR2315_GPIO_DIR_I(x) (0) /* input */
+
-+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
-+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
-+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
-+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
+
-+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
-+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
-+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
-+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
-+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
++ * AR5313_GPIO_INT_* macros */
++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
+
+#define AR2315_RESET_GPIO 5
+#define AR2315_NUM_GPIO 22
+#define SDRAM_BANKADDR_BITS_S 3
+
+/*
-+ * SPI Flash Interface Registers
-+ */
-+
-+#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
-+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
-+#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
-+
-+#define SPI_CTL_START 0x00000100
-+#define SPI_CTL_BUSY 0x00010000
-+#define SPI_CTL_TXCNT_MASK 0x0000000f
-+#define SPI_CTL_RXCNT_MASK 0x000000f0
-+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
-+#define SPI_CTL_SIZE_MASK 0x00060000
-+
-+#define SPI_CTL_CLK_SEL_MASK 0x03000000
-+#define SPI_OPCODE_MASK 0x000000ff
-+
-+/*
+ * PCI Bus Interface Registers
+ */
+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
-+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
+
+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
-+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
++ * disable */
+
+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
+
+#define AR2315_PCI_EXT_INT 0x02000000
+#define AR2315_PCI_ABORT_INT 0x04000000
+
-+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
+
+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
+ * Local Bus Interface Registers
+ */
+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
-+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
-+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
-+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
-+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
-+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
-+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
-+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
-+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
-+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
-+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
-+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
-+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
-+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
-+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
-+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
-+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
-+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
-+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
-+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
-+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
-+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
-+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
-+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
+
+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
-+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
+
+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
-+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
+
+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
-+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
-+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
-+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
-+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
-+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
+#define AR2315_LBM_TIMEOUT_SHFT 7
+#define AR2315_LBM_PORTMUX 0x07000000
+/*
+ * IR Interface Registers
+ */
-+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
-+
-+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
-+
-+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
-+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
-+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
-+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
-+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
-+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
-+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
-+
-+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
-+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
-+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
-+
-+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
-+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
-+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
-+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
-+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
-+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
-+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
-+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
-+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
-+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
++
++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
++
++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
++#define AR2315_IRCTL_SAMPLECLK_SHFT 1
++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
++
++#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
++
++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
++#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
+
+#define HOST_PCI_DEV_ID 3
+#define HOST_PCI_MBAR0 0x10000000
+#endif /* __AR2315_REG_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
-@@ -0,0 +1,233 @@
+@@ -0,0 +1,253 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
+
++/*
++ * Miscellaneous interrupts, which share IP6.
++ */
++#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
++#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
++#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
++#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
++#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
++#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
++#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
++#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
++#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
++#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
++#define AR531X_MISC_IRQ_COUNT 10
++
++
+/* Address Map */
+#define AR531X_WLAN0 0x18000000
+#define AR531X_WLAN1 0x18500000
+#define AR531X_SDRAMCTL 0x18300000
+#define AR531X_FLASHCTL 0x18400000
+#define AR531X_APBBASE 0x1c000000
++#define AR531X_UART0 0x1c000000 /* UART MMR */
+#define AR531X_FLASH 0x1e000000
-+#define AR531X_UART0 0xbc000003 /* UART MMR */
+
+/*
+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
+
++/* MII registers offset inside Ethernet MMR region */
++#define AR531X_ENET0_MII (AR531X_ENET0 + 0x14)
++#define AR531X_ENET1_MII (AR531X_ENET1 + 0x14)
++
+/*
+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\
+ * should be considered available.
+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
+
+/* GPIO Control Register bit field definitions */
-+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
-+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
-+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
-+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
+#define AR531X_NUM_GPIO 8
+
+
+
--- /dev/null
+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,579 @@
+@@ -0,0 +1,540 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include "devices.h"
+#include "ar5312.h"
+
-+static void
-+ar5312_misc_irq_dispatch(void)
++static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
++ ar231x_read_reg(AR531X_IMR);
+
+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
+ do_IRQ(AR531X_MISC_IRQ_TIMER);
+ else if (pending & CAUSEF_IP5)
+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
+ else if (pending & CAUSEF_IP6)
-+ ar5312_misc_irq_dispatch();
++ do_IRQ(AR5312_IRQ_MISC_INTRS);
+ else if (pending & CAUSEF_IP7)
+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
+}
+
+/* Enable the specified AR531X_MISC_IRQ interrupt */
+static void
-+ar5312_misc_intr_enable(struct irq_data *d)
++ar5312_misc_irq_unmask(struct irq_data *d)
+{
+ unsigned int imr;
+
+
+/* Disable the specified AR531X_MISC_IRQ interrupt */
+static void
-+ar5312_misc_intr_disable(struct irq_data *d)
++ar5312_misc_irq_mask(struct irq_data *d)
+{
+ unsigned int imr;
+
+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */
+}
+
-+static struct irq_chip ar5312_misc_intr_controller = {
-+ .irq_mask = ar5312_misc_intr_disable,
-+ .irq_unmask = ar5312_misc_intr_enable,
++static struct irq_chip ar5312_misc_irq_chip = {
++ .name = "AR5312-MISC",
++ .irq_unmask = ar5312_misc_irq_unmask,
++ .irq_mask = ar5312_misc_irq_mask,
+};
+
+
+};
+
+
-+static struct irqaction cascade = {
-+ .handler = no_action,
-+ .name = "cascade",
-+};
-+
+void __init ar5312_irq_init(void)
+{
+ int i;
+ ar231x_irq_dispatch = ar5312_irq_dispatch;
+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
+ int irq = AR531X_MISC_IRQ_BASE + i;
-+ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
-+ handle_level_irq);
++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
++ handle_level_irq);
+ }
+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
-+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
-+}
-+
-+static u32
-+ar5312_gpio_set_output(u32 mask, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = ar231x_read_reg(AR531X_GPIO_CR);
-+ reg |= mask;
-+ reg &= ~val;
-+ ar231x_write_reg(AR531X_GPIO_CR, reg);
-+ return reg;
-+}
-+
-+static u32
-+ar5312_gpio_get(u32 valid_mask)
-+{
-+ u32 reg;
-+ reg = ar231x_read_reg(AR531X_GPIO_DI);
-+ reg &= valid_mask;
-+ return reg;
-+}
-+
-+static u32
-+ar5312_gpio_set(u32 mask, u32 value)
-+{
-+ u32 reg;
-+ reg = ar231x_read_reg(AR531X_GPIO_DO);
-+ reg &= ~mask;
-+ reg |= value;
-+ ar231x_write_reg(AR531X_GPIO_DO, reg);
-+ return reg;
++ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
+}
+
+/*
-+ * gpiolib implementations. Original mask based methods preserved
++ * gpiolib implementations
+ */
+static int
+ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ u32 rett;
-+ if (!(gpch->valid_mask & mask))
-+ return 0;
-+ rett = ar5312_gpio_get(gpch->valid_mask);
-+ return !!(rett & mask);
++ return (ar231x_read_reg(AR531X_GPIO_DI) >> gpio) & 1;
+}
+
+static void
+ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return;
-+ ar5312_gpio_set(mask, (!!value) * mask);
++ u32 reg = ar231x_read_reg(AR531X_GPIO_DO);
++ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
++ ar231x_write_reg(AR531X_GPIO_DO, reg);
+}
+
+static int
+ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return -ENXIO;
-+ ar5312_gpio_set_output(mask, 0);
++ ar231x_mask_reg(AR531X_GPIO_CR, 0, 1 << gpio);
+ return 0;
+}
++
+static int
+ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return -ENXIO;
-+ ar5312_gpio_set_output(mask, mask);
-+ ar5312_gpio_set(mask, (!!value) * mask);
++ ar231x_mask_reg(AR531X_GPIO_CR, 1 << gpio, 0);
++ ar5312_gpio_set_value(chip, gpio, value);
+ return 0;
+}
+
-+static struct ar231x_gpio_chip ar5312_gpio_chip = {
-+ .valid_mask = (1 << 22) - 1,
-+ .chip = {
-+ .label = "ar5312-gpio",
-+ .direction_input = ar5312_gpio_direction_input,
-+ .direction_output = ar5312_gpio_direction_output,
-+ .set = ar5312_gpio_set_value,
-+ .get = ar5312_gpio_get_value,
-+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
-+ }
++static struct gpio_chip ar5312_gpio_chip = {
++ .label = "ar5312-gpio",
++ .direction_input = ar5312_gpio_direction_input,
++ .direction_output = ar5312_gpio_direction_output,
++ .set = ar5312_gpio_set_value,
++ .get = ar5312_gpio_get_value,
++ .base = 0,
++ .ngpio = AR531X_NUM_GPIO, /* 8 */
+};
+
+/* end of gpiolib */
+
++static void ar5312_device_reset_set(u32 mask)
++{
++ u32 val;
++
++ val = ar231x_read_reg(AR531X_RESET);
++ ar231x_write_reg(AR531X_RESET, val | mask);
++}
++
++static void ar5312_device_reset_clear(u32 mask)
++{
++ u32 val;
++
++ val = ar231x_read_reg(AR531X_RESET);
++ ar231x_write_reg(AR531X_RESET, val & ~mask);
++}
++
+static struct physmap_flash_data ar5312_flash_data = {
+ .width = 2,
+};
+};
+
+static struct ar231x_eth ar5312_eth0_data = {
-+ .reset_base = AR531X_RESET,
++ .reset_set = ar5312_device_reset_set,
++ .reset_clear = ar5312_device_reset_clear,
+ .reset_mac = AR531X_RESET_ENET0,
+ .reset_phy = AR531X_RESET_EPHY0,
-+ .phy_base = KSEG1ADDR(AR531X_ENET0),
+ .config = &ar231x_board,
+};
+
+static struct ar231x_eth ar5312_eth1_data = {
-+ .reset_base = AR531X_RESET,
++ .reset_set = ar5312_device_reset_set,
++ .reset_clear = ar5312_device_reset_clear,
+ .reset_mac = AR531X_RESET_ENET1,
+ .reset_phy = AR531X_RESET_EPHY1,
-+ .phy_base = KSEG1ADDR(AR531X_ENET1),
+ .config = &ar231x_board,
+};
+
+
+ /* Disable other flash banks */
+ ar231x_write_reg(AR531X_FLASHCTL1,
-+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
++ ar231x_read_reg(AR531X_FLASHCTL1) &
++ ~(FLASHCTL_E | FLASHCTL_AC));
+
+ ar231x_write_reg(AR531X_FLASHCTL2,
-+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
++ ar231x_read_reg(AR531X_FLASHCTL2) &
++ ~(FLASHCTL_E | FLASHCTL_AC));
+
+ return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
+}
+ switch (ar231x_devtype) {
+ case DEV_TYPE_AR5312:
+ ar5312_eth0_data.macaddr = config->enet0_mac;
-+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
-+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
++ ar231x_add_ethernet(0, AR531X_ENET0, "eth0_mii",
++ AR531X_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
++ &ar5312_eth0_data);
+
+ ar5312_eth1_data.macaddr = config->enet1_mac;
-+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
-+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
++ ar231x_add_ethernet(1, AR531X_ENET1, "eth1_mii",
++ AR531X_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
++ &ar5312_eth1_data);
+
+ if (!ar231x_board.radio)
+ return 0;
+ */
+ case DEV_TYPE_AR2312:
+ case DEV_TYPE_AR2313:
-+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
+ ar5312_eth1_data.macaddr = config->enet0_mac;
-+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
-+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
++ ar231x_add_ethernet(1, AR531X_ENET1, "eth0_mii",
++ AR531X_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
++ &ar5312_eth1_data);
+
+ if (!ar231x_board.radio)
+ return 0;
+ *
+ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
+ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
-+ * flash, Timer, Watchdog Timer)
++ * flash, Timer, Watchdog Timer)
+ *
+ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
+ *
+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
+}
+
-+int __init
++static int __init
+ar5312_gpio_init(void)
+{
+ int ret;
-+ struct ar231x_gpio_chip *gpch;
-+ gpch = &ar5312_gpio_chip;
-+ ret = gpiochip_add(&gpch->chip);
++ ret = gpiochip_add(&ar5312_gpio_chip);
+ if (ret) {
-+ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
+ return ret;
+ }
-+ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
-+ gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
++ ar5312_gpio_chip.ngpio);
+ return ret;
+}
+
+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
+
+ _machine_restart = ar5312_restart;
-+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
++ ar231x_serial_setup(AR531X_UART0, AR531X_MISC_IRQ_UART0,
++ ar5312_sys_frequency());
+}
+
--- /dev/null
+++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,693 @@
+@@ -0,0 +1,556 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+
+static u32 gpiointmask, gpiointval;
+
-+static inline void ar2315_gpio_irq(void)
++static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ u32 pend;
+ int bit = -1;
+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
+
+ /* Enable interrupt with edge detection */
-+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
++ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
++ AR2315_GPIO_DIR_I(bit))
+ return;
+
+ if (bit >= 0)
+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
+}
+
++static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
++ ar231x_read_reg(AR2315_IMR);
++
++ if (misc_intr & AR2315_ISR_SPI)
++ do_IRQ(AR2315_MISC_IRQ_SPI);
++ else if (misc_intr & AR2315_ISR_TIMER)
++ do_IRQ(AR2315_MISC_IRQ_TIMER);
++ else if (misc_intr & AR2315_ISR_AHB)
++ do_IRQ(AR2315_MISC_IRQ_AHB);
++ else if (misc_intr & AR2315_ISR_GPIO)
++ do_IRQ(AR2315_MISC_IRQ_GPIO);
++ else if (misc_intr & AR2315_ISR_UART0)
++ do_IRQ(AR2315_MISC_IRQ_UART0);
++ else if (misc_intr & AR2315_ISR_WD) {
++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
++ do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
++ } else
++ do_IRQ(AR2315_MISC_IRQ_NONE);
++}
+
+/*
+ * Called when an interrupt is received, this function
+ do_IRQ(AR2315_IRQ_WLAN0_INTRS);
+ else if (pending & CAUSEF_IP4)
+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
-+ else if (pending & CAUSEF_IP2) {
-+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
-+
-+ if (misc_intr & AR2315_ISR_SPI)
-+ do_IRQ(AR531X_MISC_IRQ_SPI);
-+ else if (misc_intr & AR2315_ISR_TIMER)
-+ do_IRQ(AR531X_MISC_IRQ_TIMER);
-+ else if (misc_intr & AR2315_ISR_AHB)
-+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
-+ else if (misc_intr & AR2315_ISR_GPIO)
-+ ar2315_gpio_irq();
-+ else if (misc_intr & AR2315_ISR_UART0)
-+ do_IRQ(AR531X_MISC_IRQ_UART0);
-+ else if (misc_intr & AR2315_ISR_WD)
-+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
-+ else
-+ do_IRQ(AR531X_MISC_IRQ_NONE);
-+ } else if (pending & CAUSEF_IP7)
++ else if (pending & CAUSEF_IP2)
++ do_IRQ(AR2315_IRQ_MISC_INTRS);
++ else if (pending & CAUSEF_IP7)
+ do_IRQ(AR531X_IRQ_CPU_CLOCK);
+}
+
+ ar231x_write_reg(AR2315_GPIO_INT, reg);
+}
+
-+static void ar2315_gpio_intr_enable(struct irq_data *d)
++static void ar2315_gpio_irq_unmask(struct irq_data *d)
+{
+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
+
+ /* Enable interrupt with edge detection */
-+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
++ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
++ AR2315_GPIO_DIR_I(gpio))
+ return;
+
+ gpiointmask |= (1 << gpio);
+ ar2315_set_gpiointmask(gpio, 3);
+}
+
-+static void ar2315_gpio_intr_disable(struct irq_data *d)
++static void ar2315_gpio_irq_mask(struct irq_data *d)
+{
+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
+
+ ar2315_set_gpiointmask(gpio, 0);
+}
+
-+static struct irq_chip ar2315_gpio_intr_controller = {
-+ .irq_mask = ar2315_gpio_intr_disable,
-+ .irq_unmask = ar2315_gpio_intr_enable,
++static struct irq_chip ar2315_gpio_irq_chip = {
++ .name = "AR2315-GPIO",
++ .irq_unmask = ar2315_gpio_irq_unmask,
++ .irq_mask = ar2315_gpio_irq_mask,
+};
+
+static void
-+ar2315_misc_intr_enable(struct irq_data *d)
++ar2315_misc_irq_unmask(struct irq_data *d)
+{
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ switch (d->irq) {
-+ case AR531X_MISC_IRQ_SPI:
-+ imr |= AR2315_ISR_SPI;
-+ break;
-+ case AR531X_MISC_IRQ_TIMER:
-+ imr |= AR2315_ISR_TIMER;
-+ break;
-+ case AR531X_MISC_IRQ_AHB_PROC:
-+ imr |= AR2315_ISR_AHB;
-+ break;
-+ case AR531X_MISC_IRQ_GPIO:
-+ imr |= AR2315_ISR_GPIO;
-+ break;
-+ case AR531X_MISC_IRQ_UART0:
-+ imr |= AR2315_ISR_UART0;
-+ break;
-+ case AR531X_MISC_IRQ_WATCHDOG:
-+ imr |= AR2315_ISR_WD;
-+ break;
-+ default:
-+ break;
-+ }
++ imr |= 1 << (d->irq - AR531X_MISC_IRQ_BASE - 1);
+ ar231x_write_reg(AR2315_IMR, imr);
+}
+
+static void
-+ar2315_misc_intr_disable(struct irq_data *d)
++ar2315_misc_irq_mask(struct irq_data *d)
+{
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ switch (d->irq) {
-+ case AR531X_MISC_IRQ_SPI:
-+ imr &= ~AR2315_ISR_SPI;
-+ break;
-+ case AR531X_MISC_IRQ_TIMER:
-+ imr &= ~AR2315_ISR_TIMER;
-+ break;
-+ case AR531X_MISC_IRQ_AHB_PROC:
-+ imr &= ~AR2315_ISR_AHB;
-+ break;
-+ case AR531X_MISC_IRQ_GPIO:
-+ imr &= ~AR2315_ISR_GPIO;
-+ break;
-+ case AR531X_MISC_IRQ_UART0:
-+ imr &= ~AR2315_ISR_UART0;
-+ break;
-+ case AR531X_MISC_IRQ_WATCHDOG:
-+ imr &= ~AR2315_ISR_WD;
-+ break;
-+ default:
-+ break;
-+ }
++ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
+ ar231x_write_reg(AR2315_IMR, imr);
+}
+
-+static struct irq_chip ar2315_misc_intr_controller = {
-+ .irq_mask = ar2315_misc_intr_disable,
-+ .irq_unmask = ar2315_misc_intr_enable,
++static struct irq_chip ar2315_misc_irq_chip = {
++ .name = "AR2315-MISC",
++ .irq_unmask = ar2315_misc_irq_unmask,
++ .irq_mask = ar2315_misc_irq_mask,
+};
+
+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
+ .name = "ar2315_ahb_proc_interrupt",
+};
+
-+static struct irqaction cascade = {
-+ .handler = no_action,
-+ .name = "cascade",
-+};
-+
+void
+ar2315_irq_init(void)
+{
+
+ ar231x_irq_dispatch = ar2315_irq_dispatch;
+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
-+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
++ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
+ int irq = AR531X_MISC_IRQ_BASE + i;
-+ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
+ handle_level_irq);
+ }
-+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
++ for (i = 0; i < AR2315_NUM_GPIO; i++) {
+ int irq = AR531X_GPIO_IRQ_BASE + i;
-+ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
++ irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
+ handle_level_irq);
+ }
-+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
-+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
-+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
-+}
-+
-+static u32
-+ar2315_gpio_set_output(u32 mask, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = ar231x_read_reg(AR2315_GPIO_CR);
-+ reg &= ~mask;
-+ reg |= val;
-+ ar231x_write_reg(AR2315_GPIO_CR, reg);
-+ return reg;
-+}
-+
-+static u32
-+ar2315_gpio_get(u32 valid_mask)
-+{
-+ u32 reg;
-+ reg = ar231x_read_reg(AR2315_GPIO_DI);
-+ reg &= valid_mask;
-+ return reg;
-+}
-+
-+static u32
-+ar2315_gpio_set(u32 mask, u32 value)
-+{
-+ u32 reg;
-+ reg = ar231x_read_reg(AR2315_GPIO_DO);
-+ reg &= ~mask;
-+ reg |= value;
-+ ar231x_write_reg(AR2315_GPIO_DO, reg);
-+ return reg;
++ irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
++ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
++ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
+}
+
+/*
-+ * gpiolib implementation. Original legacy mask based methods
-+ * preserved for now.
++ * gpiolib implementation
+ */
+static int
+ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ u32 rett;
-+ if (!(gpch->valid_mask & mask))
-+ return 0;
-+ rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
-+ return !!(rett & mask);
++ return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
+}
+
+static void
+ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return;
-+ ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
++ u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
++ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
++ ar231x_write_reg(AR2315_GPIO_DO, reg);
+}
+
+static int
+ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, 0); /* legacy */
++ ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
+ return 0;
+}
+
+static int
+ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+{
-+ struct ar231x_gpio_chip *gpch =
-+ container_of(chip, struct ar231x_gpio_chip, chip);
-+ u32 mask = 1 << gpio;
-+ if (!(gpch->valid_mask & mask))
-+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, mask); /* both legacy */
-+ ar2315_gpio_set(mask, (!!value) * mask);
++ ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
++ ar2315_gpio_set_value(chip, gpio, value);
+ return 0;
+}
+
-+static struct ar231x_gpio_chip ar2315_gpio_chip = {
-+ .valid_mask = (1 << 22) - 1,
-+ .chip = {
-+ .label = "ar2315-gpio",
-+ .direction_input = ar2315_gpio_direction_input,
-+ .direction_output = ar2315_gpio_direction_output,
-+ .set = ar2315_gpio_set_value,
-+ .get = ar2315_gpio_get_value,
-+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
-+ }
++static struct gpio_chip ar2315_gpio_chip = {
++ .label = "ar2315-gpio",
++ .direction_input = ar2315_gpio_direction_input,
++ .direction_output = ar2315_gpio_direction_output,
++ .set = ar2315_gpio_set_value,
++ .get = ar2315_gpio_get_value,
++ .base = 0,
++ .ngpio = AR2315_NUM_GPIO, /* 22 */
+};
+
+/* end of gpiolib */
+
++static void ar2315_device_reset_set(u32 mask)
++{
++ u32 val;
++
++ val = ar231x_read_reg(AR2315_RESET);
++ ar231x_write_reg(AR2315_RESET, val | mask);
++}
++
++static void ar2315_device_reset_clear(u32 mask)
++{
++ u32 val;
++
++ val = ar231x_read_reg(AR2315_RESET);
++ ar231x_write_reg(AR2315_RESET, val & ~mask);
++}
+
+static struct ar231x_eth ar2315_eth_data = {
-+ .reset_base = AR2315_RESET,
++ .reset_set = ar2315_device_reset_set,
++ .reset_clear = ar2315_device_reset_clear,
+ .reset_mac = AR2315_RESET_ENET0,
+ .reset_phy = AR2315_RESET_EPHY0,
-+ .phy_base = KSEG1ADDR(AR2315_ENET0),
+ .config = &ar231x_board,
+};
+
+static struct resource ar2315_spiflash_res[] = {
+ {
-+ .name = "flash_base",
++ .name = "spiflash_read",
+ .flags = IORESOURCE_MEM,
-+ .start = KSEG1ADDR(AR2315_SPI_READ),
-+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
++ .start = AR2315_SPI_READ,
++ .end = AR2315_SPI_READ + 0x1000000 - 1,
+ },
+ {
-+ .name = "flash_regs",
++ .name = "spiflash_mmr",
+ .flags = IORESOURCE_MEM,
-+ .start = 0x11300000,
-+ .end = 0x11300012,
++ .start = AR2315_SPI_MMR,
++ .end = AR2315_SPI_MMR + 12 - 1,
+ },
+};
+
+static struct platform_device ar2315_spiflash = {
+ .id = 0,
-+ .name = "spiflash",
++ .name = "ar2315-spiflash",
+ .resource = ar2315_spiflash_res,
+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
+};
+
++static struct resource ar2315_wdt_res[] = {
++ {
++ .flags = IORESOURCE_MEM,
++ .start = AR2315_WD,
++ .end = AR2315_WD + 8 - 1,
++ },
++ {
++ .flags = IORESOURCE_IRQ,
++ .start = AR2315_MISC_IRQ_WATCHDOG,
++ .end = AR2315_MISC_IRQ_WATCHDOG,
++ }
++};
++
+static struct platform_device ar2315_wdt = {
+ .id = 0,
-+ .name = "ar2315_wdt",
++ .name = "ar2315-wdt",
++ .resource = ar2315_wdt_res,
++ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
+};
+
-+#define SPI_FLASH_CTL 0x00
-+#define SPI_FLASH_OPCODE 0x04
-+#define SPI_FLASH_DATA 0x08
-+
-+static inline u32
-+spiflash_read_reg(int reg)
-+{
-+ return ar231x_read_reg(AR2315_SPI + reg);
-+}
-+
-+static inline void
-+spiflash_write_reg(int reg, u32 data)
-+{
-+ ar231x_write_reg(AR2315_SPI + reg, data);
-+}
-+
-+static u32
-+spiflash_wait_status(void)
-+{
-+ u32 reg;
-+
-+ do {
-+ reg = spiflash_read_reg(SPI_FLASH_CTL);
-+ } while (reg & SPI_CTL_BUSY);
-+
-+ return reg;
-+}
-+
-+static u8
-+spiflash_probe(void)
-+{
-+ u32 reg;
-+
-+ reg = spiflash_wait_status();
-+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
-+ reg |= (1 << 4) | 4 | SPI_CTL_START;
-+
-+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
-+ spiflash_write_reg(SPI_FLASH_CTL, reg);
-+
-+ reg = spiflash_wait_status();
-+ reg = spiflash_read_reg(SPI_FLASH_DATA);
-+ reg &= 0xff;
-+
-+ return (u8) reg;
-+}
-+
-+
-+#define STM_8MBIT_SIGNATURE 0x13
-+#define STM_16MBIT_SIGNATURE 0x14
-+#define STM_32MBIT_SIGNATURE 0x15
-+#define STM_64MBIT_SIGNATURE 0x16
-+#define STM_128MBIT_SIGNATURE 0x17
-+
-+static u8 __init *
-+ar2315_flash_limit(void)
++/*
++ * NB: We use mapping size that is larger than the actual flash size,
++ * but this shouldn't be a problem here, because the flash will simply
++ * be mapped multiple times.
++ */
++static u8 __init *ar2315_flash_limit(void)
+{
-+ u32 flash_size = 0;
-+
-+ /* probe the flash chip size */
-+ switch (spiflash_probe()) {
-+ case STM_8MBIT_SIGNATURE:
-+ flash_size = 0x00100000;
-+ break;
-+ case STM_16MBIT_SIGNATURE:
-+ flash_size = 0x00200000;
-+ break;
-+ case STM_32MBIT_SIGNATURE:
-+ flash_size = 0x00400000;
-+ break;
-+ case STM_64MBIT_SIGNATURE:
-+ flash_size = 0x00800000;
-+ break;
-+ case STM_128MBIT_SIGNATURE:
-+ flash_size = 0x01000000;
-+ break;
-+ }
-+
-+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
-+ flash_size - 1;
-+ return (u8 *)ar2315_spiflash_res[0].end + 1;
++ return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
+}
+
+#ifdef CONFIG_LEDS_GPIO
+ ar2315_init_gpio_leds();
+ platform_device_register(&ar2315_wdt);
+ platform_device_register(&ar2315_spiflash);
-+ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
-+ &ar2315_eth_data);
++ ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
++ AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
+
+ return 0;
+ /* try reset the system via reset control */
+ ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
+
-+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
-+ * give it some time to attempt a gpio based hardware reset
-+ * (atheros reference design workaround) */
++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
++ * a workaround. Give it some time to attempt a gpio based hardware
++ * reset (atheros reference design workaround) */
+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
+ mdelay(100);
+
+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
+}
+
-+int __init
++static int __init
+ar2315_gpio_init(void)
+{
+ int ret;
-+ struct ar231x_gpio_chip *gpch;
-+ gpch = &ar2315_gpio_chip;
-+ ret = gpiochip_add(&gpch->chip);
++ ret = gpiochip_add(&ar2315_gpio_chip);
+ if (ret) {
-+ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
+ return ret;
+ }
-+ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
-+ gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
++ ar2315_gpio_chip.ngpio);
+ return ret;
+}
+
+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
+
+ _machine_restart = ar2315_restart;
-+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
++ ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
++ ar2315_apb_frequency());
+}
--- /dev/null
+++ b/arch/mips/ar231x/ar2315.h
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
-@@ -0,0 +1,57 @@
+@@ -0,0 +1,43 @@
+#ifndef __AR531X_H
+#define __AR531X_H
+
+#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
+#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
+
-+/* Miscellaneous interrupts, which share IP6 */
-+#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
-+#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
-+#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
-+#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
-+#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
-+#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
-+#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
-+#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
-+#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
-+#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
-+#define AR531X_MISC_IRQ_COUNT 10
-+
-+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
++/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
+#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
+#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
-+#define AR531X_GPIO_IRQ_COUNT 22
+
+static inline u32
+ar231x_read_reg(u32 reg)
+{
-+ return __raw_readl((u32 *)KSEG1ADDR(reg));
++ return __raw_readl((void __iomem *)KSEG1ADDR(reg));
+}
+
+static inline void
+ar231x_write_reg(u32 reg, u32 val)
+{
-+ __raw_writel(val, (u32 *)KSEG1ADDR(reg));
++ __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
+}
+
+static inline u32
+#endif
--- /dev/null
+++ b/arch/mips/ar231x/devices.h
-@@ -0,0 +1,42 @@
+@@ -0,0 +1,38 @@
+#ifndef __AR231X_DEVICES_H
+#define __AR231X_DEVICES_H
-+#include <linux/gpio.h>
+
+enum {
+ /* handled by ar5312.c */
+extern asmlinkage void (*ar231x_irq_dispatch)(void);
+
+extern int ar231x_find_config(u8 *flash_limit);
-+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
++extern void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
+extern int ar231x_add_wmac(int nr, u32 base, int irq);
-+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
++extern int ar231x_add_ethernet(int nr, u32 base, const char *mii_name,
++ u32 mii_base, int irq, void *pdata);
+
+static inline bool is_2315(void)
+{
+ return !is_2315();
+}
+
-+struct ar231x_gpio_chip {
-+ u32 valid_mask;
-+ struct gpio_chip chip;
-+};
+#endif
--- /dev/null
+++ b/arch/mips/ar231x/devices.c
-@@ -0,0 +1,168 @@
+@@ -0,0 +1,180 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+ .flags = IORESOURCE_MEM,
+ },
+ {
++ .name = "eth0_mii",
++ .flags = IORESOURCE_MEM,
++ },
++ {
+ .name = "eth0_irq",
+ .flags = IORESOURCE_IRQ,
+ }
+ .flags = IORESOURCE_MEM,
+ },
+ {
++ .name = "eth1_mii",
++ .flags = IORESOURCE_MEM,
++ },
++ {
+ .name = "eth1_irq",
+ .flags = IORESOURCE_IRQ,
+ }
+
+
+int __init
-+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
++ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
++ int irq, void *pdata)
+{
+ struct resource *res;
+
+ res->start = base;
+ res->end = base + 0x2000 - 1;
+ res++;
++ res->name = mii_name;
++ res->start = mii_base;
++ res->end = mii_base + 8 - 1;
++ res++;
+ res->start = irq;
+ res->end = irq;
+ return platform_device_register(&ar231x_eth[nr]);
+}
+
+void __init
-+ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
++ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
+{
+ struct uart_port s;
+
+ memset(&s, 0, sizeof(s));
+
-+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-+ s.iotype = UPIO_MEM;
-+ s.irq = AR531X_MISC_IRQ_UART0;
++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
++ s.iotype = UPIO_MEM32;
++ s.irq = irq;
+ s.regshift = 2;
+ s.mapbase = mapbase;
+ s.uartclk = uartclk;
-+ s.membase = (void __iomem *)s.mapbase;
+
+ early_serial_setup(&s);
+}
projects / openwrt / svn-archive / archive.git / blobdiff