--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -96,6 +96,19 @@ config AR7
+@@ -96,6 +96,20 @@ config AR7
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select IRQ_CPU
++ select IRQ_DOMAIN
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
config ATH79
bool "Atheros AR71XX/AR724X/AR913X based boards"
select ARCH_REQUIRE_GPIOLIB
-@@ -834,6 +847,7 @@ config MIPS_PARAVIRT
+@@ -834,6 +848,7 @@ config MIPS_PARAVIRT
endchoice
+obj-$(CONFIG_SOC_AR2315) += ar2315.o
--- /dev/null
+++ b/arch/mips/ath25/board.c
-@@ -0,0 +1,234 @@
+@@ -0,0 +1,244 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+
+void (*ath25_irq_dispatch)(void);
+
-+static inline bool check_radio_magic(u8 *addr)
++static inline bool check_radio_magic(const void __iomem *addr)
+{
+ addr += 0x7a; /* offset for flash magic */
-+ return (addr[0] == 0x5a) && (addr[1] == 0xa5);
++ return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
+}
+
-+static inline bool check_notempty(u8 *addr)
++static inline bool check_notempty(const void __iomem *addr)
+{
-+ return *(u32 *)addr != 0xffffffff;
++ return __raw_readl(addr) != 0xffffffff;
+}
+
-+static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
++static inline bool check_board_data(const void __iomem *addr, bool broken)
+{
+ /* config magic found */
-+ if (*((u32 *)addr) == ATH25_BD_MAGIC)
++ if (__raw_readl(addr) == ATH25_BD_MAGIC)
+ return true;
+
+ if (!broken)
+ return false;
+
++ /* broken board data detected, use radio data to find the
++ * offset, user will fix this */
++
++ if (check_radio_magic(addr + 0x1000))
++ return true;
+ if (check_radio_magic(addr + 0xf8))
-+ ath25_board.radio = addr + 0xf8;
-+ if ((addr < flash_limit + 0x10000) &&
-+ check_radio_magic(addr + 0x10000))
-+ ath25_board.radio = addr + 0x10000;
-+
-+ if (ath25_board.radio) {
-+ /* broken board data detected, use radio data to find the
-+ * offset, user will fix this */
+ return true;
-+ }
+
+ return false;
+}
+
-+static u8 * __init find_board_config(u8 *flash_limit, bool broken)
++static const void __iomem * __init find_board_config(const void __iomem *limit,
++ const bool broken)
+{
-+ u8 *addr;
-+ u8 *begin = flash_limit - 0x1000;
-+ u8 *end = flash_limit - 0x30000;
++ const void __iomem *addr;
++ const void __iomem *begin = limit - 0x1000;
++ const void __iomem *end = limit - 0x30000;
+
+ for (addr = begin; addr >= end; addr -= 0x1000)
-+ if (check_board_data(flash_limit, addr, broken))
++ if (check_board_data(addr, broken))
+ return addr;
+
+ return NULL;
+}
+
-+static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
++static const void __iomem * __init find_radio_config(const void __iomem *limit,
++ const void __iomem *bcfg)
+{
-+ u8 *rcfg, *begin, *end;
++ const void __iomem *rcfg, *begin, *end;
+
+ /*
+ * Now find the start of Radio Configuration data, using heuristics:
+ * at a time until we find non-0xffffffff.
+ */
+ begin = bcfg + 0x1000;
-+ end = flash_limit;
++ end = limit;
+ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
+ if (check_notempty(rcfg) && check_radio_magic(rcfg))
+ return rcfg;
+
+ /* AR2316 relocates radio config to new location */
+ begin = bcfg + 0xf8;
-+ end = flash_limit - 0x1000 + 0xf8;
++ end = limit - 0x1000 + 0xf8;
+ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
+ if (check_notempty(rcfg) && check_radio_magic(rcfg))
+ return rcfg;
+
-+ pr_warn("WARNING: Could not find Radio Configuration data\n");
-+
+ return NULL;
+}
+
-+int __init ath25_find_config(u8 *flash_limit)
++/*
++ * NB: Search region size could be larger than the actual flash size,
++ * but this shouldn't be a problem here, because the flash
++ * will simply be mapped multiple times.
++ */
++int __init ath25_find_config(phys_addr_t base, unsigned long size)
+{
++ const void __iomem *flash_base, *flash_limit;
+ struct ath25_boarddata *config;
+ unsigned int rcfg_size;
+ int broken_boarddata = 0;
-+ u8 *bcfg, *rcfg;
++ const void __iomem *bcfg, *rcfg;
+ u8 *board_data;
+ u8 *radio_data;
+ u8 *mac_addr;
+ u32 offset;
+
++ flash_base = ioremap_nocache(base, size);
++ flash_limit = flash_base + size;
++
+ ath25_board.config = NULL;
+ ath25_board.radio = NULL;
++
+ /* Copy the board and radio data to RAM, because accessing the mapped
+ * memory of the flash directly after booting is not safe */
+
+
+ if (!bcfg) {
+ pr_warn("WARNING: No board configuration data found!\n");
-+ return -ENODEV;
++ goto error;
+ }
+
+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
+ ath25_board.config = (struct ath25_boarddata *)board_data;
-+ memcpy(board_data, bcfg, 0x100);
++ memcpy_fromio(board_data, bcfg, 0x100);
+ if (broken_boarddata) {
+ pr_warn("WARNING: broken board data detected\n");
+ config = ath25_board.config;
+ /* Radio config starts 0x100 bytes after board config, regardless
+ * of what the physical layout on the flash chip looks like */
+
-+ if (ath25_board.radio)
-+ rcfg = (u8 *)ath25_board.radio;
-+ else
-+ rcfg = find_radio_config(flash_limit, bcfg);
-+
-+ if (!rcfg)
-+ return -ENODEV;
++ rcfg = find_radio_config(flash_limit, bcfg);
++ if (!rcfg) {
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
++ goto error;
++ }
+
+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
+ ath25_board.radio = radio_data;
+ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
+ offset);
+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
-+ memcpy(radio_data, rcfg, rcfg_size);
++ memcpy_fromio(radio_data, rcfg, rcfg_size);
+
+ mac_addr = &radio_data[0x1d * 2];
+ if (is_broadcast_ether_addr(mac_addr)) {
+ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
+ }
+
++ iounmap(flash_base);
++
+ return 0;
++
++error:
++ iounmap(flash_base);
++ return -ENODEV;
+}
+
+static void ath25_halt(void)
+
+#endif /* __ASM_MACH_ATH25_WAR_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
-@@ -0,0 +1,511 @@
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -0,0 +1,479 @@
+/*
+ * Register definitions for AR2315+
+ *
+/*
+ * IRQs
+ */
-+#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
-+#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
-+#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
-+#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
-+#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
++#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
+
+/*
+ * Miscellaneous interrupts, which share IP2.
+ */
-+#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
-+#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
-+#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
-+#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
-+#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
-+#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
-+#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
-+#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
-+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
++#define AR2315_MISC_IRQ_UART0 0
++#define AR2315_MISC_IRQ_I2C_RSVD 1
++#define AR2315_MISC_IRQ_SPI 2
++#define AR2315_MISC_IRQ_AHB 3
++#define AR2315_MISC_IRQ_APB 4
++#define AR2315_MISC_IRQ_TIMER 5
++#define AR2315_MISC_IRQ_GPIO 6
++#define AR2315_MISC_IRQ_WATCHDOG 7
++#define AR2315_MISC_IRQ_IR_RSVD 8
+#define AR2315_MISC_IRQ_COUNT 9
+
+/*
+ * Address map
+ */
-+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
-+#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
-+#define AR2315_PCI 0x10100000 /* PCI MMR */
++#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
++#define AR2315_SPI_READ_SIZE 0x01000000
++#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
++#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
+#define AR2315_PCI_SIZE 0x00001000
-+#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
-+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
-+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
-+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
-+#define AR2315_UART0 0x11100000 /* UART MMR */
-+#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
-+#define AR2315_PCIEXT 0x80000000 /* pci external */
-+#define AR2315_PCIEXT_SZ 0x40000000
++#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
++#define AR2315_SDRAMCTL_SIZE 0x00000020
++#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
++#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
++#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
++#define AR2315_RST_SIZE 0x00000100
++#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
++#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
++#define AR2315_SPI_MMR_SIZE 0x00000010
++#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
++#define AR2315_PCI_EXT_SIZE 0x40000000
+
+/* MII registers offset inside Ethernet MMR region */
-+#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
++#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
+
+/*
+ * Cold reset register
+ */
-+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
++#define AR2315_COLD_RESET 0x0000
+
+#define AR2315_RESET_COLD_AHB 0x00000001
+#define AR2315_RESET_COLD_APB 0x00000002
+/*
+ * Reset register
+ */
-+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
++#define AR2315_RESET 0x0004
+
+/* warm reset WLAN0 MAC */
+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
+/*
+ * AHB master arbitration control
+ */
-+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
++#define AR2315_AHB_ARB_CTL 0x0008
+
+/* CPU, default */
+#define AR2315_ARB_CPU 0x00000001
+/*
+ * Config Register
+ */
-+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
++#define AR2315_ENDIAN_CTL 0x000c
+
+/* EC - AHB bridge endianess */
+#define AR2315_CONFIG_AHB 0x00000001
+/*
+ * NMI control
+ */
-+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
++#define AR2315_NMI_CTL 0x0010
+
+#define AR2315_NMI_EN 1
+
+/*
+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
+ */
-+#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
++#define AR2315_SREV 0x0014
+
+#define AR2315_REV_MAJ 0x00f0
+#define AR2315_REV_MAJ_S 4
+/*
+ * Interface Enable
+ */
-+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
++#define AR2315_IF_CTL 0x0018
+
+#define AR2315_IF_MASK 0x00000007
+#define AR2315_IF_DISABLED 0
+ * APB Interrupt control
+ */
+
-+#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
-+#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
-+#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
++#define AR2315_ISR 0x0020
++#define AR2315_IMR 0x0024
++#define AR2315_GISR 0x0028
+
+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
+#define AR2315_GISR_ETHERNET 0x0040
+
+/*
-+ * Interrupt routing from IO to the processor IP bits
-+ * Define our inter mask and level
-+ */
-+#define AR2315_INTR_MISCIO SR_IBIT3
-+#define AR2315_INTR_WLAN0 SR_IBIT4
-+#define AR2315_INTR_ENET0 SR_IBIT5
-+#define AR2315_INTR_LOCALPCI SR_IBIT6
-+#define AR2315_INTR_WMACPOLL SR_IBIT7
-+#define AR2315_INTR_COMPARE SR_IBIT8
-+
-+/*
+ * Timers
+ */
-+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
-+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
-+#define AR2315_WD (AR2315_DSLBASE + 0x0038)
-+#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
++#define AR2315_TIMER 0x0030
++#define AR2315_RELOAD 0x0034
++
++#define AR2315_WDT_TIMER 0x0038
++#define AR2315_WDT_CTRL 0x003c
+
-+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
-+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
-+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
++#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
++#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
+
+/*
+ * CPU Performance Counters
+ */
-+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
-+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
++#define AR2315_PERFCNT0 0x0048
++#define AR2315_PERFCNT1 0x004c
+
+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
+/*
+ * AHB Error Reporting.
+ */
-+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
-+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
-+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
-+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
-+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
++#define AR2315_AHB_ERR0 0x0050 /* error */
++#define AR2315_AHB_ERR1 0x0054 /* haddr */
++#define AR2315_AHB_ERR2 0x0058 /* hwdata */
++#define AR2315_AHB_ERR3 0x005c /* hrdata */
++#define AR2315_AHB_ERR4 0x0060 /* status */
+
-+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
-+ /* write 1 to clear all bits in ERR0 */
-+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
-+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
++#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
++ /* write 1 to clear all bits in ERR0 */
++#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
++#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
+
+#define AR2315_PROCERR_HMAST 0x0000000f
+#define AR2315_PROCERR_HMAST_DFLT 0
+/*
+ * Clock Control
+ */
-+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
-+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
-+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
-+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
-+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
-+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
-+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
++#define AR2315_PLLC_CTL 0x0064
++#define AR2315_PLLV_CTL 0x0068
++#define AR2315_CPUCLK 0x006c
++#define AR2315_AMBACLK 0x0070
++#define AR2315_SYNCCLK 0x0074
++#define AR2315_DSL_SLEEP_CTL 0x0080
++#define AR2315_DSL_SLEEP_DUR 0x0084
+
+/* PLLc Control fields */
-+#define PLLC_REF_DIV_M 0x00000003
-+#define PLLC_REF_DIV_S 0
-+#define PLLC_FDBACK_DIV_M 0x0000007C
-+#define PLLC_FDBACK_DIV_S 2
-+#define PLLC_ADD_FDBACK_DIV_M 0x00000080
-+#define PLLC_ADD_FDBACK_DIV_S 7
-+#define PLLC_CLKC_DIV_M 0x0001c000
-+#define PLLC_CLKC_DIV_S 14
-+#define PLLC_CLKM_DIV_M 0x00700000
-+#define PLLC_CLKM_DIV_S 20
++#define AR2315_PLLC_REF_DIV_M 0x00000003
++#define AR2315_PLLC_REF_DIV_S 0
++#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
++#define AR2315_PLLC_FDBACK_DIV_S 2
++#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
++#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
++#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
++#define AR2315_PLLC_CLKC_DIV_S 14
++#define AR2315_PLLC_CLKM_DIV_M 0x00700000
++#define AR2315_PLLC_CLKM_DIV_S 20
+
+/* CPU CLK Control fields */
-+#define CPUCLK_CLK_SEL_M 0x00000003
-+#define CPUCLK_CLK_SEL_S 0
-+#define CPUCLK_CLK_DIV_M 0x0000000c
-+#define CPUCLK_CLK_DIV_S 2
++#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
++#define AR2315_CPUCLK_CLK_SEL_S 0
++#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
++#define AR2315_CPUCLK_CLK_DIV_S 2
+
+/* AMBA CLK Control fields */
-+#define AMBACLK_CLK_SEL_M 0x00000003
-+#define AMBACLK_CLK_SEL_S 0
-+#define AMBACLK_CLK_DIV_M 0x0000000c
-+#define AMBACLK_CLK_DIV_S 2
++#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
++#define AR2315_AMBACLK_CLK_SEL_S 0
++#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
++#define AR2315_AMBACLK_CLK_DIV_S 2
+
+/* GPIO MMR base address */
-+#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
++#define AR2315_GPIO 0x0088
+
+#define AR2315_RESET_GPIO 5
+
+/*
+ * PCI Clock Control
+ */
-+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
++#define AR2315_PCICLK 0x00a4
+
+#define AR2315_PCICLK_INPUT_M 0x3
+#define AR2315_PCICLK_INPUT_S 0
+/*
+ * Observation Control Register
+ */
-+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
-+#define OCR_GPIO0_IRIN 0x0040
-+#define OCR_GPIO1_IROUT 0x0080
-+#define OCR_GPIO3_RXCLR 0x0200
++#define AR2315_OCR 0x00b0
++
++#define AR2315_OCR_GPIO0_IRIN 0x00000040
++#define AR2315_OCR_GPIO1_IROUT 0x00000080
++#define AR2315_OCR_GPIO3_RXCLR 0x00000200
+
+/*
+ * General Clock Control
+ */
++#define AR2315_MISCCLK 0x00b4
+
-+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
-+#define MISCCLK_PLLBYPASS_EN 0x00000001
-+#define MISCCLK_PROCREFCLK 0x00000002
++#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
++#define AR2315_MISCCLK_PROCREFCLK 0x00000002
+
+/*
+ * SDRAM Controller
+ * - No read or write buffers are included.
+ */
-+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
-+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
-+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
-+
-+#define SDRAM_DATA_WIDTH_M 0x00006000
-+#define SDRAM_DATA_WIDTH_S 13
-+
-+#define SDRAM_COL_WIDTH_M 0x00001E00
-+#define SDRAM_COL_WIDTH_S 9
-+
-+#define SDRAM_ROW_WIDTH_M 0x000001E0
-+#define SDRAM_ROW_WIDTH_S 5
-+
-+#define SDRAM_BANKADDR_BITS_M 0x00000018
-+#define SDRAM_BANKADDR_BITS_S 3
++#define AR2315_MEM_CFG 0x0000
++#define AR2315_MEM_CTRL 0x000c
++#define AR2315_MEM_REF 0x0010
++
++#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
++#define AR2315_MEM_CFG_DATA_WIDTH_S 13
++#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
++#define AR2315_MEM_CFG_COL_WIDTH_S 9
++#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
++#define AR2315_MEM_CFG_ROW_WIDTH_S 5
++#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
++#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
+
+/*
+ * Local Bus Interface Registers
+ */
-+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
++#define AR2315_LB_CONFIG 0x0000
++
+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
+
-+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
++#define AR2315_LB_CLKSEL 0x0004
++
+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
+
-+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
++#define AR2315_LB_1MS 0x0008
++
+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
+
-+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
++#define AR2315_LB_MISCCFG 0x000c
+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
-+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
-+#define AR2315_LBM_TIMEOUT_SHFT 7
++#define AR2315_LBM_TIMEOUT_M 0x00ffff80
++#define AR2315_LBM_TIMEOUT_S 7
+#define AR2315_LBM_PORTMUX 0x07000000
+
-+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
++#define AR2315_LB_RXTSOFF 0x0010
++
++#define AR2315_LB_TX_CHAIN_EN 0x0100
+
-+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
+#define AR2315_LB_TXEN_0 0x01
+#define AR2315_LB_TXEN_1 0x02
+#define AR2315_LB_TXEN_2 0x04
+#define AR2315_LB_TXEN_3 0x08
+
-+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
-+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
++#define AR2315_LB_TX_CHAIN_DIS 0x0104
++#define AR2315_LB_TX_DESC_PTR 0x0200
++
++#define AR2315_LB_RX_CHAIN_EN 0x0400
+
-+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
+#define AR2315_LB_RXEN 0x01
+
-+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
-+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
-+
-+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
-+#define AR2315_INT_TX_DESC 0x0001
-+#define AR2315_INT_TX_OK 0x0002
-+#define AR2315_INT_TX_ERR 0x0004
-+#define AR2315_INT_TX_EOF 0x0008
-+#define AR2315_INT_RX_DESC 0x0010
-+#define AR2315_INT_RX_OK 0x0020
-+#define AR2315_INT_RX_ERR 0x0040
-+#define AR2315_INT_RX_EOF 0x0080
-+#define AR2315_INT_TX_TRUNC 0x0100
-+#define AR2315_INT_TX_STARVE 0x0200
-+#define AR2315_INT_LB_TIMEOUT 0x0400
-+#define AR2315_INT_LB_ERR 0x0800
-+#define AR2315_INT_MBOX_WR 0x1000
-+#define AR2315_INT_MBOX_RD 0x2000
++#define AR2315_LB_RX_CHAIN_DIS 0x0404
++#define AR2315_LB_RX_DESC_PTR 0x0408
++
++#define AR2315_LB_INT_STATUS 0x0500
++
++#define AR2315_LB_INT_TX_DESC 0x00000001
++#define AR2315_LB_INT_TX_OK 0x00000002
++#define AR2315_LB_INT_TX_ERR 0x00000004
++#define AR2315_LB_INT_TX_EOF 0x00000008
++#define AR2315_LB_INT_RX_DESC 0x00000010
++#define AR2315_LB_INT_RX_OK 0x00000020
++#define AR2315_LB_INT_RX_ERR 0x00000040
++#define AR2315_LB_INT_RX_EOF 0x00000080
++#define AR2315_LB_INT_TX_TRUNC 0x00000100
++#define AR2315_LB_INT_TX_STARVE 0x00000200
++#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
++#define AR2315_LB_INT_LB_ERR 0x00000800
++#define AR2315_LB_INT_MBOX_WR 0x00001000
++#define AR2315_LB_INT_MBOX_RD 0x00002000
+
+/* Bit definitions for INT MASK are the same as INT_STATUS */
-+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
++#define AR2315_LB_INT_MASK 0x0504
+
-+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
-+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
-+
-+/*
-+ * IR Interface Registers
-+ */
-+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
-+
-+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
-+
-+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
-+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
-+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
-+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
-+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
-+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
-+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
-+
-+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
-+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
-+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
-+
-+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
-+#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
-+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
-+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
-+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
-+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
-+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
-+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
-+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
-+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
++#define AR2315_LB_INT_EN 0x0508
++#define AR2315_LB_MBOX 0x0600
+
+#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
-@@ -0,0 +1,235 @@
++++ b/arch/mips/ath25/ar5312_regs.h
+@@ -0,0 +1,229 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+/*
+ * IRQs
+ */
-+#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
-+#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
-+#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
-+#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
-+#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
++#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
+
+/*
+ * Miscellaneous interrupts, which share IP6.
+ */
-+#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
-+#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
-+#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
-+#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
-+#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
-+#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
-+#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
-+#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
-+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
++#define AR5312_MISC_IRQ_TIMER 0
++#define AR5312_MISC_IRQ_AHB_PROC 1
++#define AR5312_MISC_IRQ_AHB_DMA 2
++#define AR5312_MISC_IRQ_GPIO 3
++#define AR5312_MISC_IRQ_UART0 4
++#define AR5312_MISC_IRQ_UART0_DMA 5
++#define AR5312_MISC_IRQ_WATCHDOG 6
++#define AR5312_MISC_IRQ_LOCAL 7
++#define AR5312_MISC_IRQ_SPI 8
+#define AR5312_MISC_IRQ_COUNT 9
+
+/*
+ * Address Map
++ *
++ * The AR5312 supports 2 enet MACS, even though many reference boards only
++ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
++ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
+ */
-+#define AR5312_WLAN0 0x18000000
-+#define AR5312_WLAN1 0x18500000
-+#define AR5312_ENET0 0x18100000
-+#define AR5312_ENET1 0x18200000
-+#define AR5312_SDRAMCTL 0x18300000
-+#define AR5312_FLASHCTL 0x18400000
-+#define AR5312_APBBASE 0x1c000000
-+#define AR5312_UART0 0x1c000000 /* UART MMR */
-+#define AR5312_FLASH 0x1e000000
-+
-+/*
-+ * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
-+ * should be considered available. The AR5312 supports 2 enet MACS,
-+ * even though many reference boards only actually use 1 of them
-+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
-+ * The AR2312 supports 1 enet MAC.
-+ */
-+#define AR5312_NUM_ENET_MAC 2
++#define AR5312_WLAN0_BASE 0x18000000
++#define AR5312_ENET0_BASE 0x18100000
++#define AR5312_ENET1_BASE 0x18200000
++#define AR5312_SDRAMCTL_BASE 0x18300000
++#define AR5312_SDRAMCTL_SIZE 0x00000010
++#define AR5312_FLASHCTL_BASE 0x18400000
++#define AR5312_FLASHCTL_SIZE 0x00000010
++#define AR5312_WLAN1_BASE 0x18500000
++#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
++#define AR5312_GPIO_BASE 0x1c002000
++#define AR5312_GPIO_SIZE 0x00000010
++#define AR5312_RST_BASE 0x1c003000
++#define AR5312_RST_SIZE 0x00000100
++#define AR5312_FLASH_BASE 0x1e000000
++#define AR5312_FLASH_SIZE 0x00800000
+
+/*
+ * Need these defines to determine true number of ethernet MACs
+#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
+
+/* MII registers offset inside Ethernet MMR region */
-+#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
-+#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
-+
-+/*
-+ * AR5312_NUM_WMAC defines the number of Wireless MACs that\
-+ * should be considered available.
-+ */
-+#define AR5312_NUM_WMAC 2
++#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
++#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
+
+/* Reset/Timer Block Address Map */
-+#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
-+#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
-+#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
-+#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
-+#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
-+#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
-+#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
-+#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
-+#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
-+#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
-+#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
-+#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
-+#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
-+#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
-+#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
-+
-+/* AR5312_WD_CTRL register bit field definitions */
-+#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
-+#define AR5312_WD_CTRL_NMI 0x0001
-+#define AR5312_WD_CTRL_RESET 0x0002
++#define AR5312_TIMER 0x0000 /* countdown timer */
++#define AR5312_RELOAD 0x0004 /* timer reload value */
++#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
++#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
++#define AR5312_ISR 0x0010 /* Intr Status Reg */
++#define AR5312_IMR 0x0014 /* Intr Mask Reg */
++#define AR5312_RESET 0x0020
++#define AR5312_CLOCKCTL1 0x0064
++#define AR5312_SCRATCH 0x006c
++#define AR5312_PROCADDR 0x0070
++#define AR5312_PROC1 0x0074
++#define AR5312_DMAADDR 0x0078
++#define AR5312_DMA1 0x007c
++#define AR5312_ENABLE 0x0080 /* interface enb */
++#define AR5312_REV 0x0090 /* revision */
++
++/* AR5312_WDT_CTRL register bit field definitions */
++#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR5312_WDT_CTRL_NMI 0x00000001
++#define AR5312_WDT_CTRL_RESET 0x00000002
+
+/* AR5312_ISR register bit field definitions */
+#define AR5312_ISR_TIMER 0x0001
+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
+
-+/* AR5312_FLASHCTL register bit field definitions */
-+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
-+#define FLASHCTL_IDCY_S 0
-+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
-+#define FLASHCTL_WST1_S 5
-+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
-+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
-+#define FLASHCTL_WST2_S 11
-+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
-+#define FLASHCTL_AC_S 16
-+#define FLASHCTL_AC_128K 0x00000000
-+#define FLASHCTL_AC_256K 0x00010000
-+#define FLASHCTL_AC_512K 0x00020000
-+#define FLASHCTL_AC_1M 0x00030000
-+#define FLASHCTL_AC_2M 0x00040000
-+#define FLASHCTL_AC_4M 0x00050000
-+#define FLASHCTL_AC_8M 0x00060000
-+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
-+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
-+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
-+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
-+#define FLASHCTL_WP 0x04000000 /* Write protect */
-+#define FLASHCTL_BM 0x08000000 /* Burst mode */
-+#define FLASHCTL_MW 0x30000000 /* Memory width */
-+#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
-+#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
-+#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
-+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
-+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
-+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
-+
+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
-+#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
-+#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
-+#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
++#define AR5312_FLASHCTL0 0x0000
++#define AR5312_FLASHCTL1 0x0004
++#define AR5312_FLASHCTL2 0x0008
++
++/* AR5312_FLASHCTL register bit field definitions */
++#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
++#define AR5312_FLASHCTL_IDCY_S 0
++#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
++#define AR5312_FLASHCTL_WST1_S 5
++#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
++#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
++#define AR5312_FLASHCTL_WST2_S 11
++#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
++#define AR5312_FLASHCTL_AC_S 16
++#define AR5312_FLASHCTL_AC_128K 0x00000000
++#define AR5312_FLASHCTL_AC_256K 0x00010000
++#define AR5312_FLASHCTL_AC_512K 0x00020000
++#define AR5312_FLASHCTL_AC_1M 0x00030000
++#define AR5312_FLASHCTL_AC_2M 0x00040000
++#define AR5312_FLASHCTL_AC_4M 0x00050000
++#define AR5312_FLASHCTL_AC_8M 0x00060000
++#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
++#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
++#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
++#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
++#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
++#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
++#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
++#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
++#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
++#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
++#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
++#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
++#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
+
+/* ARM SDRAM Controller -- just enough to determine memory size */
-+#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
-+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
-+#define MEM_CFG1_AC0_S 8
-+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
-+#define MEM_CFG1_AC1_S 12
++#define AR5312_MEM_CFG1 0x0004
+
-+#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
++#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC0_S 8
++#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC1_S 12
+
+#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
--- /dev/null
+++ b/arch/mips/ath25/ar5312.c
-@@ -0,0 +1,449 @@
+@@ -0,0 +1,492 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
+#include <linux/reboot.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <ath25_platform.h>
-+#include <ar5312_regs.h>
-+#include <ar231x.h>
++
+#include "devices.h"
+#include "ar5312.h"
++#include "ar5312_regs.h"
++
++static void __iomem *ar5312_rst_base;
++static struct irq_domain *ar5312_misc_irq_domain;
++
++static inline u32 ar5312_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar5312_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar5312_rst_reg_write(reg, ret);
++}
+
+static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
+{
-+ u32 proc1 = ar231x_read_reg(AR5312_PROC1);
-+ u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
-+ u32 dma1 = ar231x_read_reg(AR5312_DMA1);
-+ u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
++ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
++ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
++ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
++ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
+
+ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
+ proc_addr, proc1, dma_addr, dma1);
+
+static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
-+ ar231x_read_reg(AR5312_IMR);
-+
-+ if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
-+ generic_handle_irq(AR5312_MISC_IRQ_TIMER);
-+ (void)ar231x_read_reg(AR5312_TIMER);
-+ } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
-+ generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
-+ else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
-+ generic_handle_irq(AR5312_MISC_IRQ_UART0);
-+ else if (ar231x_misc_intrs & AR5312_ISR_WD)
-+ generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
-+ else
++ u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
++ ar5312_rst_reg_read(AR5312_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ generic_handle_irq(misc_irq);
++ if (nr == AR5312_MISC_IRQ_TIMER)
++ ar5312_rst_reg_read(AR5312_TIMER);
++ } else {
+ spurious_interrupt();
++ }
+}
+
+/* Enable the specified AR5312_MISC_IRQ interrupt */
+static void ar5312_misc_irq_unmask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR5312_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar231x_write_reg(AR5312_IMR, imr);
++ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
+}
+
+/* Disable the specified AR5312_MISC_IRQ interrupt */
+static void ar5312_misc_irq_mask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR5312_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar231x_write_reg(AR5312_IMR, imr);
-+ ar231x_read_reg(AR5312_IMR); /* flush write buffer */
++ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
++ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
+}
+
+static struct irq_chip ar5312_misc_irq_chip = {
+ .irq_mask = ar5312_misc_irq_mask,
+};
+
++static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
++ .map = ar5312_misc_irq_map,
++};
++
+static void ar5312_irq_dispatch(void)
+{
-+ int pending = read_c0_status() & read_c0_cause();
++ u32 pending = read_c0_status() & read_c0_cause();
+
+ if (pending & CAUSEF_IP2)
-+ do_IRQ(AR5312_IRQ_WLAN0_INTRS);
++ do_IRQ(AR5312_IRQ_WLAN0);
+ else if (pending & CAUSEF_IP3)
-+ do_IRQ(AR5312_IRQ_ENET0_INTRS);
++ do_IRQ(AR5312_IRQ_ENET0);
+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR5312_IRQ_ENET1_INTRS);
++ do_IRQ(AR5312_IRQ_ENET1);
+ else if (pending & CAUSEF_IP5)
-+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
++ do_IRQ(AR5312_IRQ_WLAN1);
+ else if (pending & CAUSEF_IP6)
-+ do_IRQ(AR5312_IRQ_MISC_INTRS);
++ do_IRQ(AR5312_IRQ_MISC);
+ else if (pending & CAUSEF_IP7)
-+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
+ else
+ spurious_interrupt();
+}
+
+void __init ar5312_arch_init_irq(void)
+{
-+ int i;
++ struct irq_domain *domain;
++ unsigned irq;
+
+ ath25_irq_dispatch = ar5312_irq_dispatch;
-+ for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
-+ int irq = AR231X_MISC_IRQ_BASE + i;
+
-+ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
-+ handle_level_irq);
-+ }
-+ setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
-+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
++ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
++ &ar5312_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
++ setup_irq(irq, &ar5312_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
++ irq_set_handler_data(AR5312_IRQ_MISC, domain);
++
++ ar5312_misc_irq_domain = domain;
+}
+
+static void ar5312_device_reset_set(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR5312_RESET);
-+ ar231x_write_reg(AR5312_RESET, val | mask);
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val | mask);
+}
+
+static void ar5312_device_reset_clear(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR5312_RESET);
-+ ar231x_write_reg(AR5312_RESET, val & ~mask);
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
+}
+
+static struct physmap_flash_data ar5312_flash_data = {
+};
+
+static struct resource ar5312_flash_resource = {
-+ .start = AR5312_FLASH,
-+ .end = AR5312_FLASH + 0x800000 - 1,
++ .start = AR5312_FLASH_BASE,
++ .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+};
+#endif
+
-+/*
-+ * NB: This mapping size is larger than the actual flash size,
-+ * but this shouldn't be a problem here, because the flash
-+ * will simply be mapped multiple times.
-+ */
-+static char __init *ar5312_flash_limit(void)
++static void __init ar5312_flash_init(void)
+{
++ void __iomem *flashctl_base;
+ u32 ctl;
++
++ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
++ AR5312_FLASHCTL_SIZE);
++
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
++ ctl &= AR5312_FLASHCTL_MW;
++
++ /* fixup flash width */
++ switch (ctl) {
++ case AR5312_FLASHCTL_MW16:
++ ar5312_flash_data.width = 2;
++ break;
++ case AR5312_FLASHCTL_MW8:
++ default:
++ ar5312_flash_data.width = 1;
++ break;
++ }
++
+ /*
+ * Configure flash bank 0.
+ * Assume 8M window size. Flash will be aliased if it's smaller
+ */
-+ ctl = FLASHCTL_E |
-+ FLASHCTL_AC_8M |
-+ FLASHCTL_RBLE |
-+ (0x01 << FLASHCTL_IDCY_S) |
-+ (0x07 << FLASHCTL_WST1_S) |
-+ (0x07 << FLASHCTL_WST2_S) |
-+ (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
-+
-+ ar231x_write_reg(AR5312_FLASHCTL0, ctl);
++ ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
++ ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
+
+ /* Disable other flash banks */
-+ ar231x_write_reg(AR5312_FLASHCTL1,
-+ ar231x_read_reg(AR5312_FLASHCTL1) &
-+ ~(FLASHCTL_E | FLASHCTL_AC));
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
+
-+ ar231x_write_reg(AR5312_FLASHCTL2,
-+ ar231x_read_reg(AR5312_FLASHCTL2) &
-+ ~(FLASHCTL_E | FLASHCTL_AC));
-+
-+ return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
++ iounmap(flashctl_base);
+}
+
+void __init ar5312_init_devices(void)
+{
+ struct ath25_boarddata *config;
-+ u32 fctl = 0;
+ u8 *c;
+
++ ar5312_flash_init();
++
+ /* Locate board/radio config data */
-+ ath25_find_config(ar5312_flash_limit());
++ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
+ config = ath25_board.config;
+
+ /* AR2313 has CPU minor rev. 10 */
+ else
+ ath25_soc = ATH25_SOC_AR5312;
+
-+ /* fixup flash width */
-+ fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
-+ switch (fctl) {
-+ case FLASHCTL_MW16:
-+ ar5312_flash_data.width = 2;
-+ break;
-+ case FLASHCTL_MW8:
-+ default:
-+ ar5312_flash_data.width = 1;
-+ break;
-+ }
-+
+ platform_device_register(&ar5312_physmap_flash);
+
+#ifdef CONFIG_LEDS_GPIO
+ switch (ath25_soc) {
+ case ATH25_SOC_AR5312:
+ ar5312_eth0_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
-+ AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
++ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
+ &ar5312_eth0_data);
+
+ ar5312_eth1_data.macaddr = config->enet1_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
-+ AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
++ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
+ &ar5312_eth1_data);
+
+ if (!ath25_board.radio)
+ if (!(config->flags & BD_WLAN0))
+ break;
+
-+ ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
++ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
+ break;
+ /*
+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
+ case ATH25_SOC_AR2313:
+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
+ ar5312_eth1_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
-+ AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
+ &ar5312_eth1_data);
+
+ if (!ath25_board.radio)
+ }
+
+ if (config->flags & BD_WLAN1)
-+ ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
++ ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
+}
+
+static void ar5312_restart(char *command)
+ /* reset the system */
+ local_irq_disable();
+ while (1)
-+ ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
++ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
+}
+
+/*
+ u16 devid;
+
+ /* Trust the bootrom's idea of cpu frequency. */
-+ scratch = ar231x_read_reg(AR5312_SCRATCH);
++ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
+ if (scratch)
+ return scratch;
+
-+ devid = ar231x_read_reg(AR5312_REV);
++ devid = ar5312_rst_reg_read(AR5312_REV);
+ devid &= AR5312_REV_MAJ;
+ devid >>= AR5312_REV_MAJ_S;
+ if (devid == AR5312_REV_MAJ_AR2313) {
+ * We compute the CPU frequency, based on PLL settings.
+ */
+
-+ clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
++ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
+ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
+ predivisor = clockctl1_predivide_table[predivide_select];
+ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
+
+void __init ar5312_plat_mem_setup(void)
+{
-+ u32 memsize, memcfg, bank0AC, bank1AC;
++ void __iomem *sdram_base;
++ u32 memsize, memcfg, bank0_ac, bank1_ac;
+ u32 devid;
+
+ /* Detect memory size */
-+ memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
-+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
-+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
-+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
-+ (bank1AC ? (1 << (bank1AC+1)) : 0);
++ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
++ AR5312_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
++ bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
++ bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
++ memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
++ (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
+ memsize <<= 20;
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
+
-+ devid = ar231x_read_reg(AR5312_REV);
++ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
+ devid >>= AR5312_REV_WMAC_MIN_S;
+ devid &= AR5312_REV_CHIP;
+ ath25_board.devid = (u16)devid;
+
+ /* Clear any lingering AHB errors */
-+ ar231x_read_reg(AR5312_PROCADDR);
-+ ar231x_read_reg(AR5312_DMAADDR);
-+ ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
++ ar5312_rst_reg_read(AR5312_PROCADDR);
++ ar5312_rst_reg_read(AR5312_DMAADDR);
++ ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
+
+ _machine_restart = ar5312_restart;
+}
+
+void __init ar5312_arch_init(void)
+{
-+ ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
-+ ar5312_sys_frequency());
++ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
++ AR5312_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
+}
--- /dev/null
+++ b/arch/mips/ath25/ar2315.c
-@@ -0,0 +1,401 @@
+@@ -0,0 +1,438 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
+#include <linux/reboot.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/io.h>
+
+#include <ath25_platform.h>
-+#include <ar2315_regs.h>
-+#include <ar231x.h>
++
+#include "devices.h"
+#include "ar2315.h"
++#include "ar2315_regs.h"
++
++static void __iomem *ar2315_rst_base;
++static struct irq_domain *ar2315_misc_irq_domain;
++
++static inline u32 ar2315_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar2315_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar2315_rst_reg_write(reg, ret);
++}
+
+static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
+{
-+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
-+ ar231x_read_reg(AR2315_AHB_ERR1);
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
+
+ pr_emerg("AHB fatal error\n");
+ machine_restart("AHB error"); /* Catastrophic failure */
+
+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
-+ ar231x_read_reg(AR2315_IMR);
-+
-+ if (misc_intr & AR2315_ISR_SPI)
-+ generic_handle_irq(AR2315_MISC_IRQ_SPI);
-+ else if (misc_intr & AR2315_ISR_TIMER)
-+ generic_handle_irq(AR2315_MISC_IRQ_TIMER);
-+ else if (misc_intr & AR2315_ISR_AHB)
-+ generic_handle_irq(AR2315_MISC_IRQ_AHB);
-+ else if (misc_intr & AR2315_ISR_GPIO) {
-+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
-+ generic_handle_irq(AR2315_MISC_IRQ_GPIO);
-+ } else if (misc_intr & AR2315_ISR_UART0)
-+ generic_handle_irq(AR2315_MISC_IRQ_UART0);
-+ else if (misc_intr & AR2315_ISR_WD) {
-+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
-+ generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
-+ } else
++ u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
++ ar2315_rst_reg_read(AR2315_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ if (nr == AR2315_MISC_IRQ_GPIO)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
++ else if (nr == AR2315_MISC_IRQ_WATCHDOG)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
++ generic_handle_irq(misc_irq);
++ } else {
+ spurious_interrupt();
++ }
+}
+
+static void ar2315_misc_irq_unmask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar231x_write_reg(AR2315_IMR, imr);
++ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
+}
+
+static void ar2315_misc_irq_mask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar231x_write_reg(AR2315_IMR, imr);
++ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
+}
+
+static struct irq_chip ar2315_misc_irq_chip = {
+ .irq_mask = ar2315_misc_irq_mask,
+};
+
++static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
++ .map = ar2315_misc_irq_map,
++};
++
+/*
+ * Called when an interrupt is received, this function
+ * determines exactly which interrupt it was, and it
+ */
+static void ar2315_irq_dispatch(void)
+{
-+ int pending = read_c0_status() & read_c0_cause();
++ u32 pending = read_c0_status() & read_c0_cause();
+
+ if (pending & CAUSEF_IP3)
-+ do_IRQ(AR2315_IRQ_WLAN0_INTRS);
++ do_IRQ(AR2315_IRQ_WLAN0);
+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR2315_IRQ_ENET0_INTRS);
++ do_IRQ(AR2315_IRQ_ENET0);
+ else if (pending & CAUSEF_IP2)
-+ do_IRQ(AR2315_IRQ_MISC_INTRS);
++ do_IRQ(AR2315_IRQ_MISC);
+ else if (pending & CAUSEF_IP7)
-+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
+ else
+ spurious_interrupt();
+}
+
+void __init ar2315_arch_init_irq(void)
+{
-+ int i;
++ struct irq_domain *domain;
++ unsigned irq;
+
+ ath25_irq_dispatch = ar2315_irq_dispatch;
-+ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
-+ int irq = AR231X_MISC_IRQ_BASE + i;
+
-+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
-+ handle_level_irq);
-+ }
-+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
-+ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
++ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
++ &ar2315_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
++ setup_irq(irq, &ar2315_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
++ irq_set_handler_data(AR2315_IRQ_MISC, domain);
++
++ ar2315_misc_irq_domain = domain;
+}
+
+static void ar2315_device_reset_set(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR2315_RESET);
-+ ar231x_write_reg(AR2315_RESET, val | mask);
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val | mask);
+}
+
+static void ar2315_device_reset_clear(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR2315_RESET);
-+ ar231x_write_reg(AR2315_RESET, val & ~mask);
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
+}
+
+static struct ar231x_eth ar2315_eth_data = {
+ {
+ .name = "spiflash_read",
+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_READ,
-+ .end = AR2315_SPI_READ + 0x1000000 - 1,
++ .start = AR2315_SPI_READ_BASE,
++ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
+ },
+ {
+ .name = "spiflash_mmr",
+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_MMR,
-+ .end = AR2315_SPI_MMR + 12 - 1,
++ .start = AR2315_SPI_MMR_BASE,
++ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
+ },
+};
+
+static struct resource ar2315_wdt_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_WD,
-+ .end = AR2315_WD + 8 - 1,
++ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
++ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
-+ .start = AR2315_MISC_IRQ_WATCHDOG,
-+ .end = AR2315_MISC_IRQ_WATCHDOG,
+ }
+};
+
+ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
+};
+
-+/*
-+ * NB: We use mapping size that is larger than the actual flash size,
-+ * but this shouldn't be a problem here, because the flash will simply
-+ * be mapped multiple times.
-+ */
-+static u8 __init *ar2315_flash_limit(void)
-+{
-+ return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
-+}
-+
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led ar2315_leds[6];
+static struct gpio_led_platform_data ar2315_led_data = {
+void __init ar2315_init_devices(void)
+{
+ /* Find board configuration */
-+ ath25_find_config(ar2315_flash_limit());
++ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
+
+ ar2315_init_gpio_leds();
++
++ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_WATCHDOG);
++ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
+ platform_device_register(&ar2315_wdt);
++
+ platform_device_register(&ar2315_spiflash);
-+ ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
-+ AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
-+ ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
++
++ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
++ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
++ &ar2315_eth_data);
++
++ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
+}
+
+static void ar2315_restart(char *command)
+ local_irq_disable();
+
+ /* try reset the system via reset control */
-+ ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
++ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
+
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
+ * a workaround. Give it some time to attempt a gpio based hardware
+ unsigned int pllc_out, refdiv, fdiv, divby2;
+ unsigned int clk_div;
+
-+ pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
-+ refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
++ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
++ refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
+ refdiv = clockctl1_predivide_table[refdiv];
-+ fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
-+ divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
-+ divby2 += 1;
++ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
++ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
+ pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
+
+ /* clkm input selected */
-+ switch (clock_ctl & CPUCLK_CLK_SEL_M) {
++ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
+ case 0:
+ case 1:
-+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
-+ PLLC_CLKM_DIV_S];
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
++ clk_div = pllc_divide_table[clk_div];
+ break;
+ case 2:
-+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
-+ PLLC_CLKC_DIV_S];
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
++ clk_div = pllc_divide_table[clk_div];
+ break;
+ default:
+ pllc_out = 40000000;
+ break;
+ }
+
-+ cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
++ cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
+ cpu_div = cpu_div * 2 ?: 1;
+
+ return pllc_out / (clk_div * cpu_div);
+
+static inline unsigned ar2315_cpu_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
+}
+
+static inline unsigned ar2315_apb_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
+}
+
+void __init ar2315_plat_time_init(void)
+
+void __init ar2315_plat_mem_setup(void)
+{
++ void __iomem *sdram_base;
+ u32 memsize, memcfg;
+ u32 devid;
+ u32 config;
+
-+ memcfg = ar231x_read_reg(AR2315_MEM_CFG);
-+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
-+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
-+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
++ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
++ AR2315_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
++ memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
+ memsize <<= 3;
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
+
+ /* Detect the hardware based on the device ID */
-+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
++ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
+ switch (devid) {
+ case 0x91: /* Need to check */
+ ath25_soc = ATH25_SOC_AR2318;
+ /* Clear any lingering AHB errors */
+ config = read_c0_config();
+ write_c0_config(config & ~0x3);
-+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
-+ ar231x_read_reg(AR2315_AHB_ERR1);
-+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++ ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
+
+ _machine_restart = ar2315_restart;
+}
+
+void __init ar2315_arch_init(void)
+{
-+ ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
-+ ar2315_apb_frequency());
++ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
+}
--- /dev/null
+++ b/arch/mips/ath25/ar2315.h
+
+#endif
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ath25/ar231x.h
-@@ -0,0 +1,38 @@
-+#ifndef __ASM_MACH_ATH25_AR231X_H
-+#define __ASM_MACH_ATH25_AR231X_H
-+
-+#include <linux/types.h>
-+#include <linux/io.h>
++++ b/arch/mips/ath25/devices.h
+@@ -0,0 +1,45 @@
++#ifndef __ATH25_DEVICES_H
++#define __ATH25_DEVICES_H
+
-+#define AR231X_MISC_IRQ_BASE 0x20
+#define AR231X_GPIO_IRQ_BASE 0x30
+
-+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
-+
-+static inline u32
-+ar231x_read_reg(u32 reg)
-+{
-+ return __raw_readl((void __iomem *)KSEG1ADDR(reg));
-+}
++#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
+
-+static inline void
-+ar231x_write_reg(u32 reg, u32 val)
-+{
-+ __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
-+}
-+
-+static inline u32
-+ar231x_mask_reg(u32 reg, u32 mask, u32 val)
-+{
-+ u32 ret;
-+
-+ ret = ar231x_read_reg(reg);
-+ ret &= ~mask;
-+ ret |= val;
-+ ar231x_write_reg(reg, ret);
-+
-+ return ret;
-+}
-+
-+#endif /* __ASM_MACH_ATH25_AR231X_H */
---- /dev/null
-+++ b/arch/mips/ath25/devices.h
-@@ -0,0 +1,39 @@
-+#ifndef __ATH25_DEVICES_H
-+#define __ATH25_DEVICES_H
++#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
+
+enum ath25_soc_type {
+ /* handled by ar5312.c */
+extern struct ar231x_board_config ath25_board;
+extern void (*ath25_irq_dispatch)(void);
+
-+int ath25_find_config(u8 *flash_limit);
++int ath25_find_config(phys_addr_t offset, unsigned long size);
+int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
+ int irq, void *pdata);
+void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
+#endif
--- /dev/null
+++ b/arch/mips/ath25/devices.c
-@@ -0,0 +1,192 @@
+@@ -0,0 +1,191 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <asm/bootinfo.h>
+
+#include <ath25_platform.h>
-+#include <ar231x.h>
+#include "devices.h"
+#include "ar5312.h"
+#include "ar2315.h"
projects / openwrt / svn-archive / archive.git / blobdiff