[brcm63xx] more fixes for bcm6338, no need not to prevent reads from MPI registers...

[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 6209f47bcc890a17a842acb3518f573fbefbccd0..58ed2705ba170f28177026751315e0b6c4b3516c 100644 (file)
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -123,7 +123,7 @@ enum bcm63xx_regs_set {
 
 #define BCM_6338_DSL_LMEM_BASE         (0xfff00000)
 #define BCM_6338_PERF_BASE             (0xfffe0000)
 
 #define BCM_6338_DSL_LMEM_BASE         (0xfff00000)
 #define BCM_6338_PERF_BASE             (0xfffe0000)

-#define BCM_6338_BB_BASE               (0xdeadbeef)
+#define BCM_6338_BB_BASE               (0xfffe0100)

 #define BCM_6338_TIMER_BASE            (0xfffe0200)
 #define BCM_6338_WDT_BASE              (0xfffe021c)
 #define BCM_6338_UART0_BASE            (0xfffe0300)
 #define BCM_6338_TIMER_BASE            (0xfffe0200)
 #define BCM_6338_WDT_BASE              (0xfffe021c)
 #define BCM_6338_UART0_BASE            (0xfffe0300)


@@ -132,9 +132,9 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UDC0_BASE             (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE           (0xfffe2400)
 #define BCM_6338_OHCI0_BASE            (0xdeadbeef)
 #define BCM_6338_UDC0_BASE             (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE           (0xfffe2400)
 #define BCM_6338_OHCI0_BASE            (0xdeadbeef)

-#define BCM_6338_OHCI_PRIV_BASE                (0xdeadbeef)
+#define BCM_6338_OHCI_PRIV_BASE                (0xfffe3000)

 #define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)
 #define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)

-#define BCM_6338_MPI_BASE              (0xdeadbeef)
+#define BCM_6338_MPI_BASE              (0xfffe3160)

 #define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE       (0xfffe3100)
 #define BCM_6338_DSL_BASE              (0xfffe1000)
 #define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE       (0xfffe3100)
 #define BCM_6338_DSL_BASE              (0xfffe1000)


@@ -142,7 +142,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UBUS_BASE             (0xdeadbeef)
 #define BCM_6338_ENET0_BASE            (0xfffe2800)
 #define BCM_6338_ENET1_BASE            (0xdeadbeef)
 #define BCM_6338_UBUS_BASE             (0xdeadbeef)
 #define BCM_6338_ENET0_BASE            (0xfffe2800)
 #define BCM_6338_ENET1_BASE            (0xdeadbeef)

-#define BCM_6338_ENETDMA_BASE          (0xfffe3800)
+#define BCM_6338_ENETDMA_BASE          (0xfffe2400)

 #define BCM_6338_EHCI0_BASE            (0xdeadbeef)
 #define BCM_6338_SDRAM_BASE            (0xfffe3100)
 #define BCM_6338_MEMC_BASE             (0xdeadbeef)
 #define BCM_6338_EHCI0_BASE            (0xdeadbeef)
 #define BCM_6338_SDRAM_BASE            (0xfffe3100)
 #define BCM_6338_MEMC_BASE             (0xdeadbeef)