-From d93661c9e164ccc41820eeb4f1881e59a34a9e5c Mon Sep 17 00:00:00 2001
+From cfe7647c2a4decf874dff8abb60704e9917f76fe Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:55:02 +0100
-Subject: [PATCH 19/20] MIPS: BCM63XX: switch to IRQ_DOMAIN
+Subject: [PATCH 3/5] MIPS: BCM63XX: switch to IRQ_DOMAIN
Now that we have working IRQ_DOMAIN drivers for both interrupt controllers,
switch to using them.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/Kconfig | 3 +
- arch/mips/bcm63xx/irq.c | 608 ++++++++---------------------------------------
- 2 files changed, 108 insertions(+), 503 deletions(-)
+ arch/mips/bcm63xx/irq.c | 609 +++++++++--------------------------------------
+ 2 files changed, 109 insertions(+), 503 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
select DMA_NONCOHERENT
select IRQ_CPU
+ select BCM6345_EXT_IRQ
-+ select BCM6345_L2_IRQ
++ select BCM6345_PERIPH_IRQ
+ select IRQ_DOMAIN
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
#include <linux/irq.h>
-#include <linux/spinlock.h>
+#include <linux/irqchip.h>
-+#include <linux/irqchip/irq-bcm6345-ext-intc.h>
-+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
-@@ -20,544 +22,144 @@
+@@ -20,544 +22,145 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
-+ void __iomem *l2_intc_bases[2];
++ void __iomem *periph_bases[2];
+ void __iomem *ext_intc_bases[2];
-+ int l2_irq_count, l2_width, ext_irq_count, ext_shift;
-+ int l2_irqs[2] = { 2, 3 };
++ int periph_irq_count, periph_width, ext_irq_count, ext_shift;
++ int periph_irqs[2] = { 2, 3 };
+ int ext_irqs[6];
+
-+ l2_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
-+ l2_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
-+ l2_intc_bases[0] += PERF_IRQMASK_3368_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_3368_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
-+ l2_intc_bases[0] += PERF_IRQMASK_6328_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6328_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
-+ l2_intc_bases[0] += PERF_IRQMASK_6338_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6338_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
-+ l2_intc_bases[0] += PERF_IRQMASK_6345_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6345_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
-+ l2_intc_bases[0] += PERF_IRQMASK_6348_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6348_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
-+ l2_intc_bases[0] += PERF_IRQMASK_6358_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6358_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6358_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6358_REG(1);
++ periph_irq_count = 2;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
-+ l2_intc_bases[0] += PERF_IRQMASK_6362_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6362_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6362_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6362_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
+ ext_irq_count = 4;
- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
- irq_bits = 64;
-+ l2_intc_bases[0] += PERF_IRQMASK_6368_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6368_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6368_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6368_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
+ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
- internal_irq_unmask = __internal_irq_unmask_64;
- }
+ mips_cpu_irq_init();
-+ bcm6345_l2_intc_init(l2_irq_count, l2_irqs, l2_intc_bases, l2_width);
++ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,
++ periph_width);
+ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
+ if (ext_irq_count > 4)
+ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],
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