config BCMA_DRIVER_PCI_HOSTMODE
bool "Driver for PCI core working in hostmode"
+@@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
+ PCI core hostmode operation (external PCI bus).
+
+ config BCMA_HOST_SOC
+- bool
+- depends on BCMA_DRIVER_MIPS
++ bool "Support for BCMA in a SoC"
++ depends on BCMA
++ help
++ Host interface for a Broadcom AIX bus directly mapped into
++ the memory. This only works with the Broadcom SoCs from the
++ BCM47XX line.
++
++ If unsure, say N
+
+ config BCMA_DRIVER_MIPS
+ bool "BCMA Broadcom MIPS core driver"
+@@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
+ config BCMA_DRIVER_GPIO
+ bool "BCMA GPIO driver"
+ depends on BCMA && GPIOLIB
++ select IRQ_DOMAIN if BCMA_HOST_SOC
+ help
+ Driver to provide access to the GPIO pins of the bcma bus.
+
+--- a/drivers/bcma/Makefile
++++ b/drivers/bcma/Makefile
+@@ -1,8 +1,10 @@
+ bcma-y += main.o scan.o core.o sprom.o
+ bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
++bcma-y += driver_chipcommon_b.o
+ bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
+ bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
+ bcma-y += driver_pci.o
++bcma-y += driver_pcie2.o
+ bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
+ bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
+ bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
--- a/drivers/bcma/bcma_private.h
+++ b/drivers/bcma/bcma_private.h
@@ -22,6 +22,8 @@
int bcma_bus_register(struct bcma_bus *bus);
void bcma_bus_unregister(struct bcma_bus *bus);
int __init bcma_bus_early_register(struct bcma_bus *bus,
+@@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
+ int bcma_bus_suspend(struct bcma_bus *bus);
+ int bcma_bus_resume(struct bcma_bus *bus);
+ #endif
+-struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
+- u8 unit);
+
+ /* scan.c */
+ int bcma_bus_scan(struct bcma_bus *bus);
+@@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
+ extern struct platform_device bcma_pflash_dev;
+ #endif /* CONFIG_BCMA_DRIVER_MIPS */
+
++/* driver_chipcommon_b.c */
++int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
++void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
++
+ /* driver_chipcommon_pmu.c */
+ u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
+ u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
--- a/drivers/bcma/core.c
+++ b/drivers/bcma/core.c
@@ -9,6 +9,25 @@
bcma_pmu_resources_init(cc);
bcma_pmu_workarounds(cc);
}
+@@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
+ break;
+
++ case BCMA_CHIP_ID_BCM43131:
++ case BCMA_CHIP_ID_BCM43217:
+ case BCMA_CHIP_ID_BCM43227:
+ case BCMA_CHIP_ID_BCM43228:
+ case BCMA_CHIP_ID_BCM43428:
--- a/drivers/bcma/driver_chipcommon_sflash.c
+++ b/drivers/bcma/driver_chipcommon_sflash.c
@@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
{ "M25P20", 0x11, 0x10000, 4, },
{ "M25P40", 0x12, 0x10000, 8, },
-@@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
- { 0 },
+@@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
+ { "M25P32", 0x15, 0x10000, 64, },
+ { "M25P64", 0x16, 0x10000, 128, },
+ { "M25FL128", 0x17, 0x10000, 256, },
+- { 0 },
++ { NULL },
};
-static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
{ "SST25WF512", 1, 0x1000, 16, },
{ "SST25VF512", 0x48, 0x1000, 16, },
{ "SST25WF010", 2, 0x1000, 32, },
-@@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
- { 0 },
+@@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
+ { "SST25VF016", 0x41, 0x1000, 512, },
+ { "SST25VF032", 0x4a, 0x1000, 1024, },
+ { "SST25VF064", 0x4b, 0x1000, 2048, },
+- { 0 },
++ { NULL },
};
-static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
{ "AT45DB011", 0xc, 256, 512, },
{ "AT45DB021", 0x14, 256, 1024, },
{ "AT45DB041", 0x1c, 256, 2048, },
+@@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
+ { "AT45DB161", 0x2c, 512, 4096, },
+ { "AT45DB321", 0x34, 512, 8192, },
+ { "AT45DB642", 0x3c, 1024, 8192, },
+- { 0 },
++ { NULL },
+ };
+
+ static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
@@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
{
struct bcma_bus *bus = cc->core->bus;
u32 id, id2;
switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+--- a/drivers/bcma/driver_gpio.c
++++ b/drivers/bcma/driver_gpio.c
+@@ -9,6 +9,9 @@
+ */
+
+ #include <linux/gpio.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/irqdomain.h>
+ #include <linux/export.h>
+ #include <linux/bcma/bcma.h>
+
+@@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
+ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
+ }
+
++#if IS_BUILTIN(CONFIG_BCM47XX)
+ static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
+ {
+ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
+
+ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
+- return bcma_core_irq(cc->core);
++ return irq_find_mapping(cc->irq_domain, gpio);
+ else
+ return -EINVAL;
+ }
+
++static void bcma_gpio_irq_unmask(struct irq_data *d)
++{
++ struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
++ int gpio = irqd_to_hwirq(d);
++ u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
++
++ bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
++ bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
++}
++
++static void bcma_gpio_irq_mask(struct irq_data *d)
++{
++ struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
++ int gpio = irqd_to_hwirq(d);
++
++ bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
++}
++
++static struct irq_chip bcma_gpio_irq_chip = {
++ .name = "BCMA-GPIO",
++ .irq_mask = bcma_gpio_irq_mask,
++ .irq_unmask = bcma_gpio_irq_unmask,
++};
++
++static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
++{
++ struct bcma_drv_cc *cc = dev_id;
++ u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
++ u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
++ u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
++ unsigned long irqs = (val ^ pol) & mask;
++ int gpio;
++
++ if (!irqs)
++ return IRQ_NONE;
++
++ for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
++ generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
++ bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
++
++ return IRQ_HANDLED;
++}
++
++static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
++{
++ struct gpio_chip *chip = &cc->gpio;
++ int gpio, hwirq, err;
++
++ if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
++ return 0;
++
++ cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
++ &irq_domain_simple_ops, cc);
++ if (!cc->irq_domain) {
++ err = -ENODEV;
++ goto err_irq_domain;
++ }
++ for (gpio = 0; gpio < chip->ngpio; gpio++) {
++ int irq = irq_create_mapping(cc->irq_domain, gpio);
++
++ irq_set_chip_data(irq, cc);
++ irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
++ handle_simple_irq);
++ }
++
++ hwirq = bcma_core_irq(cc->core);
++ err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
++ cc);
++ if (err)
++ goto err_req_irq;
++
++ bcma_chipco_gpio_intmask(cc, ~0, 0);
++ bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
++
++ return 0;
++
++err_req_irq:
++ for (gpio = 0; gpio < chip->ngpio; gpio++) {
++ int irq = irq_find_mapping(cc->irq_domain, gpio);
++
++ irq_dispose_mapping(irq);
++ }
++ irq_domain_remove(cc->irq_domain);
++err_irq_domain:
++ return err;
++}
++
++static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
++{
++ struct gpio_chip *chip = &cc->gpio;
++ int gpio;
++
++ if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
++ return;
++
++ bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
++ free_irq(bcma_core_irq(cc->core), cc);
++ for (gpio = 0; gpio < chip->ngpio; gpio++) {
++ int irq = irq_find_mapping(cc->irq_domain, gpio);
++
++ irq_dispose_mapping(irq);
++ }
++ irq_domain_remove(cc->irq_domain);
++}
++#else
++static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
++{
++ return 0;
++}
++
++static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
++{
++}
++#endif
++
+ int bcma_gpio_init(struct bcma_drv_cc *cc)
+ {
+ struct gpio_chip *chip = &cc->gpio;
++ int err;
+
+ chip->label = "bcma_gpio";
+ chip->owner = THIS_MODULE;
+@@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
+ chip->set = bcma_gpio_set_value;
+ chip->direction_input = bcma_gpio_direction_input;
+ chip->direction_output = bcma_gpio_direction_output;
++#if IS_BUILTIN(CONFIG_BCM47XX)
+ chip->to_irq = bcma_gpio_to_irq;
+- chip->ngpio = 16;
++#endif
++ switch (cc->core->bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM53572:
++ chip->ngpio = 32;
++ break;
++ default:
++ chip->ngpio = 16;
++ }
++
+ /* There is just one SoC in one device and its GPIO addresses should be
+ * deterministic to address them more easily. The other buses could get
+ * a random base number. */
+@@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
+ else
+ chip->base = -1;
+
+- return gpiochip_add(chip);
++ err = bcma_gpio_irq_domain_init(cc);
++ if (err)
++ return err;
++
++ err = gpiochip_add(chip);
++ if (err) {
++ bcma_gpio_irq_domain_exit(cc);
++ return err;
++ }
++
++ return 0;
+ }
+
+ int bcma_gpio_unregister(struct bcma_drv_cc *cc)
+ {
++ bcma_gpio_irq_domain_exit(cc);
+ return gpiochip_remove(&cc->gpio);
+ }
+--- a/drivers/bcma/driver_pci.c
++++ b/drivers/bcma/driver_pci.c
+@@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
+ }
+
+-static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
++static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
+ {
+ u32 v;
+ int i;
+@@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
+ }
+ }
+
+-static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
++static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
+ {
+ int max_retries = 10;
+ u16 ret = 0;
+@@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
+ return ret;
+ }
+
+-static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
++static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
+ u8 address, u16 data)
+ {
+ int max_retries = 10;
+@@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
+ }
+
++static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
++ u8 address, u16 data)
++{
++ bcma_pcie_mdio_write(pc, device, address, data);
++ return bcma_pcie_mdio_read(pc, device, address);
++}
++
+ /**************************************************
+ * Workarounds.
+ **************************************************/
+@@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
+ bcma_core_pci_clientmode_init(pc);
+ }
+
++void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
++{
++ struct bcma_drv_pci *pc;
++ u16 data;
++
++ if (bus->hosttype != BCMA_HOSTTYPE_PCI)
++ return;
++
++ pc = &bus->drv_pci[0];
++
++ if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
++ data = up ? 0x74 : 0x7C;
++ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
++ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
++ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
++ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
++ } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
++ data = up ? 0x75 : 0x7D;
++ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
++ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
++ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
++ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
++ }
++}
++EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
++
+ int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
+ bool enable)
+ {
+@@ -262,7 +295,7 @@ out:
+ }
+ EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
+
+-void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
++static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
+ {
+ u32 w;
+
+@@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
+ bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
+ bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
+ }
+-EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
++
++void bcma_core_pci_up(struct bcma_bus *bus)
++{
++ struct bcma_drv_pci *pc;
++
++ if (bus->hosttype != BCMA_HOSTTYPE_PCI)
++ return;
++
++ pc = &bus->drv_pci[0];
++
++ bcma_core_pci_extend_L1timer(pc, true);
++}
++EXPORT_SYMBOL_GPL(bcma_core_pci_up);
++
++void bcma_core_pci_down(struct bcma_bus *bus)
++{
++ struct bcma_drv_pci *pc;
++
++ if (bus->hosttype != BCMA_HOSTTYPE_PCI)
++ return;
++
++ pc = &bus->drv_pci[0];
++
++ bcma_core_pci_extend_L1timer(pc, false);
++}
++EXPORT_SYMBOL_GPL(bcma_core_pci_down);
+--- a/drivers/bcma/driver_pci_host.c
++++ b/drivers/bcma/driver_pci_host.c
+@@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
+ int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
+ {
+ struct bcma_drv_pci_host *pc_host;
++ int readrq;
+
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
+ /* This is not a device on the PCI-core bridge. */
+@@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
+ dev->irq = bcma_core_irq(pc_host->pdev->core);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+
++ readrq = pcie_get_readrq(dev);
++ if (readrq > 128) {
++ pr_info("change PCIe max read request size from %i to 128\n", readrq);
++ pcie_set_readrq(dev, 128);
++ }
+ return 0;
+ }
+ EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
+--- /dev/null
++++ b/drivers/bcma/driver_pcie2.c
+@@ -0,0 +1,175 @@
++/*
++ * Broadcom specific AMBA
++ * PCIe Gen 2 Core
++ *
++ * Copyright 2014, Broadcom Corporation
++ * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++/**************************************************
++ * R/W ops.
++ **************************************************/
++
++#if 0
++static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
++ pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
++ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
++}
++#endif
++
++static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
++ u32 val)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
++}
++
++/**************************************************
++ * Init.
++ **************************************************/
++
++static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
++ bool enable)
++{
++ u32 val;
++
++ /* restore back to default */
++ val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
++ val |= PCIE2_CLKC_DLYPERST;
++ val &= ~PCIE2_CLKC_DISSPROMLD;
++ if (enable) {
++ val &= ~PCIE2_CLKC_DLYPERST;
++ val |= PCIE2_CLKC_DISSPROMLD;
++ }
++ pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
++ /* flush */
++ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
++}
++
++static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
++{
++ /* LTR0 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
++ /* LTR1 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
++ /* LTR2 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
++}
++
++static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
++{
++ u8 core_rev = pcie2->core->id.rev;
++ u32 devstsctr2;
++
++ if (core_rev < 2 || core_rev == 10 || core_rev > 13)
++ return;
++
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
++ devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
++ if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
++ /* force the right LTR values */
++ bcma_core_pcie2_set_ltr_vals(pcie2);
++
++ /* TODO:
++ si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
++
++ /* enable the LTR */
++ devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
++
++ /* set the LTR state to be active */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
++ PCIE2_LTR_ACTIVE);
++ usleep_range(1000, 2000);
++
++ /* set the LTR state to be sleep */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
++ PCIE2_LTR_SLEEP);
++ usleep_range(1000, 2000);
++ }
++}
++
++static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
++{
++ u8 core_rev = pcie2->core->id.rev;
++ bool pciewar160, pciewar162;
++
++ pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
++ pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
++ core_rev == 9 || core_rev == 11;
++
++ if (!pciewar160 && !pciewar162)
++ return;
++
++/* TODO */
++#if 0
++ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
++ PCIE_DISABLE_L1CLK_GATING);
++#if 0
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIEGEN2_COE_PVT_TL_CTRL_0);
++ pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
++ ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
++#endif
++#endif
++}
++
++static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
++ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
++}
++
++static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
++}
++
++static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
++{
++ struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
++ u8 core_rev = pcie2->core->id.rev;
++ u32 alp_khz, pm_value;
++
++ if (core_rev <= 13) {
++ alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
++ pm_value = (1000000 * 2) / alp_khz;
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_PVT_REG_PM_CLK_PERIOD);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
++ }
++}
++
++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
++{
++ struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
++ u32 tmp;
++
++ tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
++ if ((tmp & 0xe) >> 1 == 2)
++ bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
++
++ /* TODO: Do we need pcie_reqsize? */
++
++ if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
++ bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
++ bcma_core_pcie2_hw_ltr_war(pcie2);
++ pciedev_crwlpciegen2(pcie2);
++ pciedev_reg_pm_clk_period(pcie2);
++ pciedev_crwlpciegen2_180(pcie2);
++ pciedev_crwlpciegen2_182(pcie2);
++}
--- a/drivers/bcma/host_pci.c
+++ b/drivers/bcma/host_pci.c
-@@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
+@@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
+ pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
+
+ /* SSB needed additional powering up, do we have any AMBA PCI cards? */
+- if (!pci_is_pcie(dev))
+- bcma_err(bus, "PCI card detected, report problems.\n");
++ if (!pci_is_pcie(dev)) {
++ bcma_err(bus, "PCI card detected, they are not supported.\n");
++ err = -ENXIO;
++ goto err_pci_release_regions;
++ }
+
+ /* Map MMIO */
+ err = -ENOMEM;
+@@ -205,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
+ bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
+ bus->boardinfo.type = bus->host_pci->subsystem_device;
+
++ /* Initialize struct, detect chip */
++ bcma_init_bus(bus);
++
+ /* Register */
+ err = bcma_bus_register(bus);
+ if (err)
+@@ -235,7 +241,6 @@ static void bcma_host_pci_remove(struct
+ pci_release_regions(dev);
+ pci_disable_device(dev);
+ kfree(bus);
+- pci_set_drvdata(dev, NULL);
+ }
+
+ #ifdef CONFIG_PM_SLEEP
+@@ -267,15 +272,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
+
+ #endif /* CONFIG_PM_SLEEP */
+
+-static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
++static const struct pci_device_id bcma_pci_bridge_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
{ 0, },
};
+ MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
--- a/drivers/bcma/main.c
+++ b/drivers/bcma/main.c
-@@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(
+@@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b
+ return BCMA_CORE_CHIPCOMMON;
+ }
+
+-struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit)
+ {
+ struct bcma_device *core;
+
+ list_for_each_entry(core, &bus->cores, list) {
+- if (core->id.id == coreid)
++ if (core->id.id == coreid && core->core_unit == unit)
+ return core;
+ }
return NULL;
}
+-EXPORT_SYMBOL_GPL(bcma_find_core);
++EXPORT_SYMBOL_GPL(bcma_find_core_unit);
+-struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
+- u8 unit)
+bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
+ int timeout)
-+{
+ {
+- struct bcma_device *core;
+ unsigned long deadline = jiffies + timeout;
+ u32 val;
-+
+
+- list_for_each_entry(core, &bus->cores, list) {
+- if (core->id.id == coreid && core->core_unit == unit)
+- return core;
+- }
+- return NULL;
+ do {
+ val = bcma_read32(core, reg);
+ if ((val & mask) == value)
+
+ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
+
++ return false;
+ }
+
+ static void bcma_release_core_dev(struct device *dev)
+@@ -103,55 +111,78 @@ static void bcma_release_core_dev(struct
+ kfree(core);
+ }
+
+-static int bcma_register_cores(struct bcma_bus *bus)
++static bool bcma_is_core_needed_early(u16 core_id)
++{
++ switch (core_id) {
++ case BCMA_CORE_NS_NAND:
++ case BCMA_CORE_NS_QSPI:
++ return true;
++ }
++
+ return false;
+}
+
- static void bcma_release_core_dev(struct device *dev)
++static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
++{
++ int err;
++
++ core->dev.release = bcma_release_core_dev;
++ core->dev.bus = &bcma_bus_type;
++ dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
++
++ switch (bus->hosttype) {
++ case BCMA_HOSTTYPE_PCI:
++ core->dev.parent = &bus->host_pci->dev;
++ core->dma_dev = &bus->host_pci->dev;
++ core->irq = bus->host_pci->irq;
++ break;
++ case BCMA_HOSTTYPE_SOC:
++ core->dev.dma_mask = &core->dev.coherent_dma_mask;
++ core->dma_dev = &core->dev;
++ break;
++ case BCMA_HOSTTYPE_SDIO:
++ break;
++ }
++
++ err = device_register(&core->dev);
++ if (err) {
++ bcma_err(bus, "Could not register dev for core 0x%03X\n",
++ core->id.id);
++ put_device(&core->dev);
++ return;
++ }
++ core->dev_registered = true;
++}
++
++static int bcma_register_devices(struct bcma_bus *bus)
{
- struct bcma_device *core = container_of(dev, struct bcma_device, dev);
+ struct bcma_device *core;
+- int err, dev_id = 0;
++ int err;
+
+ list_for_each_entry(core, &bus->cores, list) {
+ /* We support that cores ourself */
+ switch (core->id.id) {
+ case BCMA_CORE_4706_CHIPCOMMON:
+ case BCMA_CORE_CHIPCOMMON:
++ case BCMA_CORE_NS_CHIPCOMMON_B:
+ case BCMA_CORE_PCI:
+ case BCMA_CORE_PCIE:
++ case BCMA_CORE_PCIE2:
+ case BCMA_CORE_MIPS_74K:
+ case BCMA_CORE_4706_MAC_GBIT_COMMON:
+ continue;
+ }
+
++ /* Early cores were already registered */
++ if (bcma_is_core_needed_early(core->id.id))
++ continue;
++
+ /* Only first GMAC core on BCM4706 is connected and working */
+ if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
+ core->core_unit > 0)
+ continue;
+
+- core->dev.release = bcma_release_core_dev;
+- core->dev.bus = &bcma_bus_type;
+- dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
+-
+- switch (bus->hosttype) {
+- case BCMA_HOSTTYPE_PCI:
+- core->dev.parent = &bus->host_pci->dev;
+- core->dma_dev = &bus->host_pci->dev;
+- core->irq = bus->host_pci->irq;
+- break;
+- case BCMA_HOSTTYPE_SOC:
+- core->dev.dma_mask = &core->dev.coherent_dma_mask;
+- core->dma_dev = &core->dev;
+- break;
+- case BCMA_HOSTTYPE_SDIO:
+- break;
+- }
+-
+- err = device_register(&core->dev);
+- if (err) {
+- bcma_err(bus,
+- "Could not register dev for core 0x%03X\n",
+- core->id.id);
+- continue;
+- }
+- core->dev_registered = true;
+- dev_id++;
++ bcma_register_core(bus, core);
+ }
+
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+@@ -218,7 +249,7 @@ int bcma_bus_register(struct bcma_bus *b
+ err = bcma_bus_scan(bus);
+ if (err) {
+ bcma_err(bus, "Failed to scan: %d\n", err);
+- return -1;
++ return err;
+ }
+
+ /* Early init CC core */
+@@ -228,6 +259,12 @@ int bcma_bus_register(struct bcma_bus *b
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
+ }
+
++ /* Cores providing flash access go before SPROM init */
++ list_for_each_entry(core, &bus->cores, list) {
++ if (bcma_is_core_needed_early(core->id.id))
++ bcma_register_core(bus, core);
++ }
++
+ /* Try to get SPROM */
+ err = bcma_sprom_get(bus);
+ if (err == -ENOENT) {
+@@ -242,6 +279,13 @@ int bcma_bus_register(struct bcma_bus *b
+ bcma_core_chipcommon_init(&bus->drv_cc);
+ }
+
++ /* Init CC core */
++ core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
++ if (core) {
++ bus->drv_cc_b.core = core;
++ bcma_core_chipcommon_b_init(&bus->drv_cc_b);
++ }
++
+ /* Init MIPS core */
+ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
+ if (core) {
+@@ -263,6 +307,13 @@ int bcma_bus_register(struct bcma_bus *b
+ bcma_core_pci_init(&bus->drv_pci[1]);
+ }
+
++ /* Init PCIe Gen 2 core */
++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
++ if (core) {
++ bus->drv_pcie2.core = core;
++ bcma_core_pcie2_init(&bus->drv_pcie2);
++ }
++
+ /* Init GBIT MAC COMMON core */
+ core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
+ if (core) {
+@@ -271,7 +322,7 @@ int bcma_bus_register(struct bcma_bus *b
+ }
+
+ /* Register found cores */
+- bcma_register_cores(bus);
++ bcma_register_devices(bus);
+
+ bcma_info(bus, "Bus registered\n");
+
+@@ -289,6 +340,8 @@ void bcma_bus_unregister(struct bcma_bus
+ else if (err)
+ bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
+
++ bcma_core_chipcommon_b_free(&bus->drv_cc_b);
++
+ cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
+ cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
+ cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
+@@ -308,8 +361,6 @@ int __init bcma_bus_early_register(struc
+ struct bcma_device *core;
+ struct bcma_device_id match;
+
+- bcma_init_bus(bus);
+-
+ match.manuf = BCMA_MANUF_BCM;
+ match.id = bcma_cc_core_id(bus);
+ match.class = BCMA_CL_SIM;
+--- a/drivers/bcma/scan.c
++++ b/drivers/bcma/scan.c
+@@ -32,6 +32,18 @@ static const struct bcma_device_id_name
+ { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
+ { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
+ { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
++ { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
++ { BCMA_CORE_NS_DMA, "DMA" },
++ { BCMA_CORE_NS_SDIO3, "SDIO3" },
++ { BCMA_CORE_NS_USB20, "USB 2.0" },
++ { BCMA_CORE_NS_USB30, "USB 3.0" },
++ { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
++ { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
++ { BCMA_CORE_NS_ROM, "ROM" },
++ { BCMA_CORE_NS_NAND, "NAND flash controller" },
++ { BCMA_CORE_NS_QSPI, "SPI flash controller" },
++ { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
++ { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
+ { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
+ { BCMA_CORE_ALTA, "ALTA (I2S)" },
+ { BCMA_CORE_INVALID, "Invalid" },
+@@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
+ return ent;
+ }
+
+-static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
++static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
+ u32 type, u8 port)
+ {
+ u32 addrl, addrh, sizel, sizeh = 0;
+@@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
+ ((ent & SCAN_ADDR_TYPE) != type) ||
+ (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
+ bcma_erom_push_ent(eromptr);
+- return -EINVAL;
++ return (u32)-EINVAL;
+ }
+
+ addrl = ent & SCAN_ADDR_ADDR;
+@@ -257,12 +269,14 @@ static struct bcma_device *bcma_find_cor
+ return NULL;
+ }
+
++#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
++
+ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
+ struct bcma_device_id *match, int core_num,
+ struct bcma_device *core)
+ {
+- s32 tmp;
+- u8 i, j;
++ u32 tmp;
++ u8 i, j, k;
+ s32 cia, cib;
+ u8 ports[2], wrappers[2];
+
+@@ -300,6 +314,7 @@ static int bcma_get_next_core(struct bcm
+ /* Some specific cores don't need wrappers */
+ switch (core->id.id) {
+ case BCMA_CORE_4706_MAC_GBIT_COMMON:
++ case BCMA_CORE_NS_CHIPCOMMON_B:
+ /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
+ break;
+ default:
+@@ -339,11 +354,11 @@ static int bcma_get_next_core(struct bcm
+ * the main register space for the core
+ */
+ tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
+- if (tmp <= 0) {
++ if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
+ /* Try again to see if it is a bridge */
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
+ SCAN_ADDR_TYPE_BRIDGE, 0);
+- if (tmp <= 0) {
++ if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
+ return -EILSEQ;
+ } else {
+ bcma_info(bus, "Bridge found\n");
+@@ -353,18 +368,19 @@ static int bcma_get_next_core(struct bcm
+ core->addr = tmp;
+
+ /* get & parse slave ports */
++ k = 0;
+ for (i = 0; i < ports[1]; i++) {
+ for (j = 0; ; j++) {
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
+ SCAN_ADDR_TYPE_SLAVE, i);
+- if (tmp < 0) {
++ if (IS_ERR_VALUE_U32(tmp)) {
+ /* no more entries for port _i_ */
+ /* pr_debug("erom: slave port %d "
+ * "has %d descriptors\n", i, j); */
+ break;
+- } else {
+- if (i == 0 && j == 0)
+- core->addr1 = tmp;
++ } else if (k < ARRAY_SIZE(core->addr_s)) {
++ core->addr_s[k] = tmp;
++ k++;
+ }
+ }
+ }
+@@ -374,7 +390,7 @@ static int bcma_get_next_core(struct bcm
+ for (j = 0; ; j++) {
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
+ SCAN_ADDR_TYPE_MWRAP, i);
+- if (tmp < 0) {
++ if (IS_ERR_VALUE_U32(tmp)) {
+ /* no more entries for port _i_ */
+ /* pr_debug("erom: master wrapper %d "
+ * "has %d descriptors\n", i, j); */
+@@ -392,7 +408,7 @@ static int bcma_get_next_core(struct bcm
+ for (j = 0; ; j++) {
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
+ SCAN_ADDR_TYPE_SWRAP, i + hack);
+- if (tmp < 0) {
++ if (IS_ERR_VALUE_U32(tmp)) {
+ /* no more entries for port _i_ */
+ /* pr_debug("erom: master wrapper %d "
+ * has %d descriptors\n", i, j); */
+@@ -407,10 +423,13 @@ static int bcma_get_next_core(struct bcm
+ core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
+ if (!core->io_addr)
+ return -ENOMEM;
+- core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
+- if (!core->io_wrap) {
+- iounmap(core->io_addr);
+- return -ENOMEM;
++ if (core->wrap) {
++ core->io_wrap = ioremap_nocache(core->wrap,
++ BCMA_CORE_SIZE);
++ if (!core->io_wrap) {
++ iounmap(core->io_addr);
++ return -ENOMEM;
++ }
+ }
+ }
+ return 0;
+@@ -420,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
+ {
+ s32 tmp;
+ struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
+-
+- if (bus->init_done)
+- return;
++ char chip_id[8];
+
+ INIT_LIST_HEAD(&bus->cores);
+ bus->nr_cores = 0;
+@@ -433,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
+ chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
+ chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
+ chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
+- bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
+- chipinfo->id, chipinfo->rev, chipinfo->pkg);
+
+- bus->init_done = true;
++ snprintf(chip_id, ARRAY_SIZE(chip_id),
++ (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
++ bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
++ chip_id, chipinfo->rev, chipinfo->pkg);
+ }
+
+ int bcma_bus_scan(struct bcma_bus *bus)
+@@ -446,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
+
+ int err, core_num = 0;
+
+- bcma_init_bus(bus);
+-
+ erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
+ eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
--- a/drivers/bcma/sprom.c
+++ b/drivers/bcma/sprom.c
@@ -72,12 +72,12 @@ fail:
return 0;
}
-@@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct
+@@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
+ SPEX(_field[7], _offset + 14, _mask, _shift); \
+ } while (0)
+
++static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
++{
++ u16 v;
++ u8 gain;
++
++ v = in[SPOFF(offset)];
++ gain = (v & mask) >> shift;
++ if (gain == 0xFF) {
++ gain = 8; /* If unset use 2dBm */
++ } else {
++ /* Q5.2 Fractional part is stored in 0xC0 */
++ gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
++ }
++
++ return (s8)gain;
++}
++
+ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
+ {
+ u16 v, o;
+@@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
ARRAY_SIZE(bus->sprom.core_pwr_info));
for (i = 0; i < 3; i++) {
v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
-@@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(
+@@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
+ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
+
+ /* Extract the antenna gain values. */
+- SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
+- SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
+- SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
+- SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
+- SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
+- SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
+- SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
+- SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
++ bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
++ SSB_SPROM8_AGAIN01,
++ SSB_SPROM8_AGAIN0,
++ SSB_SPROM8_AGAIN0_SHIFT);
++ bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
++ SSB_SPROM8_AGAIN01,
++ SSB_SPROM8_AGAIN1,
++ SSB_SPROM8_AGAIN1_SHIFT);
++ bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
++ SSB_SPROM8_AGAIN23,
++ SSB_SPROM8_AGAIN2,
++ SSB_SPROM8_AGAIN2_SHIFT);
++ bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
++ SSB_SPROM8_AGAIN23,
++ SSB_SPROM8_AGAIN3,
++ SSB_SPROM8_AGAIN3_SHIFT);
+
+ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
+ SSB_SPROM8_LEDDC_ON_SHIFT);
+@@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available(
case BCMA_CHIP_ID_BCM4331:
present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
break;
case BCMA_CHIP_ID_BCM43224:
case BCMA_CHIP_ID_BCM43225:
/* for these chips OTP is always available */
-@@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ present = true;
+ break;
++ case BCMA_CHIP_ID_BCM43131:
++ case BCMA_CHIP_ID_BCM43217:
+ case BCMA_CHIP_ID_BCM43227:
+ case BCMA_CHIP_ID_BCM43228:
+ case BCMA_CHIP_ID_BCM43428:
+@@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
{
u16 offset = BCMA_CC_SPROM;
u16 *sprom;
if (!bus->drv_cc.core)
return -EOPNOTSUPP;
-@@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
+@@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
}
}
}
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
-@@ -144,6 +144,7 @@ struct bcma_host_ops {
+@@ -6,6 +6,7 @@
+
+ #include <linux/bcma/bcma_driver_chipcommon.h>
+ #include <linux/bcma/bcma_driver_pci.h>
++#include <linux/bcma/bcma_driver_pcie2.h>
+ #include <linux/bcma/bcma_driver_mips.h>
+ #include <linux/bcma/bcma_driver_gmac_cmn.h>
+ #include <linux/ssb/ssb.h> /* SPROM sharing */
+@@ -72,7 +73,19 @@ struct bcma_host_ops {
+ /* Core-ID values. */
+ #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
+ #define BCMA_CORE_4706_CHIPCOMMON 0x500
++#define BCMA_CORE_NS_PCIEG2 0x501
++#define BCMA_CORE_NS_DMA 0x502
++#define BCMA_CORE_NS_SDIO3 0x503
++#define BCMA_CORE_NS_USB20 0x504
++#define BCMA_CORE_NS_USB30 0x505
++#define BCMA_CORE_NS_A9JTAG 0x506
++#define BCMA_CORE_NS_DDR23 0x507
++#define BCMA_CORE_NS_ROM 0x508
++#define BCMA_CORE_NS_NAND 0x509
++#define BCMA_CORE_NS_QSPI 0x50A
++#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
+ #define BCMA_CORE_4706_SOC_RAM 0x50E
++#define BCMA_CORE_ARMCA9 0x510
+ #define BCMA_CORE_4706_MAC_GBIT 0x52D
+ #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
+ #define BCMA_CORE_ALTA 0x534 /* I2S core */
+@@ -144,6 +157,10 @@ struct bcma_host_ops {
/* Chip IDs of PCIe devices */
#define BCMA_CHIP_ID_BCM4313 0x4313
+#define BCMA_CHIP_ID_BCM43142 43142
++#define BCMA_CHIP_ID_BCM43131 43131
++#define BCMA_CHIP_ID_BCM43217 43217
++#define BCMA_CHIP_ID_BCM43222 43222
#define BCMA_CHIP_ID_BCM43224 43224
#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
+@@ -176,6 +193,11 @@ struct bcma_host_ops {
+ #define BCMA_PKG_ID_BCM5357 11
+ #define BCMA_CHIP_ID_BCM53572 53572
+ #define BCMA_PKG_ID_BCM47188 9
++#define BCMA_CHIP_ID_BCM4707 53010
++#define BCMA_PKG_ID_BCM4707 1
++#define BCMA_PKG_ID_BCM4708 2
++#define BCMA_PKG_ID_BCM4709 0
++#define BCMA_CHIP_ID_BCM53018 53018
+
+ /* Board types (on PCI usually equals to the subsystem dev id) */
+ /* BCM4313 */
+@@ -245,7 +267,7 @@ struct bcma_device {
+ u8 core_unit;
+
+ u32 addr;
+- u32 addr1;
++ u32 addr_s[8];
+ u32 wrap;
+
+ void __iomem *io_addr;
+@@ -310,11 +332,12 @@ struct bcma_bus {
+ struct bcma_device *mapped_core;
+ struct list_head cores;
+ u8 nr_cores;
+- u8 init_done:1;
+ u8 num;
+
+ struct bcma_drv_cc drv_cc;
++ struct bcma_drv_cc_b drv_cc_b;
+ struct bcma_drv_pci drv_pci[2];
++ struct bcma_drv_pcie2 drv_pcie2;
+ struct bcma_drv_mips drv_mips;
+ struct bcma_drv_gmac_cmn drv_gmac_cmn;
+
+@@ -400,7 +423,14 @@ static inline void bcma_maskset16(struct
+ bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
+ }
+
+-extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
++extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit);
++static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
++ u16 coreid)
++{
++ return bcma_find_core_unit(bus, coreid, 0);
++}
++
+ extern bool bcma_core_is_enabled(struct bcma_device *core);
+ extern void bcma_core_disable(struct bcma_device *core, u32 flags);
+ extern int bcma_core_enable(struct bcma_device *core, u32 flags);
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -330,6 +330,8 @@
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
+@@ -585,9 +640,16 @@ struct bcma_drv_cc {
+ spinlock_t gpio_lock;
+ #ifdef CONFIG_BCMA_DRIVER_GPIO
+ struct gpio_chip gpio;
++ struct irq_domain *irq_domain;
+ #endif
+ };
+
++struct bcma_drv_cc_b {
++ struct bcma_device *core;
++ u8 setup_done:1;
++ void __iomem *mii;
++};
++
+ /* Register access */
+ #define bcma_cc_read32(cc, offset) \
+ bcma_read32((cc)->core, offset)
+@@ -643,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
+
+ extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
+
++void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
++
+ #endif /* LINUX_BCMA_DRIVER_CC_H_ */
+--- a/include/linux/bcma/bcma_driver_pci.h
++++ b/include/linux/bcma/bcma_driver_pci.h
+@@ -181,10 +181,31 @@ struct pci_dev;
+
+ #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
+
++#define BCMA_CORE_PCI_
++
++/* MDIO devices (SERDES modules) */
++#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
++#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
++#define BCMA_CORE_PCI_MDIO_BLK0 0x800
++#define BCMA_CORE_PCI_MDIO_BLK1 0x801
++#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
++#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
++#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
++#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
++#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
++#define BCMA_CORE_PCI_MDIO_BLK2 0x802
++#define BCMA_CORE_PCI_MDIO_BLK3 0x803
++#define BCMA_CORE_PCI_MDIO_BLK4 0x804
++#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
++#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
++#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
++#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
++
+ /* PCIE Root Capability Register bits (Host mode only) */
+ #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
+
+ struct bcma_drv_pci;
++struct bcma_bus;
+
+ #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
+ struct bcma_drv_pci_host {
+@@ -219,7 +240,9 @@ struct bcma_drv_pci {
+ extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
+ extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
+ struct bcma_device *core, bool enable);
+-extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
++extern void bcma_core_pci_up(struct bcma_bus *bus);
++extern void bcma_core_pci_down(struct bcma_bus *bus);
++extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
+
+ extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
+ extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
+--- /dev/null
++++ b/include/linux/bcma/bcma_driver_pcie2.h
+@@ -0,0 +1,158 @@
++#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
++#define LINUX_BCMA_DRIVER_PCIE2_H_
++
++#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
++#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
++#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
++#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
++#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
++#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
++#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
++#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
++#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
++#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
++#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
++#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
++#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
++#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
++#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
++#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
++#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
++#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
++#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
++#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
++#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
++#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
++#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
++#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
++#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
++#define BCMA_CORE_PCIE2_DATAINTF 0x0180
++#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
++#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
++#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
++#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
++#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
++#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
++#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
++#define PCIE2_LTR_ACTIVE 2
++#define PCIE2_LTR_ACTIVE_IDLE 1
++#define PCIE2_LTR_SLEEP 0
++#define PCIE2_LTR_FINAL_MASK 0x300
++#define PCIE2_LTR_FINAL_SHIFT 8
++#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
++#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
++#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
++#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
++#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
++#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
++#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
++#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
++#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
++#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
++#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
++#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
++#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
++#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
++#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
++#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
++#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
++#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
++#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
++#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
++#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
++#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
++#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
++#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
++#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
++#define BCMA_CORE_PCIE2_OARR0 0x0D20
++#define BCMA_CORE_PCIE2_OARR1 0x0D28
++#define BCMA_CORE_PCIE2_OARR2 0x0D30
++#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
++#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
++#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
++#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
++#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
++#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
++#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
++#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
++#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
++#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
++#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
++#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
++#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
++#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
++#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
++#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
++#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
++#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
++#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
++#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
++#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
++#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
++
++/* PCIE gen2 config regs */
++#define PCIE2_INTSTATUS 0x090
++#define PCIE2_INTMASK 0x094
++#define PCIE2_SBMBX 0x098
++
++#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
++
++#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
++#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
++#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
++
++struct bcma_drv_pcie2 {
++ struct bcma_device *core;
++};
++
++#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
++#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
++#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
++#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
++
++#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
++#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
++
++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
++
++#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+@@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
+ return mode == BCMA_CLKMODE_FAST;
+ }
+
+-void ai_pci_up(struct si_pub *sih)
+-{
+- struct si_info *sii;
+-
+- sii = container_of(sih, struct si_info, pub);
+-
+- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
+-}
+-
+-/* Unconfigure and/or apply various WARs when going down */
+-void ai_pci_down(struct si_pub *sih)
+-{
+- struct si_info *sii;
+-
+- sii = container_of(sih, struct si_info, pub);
+-
+- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
+-}
+-
+ /* Enable BT-COEX & Ex-PA for 4313 */
+ void ai_epa_4313war(struct si_pub *sih)
+ {
+--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
++++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+@@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
+ extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
+ extern bool ai_deviceremoved(struct si_pub *sih);
+
+-extern void ai_pci_down(struct si_pub *sih);
+-extern void ai_pci_up(struct si_pub *sih);
+-
+ /* Enable Ex-PA for 4313 */
+ extern void ai_epa_4313war(struct si_pub *sih);
+
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
+ brcms_c_coredisable(wlc_hw);
+
+ /* Match driver "down" state */
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+
+ /* turn off pll and xtal to match driver "down" state */
+ brcms_b_xtal(wlc_hw, OFF);
+@@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
+ */
+ if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
+ /* put SB PCI in down state again */
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+ brcms_b_xtal(wlc_hw, OFF);
+ return -ENOMEDIUM;
+ }
+
+- ai_pci_up(wlc_hw->sih);
++ bcma_core_pci_up(wlc_hw->d11core->bus);
+
+ /* reset the d11 core */
+ brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
+@@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
+
+ /* turn off primary xtal and pll */
+ if (!wlc_hw->noreset) {
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+ brcms_b_xtal(wlc_hw, OFF);
+ }
+ }
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -21,6 +21,14 @@
+ #include <linux/serial_reg.h>
+ #include <linux/time.h>
+
++enum bcma_boot_dev {
++ BCMA_BOOT_DEV_UNK = 0,
++ BCMA_BOOT_DEV_ROM,
++ BCMA_BOOT_DEV_PARALLEL,
++ BCMA_BOOT_DEV_SERIAL,
++ BCMA_BOOT_DEV_NAND,
++};
++
+ static const char * const part_probes[] = { "bcm47xxpart", NULL };
+
+ static struct physmap_flash_data bcma_pflash_data = {
+@@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+ }
+ EXPORT_SYMBOL(bcma_cpu_clock);
+
++static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
++{
++ struct bcma_drv_cc *cc = &bus->drv_cc;
++ u8 cc_rev = cc->core->id.rev;
++
++ if (cc_rev == 42) {
++ struct bcma_device *core;
++
++ core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
++ if (core) {
++ switch (bcma_aread32(core, BCMA_IOST) &
++ BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
++ case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
++ return BCMA_BOOT_DEV_SERIAL;
++ case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
++ return BCMA_BOOT_DEV_NAND;
++ case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
++ default:
++ return BCMA_BOOT_DEV_ROM;
++ }
++ }
++ } else {
++ if (cc_rev == 38) {
++ if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
++ return BCMA_BOOT_DEV_NAND;
++ else if (cc->status & BIT(5))
++ return BCMA_BOOT_DEV_ROM;
++ }
++
++ if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
++ BCMA_CC_FLASHT_PARA)
++ return BCMA_BOOT_DEV_PARALLEL;
++ else
++ return BCMA_BOOT_DEV_SERIAL;
++ }
++
++ return BCMA_BOOT_DEV_SERIAL;
++}
++
+ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
+ {
+ struct bcma_bus *bus = mcore->core->bus;
+ struct bcma_drv_cc *cc = &bus->drv_cc;
+ struct bcma_pflash *pflash = &cc->pflash;
++ enum bcma_boot_dev boot_dev;
+
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+ case BCMA_CC_FLASHT_STSER:
+@@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
+ bcma_nflash_init(cc);
+ }
+ }
++
++ /* Determine flash type this SoC boots from */
++ boot_dev = bcma_boot_dev(bus);
++ switch (boot_dev) {
++ case BCMA_BOOT_DEV_PARALLEL:
++ case BCMA_BOOT_DEV_SERIAL:
++ /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
++ break;
++ case BCMA_BOOT_DEV_NAND:
++ /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
++ break;
++ default:
++ break;
++ }
+ }
+
+ void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
+--- a/drivers/bcma/host_soc.c
++++ b/drivers/bcma/host_soc.c
+@@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
+
+ static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
+ {
++ if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
++ return ~0;
+ return readl(core->io_wrap + offset);
+ }
+
+ static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
+ u32 value)
+ {
++ if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
++ return;
+ writel(value, core->io_wrap + offset);
+ }
+
+@@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
+ int __init bcma_host_soc_register(struct bcma_soc *soc)
+ {
+ struct bcma_bus *bus = &soc->bus;
+- int err;
+
+ /* iomap only first core. We have to read some register on this core
+ * to scan the bus.
+@@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
+ bus->hosttype = BCMA_HOSTTYPE_SOC;
+ bus->ops = &bcma_host_soc_ops;
+
+- /* Register */
++ /* Initialize struct, detect chip */
++ bcma_init_bus(bus);
++
++ return 0;
++}
++
++int __init bcma_host_soc_init(struct bcma_soc *soc)
++{
++ struct bcma_bus *bus = &soc->bus;
++ int err;
++
++ /* Scan bus and initialize it */
+ err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
+ if (err)
+ iounmap(bus->mmio);
+--- a/include/linux/bcma/bcma_regs.h
++++ b/include/linux/bcma/bcma_regs.h
+@@ -39,6 +39,11 @@
+ #define BCMA_RESET_CTL_RESET 0x0001
+ #define BCMA_RESET_ST 0x0804
+
++#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
++#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
++#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
++#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
++
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
+ #define BCMA_PCI_PE 0x100
+--- a/drivers/usb/host/bcma-hcd.c
++++ b/drivers/usb/host/bcma-hcd.c
+@@ -238,7 +238,7 @@ static int bcma_hcd_probe(struct bcma_de
+ bcma_hcd_init_chip(dev);
+
+ /* In AI chips EHCI is addrspace 0, OHCI is 1 */
+- ohci_addr = dev->addr1;
++ ohci_addr = dev->addr_s[0];
+ if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
+ && chipinfo->rev == 0)
+ ohci_addr = 0x18009000;
+--- /dev/null
++++ b/drivers/bcma/driver_chipcommon_b.c
+@@ -0,0 +1,61 @@
++/*
++ * Broadcom specific AMBA
++ * ChipCommon B Unit driver
++ *
++ * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/export.h>
++#include <linux/bcma/bcma.h>
++
++static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
++ u32 value, int timeout)
++{
++ unsigned long deadline = jiffies + timeout;
++ u32 val;
++
++ do {
++ val = readl(addr);
++ if ((val & mask) == value)
++ return true;
++ cpu_relax();
++ udelay(10);
++ } while (!time_after_eq(jiffies, deadline));
++
++ bcma_err(bus, "Timeout waiting for register %p\n", addr);
++
++ return false;
++}
++
++void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
++{
++ struct bcma_bus *bus = ccb->core->bus;
++
++ writel(offset, ccb->mii + 0x00);
++ bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
++ writel(value, ccb->mii + 0x04);
++ bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
++}
++EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
++
++int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
++{
++ if (ccb->setup_done)
++ return 0;
++
++ ccb->setup_done = 1;
++ ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
++ if (!ccb->mii)
++ return -ENOMEM;
++
++ return 0;
++}
++
++void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
++{
++ if (ccb->mii)
++ iounmap(ccb->mii);
++}
+--- a/include/linux/bcma/bcma_soc.h
++++ b/include/linux/bcma/bcma_soc.h
+@@ -10,6 +10,7 @@ struct bcma_soc {
+ };
+
+ int __init bcma_host_soc_register(struct bcma_soc *soc);
++int __init bcma_host_soc_init(struct bcma_soc *soc);
+
+ int bcma_bus_register(struct bcma_bus *bus);
+
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -194,6 +194,10 @@ static void __init bcm47xx_register_bcma
+
+ err = bcma_host_soc_register(&bcm47xx_bus.bcma);
+ if (err)
++ panic("Failed to register BCMA bus (err %d)", err);
++
++ err = bcma_host_soc_init(&bcm47xx_bus.bcma);
++ if (err)
+ panic("Failed to initialize BCMA bus (err %d)", err);
+
+ bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
projects / openwrt / svn-archive / archive.git / blobdiff