compatible = "mti,cpu-interrupt-controller";
};
+ aliases {
+ spi0 = &spi0;
+ spi1 = &spi1;
+ serial0 = &uartlite;
+ };
+
palmbus@10000000 {
compatible = "palmbus";
reg = <0x10000000 0x200000>;
- ranges = <0x0 0x10000000 0x1FFFFF>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
+ gpio3: gpio@688 {
+ compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+ reg = <0x688 0x24>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <6>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,gpio-base = <72>;
+ ralink,num-gpios = <1>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+
+ status = "disabled";
+ };
+
i2c@900 {
compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c";
reg = <0x900 0x100>;
interrupt-parent = <&intc>;
interrupts = <10>;
+ dmas = <&gdma 4>,
+ <&gdma 5>;
+ dma-names = "tx", "rx";
+
status = "disabled";
};
- spi@b00 {
+ spi0: spi@b00 {
compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
- reg = <0xb00 0x100>;
+ reg = <0xb00 0x40>;
resets = <&rstctrl 18>;
reset-names = "spi";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
pinctrl-0 = <&spi_pins>;
};
- uartlite@c00 {
+ spi1: spi@b40 {
+ compatible = "ralink,rt2880-spi";
+ reg = <0xb40 0x60>;
+
+ resets = <&rstctrl 18>;
+ reset-names = "spi";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_cs1>;
+ };
+
+ uartlite: uartlite@c00 {
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
status = "disabled";
};
- gdma@2800 {
+ gdma: gdma@2800 {
compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
reg = <0x2800 0x800>;
interrupt-parent = <&intc>;
interrupts = <7>;
+ #dma-cells = <1>;
+ #dma-channels = <16>;
+ #dma-requests = <16>;
+
status = "disabled";
};
};
compatible = "ralink,rt2880-pinmux";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
+
state_default: pinctrl0 {
};
+
+ pcm_i2s_pins: pcm_i2s {
+ pcm_i2s {
+ ralink,group = "uartf";
+ ralink,function = "pcm i2s";
+ };
+ };
+
+ uartf_gpio_pins: uartf_gpio {
+ uartf_gpio {
+ ralink,group = "uartf";
+ ralink,function = "gpio uartf";
+ };
+ };
+
spi_pins: spi {
spi {
ralink,group = "spi";
ralink,function = "spi";
};
};
+
+ spi_cs1: spi1 {
+ spi1 {
+ ralink,group = "spi_cs1";
+ ralink,function = "spi_cs1";
+ };
+ };
+
i2c_pins: i2c {
i2c {
- lantiq,group = "i2c";
- lantiq,function = "i2c";
+ ralink,group = "i2c";
+ ralink,function = "i2c";
};
};
+
uartlite_pins: uartlite {
uart {
ralink,group = "uartlite";
ralink,function = "uartlite";
};
};
+
mdio_pins: mdio {
mdio {
ralink,group = "mdio";
ralink,function = "mdio";
};
};
+
ephy_pins: ephy {
ephy {
ralink,group = "ephy";
ralink,function = "ephy";
};
};
+
wled_pins: wled {
wled {
ralink,group = "wled";
ralink,function = "wled";
};
};
+
rgmii1_pins: rgmii1 {
- mdio {
+ rgmii1 {
ralink,group = "rgmii1";
ralink,function = "rgmii1";
};
};
+
rgmii2_pins: rgmii2 {
- mdio {
+ rgmii2 {
ralink,group = "rgmii2";
ralink,function = "rgmii2";
};
};
+
+ pcie_pins: pcie {
+ pcie {
+ ralink,group = "pcie";
+ ralink,function = "pcie rst";
+ };
+ };
};
rstctrl: rstctrl {
#reset-cells = <1>;
};
- ubsphy {
- compatible = "ralink,mt7620a-usbphy";
+ usbphy: usbphy {
+ compatible = "mediatek,mt7620-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
reset-names = "host", "device";
};
ethernet@10100000 {
- compatible = "ralink,mt7620a-eth";
- reg = <0x10100000 10000>;
+ compatible = "mediatek,mt7620-eth";
+ reg = <0x10100000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&cpuintc>;
interrupts = <5>;
+ resets = <&rstctrl 21 &rstctrl 23>;
+ reset-names = "fe", "esw";
+
+ mediatek,switch = <&gsw>;
+
+ port@4 {
+ compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
+ reg = <4>;
+
+ status = "disabled";
+ };
+
+ port@5 {
+ compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
+ reg = <5>;
+
+ status = "disabled";
+ };
+
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
};
};
- gsw@10110000 {
- compatible = "ralink,mt7620a-gsw";
- reg = <0x10110000 8000>;
+ gsw: gsw@10110000 {
+ compatible = "mediatek,mt7620-gsw";
+ reg = <0x10110000 0x8000>;
+
+ resets = <&rstctrl 23>;
+ reset-names = "esw";
interrupt-parent = <&intc>;
interrupts = <17>;
};
sdhci@10130000 {
- compatible = "ralink,mt7620a-sdhci";
- reg = <0x10130000 4000>;
+ compatible = "ralink,mt7620-sdhci";
+ reg = <0x10130000 0x4000>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
ehci@101c0000 {
- compatible = "ralink,rt3xxx-ehci";
+ compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <18>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
status = "disabled";
};
ohci@101c1000 {
- compatible = "ralink,rt3xxx-ohci";
+ compatible = "generic-ohci";
reg = <0x101c1000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <18>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
status = "disabled";
};
pcie@10140000 {
- compatible = "ralink,mt7620a-pci";
+ compatible = "mediatek,mt7620-pci";
reg = <0x10140000 0x100
0x10142000 0x100>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
resets = <&rstctrl 26>;
reset-names = "pcie0";
interrupt-parent = <&cpuintc>;
interrupts = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+
+ device_type = "pci";
+
+ bus-range = <0 255>;
+ ranges = <
+ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
+ 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
+ >;
+
status = "disabled";
+
+ pcie-bridge {
+ reg = <0x0000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ };
+ };
+
+ wmac@10180000 {
+ compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
+ reg = <0x10180000 0x40000>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ ralink,eeprom = "soc_wmac.eeprom";
};
};
projects / openwrt / svn-archive / archive.git / blobdiff