ramips: register mt7621 pcie through device tree

[openwrt/svn-archive/archive.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 8bea94624137e620296b47a496c821d7e3339d8b..a36c2b771130dfc0923dcb079d74c645c3502208 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -104,7 +104,7 @@
                                #size-cells = <1>;
                                reg = <0 0>;
                                spi-max-frequency = <10000000>;
-                               m25p,chunked-io;
+                               m25p,chunked-io = <32>;
                        };
                };
        };
@@ -201,6 +201,8 @@
        };
 
        xhci@1E1C0000 {
+               status = "disabled";
+
                compatible = "xhci-platform";
                reg = <0x1E1C0000 4000>;
 
@@ -272,4 +274,53 @@
                interrupt-parent = <&gic>;
                interrupts = <23>; 
        };
+
+       pcie@1e140000 {
+               compatible = "mediatek,mt7621-pci";
+               reg = <0x1e140000 0x100
+                       0x1e142000 0x100>;
+
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie_pins>;
+
+               device_type = "pci";
+
+               bus-range = <0 255>;
+               ranges = <
+                       0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
+                       0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
+               >;
+
+               status = "okay";
+
+               pcie0 {
+                       reg = <0x0000 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+
+               pcie1 {
+                       reg = <0x0800 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+
+               pcie2 {
+                       reg = <0x1000 0 0 0 0>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+               };
+       };
 };