ramips: add watchdog device for RT288x

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt288x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
index dfd5b31599932de62ac4ad0ca76354e5dd001a19..a95cb82963569ad9d4af80329a37d6c36a7e822c 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
@@ -1,7 +1,7 @@
 /*
  *  Ralink RT288x SoC register definitions
  *
- *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
@@ -16,21 +16,24 @@
 
 #define RT2880_SYSC_BASE       0x00300000
 #define RT2880_TIMER_BASE      0x00300100
+#define RT2880_INTC_BASE       0x00300200
 #define RT2880_MEMC_BASE       0x00300300
 #define RT2880_UART0_BASE      0x00300500
 #define RT2880_PIO_BASE                0x00300600
 #define RT2880_I2C_BASE                0x00300900
 #define RT2880_SPI_BASE                0x00300b00
 #define RT2880_UART1_BASE      0x00300c00
-#define RT2880_FE_BASE         0x00310000
-#define RT2880_ROM_BASE                0x00400000
-#define RT2880_PCI_BASE                0x00500000
-#define RT2880_WMAC_BASE       0x00600000
+#define RT2880_FE_BASE         0x00400000
+#define RT2880_ROM_BASE                0x00410000
+#define RT2880_PCM_BASE                0x00420000
+#define RT2880_PCI_BASE                0x00440000
+#define RT2880_WMAC_BASE       0x00480000
 #define RT2880_FLASH1_BASE     0x01000000
 #define RT2880_FLASH0_BASE     0x1fc00000
 #define RT2880_SDRAM_BASE      0x08000000
 
 #define RT2880_SYSC_SIZE       0x100
+#define RT2880_TIMER_SIZE      0x100
 #define RT2880_INTC_SIZE       0x100
 #define RT2880_MEMC_SIZE       0x100
 #define RT2880_UART0_SIZE      0x100
@@ -43,8 +46,10 @@
 #define SYSC_REG_CHIP_NAME1    0x004   /* Chip Name 1 */
 #define SYSC_REG_CHIP_ID       0x00c   /* Chip Identification */
 #define SYSC_REG_SYSTEM_CONFIG 0x010   /* System Configuration */
+#define SYSC_REG_CLKCFG                0x030
 #define SYSC_REG_RESET_CTRL    0x034   /* Reset Control*/
 #define SYSC_REG_RESET_STATUS  0x038   /* Reset Status*/
+#define SYSC_REG_GPIO_MODE     0x060   /* GPIO Purpose Select */
 #define SYSC_REG_IA_ADDRESS    0x310   /* Illegal Access Address */
 #define SYSC_REG_IA_TYPE       0x314   /* Illegal Access Type */
 
@@ -59,6 +64,8 @@
 #define SYSTEM_CONFIG_CPUCLK_280       0x2
 #define SYSTEM_CONFIG_CPUCLK_300       0x3
 
+#define CLKCFG_SRAM_CS_N_WDT   BIT(9)
+
 #define RT2880_RESET_SYSTEM    BIT(0)
 #define RT2880_RESET_TIMER     BIT(1)
 #define RT2880_RESET_INTC      BIT(2)
@@ -74,6 +81,15 @@
 #define RT2880_RESET_FE                BIT(18)
 #define RT2880_RESET_PCM       BIT(19)
 
+#define RT2880_GPIO_MODE_I2C   BIT(0)
+#define RT2880_GPIO_MODE_UART0 BIT(1)
+#define RT2880_GPIO_MODE_SPI   BIT(2)
+#define RT2880_GPIO_MODE_UART1 BIT(3)
+#define RT2880_GPIO_MODE_JTAG  BIT(4)
+#define RT2880_GPIO_MODE_MDIO  BIT(5)
+#define RT2880_GPIO_MODE_SDRAM BIT(6)
+#define RT2880_GPIO_MODE_PCI   BIT(7)
+
 #define RT2880_INTC_INT_TIMER0 BIT(0)
 #define RT2880_INTC_INT_TIMER1 BIT(1)
 #define RT2880_INTC_INT_UART0  BIT(2)