ramips: rt305x: rename SYSTEM_CONFIG_* defines to RT305X_SYSCFG_*

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index a17962d5aaaab0e5538f391f291f995bdb157640..1ba55355571e12006c33448f71c050d9379c59ff 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -20,6 +20,7 @@
 #define RT305X_MEMC_BASE       0x10000300
 #define RT305X_PCM_BASE                0x10000400
 #define RT305X_UART0_BASE      0x10000500
+#define RT305X_PIO_BASE                0x10000600
 #define RT305X_GDMA_BASE       0x10000700
 #define RT305X_NANDC_BASE      0x10000800
 #define RT305X_I2C_BASE                0x10000900
@@ -28,7 +29,7 @@
 #define RT305X_UART1_BASE      0x10000c00
 #define RT305X_FE_BASE         0x10100000
 #define RT305X_SWITCH_BASE     0x10110000
-#define RT305X_WMAC_BASE       0x00180000
+#define RT305X_WMAC_BASE       0x10180000
 #define RT305X_OTG_BASE                0x101c0000
 #define RT305X_ROM_BASE                0x00400000
 #define RT305X_FLASH1_BASE     0x1b000000
@@ -39,9 +40,11 @@
 #define RT305X_INTC_SIZE       0x100
 #define RT305X_MEMC_SIZE       0x100
 #define RT305X_UART0_SIZE      0x100
+#define RT305X_PIO_SIZE                0x100
 #define RT305X_UART1_SIZE      0x100
+#define RT305X_SPI_SIZE                0x100
 #define RT305X_FLASH1_SIZE     (16 * 1024 * 1024)
-#define RT305X_FLASH0_SIZE     (4 * 1024 * 1024)
+#define RT305X_FLASH0_SIZE     (8 * 1024 * 1024)
 
 /* SYSC registers */
 #define SYSC_REG_CHIP_NAME0    0x000   /* Chip Name 0 */
@@ -58,10 +61,15 @@
 #define CHIP_ID_ID_SHIFT       8
 #define CHIP_ID_REV_MASK       0xff
 
-#define SYSTEM_CONFIG_CPUCLK_SHIFT     18
-#define SYSTEM_CONFIG_CPUCLK_MASK      0x1
-#define SYSTEM_CONFIG_CPUCLK_320       0x0
-#define SYSTEM_CONFIG_CPUCLK_384       0x1
+#define RT305X_SYSCFG_CPUCLK_SHIFT     18
+#define RT305X_SYSCFG_CPUCLK_MASK      0x1
+#define RT305X_SYSCFG_CPUCLK_LOW       0x0
+#define RT305X_SYSCFG_CPUCLK_HIGH      0x1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT      2
+#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK       0x3
+#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL     0
+#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT                1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX     2
 
 #define RT305X_GPIO_MODE_I2C           BIT(0)
 #define RT305X_GPIO_MODE_SPI           BIT(1)