ramips: add watchdog device for RT305x

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index 139dc92e5446d5930c74d734a9b5e6ee1401596a..c4964b0b450d723551ce502b45d3361909643f91 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -14,34 +14,34 @@
 #include <linux/bitops.h>
 
 #define RT305X_SDRAM_BASE      0x00000000
-#define RT305X_SYSC_BASE       0x10000000
+#define RT305X_SYSC_BASE       0x10000000
 #define RT305X_TIMER_BASE      0x10000100
 #define RT305X_INTC_BASE       0x10000200
 #define RT305X_MEMC_BASE       0x10000300
 #define RT305X_PCM_BASE                0x10000400
 #define RT305X_UART0_BASE      0x10000500
-#define RT305X_PIO_BASE                0x10000600
 #define RT305X_GDMA_BASE       0x10000700
 #define RT305X_NANDC_BASE      0x10000800
 #define RT305X_I2C_BASE                0x10000900
 #define RT305X_I2S_BASE                0x10000a00
 #define RT305X_SPI_BASE                0x10000b00
 #define RT305X_UART1_BASE      0x10000c00
-#define RT305X_FE_BASE         0x10010000
+#define RT305X_FE_BASE         0x10100000
 #define RT305X_SWITCH_BASE     0x10110000
-#define RT305X_WMAC_BASE       0x00180000
+#define RT305X_WMAC_BASE       0x10180000
 #define RT305X_OTG_BASE                0x101c0000
 #define RT305X_ROM_BASE                0x00400000
 #define RT305X_FLASH1_BASE     0x1b000000
 #define RT305X_FLASH0_BASE     0x1f000000
 
 #define RT305X_SYSC_SIZE       0x100
+#define RT305X_TIMER_SIZE      0x100
 #define RT305X_INTC_SIZE       0x100
 #define RT305X_MEMC_SIZE       0x100
 #define RT305X_UART0_SIZE      0x100
 #define RT305X_UART1_SIZE      0x100
 #define RT305X_FLASH1_SIZE     (16 * 1024 * 1024)
-#define RT305X_FLASH0_SIZE     (4 * 1024 * 1024)
+#define RT305X_FLASH0_SIZE     (8 * 1024 * 1024)
 
 /* SYSC registers */
 #define SYSC_REG_CHIP_NAME0    0x000   /* Chip Name 0 */
@@ -50,6 +50,7 @@
 #define SYSC_REG_SYSTEM_CONFIG 0x010   /* System Configuration */
 #define SYSC_REG_RESET_CTRL    0x034   /* Reset Control*/
 #define SYSC_REG_RESET_STATUS  0x038   /* Reset Status*/
+#define SYSC_REG_GPIO_MODE     0x060   /* GPIO Purpose Select */
 #define SYSC_REG_IA_ADDRESS    0x310   /* Illegal Access Address */
 #define SYSC_REG_IA_TYPE       0x314   /* Illegal Access Type */
 
@@ -61,6 +62,30 @@
 #define SYSTEM_CONFIG_CPUCLK_MASK      0x1
 #define SYSTEM_CONFIG_CPUCLK_320       0x0
 #define SYSTEM_CONFIG_CPUCLK_384       0x1
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT      2
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK       0x3
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL     0
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT                1
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX     2
+
+#define RT305X_GPIO_MODE_I2C           BIT(0)
+#define RT305X_GPIO_MODE_SPI           BIT(1)
+#define RT305X_GPIO_MODE_UART0_SHIFT   2
+#define RT305X_GPIO_MODE_UART0_MASK    0x7
+#define RT305X_GPIO_MODE_UART0(x)      ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF         0x0
+#define RT305X_GPIO_MODE_PCM_UARTF     0x1
+#define RT305X_GPIO_MODE_PCM_I2S       0x2
+#define RT305X_GPIO_MODE_I2S_UARTF     0x3
+#define RT305X_GPIO_MODE_PCM_GPIO      0x4
+#define RT305X_GPIO_MODE_GPIO_UARTF    0x5
+#define RT305X_GPIO_MODE_GPIO_I2S      0x6
+#define RT305X_GPIO_MODE_GPIO          0x7
+#define RT305X_GPIO_MODE_UART1         BIT(5)
+#define RT305X_GPIO_MODE_JTAG          BIT(6)
+#define RT305X_GPIO_MODE_MDIO          BIT(7)
+#define RT305X_GPIO_MODE_SDRAM         BIT(8)
+#define RT305X_GPIO_MODE_RGMII         BIT(9)
 
 #define RT305X_RESET_SYSTEM    BIT(0)
 #define RT305X_RESET_TIMER     BIT(8)