ramips: add watchdog device for RT305x

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index 7f0666d5b1ee823a252fc8c4844429f8a2d88022..c4964b0b450d723551ce502b45d3361909643f91 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -14,7 +14,7 @@
 #include <linux/bitops.h>
 
 #define RT305X_SDRAM_BASE      0x00000000
-#define RT305X_SYSC_BASE       0x10000000
+#define RT305X_SYSC_BASE       0x10000000
 #define RT305X_TIMER_BASE      0x10000100
 #define RT305X_INTC_BASE       0x10000200
 #define RT305X_MEMC_BASE       0x10000300
@@ -26,21 +26,22 @@
 #define RT305X_I2S_BASE                0x10000a00
 #define RT305X_SPI_BASE                0x10000b00
 #define RT305X_UART1_BASE      0x10000c00
-#define RT305X_FE_BASE         0x10010000
+#define RT305X_FE_BASE         0x10100000
 #define RT305X_SWITCH_BASE     0x10110000
-#define RT305X_WMAC_BASE       0x00180000
+#define RT305X_WMAC_BASE       0x10180000
 #define RT305X_OTG_BASE                0x101c0000
 #define RT305X_ROM_BASE                0x00400000
 #define RT305X_FLASH1_BASE     0x1b000000
 #define RT305X_FLASH0_BASE     0x1f000000
 
 #define RT305X_SYSC_SIZE       0x100
+#define RT305X_TIMER_SIZE      0x100
 #define RT305X_INTC_SIZE       0x100
 #define RT305X_MEMC_SIZE       0x100
 #define RT305X_UART0_SIZE      0x100
 #define RT305X_UART1_SIZE      0x100
 #define RT305X_FLASH1_SIZE     (16 * 1024 * 1024)
-#define RT305X_FLASH0_SIZE     (4 * 1024 * 1024)
+#define RT305X_FLASH0_SIZE     (8 * 1024 * 1024)
 
 /* SYSC registers */
 #define SYSC_REG_CHIP_NAME0    0x000   /* Chip Name 0 */
@@ -61,6 +62,11 @@
 #define SYSTEM_CONFIG_CPUCLK_MASK      0x1
 #define SYSTEM_CONFIG_CPUCLK_320       0x0
 #define SYSTEM_CONFIG_CPUCLK_384       0x1
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT      2
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK       0x3
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL     0
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT                1
+#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX     2
 
 #define RT305X_GPIO_MODE_I2C           BIT(0)
 #define RT305X_GPIO_MODE_SPI           BIT(1)