#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
-#ifdef CONFIG_SOC_MT7620
-static inline int soc_is_rt3352(void)
-{
- return 0;
-}
-
-static inline int soc_is_rt3052(void)
-{
- return 0;
-}
-#else
-#include <asm/mach-ralink/rt305x.h>
-#endif
#include "ralink_soc_eth.h"
#include "mdio_rt2880.h"
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
+ [FE_REG_FE_RST_GL] = 0,
[FE_REG_FE_DMA_VID_BASE] = 0,
};
{
int ret;
- if (soc_is_rt3052()) {
+ if (ralink_soc != RT305X_SOC_RT3052) {
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
}
fe_fwd_config(priv);
- if (!soc_is_rt3352())
+ if (ralink_soc != RT305X_SOC_RT3352)
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return 0;
}
-static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
+static void rt5350_tx_dma(struct fe_tx_dma *txd)
{
- priv->tx_dma[idx].txd4 = 0;
+ txd->txd4 = 0;
}
static void rt5350_fe_reset(void)
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
- .rx_dly_int = FE_RX_DLY_INT,
- .tx_dly_int = FE_TX_DLY_INT,
+ .rx_int = FE_RX_DONE_INT,
+ .tx_int = FE_TX_DONE_INT,
};
static struct fe_soc_data rt5350_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
- .rx_dly_int = RT5350_RX_DLY_INT,
- .tx_dly_int = RT5350_TX_DLY_INT,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
};
const struct of_device_id of_fe_match[] = {