#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
+#define RT305X_ESW_PVIDC_PVID_M 0xfff
+#define RT305X_ESW_PVIDC_PVID_S 12
+
+#define RT305X_ESW_VLANI_VID_M 0xfff
+#define RT305X_ESW_VLANI_VID_S 12
+
+#define RT305X_ESW_VMSC_MSC_M 0xff
+#define RT305X_ESW_VMSC_MSC_S 8
+
+#define RT305X_ESW_PORT0 0
+#define RT305X_ESW_PORT1 1
+#define RT305X_ESW_PORT2 2
+#define RT305X_ESW_PORT3 3
+#define RT305X_ESW_PORT4 4
+#define RT305X_ESW_PORT5 5
+#define RT305X_ESW_PORT6 6
+
struct rt305x_esw {
void __iomem *base;
struct rt305x_esw_platform_data *pdata;
+ spinlock_t reg_rw_lock;
};
static inline void
return __raw_readl(esw->base + reg);
}
+static inline void
+rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
+ unsigned long val)
+{
+ unsigned long t;
+
+ t = __raw_readl(esw->base + reg) & ~mask;
+ __raw_writel(t | val, esw->base + reg);
+}
+
+static void
+rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
+ unsigned long val)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&esw->reg_rw_lock, flags);
+ rt305x_esw_rmw_raw(esw, reg, mask, val);
+ spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
+}
+
static u32
rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
u32 write_data)
return ret;
}
+static void
+rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
+{
+ unsigned s;
+
+ s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
+ rt305x_esw_rmw(esw,
+ RT305X_ESW_REG_VLANI(vlan / 2),
+ RT305X_ESW_VLANI_VID_M << s,
+ (vid & RT305X_ESW_VLANI_VID_M) << s);
+}
+
+static void
+rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
+{
+ unsigned s;
+
+ s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
+ rt305x_esw_rmw(esw,
+ RT305X_ESW_REG_PVIDC(port / 2),
+ RT305X_ESW_PVIDC_PVID_S << s,
+ (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
+}
+
+static void
+rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
+{
+ unsigned s;
+
+ s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
+ rt305x_esw_rmw(esw,
+ RT305X_ESW_REG_VMSC(vlan / 4),
+ RT305X_ESW_VMSC_MSC_M << s,
+ (msc & RT305X_ESW_VMSC_MSC_M) << s);
+}
+
static void
rt305x_esw_hw_init(struct rt305x_esw *esw)
{
rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
- rt305x_esw_wr(esw, 0x00002001, RT305X_ESW_REG_VLANI(0));
rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
- rt305x_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2));
+ rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
+ rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1);
rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
rt305x_mii_write(esw, 0, 31, 0x8000);
/* set default vlan */
- rt305x_esw_wr(esw, 0x2001, RT305X_ESW_REG_VLANI(0));
- rt305x_esw_wr(esw, 0x504f, RT305X_ESW_REG_VMSC(0));
+ rt305x_esw_set_vlan_id(esw, 0, 1);
+ rt305x_esw_set_vlan_id(esw, 1, 2);
+ rt305x_esw_set_vmsc(esw, 0,
+ (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
+ BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
+ BIT(RT305X_ESW_PORT6)));
+ rt305x_esw_set_vmsc(esw, 1,
+ (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
+ rt305x_esw_set_vmsc(esw, 2, 0);
+ rt305x_esw_set_vmsc(esw, 3, 0);
}
static int
platform_set_drvdata(pdev, esw);
esw->pdata = pdata;
+ spin_lock_init(&esw->reg_rw_lock);
rt305x_esw_hw_init(esw);
return 0;