#include <linux/err.h>
#include <asm/mach-jz4740/clock.h>
+#include "clock.h"
#define JZ_REG_CLOCK_CTRL 0x00
#define JZ_REG_CLOCK_LOW_POWER 0x04
-#define JZ_REG_CLOCK_SLEEP_CTRL 0x08
#define JZ_REG_CLOCK_PLL 0x10
#define JZ_REG_CLOCK_GATE 0x20
+#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
#define JZ_REG_CLOCK_I2S 0x60
#define JZ_REG_CLOCK_LCD 0x64
#define JZ_REG_CLOCK_MMC 0x68
#define JZ_CLOCK_GATE_RTC BIT(2)
#define JZ_CLOCK_GATE_I2C BIT(3)
#define JZ_CLOCK_GATE_SPI BIT(4)
-#define JZ_CLOCK_GATE_AIC_PCLK BIT(5)
-#define JZ_CLOCK_GATE_AIC BIT(6)
+#define JZ_CLOCK_GATE_AIC BIT(5)
+#define JZ_CLOCK_GATE_I2S BIT(6)
#define JZ_CLOCK_GATE_MMC BIT(7)
#define JZ_CLOCK_GATE_ADC BIT(8)
#define JZ_CLOCK_GATE_CIM BIT(9)
static spinlock_t jz_clock_lock;
static LIST_HEAD(jz_clocks);
-struct clk_ops {
- unsigned long (*get_rate)(struct clk* clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk* clk, unsigned long rate);
- int (*enable)(struct clk* clk);
- int (*disable)(struct clk* clk);
-
- int (*set_parent)(struct clk* clk, struct clk *parent);
-};
-
-struct clk {
- const char *name;
- struct clk* parent;
-
- uint32_t gate_bit;
-
- const struct clk_ops *ops;
-
- struct list_head list;
-};
-
struct main_clk {
struct clk clk;
uint32_t div_offset;
static int jz_clk_enable_gating(struct clk *clk)
{
+ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+ return -EINVAL;
+
jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
return 0;
}
static int jz_clk_disable_gating(struct clk *clk)
{
+ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+ return -EINVAL;
+
jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
return 0;
}
+static int jz_clk_is_enabled_gating(struct clk *clk)
+{
+ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+ return 1;
+
+ return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
+}
+
static unsigned long jz_clk_static_get_rate(struct clk *clk)
{
return ((struct static_clk*)clk)->rate;
}
-static int jz_clk_ko_enable(struct clk* clk)
+static int jz_clk_ko_enable(struct clk *clk)
{
jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
return 0;
}
-static int jz_clk_ko_disable(struct clk* clk)
+static int jz_clk_ko_disable(struct clk *clk)
{
jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
return 0;
}
+static int jz_clk_ko_is_enabled(struct clk *clk)
+{
+ return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
+}
static const int pllno[] = {1, 2, 2, 4};
.get_rate = jz_clk_static_get_rate,
.enable = jz_clk_enable_gating,
.disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
};
static struct static_clk jz_clk_ext = {
.clk = {
.name = "ext",
- .gate_bit = (uint32_t)-1,
+ .gate_bit = JZ4740_CLK_NOT_GATED,
.ops = &jz_clk_static_ops,
},
};
static const struct clk_ops jz_clk_ko_ops = {
.enable = jz_clk_ko_enable,
.disable = jz_clk_ko_disable,
+ .is_enabled = jz_clk_ko_is_enabled,
};
static struct clk jz_clk_ko = {
return 0;
}
-static int jz_clk_udc_disable(struct clk *clk)
+static int jz_clk_udc_enable(struct clk *clk)
{
- jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+ jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
return 0;
}
-static int jz_clk_udc_enable(struct clk *clk)
+static int jz_clk_udc_disable(struct clk *clk)
{
- jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+ jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
return 0;
}
+static int jz_clk_udc_is_enabled(struct clk *clk)
+{
+ return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
+ JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+}
static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
{
if (parent == &jz_clk_pll_half)
.set_rate = jz_clk_ldclk_set_rate,
.get_rate = jz_clk_ldclk_get_rate,
.round_rate = jz_clk_ldclk_round_rate,
+ .enable = jz_clk_enable_gating,
+ .disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
};
static struct clk jz_clk_ld = {
.name = "lcd",
+ .gate_bit = JZ_CLOCK_GATE_LCD,
.parent = &jz_clk_pll_half,
- .ops= &jz_clk_ops_ld,
-};
-
-static struct divided_clk jz_clk_lp = {
- .clk = {
- .name = "lcd_pclk",
- .parent = &jz_clk_pll_half,
- },
- .reg = JZ_REG_CLOCK_LCD,
- .mask = JZ_CLOCK_LCD_DIV_MASK,
+ .ops = &jz_clk_ops_ld,
};
+/* TODO: ops!!! */
static struct clk jz_clk_cim_mclk = {
.name = "cim_mclk",
.parent = &jz_clk_high_speed_peripheral.clk,
.get_rate = jz_clk_divided_get_rate,
.enable = jz_clk_enable_gating,
.disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
.set_parent = jz_clk_i2s_set_parent,
};
.get_rate = jz_clk_divided_get_rate,
.enable = jz_clk_enable_gating,
.disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
.set_parent = jz_clk_spi_set_parent,
};
.get_rate = jz_clk_divided_get_rate,
.enable = jz_clk_enable_gating,
.disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
};
static struct divided_clk jz4740_clock_divided_clks[] = {
+ {
+ .clk = {
+ .name = "lcd_pclk",
+ .parent = &jz_clk_pll_half,
+ .gate_bit = JZ4740_CLK_NOT_GATED,
+ .ops = &jz_clk_divided_ops,
+ },
+ .reg = JZ_REG_CLOCK_LCD,
+ .mask = JZ_CLOCK_LCD_DIV_MASK,
+ },
{
.clk = {
.name = "i2s",
.parent = &jz_clk_ext.clk,
- .gate_bit = JZ_CLOCK_GATE_AIC,
+ .gate_bit = JZ_CLOCK_GATE_I2S,
.ops = &jz_clk_i2s_ops,
},
.reg = JZ_REG_CLOCK_I2S,
.get_rate = jz_clk_udc_get_rate,
.enable = jz_clk_udc_enable,
.disable = jz_clk_udc_disable,
+ .is_enabled = jz_clk_udc_is_enabled,
};
static const struct clk_ops jz_clk_simple_ops = {
.enable = jz_clk_enable_gating,
.disable = jz_clk_disable_gating,
+ .is_enabled = jz_clk_is_enabled_gating,
};
static struct clk jz4740_clock_simple_clks[] = {
.gate_bit = JZ_CLOCK_GATE_I2C,
.ops = &jz_clk_simple_ops,
},
+ {
+ .name = "aic",
+ .parent = &jz_clk_ext.clk,
+ .gate_bit = JZ_CLOCK_GATE_AIC,
+ .ops = &jz_clk_simple_ops,
+ },
};
static struct static_clk jz_clk_rtc = {
}
EXPORT_SYMBOL_GPL(clk_disable);
+int clk_is_enabled(struct clk *clk)
+{
+ if (clk->ops->is_enabled)
+ return clk->ops->is_enabled(clk);
+
+ return 1;
+}
+
unsigned long clk_get_rate(struct clk *clk)
{
if (clk->ops->get_rate)
ret = clk->ops->set_parent(clk, parent);
clk_enable(clk);
+ jz4740_clock_debugfs_update_parent(clk);
+
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
}
EXPORT_SYMBOL_GPL(clk_put);
+
inline static void clk_add(struct clk *clk)
{
- list_add_tail(&clk->list, &jz_clocks);
+ list_add_tail(&clk->list, &jz_clocks);
+
+ jz4740_clock_debugfs_add_clk(clk);
}
static void clk_register_clks(void)
{
size_t i;
- clk_add(&jz_clk_ext.clk);
- clk_add(&jz_clk_pll);
- clk_add(&jz_clk_pll_half);
- clk_add(&jz_clk_cpu.clk);
- clk_add(&jz_clk_high_speed_peripheral.clk);
- clk_add(&jz_clk_low_speed_peripheral.clk);
- clk_add(&jz_clk_ko);
- clk_add(&jz_clk_ld);
- clk_add(&jz_clk_lp.clk);
- clk_add(&jz_clk_cim_mclk);
- clk_add(&jz_clk_cim_pclk.clk);
- clk_add(&jz_clk_rtc.clk);
+ clk_add(&jz_clk_ext.clk);
+ clk_add(&jz_clk_pll);
+ clk_add(&jz_clk_pll_half);
+ clk_add(&jz_clk_cpu.clk);
+ clk_add(&jz_clk_high_speed_peripheral.clk);
+ clk_add(&jz_clk_low_speed_peripheral.clk);
+ clk_add(&jz_clk_ko);
+ clk_add(&jz_clk_ld);
+ clk_add(&jz_clk_cim_mclk);
+ clk_add(&jz_clk_cim_pclk.clk);
+ clk_add(&jz_clk_rtc.clk);
for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
clk_add(&jz4740_clock_divided_clks[i].clk);
}
EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
-int jz_init_clocks(unsigned long ext_rate)
+void jz4740_clock_suspend(void)
+{
+ jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
+ JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+
+ jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+}
+
+void jz4740_clock_resume(void)
+{
+ jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+ while ((jz_clk_reg_read(JZ_REG_CLOCK_PLL) & JZ_CLOCK_PLL_STABLE) == 0);
+
+ jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
+ JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+}
+
+int jz4740_clock_init(void)
{
uint32_t val;
spin_lock_init(&jz_clock_lock);
- jz_clk_ext.rate = ext_rate;
+ jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
+ jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
+ jz4740_clock_debugfs_init();
+
clk_register_clks();
return 0;
}
-EXPORT_SYMBOL_GPL(jz_init_clocks);
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