X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Farch%2Fmips%2Far71xx%2Fsetup.c;h=d70347041ac5853c2b5814c5f8aae11ba215e1a2;hp=5d3f2a8e4248752702ca108d7938955b7d6fc04e;hb=2dee89f8ef76e76a54b4a5d1bb1db5b29b133900;hpb=0992cec37834d7c45f5727ff294cb12dbf6ab1f3 diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c index 5d3f2a8e42..d70347041a 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c @@ -1,10 +1,12 @@ /* * Atheros AR71xx SoC specific setup * - * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2009 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -12,30 +14,20 @@ */ #include -#include #include -#include -#include -#include #include #include -#include #include /* for mips_hpt_frequency */ #include /* for _machine_{restart,halt} */ +#include #include -#include -#include -#define AR71XX_SYS_TYPE_LEN 64 -#define AR71XX_BASE_FREQ 40000000 -#define AR91XX_BASE_FREQ 5000000 - -#define AR71XX_MEM_SIZE_MIN 0x0200000 -#define AR71XX_MEM_SIZE_MAX 0x8000000 +#include "machtype.h" +#include "devices.h" -unsigned long ar71xx_mach_type; +#define AR71XX_SYS_TYPE_LEN 64 u32 ar71xx_cpu_freq; EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); @@ -46,14 +38,12 @@ EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); u32 ar71xx_ddr_freq; EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); +u32 ar71xx_ref_freq; +EXPORT_SYMBOL_GPL(ar71xx_ref_freq); + enum ar71xx_soc_type ar71xx_soc; EXPORT_SYMBOL_GPL(ar71xx_soc); -int (*ar71xx_pci_bios_init)(unsigned nr_irqs, - struct ar71xx_pci_irq *map) __initdata; - -int (*ar71xx_pci_be_handler)(int is_fixup); - static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; static void ar71xx_restart(char *command) @@ -70,30 +60,12 @@ static void ar71xx_halt(void) cpu_wait(); } -static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) -{ - int err = 0; - - if (ar71xx_pci_be_handler) - err = ar71xx_pci_be_handler(is_fixup); - - return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; -} - -int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -{ - if (!ar71xx_pci_bios_init) - return 0; - - return ar71xx_pci_bios_init(nr_irqs, map); -} - static void __init ar71xx_detect_mem_size(void) { unsigned long size; for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; - size <<= 1 ) { + size <<= 1) { if (!memcmp(ar71xx_detect_mem_size, ar71xx_detect_mem_size + size, 1024)) break; @@ -104,45 +76,141 @@ static void __init ar71xx_detect_mem_size(void) static void __init ar71xx_detect_sys_type(void) { - char *chip; + char *chip = "????"; u32 id; - u32 rev; + u32 major; + u32 minor; + u32 rev = 0; + + id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + ar71xx_soc = AR71XX_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + ar71xx_soc = AR71XX_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + ar71xx_soc = AR71XX_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + ar71xx_soc = AR71XX_SOC_AR7240; + chip = "7240"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7241: + ar71xx_soc = AR71XX_SOC_AR7241; + chip = "7241"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; - id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK; - rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK; + case REV_ID_MAJOR_AR7242: + ar71xx_soc = AR71XX_SOC_AR7242; + chip = "7242"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; - switch (id & REV_ID_CHIP_MASK) { - case REV_ID_CHIP_AR7130: - ar71xx_soc = AR71XX_SOC_AR7130; - chip = "7130"; + case REV_ID_MAJOR_AR913X: + minor = id & AR91XX_REV_ID_MINOR_MASK; + rev = id >> AR91XX_REV_ID_REVISION_SHIFT; + rev &= AR91XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR91XX_REV_ID_MINOR_AR9130: + ar71xx_soc = AR71XX_SOC_AR9130; + chip = "9130"; + break; + + case AR91XX_REV_ID_MINOR_AR9132: + ar71xx_soc = AR71XX_SOC_AR9132; + chip = "9132"; + break; + } break; - case REV_ID_CHIP_AR7141: - ar71xx_soc = AR71XX_SOC_AR7141; - chip = "7141"; + case REV_ID_MAJOR_AR9330: + ar71xx_soc = AR71XX_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; break; - case REV_ID_CHIP_AR7161: - ar71xx_soc = AR71XX_SOC_AR7161; - chip = "7161"; + case REV_ID_MAJOR_AR9331: + ar71xx_soc = AR71XX_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; break; - case REV_ID_CHIP_AR9130: - ar71xx_soc = AR71XX_SOC_AR9130; - chip = "9130"; + case REV_ID_MAJOR_AR9342: + ar71xx_soc = AR71XX_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; break; - case REV_ID_CHIP_AR9132: - ar71xx_soc = AR71XX_SOC_AR9132; - chip = "9132"; + case REV_ID_MAJOR_AR9344: + ar71xx_soc = AR71XX_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; break; default: - panic("ar71xx: unknown chip id:0x%02x\n", id); + panic("ar71xx: unknown chip id:0x%08x\n", id); + } + + sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ar71xx_sys_type); +} + +static void __init ar934x_detect_sys_frequency(void) +{ + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + + if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) + ar71xx_ref_freq = 40 * 1000 * 1000; + else + ar71xx_ref_freq = 25 * 1000 * 1000; + + clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); + + pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); + out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll); + ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll); + nint = AR934X_CPU_PLL_CFG_NINT_GET(pll); + frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); + postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); + ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / + (postdiv + 1); + + out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); + ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); + nint = AR934X_DDR_PLL_CFG_NINT_GET(pll); + frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); + postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); + ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / + (postdiv + 1); + + postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); + + if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { + ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1); + } else { + ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); } - sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)", - chip, rev, id); } static void __init ar91xx_detect_sys_frequency(void) @@ -151,10 +219,12 @@ static void __init ar91xx_detect_sys_frequency(void) u32 freq; u32 div; + ar71xx_ref_freq = 5 * 1000 * 1000; + pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); - freq = div * AR91XX_BASE_FREQ; + freq = div * ar71xx_ref_freq; ar71xx_cpu_freq = freq; @@ -171,10 +241,12 @@ static void __init ar71xx_detect_sys_frequency(void) u32 freq; u32 div; + ar71xx_ref_freq = 40 * 1000 * 1000; + pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; - freq = div * AR71XX_BASE_FREQ; + freq = div * ar71xx_ref_freq; div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; ar71xx_cpu_freq = freq / div; @@ -186,6 +258,31 @@ static void __init ar71xx_detect_sys_frequency(void) ar71xx_ahb_freq = ar71xx_cpu_freq / div; } +static void __init ar724x_detect_sys_frequency(void) +{ + u32 pll; + u32 freq; + u32 div; + + ar71xx_ref_freq = 5 * 1000 * 1000; + + pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ar71xx_ref_freq; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + ar71xx_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ar71xx_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + ar71xx_ahb_freq = ar71xx_cpu_freq / div; +} + static void __init detect_sys_frequency(void) { switch (ar71xx_soc) { @@ -195,36 +292,27 @@ static void __init detect_sys_frequency(void) ar71xx_detect_sys_frequency(); break; + case AR71XX_SOC_AR7240: + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + ar724x_detect_sys_frequency(); + break; + case AR71XX_SOC_AR9130: case AR71XX_SOC_AR9132: ar91xx_detect_sys_frequency(); break; + case AR71XX_SOC_AR9341: + case AR71XX_SOC_AR9342: + case AR71XX_SOC_AR9344: + ar934x_detect_sys_frequency(); + break; default: BUG(); } } -#ifdef CONFIG_AR71XX_EARLY_SERIAL -static void __init ar71xx_early_serial_setup(void) -{ - struct uart_port p; - - memset(&p, 0, sizeof(p)); - - p.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP; - p.iotype = UPIO_MEM32; - p.uartclk = ar71xx_ahb_freq; - p.irq = AR71XX_MISC_IRQ_UART; - p.regshift = 2; - p.mapbase = AR71XX_UART_BASE; - - early_serial_setup(&p); -} -#else -static inline void ar71xx_early_serial_setup(void) {}; -#endif /* CONFIG_AR71XX_EARLY_SERIAL */ - const char *get_system_type(void) { return ar71xx_sys_type; @@ -257,16 +345,42 @@ void __init plat_mem_setup(void) ar71xx_detect_sys_type(); detect_sys_frequency(); + pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, " + "Ref:%u.%03uMHz", + ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, + ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000, + ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, + ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000); + _machine_restart = ar71xx_restart; _machine_halt = ar71xx_halt; pm_power_off = ar71xx_halt; - - board_be_handler = ar71xx_be_handler; - - ar71xx_early_serial_setup(); } void __init plat_time_init(void) { mips_hpt_frequency = ar71xx_cpu_freq / 2; } + +__setup("board=", mips_machtype_setup); + +static int __init ar71xx_machine_setup(void) +{ + ar71xx_gpio_init(); + + ar71xx_add_device_uart(); + ar71xx_add_device_wdt(); + + mips_machine_setup(); + return 0; +} + +arch_initcall(ar71xx_machine_setup); + +static void __init ar71xx_generic_init(void) +{ + /* Nothing to do */ +} + +MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", + ar71xx_generic_init);