X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Fdrivers%2Fnet%2Fag71xx%2Fag71xx.h;h=40715c90683583ac9e87fdb0c4ebca13caa2e440;hp=f7865523c345bc0871353569cb35c544836a7b3e;hb=caa92d1d00a52cc9562338fa4687ccb6c6632031;hpb=e31a7dea09669bf9ae9c621252ffabef364a6384

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index f7865523c3..40715c9068 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -37,7 +37,7 @@
 #define ETH_FCS_LEN	4
 
 #define AG71XX_DRV_NAME		"ag71xx"
-#define AG71XX_DRV_VERSION	"0.4.4"
+#define AG71XX_DRV_VERSION	"0.5.7"
 
 #define AG71XX_NAPI_TX		1
 
@@ -198,12 +198,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define AG71XX_REG_INT_ENABLE	0x0198
 #define AG71XX_REG_INT_STATUS	0x019c
 
-#define MAC_CFG1_TXE		BIT(0)
-#define MAC_CFG1_STX		BIT(1)
-#define MAC_CFG1_RXE		BIT(2)
-#define MAC_CFG1_SRX		BIT(3)
-#define MAC_CFG1_LB		BIT(8)
-#define MAC_CFG1_SR		BIT(31)
+#define MAC_CFG1_TXE		BIT(0)	/* Tx Enable */
+#define MAC_CFG1_STX		BIT(1)	/* Synchronize Tx Enable */
+#define MAC_CFG1_RXE		BIT(2)	/* Rx Enable */
+#define MAC_CFG1_SRX		BIT(3)	/* Synchronize Rx Enable */
+#define MAC_CFG1_TFC		BIT(4)	/* Tx Flow Control Enable */
+#define MAC_CFG1_RFC		BIT(5)	/* Rx Flow Control Enable */
+#define MAC_CFG1_LB		BIT(8)	/* Loopback mode */
+#define MAC_CFG1_SR		BIT(31)	/* Soft Reset */
 
 #define MAC_CFG2_FDX		BIT(0)
 #define MAC_CFG2_CRC_EN		BIT(1)
@@ -285,17 +287,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MII_IND_BUSY		BIT(0)
 #define MII_IND_INVALID		BIT(2)
 
-#define TX_CTRL_TXE		BIT(0)
+#define TX_CTRL_TXE		BIT(0)	/* Tx Enable */
 
-#define TX_STATUS_PS		BIT(0)
-#define TX_STATUS_UR		BIT(1)
-#define TX_STATUS_BE		BIT(3)
+#define TX_STATUS_PS		BIT(0)	/* Packet Sent */
+#define TX_STATUS_UR		BIT(1)	/* Tx Underrun */
+#define TX_STATUS_BE		BIT(3)	/* Bus Error */
 
-#define RX_CTRL_RXE		BIT(0)
+#define RX_CTRL_RXE		BIT(0)	/* Rx Enable */
 
-#define RX_STATUS_PR		BIT(0)
-#define RX_STATUS_OF		BIT(1)
-#define RX_STATUS_BE		BIT(3)
+#define RX_STATUS_PR		BIT(0)	/* Packet Received */
+#define RX_STATUS_OF		BIT(2)	/* Rx Overflow */
+#define RX_STATUS_BE		BIT(3)	/* Bus Error */
 
 #define MII_CTRL_IF_MASK	3
 #define MII_CTRL_SPEED_SHIFT	4
@@ -331,6 +333,8 @@ static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 		reg -= AG71XX_REG_MAC_IFCTL;
 		ret = __raw_readl(ag->mac_base2 + reg);
 		break;
+	default:
+		BUG();
 	}
 
 	return ret;