X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Fdrivers%2Fnet%2Fag71xx%2Fag71xx.h;h=cddf3a0729c32eec5578a0b18737c90c6f62f705;hp=f7865523c345bc0871353569cb35c544836a7b3e;hb=9c3697a13acd57773e8269931308c9da15f4c6df;hpb=e31a7dea09669bf9ae9c621252ffabef364a6384

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index f7865523c3..cddf3a0729 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -37,7 +37,7 @@
 #define ETH_FCS_LEN	4
 
 #define AG71XX_DRV_NAME		"ag71xx"
-#define AG71XX_DRV_VERSION	"0.4.4"
+#define AG71XX_DRV_VERSION	"0.5.8"
 
 #define AG71XX_NAPI_TX		1
 
@@ -198,12 +198,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define AG71XX_REG_INT_ENABLE	0x0198
 #define AG71XX_REG_INT_STATUS	0x019c
 
-#define MAC_CFG1_TXE		BIT(0)
-#define MAC_CFG1_STX		BIT(1)
-#define MAC_CFG1_RXE		BIT(2)
-#define MAC_CFG1_SRX		BIT(3)
-#define MAC_CFG1_LB		BIT(8)
-#define MAC_CFG1_SR		BIT(31)
+#define MAC_CFG1_TXE		BIT(0)	/* Tx Enable */
+#define MAC_CFG1_STX		BIT(1)	/* Synchronize Tx Enable */
+#define MAC_CFG1_RXE		BIT(2)	/* Rx Enable */
+#define MAC_CFG1_SRX		BIT(3)	/* Synchronize Rx Enable */
+#define MAC_CFG1_TFC		BIT(4)	/* Tx Flow Control Enable */
+#define MAC_CFG1_RFC		BIT(5)	/* Rx Flow Control Enable */
+#define MAC_CFG1_LB		BIT(8)	/* Loopback mode */
+#define MAC_CFG1_SR		BIT(31)	/* Soft Reset */
 
 #define MAC_CFG2_FDX		BIT(0)
 #define MAC_CFG2_CRC_EN		BIT(1)
@@ -285,17 +287,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define MII_IND_BUSY		BIT(0)
 #define MII_IND_INVALID		BIT(2)
 
-#define TX_CTRL_TXE		BIT(0)
+#define TX_CTRL_TXE		BIT(0)	/* Tx Enable */
 
-#define TX_STATUS_PS		BIT(0)
-#define TX_STATUS_UR		BIT(1)
-#define TX_STATUS_BE		BIT(3)
+#define TX_STATUS_PS		BIT(0)	/* Packet Sent */
+#define TX_STATUS_UR		BIT(1)	/* Tx Underrun */
+#define TX_STATUS_BE		BIT(3)	/* Bus Error */
 
-#define RX_CTRL_RXE		BIT(0)
+#define RX_CTRL_RXE		BIT(0)	/* Rx Enable */
 
-#define RX_STATUS_PR		BIT(0)
-#define RX_STATUS_OF		BIT(1)
-#define RX_STATUS_BE		BIT(3)
+#define RX_STATUS_PR		BIT(0)	/* Packet Received */
+#define RX_STATUS_OF		BIT(2)	/* Rx Overflow */
+#define RX_STATUS_BE		BIT(3)	/* Bus Error */
 
 #define MII_CTRL_IF_MASK	3
 #define MII_CTRL_SPEED_SHIFT	4
@@ -306,13 +308,18 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 
 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 {
+	void __iomem *r;
+
 	switch (reg) {
 	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-		__raw_writel(value, ag->mac_base + reg);
+		r = ag->mac_base + reg;
+		__raw_writel(value, r);
+		__raw_readl(r);
 		break;
 	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-		reg -= AG71XX_REG_MAC_IFCTL;
-		__raw_writel(value, ag->mac_base2 + reg);
+		r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+		__raw_writel(value, r);
+		__raw_readl(r);
 		break;
 	default:
 		BUG();
@@ -321,16 +328,20 @@ static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 
 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 {
+	void __iomem *r;
 	u32 ret;
 
 	switch (reg) {
 	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-		ret = __raw_readl(ag->mac_base + reg);
+		r = ag->mac_base + reg;
+		ret = __raw_readl(r);
 		break;
 	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
-		reg -= AG71XX_REG_MAC_IFCTL;
-		ret = __raw_readl(ag->mac_base2 + reg);
+		r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+		ret = __raw_readl(r);
 		break;
+	default:
+		BUG();
 	}
 
 	return ret;
@@ -344,10 +355,12 @@ static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 		r = ag->mac_base + reg;
 		__raw_writel(__raw_readl(r) | mask, r);
+		__raw_readl(r);
 		break;
 	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 		r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
 		__raw_writel(__raw_readl(r) | mask, r);
+		__raw_readl(r);
 		break;
 	default:
 		BUG();
@@ -362,10 +375,12 @@ static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 		r = ag->mac_base + reg;
 		__raw_writel(__raw_readl(r) & ~mask, r);
+		__raw_readl(r);
 		break;
 	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
 		r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
 		__raw_writel(__raw_readl(r) & ~mask, r);
+		__raw_readl(r);
 		break;
 	default:
 		BUG();
@@ -385,6 +400,7 @@ static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
 {
 	__raw_writel(value, ag->mii_ctrl);
+	__raw_readl(ag->mii_ctrl);
 }
 
 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)