X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Fdrivers%2Fnet%2Fag71xx%2Fag71xx_phy.c;h=aa9a74f34a4d4417c76d150a98b90019b23bdda9;hp=b1838d578b7a0865b0c423eb7e4721afa4e2633c;hb=b1eb74bd4f752da66a3a0f31a9431d89898d5b3d;hpb=563470e4756bb6f4d6aedde39cc34506b83679d8 diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c index b1838d578b..aa9a74f34a 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c @@ -13,46 +13,6 @@ #include "ag71xx.h" -#define PLL_SEC_CONFIG 0x18050004 -#define PLL_ETH0_INT_CLOCK 0x18050010 -#define PLL_ETH1_INT_CLOCK 0x18050014 -#define PLL_ETH_EXT_CLOCK 0x18050018 - -#define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17) -#define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \ - : PLL_ETH0_INT_CLOCK) - -static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val) -{ - void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4); - void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4); - u32 s; - u32 t; - - s = ag71xx_pll_shift(ag); - - t = __raw_readl(pll_cfg); - t &= ~(3 << s); - t |= (2 << s); - __raw_writel(t, pll_cfg); - udelay(100); - - __raw_writel(pll_val, pll_reg); - - t |= (3 << s); - __raw_writel(t, pll_cfg); - udelay(100); - - t &= ~(3 << s); - __raw_writel(t, pll_cfg); - udelay(100); - DBG("%s: pll_reg %#x: %#x\n", ag->dev->name, - (unsigned int)pll_reg, __raw_readl(pll_reg)); - - iounmap(pll_cfg); - iounmap(pll_reg); -} - static unsigned char *ag71xx_speed_str(struct ag71xx *ag) { switch (ag->speed) { @@ -67,18 +27,17 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag) return "?"; } -#if 1 -#define PLL_VAL_1000 0x00110000 -#define PLL_VAL_100 0x00001099 -#define PLL_VAL_10 0x00991099 -#else -#define PLL_VAL_1000 0x01111000 -#define PLL_VAL_100 0x09991000 -#define PLL_VAL_10 0x09991999 -#endif +#define AR71XX_PLL_VAL_1000 0x00110000 +#define AR71XX_PLL_VAL_100 0x00001099 +#define AR71XX_PLL_VAL_10 0x00991099 + +#define AR91XX_PLL_VAL_1000 0x1a000000 +#define AR91XX_PLL_VAL_100 0x13000a44 +#define AR91XX_PLL_VAL_10 0x00441099 static void ag71xx_phy_link_update(struct ag71xx *ag) { + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); u32 cfg2; u32 ifctl; u32 pll; @@ -87,7 +46,8 @@ static void ag71xx_phy_link_update(struct ag71xx *ag) if (!ag->link) { netif_carrier_off(ag->dev); - printk(KERN_INFO "%s: link down\n", ag->dev->name); + if (netif_msg_link(ag)) + printk(KERN_INFO "%s: link down\n", ag->dev->name); return; } @@ -99,33 +59,37 @@ static void ag71xx_phy_link_update(struct ag71xx *ag) ifctl &= ~(MAC_IFCTL_SPEED); fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); - fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK; + fifo5 &= ~FIFO_CFG5_BM; switch (ag->speed) { case SPEED_1000: mii_speed = MII_CTRL_SPEED_1000; cfg2 |= MAC_CFG2_IF_1000; - pll = PLL_VAL_1000; - fifo5 |= FIFO_CFG5_BYTE_PER_CLK; + pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000 + : AR71XX_PLL_VAL_1000; + fifo5 |= FIFO_CFG5_BM; break; case SPEED_100: mii_speed = MII_CTRL_SPEED_100; cfg2 |= MAC_CFG2_IF_10_100; ifctl |= MAC_IFCTL_SPEED; - pll = PLL_VAL_100; + pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100 + : AR71XX_PLL_VAL_100; break; case SPEED_10: mii_speed = MII_CTRL_SPEED_10; cfg2 |= MAC_CFG2_IF_10_100; - pll = PLL_VAL_10; + pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10 + : AR71XX_PLL_VAL_10; break; default: BUG(); return; } - ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); - ag71xx_set_pll(ag, pll); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, + pdata->is_ar91xx ? 0x780fff : 0x008001ff); + pdata->set_pll(pll); ag71xx_mii_ctrl_set_speed(ag, mii_speed); ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); @@ -133,20 +97,25 @@ static void ag71xx_phy_link_update(struct ag71xx *ag) ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); netif_carrier_on(ag->dev); - printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", - ag->dev->name, - ag71xx_speed_str(ag), - (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); + if (netif_msg_link(ag)) + printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", + ag->dev->name, + ag71xx_speed_str(ag), + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); - DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n", + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), - ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", + ag->dev->name, ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); - DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n", + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", ag->dev->name, ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), @@ -191,8 +160,10 @@ void ag71xx_phy_start(struct ag71xx *ag) if (ag->phy_dev) { phy_start(ag->phy_dev); } else { - ag->duplex = DUPLEX_FULL; - ag->speed = SPEED_100; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + ag->duplex = pdata->duplex; + ag->speed = pdata->speed; ag->link = 1; ag71xx_phy_link_update(ag); } @@ -218,8 +189,8 @@ int ag71xx_phy_connect(struct ag71xx *ag) int phy_count = 0; int phy_addr; - if (ag->mii_bus) { - /* TODO: use mutex of the mdio bus */ + if (ag->mii_bus && pdata->phy_mask) { + /* TODO: use mutex of the mdio bus? */ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { if (!(pdata->phy_mask & (1 << phy_addr))) continue; @@ -240,9 +211,6 @@ int ag71xx_phy_connect(struct ag71xx *ag) } switch (phy_count) { - case 0: - printk(KERN_ERR "%s: no PHY found\n", dev->name); - return -ENODEV; case 1: ag->phy_dev = phy_connect(dev, phydev->dev.bus_id, &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode); @@ -254,13 +222,10 @@ int ag71xx_phy_connect(struct ag71xx *ag) } /* mask with MAC supported features */ - phydev->supported &= (SUPPORTED_10baseT_Half - | SUPPORTED_10baseT_Full - | SUPPORTED_100baseT_Half - | SUPPORTED_100baseT_Full - | SUPPORTED_Autoneg - | SUPPORTED_MII - | SUPPORTED_TP); + if (pdata->has_gbit) + phydev->supported &= PHY_GBIT_FEATURES; + else + phydev->supported &= PHY_BASIC_FEATURES; phydev->advertising = phydev->supported; @@ -273,9 +238,21 @@ int ag71xx_phy_connect(struct ag71xx *ag) ag->speed = 0; ag->duplex = -1; break; + default: + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + printk(KERN_ERR "%s: invalid speed specified\n", + dev->name); + return -EINVAL; + } + ag->phy_dev = NULL; - printk(KERN_DEBUG "%s: connected to multiple PHYs (%d)\n", + printk(KERN_DEBUG "%s: connected to %d PHYs\n", dev->name, phy_count); break; }