X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Framips%2Ffiles%2Fdrivers%2Fnet%2Fethernet%2Fralink%2Fsoc_mt7620.c;h=5a7ee35eb0379ae7f227eca2aa613e835e192f51;hp=2f3018d6a404136fd57ed69c60960df04183c07d;hb=8844506e3ce357c16afce86fda09dd434fb9fea1;hpb=262eb6105804a4aa8545f99937d060ceb77498c6

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index 2f3018d6a4..5a7ee35eb0 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -27,7 +27,7 @@
 
 #define MT7620A_CDMA_CSG_CFG	0x400
 #define MT7620_DMA_VID		(MT7620A_CDMA_CSG_CFG | 0x30)
-#define MT7620A_DMA_2B_OFFSET	BIT(31)
+#define MT7621_DMA_VID		0xa8
 #define MT7620A_RESET_FE	BIT(21)
 #define MT7621_RESET_FE		BIT(6)
 #define MT7620A_RESET_ESW	BIT(23)
@@ -38,8 +38,6 @@
 #define MT7621_TX_DMA_UDF	BIT(19)
 #define TX_DMA_FP_BMAP		((0xff) << 19)
 
-#define SYSC_REG_RESET_CTRL     0x34
-
 #define CDMA_ICS_EN		BIT(2)
 #define CDMA_UCS_EN		BIT(1)
 #define CDMA_TCS_EN		BIT(0)
@@ -54,6 +52,11 @@
 #define MT7620_GDM1_TX_GBCNT	(MT7620_REG_MIB_OFFSET + 0x300)
 #define MT7620_GDM2_TX_GBCNT	(MT7620_GDM1_TX_GBCNT + 0x40)
 
+#define MT7621_REG_MIB_OFFSET	0x2000
+#define MT7621_PPE_AC_BCNT0	(MT7621_REG_MIB_OFFSET + 0x00)
+#define MT7621_GDM1_TX_GBCNT	(MT7621_REG_MIB_OFFSET + 0x400)
+#define MT7621_GDM2_TX_GBCNT	(MT7621_GDM1_TX_GBCNT + 0x40)
+
 #define GSW_REG_GDMA1_MAC_ADRL	0x508
 #define GSW_REG_GDMA1_MAC_ADRH	0x50C
 
@@ -66,9 +69,11 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = {
 	[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
 	[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
 	[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+	[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
 	[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
 	[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
 	[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+	[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
 	[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
 	[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
 	[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
@@ -76,20 +81,33 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = {
 	[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 };
 
+static const u32 mt7621_reg_table[FE_REG_COUNT] = {
+	[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+	[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+	[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+	[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+	[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+	[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+	[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+	[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+	[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+	[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+	[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+	[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
+	[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
+	[FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
+	[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
+	[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
+};
+
 static void mt7620_fe_reset(void)
 {
-	u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-
-	rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
-	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+	fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 }
 
 static void mt7621_fe_reset(void)
 {
-	u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-
-	rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL);
-	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+	fe_reset(MT7621_RESET_FE);
 }
 
 static void mt7620_rxcsum_config(bool enable)
@@ -140,19 +158,14 @@ static int mt7621_fwd_config(struct fe_priv *priv)
 	return 0;
 }
 
-static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
+static void mt7620_tx_dma(struct fe_tx_dma *txd)
 {
-	priv->tx_dma[idx].txd4 = 0;
+	txd->txd4 = 0;
 }
 
-static void mt7621_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
+static void mt7621_tx_dma(struct fe_tx_dma *txd)
 {
-	priv->tx_dma[idx].txd4 = BIT(25);
-}
-
-static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
-{
-	priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
+	txd->txd4 = BIT(25);
 }
 
 static void mt7620_init_data(struct fe_soc_data *data,
@@ -160,7 +173,8 @@ static void mt7620_init_data(struct fe_soc_data *data,
 {
 	struct fe_priv *priv = netdev_priv(netdev);
 
-	priv->flags = FE_FLAG_PADDING_64B;
+	priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
+		FE_FLAG_RX_SG_DMA;
 	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 		NETIF_F_HW_VLAN_CTAG_TX;
 
@@ -169,6 +183,16 @@ static void mt7620_init_data(struct fe_soc_data *data,
 			NETIF_F_IPV6_CSUM;
 }
 
+static void mt7621_init_data(struct fe_soc_data *data,
+		struct net_device *netdev)
+{
+	struct fe_priv *priv = netdev_priv(netdev);
+
+	priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
+		FE_FLAG_RX_SG_DMA;
+	netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
+}
+
 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 {
 	unsigned long flags;
@@ -187,14 +211,13 @@ static struct fe_soc_data mt7620_data = {
 	.set_mac = mt7620_set_mac,
 	.fwd_config = mt7620_fwd_config,
 	.tx_dma = mt7620_tx_dma,
-	.rx_dma = mt7620_rx_dma,
 	.switch_init = mt7620_gsw_probe,
 	.switch_config = mt7620_gsw_config,
 	.port_init = mt7620_port_init,
 	.reg_table = mt7620_reg_table,
-	.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
-	.rx_dly_int = RT5350_RX_DLY_INT,
-	.tx_dly_int = RT5350_TX_DLY_INT,
+	.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
+	.rx_int = RT5350_RX_DONE_INT,
+	.tx_int = RT5350_TX_DONE_INT,
 	.checksum_bit = MT7620_L4_VALID,
 	.tx_udf_bit = MT7620_TX_DMA_UDF,
 	.has_carrier = mt7620a_has_carrier,
@@ -205,18 +228,17 @@ static struct fe_soc_data mt7620_data = {
 
 static struct fe_soc_data mt7621_data = {
 	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-	.init_data = mt7620_init_data,
+	.init_data = mt7621_init_data,
 	.reset_fe = mt7621_fe_reset,
 	.set_mac = mt7621_set_mac,
 	.fwd_config = mt7621_fwd_config,
 	.tx_dma = mt7621_tx_dma,
-	.rx_dma = mt7620_rx_dma,
 	.switch_init = mt7620_gsw_probe,
 	.switch_config = mt7621_gsw_config,
-	.reg_table = mt7620_reg_table,
-	.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
-	.rx_dly_int = RT5350_RX_DLY_INT,
-	.tx_dly_int = RT5350_TX_DLY_INT,
+	.reg_table = mt7621_reg_table,
+	.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
+	.rx_int = RT5350_RX_DONE_INT,
+	.tx_int = RT5350_TX_DONE_INT,
 	.checksum_bit = MT7621_L4_VALID,
 	.tx_udf_bit = MT7621_TX_DMA_UDF,
 	.has_carrier = mt7620a_has_carrier,