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(parent: 9b2e6e7) | patch
ar71xx: fix ar724x clock calculation
authorFelix Fietkau <nbd@openwrt.org>
Fri, 11 Sep 2015 16:32:45 +0000 (16:32 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Fri, 11 Sep 2015 16:32:45 +0000 (16:32 +0000)
commit7f60f94d547fd2fef08dd49c48cc769ce552a533
treece316408cc89b5ea495a0fcdbd49c50970d99a91tree | snapshot
parent9b2e6e7dd76bfebc179aa541abdd24c265a242f6commit | diff
ar71xx: fix ar724x clock calculation

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.

Test on both AR7240, AR7241 and AR7242.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
SVN-Revision: 46856
target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch [new file with mode: 0644] blob
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