lantiq: Fixed reading the number of RX FIFOs in the SPI driver
authorJohn Crispin <john@openwrt.org>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
committerJohn Crispin <john@openwrt.org>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
commita7e3dbb93f94c7e685582616f4af02be7d023bb2
treebfb0223d378b3800b0822ce1fea583f10740cfd2
parent606e1ccaa047422c374b9f913f4ecad736d807bc
lantiq: Fixed reading the number of RX FIFOs in the SPI driver

Until now the SPI driver used the TX bits for the RX FIFO. This seems
uncritical for now since both are equals on my devices (VR9), but this
could cause problems on other SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 47208
target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch
target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch