ramips: define GPIO chips separately for each SoCs
authorGabor Juhos <juhosg@openwrt.org>
Sun, 27 Mar 2011 19:19:59 +0000 (19:19 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Sun, 27 Mar 2011 19:19:59 +0000 (19:19 +0000)
SVN-Revision: 26326

target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
target/linux/ramips/files/arch/mips/ralink/common/gpio.c
target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c
target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

index 60ca647..73301e2 100644 (file)
 #define RALINK_SOC_MEM_SIZE_MIN                (2 * 1024 * 1024)
 #define RALINK_SOC_MEM_SIZE_MAX                (128 * 1024 * 1024)
 
-#define RALINK_SOC_GPIO_BASE   0x300600
-
-#define RALINK_SOC_GPIO0_COUNT 24
-#define RALINK_SOC_GPIO1_COUNT 16
-#define RALINK_SOC_GPIO2_COUNT 32
-
 #endif /* __RT288X_RALINK_SOC_H */
index a95cb82..2ae26ef 100644 (file)
@@ -37,6 +37,7 @@
 #define RT2880_INTC_SIZE       0x100
 #define RT2880_MEMC_SIZE       0x100
 #define RT2880_UART0_SIZE      0x100
+#define RT2880_PIO_SIZE                0x100
 #define RT2880_UART1_SIZE      0x100
 #define RT2880_FLASH1_SIZE     (16 * 1024 * 1024)
 #define RT2880_FLASH0_SIZE     (4 * 1024 * 1024)
index fd0e8b3..c3206ec 100644 (file)
 #define RALINK_SOC_MEM_SIZE_MIN                (2 * 1024 * 1024)
 #define RALINK_SOC_MEM_SIZE_MAX                (64 * 1024 * 1024)
 
-#define RALINK_SOC_GPIO_BASE   0x10000600
-
-#define RALINK_SOC_GPIO0_COUNT 24
-#define RALINK_SOC_GPIO1_COUNT 16
-#define RALINK_SOC_GPIO2_COUNT 12
-
 #endif /* __RT288X_RALINK_SOC_H */
index c4964b0..5970f78 100644 (file)
@@ -20,6 +20,7 @@
 #define RT305X_MEMC_BASE       0x10000300
 #define RT305X_PCM_BASE                0x10000400
 #define RT305X_UART0_BASE      0x10000500
+#define RT305X_PIO_BASE                0x10000600
 #define RT305X_GDMA_BASE       0x10000700
 #define RT305X_NANDC_BASE      0x10000800
 #define RT305X_I2C_BASE                0x10000900
@@ -39,6 +40,7 @@
 #define RT305X_INTC_SIZE       0x100
 #define RT305X_MEMC_SIZE       0x100
 #define RT305X_UART0_SIZE      0x100
+#define RT305X_PIO_SIZE                0x100
 #define RT305X_UART1_SIZE      0x100
 #define RT305X_FLASH1_SIZE     (16 * 1024 * 1024)
 #define RT305X_FLASH0_SIZE     (8 * 1024 * 1024)
index ebaceea..feb6cc2 100644 (file)
@@ -86,72 +86,6 @@ static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
        return !!(t & (1 << offset));
 }
 
-static struct ramips_gpio_chip ramips_gpio_chip0 = {
-       .chip = {
-               .label                  = "ramips-gpio0",
-               .base                   = 0,
-               .ngpio                  = RALINK_SOC_GPIO0_COUNT,
-       },
-       .regs = {
-               [RAMIPS_GPIO_REG_INT]   = GPIO0_REG_INT,
-               [RAMIPS_GPIO_REG_EDGE]  = GPIO0_REG_EDGE,
-               [RAMIPS_GPIO_REG_RENA]  = GPIO0_REG_RENA,
-               [RAMIPS_GPIO_REG_FENA]  = GPIO0_REG_FENA,
-               [RAMIPS_GPIO_REG_DATA]  = GPIO0_REG_DATA,
-               [RAMIPS_GPIO_REG_DIR]   = GPIO0_REG_DIR,
-               [RAMIPS_GPIO_REG_POL]   = GPIO0_REG_POL,
-               [RAMIPS_GPIO_REG_SET]   = GPIO0_REG_SET,
-               [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
-               [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
-       },
-       .map_base       = RALINK_SOC_GPIO_BASE,
-       .map_size       = PAGE_SIZE,
-};
-
-static struct ramips_gpio_chip ramips_gpio_chip1 = {
-       .chip = {
-               .label                  = "ramips-gpio1",
-               .base                   = 32,
-               .ngpio                  = RALINK_SOC_GPIO1_COUNT,
-       },
-       .regs = {
-               [RAMIPS_GPIO_REG_INT]   = GPIO1_REG_INT,
-               [RAMIPS_GPIO_REG_EDGE]  = GPIO1_REG_EDGE,
-               [RAMIPS_GPIO_REG_RENA]  = GPIO1_REG_RENA,
-               [RAMIPS_GPIO_REG_FENA]  = GPIO1_REG_FENA,
-               [RAMIPS_GPIO_REG_DATA]  = GPIO1_REG_DATA,
-               [RAMIPS_GPIO_REG_DIR]   = GPIO1_REG_DIR,
-               [RAMIPS_GPIO_REG_POL]   = GPIO1_REG_POL,
-               [RAMIPS_GPIO_REG_SET]   = GPIO1_REG_SET,
-               [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
-               [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
-       },
-       .map_base       = RALINK_SOC_GPIO_BASE,
-       .map_size       = PAGE_SIZE,
-};
-
-static struct ramips_gpio_chip ramips_gpio_chip2 = {
-       .chip = {
-               .label                  = "ramips-gpio2",
-               .base                   = 64,
-               .ngpio                  = RALINK_SOC_GPIO2_COUNT,
-       },
-       .regs = {
-               [RAMIPS_GPIO_REG_INT]   = GPIO2_REG_INT,
-               [RAMIPS_GPIO_REG_EDGE]  = GPIO2_REG_EDGE,
-               [RAMIPS_GPIO_REG_RENA]  = GPIO2_REG_RENA,
-               [RAMIPS_GPIO_REG_FENA]  = GPIO2_REG_FENA,
-               [RAMIPS_GPIO_REG_DATA]  = GPIO2_REG_DATA,
-               [RAMIPS_GPIO_REG_DIR]   = GPIO2_REG_DIR,
-               [RAMIPS_GPIO_REG_POL]   = GPIO2_REG_POL,
-               [RAMIPS_GPIO_REG_SET]   = GPIO2_REG_SET,
-               [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
-               [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
-       },
-       .map_base       = RALINK_SOC_GPIO_BASE,
-       .map_size       = PAGE_SIZE,
-};
-
 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
 {
        spin_lock_init(&rg->lock);
@@ -169,11 +103,12 @@ static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
        gpiochip_add(&rg->chip);
 }
 
-__init int ramips_gpio_init(void)
+__init int ramips_gpio_init(struct ramips_gpio_data *data)
 {
-       ramips_gpio_chip_add(&ramips_gpio_chip0);
-       ramips_gpio_chip_add(&ramips_gpio_chip1);
-       ramips_gpio_chip_add(&ramips_gpio_chip2);
+       int i;
+
+       for (i = 0; i < data->num_chips; i++)
+               ramips_gpio_chip_add(&data->chips[i]);
 
        return 0;
 }
index c87a360..53b1a69 100644 (file)
@@ -43,6 +43,77 @@ void __init rt288x_detect_sys_type(void)
                (id & CHIP_ID_REV_MASK));
 }
 
+static struct ramips_gpio_chip rt288x_gpio_chips[] = {
+       {
+               .chip = {
+                       .label  = "RT288X-GPIO0",
+                       .base   = 0,
+                       .ngpio  = 24,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x00,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x04,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x08,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x0c,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x20,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x24,
+                       [RAMIPS_GPIO_REG_POL]   = 0x28,
+                       [RAMIPS_GPIO_REG_SET]   = 0x2c,
+                       [RAMIPS_GPIO_REG_RESET] = 0x30,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
+               },
+               .map_base = RT2880_PIO_BASE,
+               .map_size = RT2880_PIO_SIZE,
+       },
+       {
+               .chip = {
+                       .label  = "RT288X-GPIO1",
+                       .base   = 24,
+                       .ngpio  = 16,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x38,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x40,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x44,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x48,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x4c,
+                       [RAMIPS_GPIO_REG_POL]   = 0x50,
+                       [RAMIPS_GPIO_REG_SET]   = 0x54,
+                       [RAMIPS_GPIO_REG_RESET] = 0x58,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
+               },
+               .map_base = RT2880_PIO_BASE,
+               .map_size = RT2880_PIO_SIZE,
+       },
+       {
+               .chip = {
+                       .label  = "RT288X-GPIO2",
+                       .base   = 40,
+                       .ngpio  = 32,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x60,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x64,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x68,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x6c,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x70,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x74,
+                       [RAMIPS_GPIO_REG_POL]   = 0x78,
+                       [RAMIPS_GPIO_REG_SET]   = 0x7c,
+                       [RAMIPS_GPIO_REG_RESET] = 0x80,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
+               },
+               .map_base = RT2880_PIO_BASE,
+               .map_size = RT2880_PIO_SIZE,
+       },
+};
+
+static struct ramips_gpio_data rt288x_gpio_data = {
+       .chips = rt288x_gpio_chips,
+       .num_chips = ARRAY_SIZE(rt288x_gpio_chips),
+};
+
 static void rt288x_gpio_reserve(int first, int last)
 {
        for (; first <= last; first++)
@@ -53,7 +124,7 @@ void __init rt288x_gpio_init(u32 mode)
 {
        rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 
-       ramips_gpio_init();
+       ramips_gpio_init(&rt288x_gpio_data);
        if ((mode & RT2880_GPIO_MODE_I2C) == 0)
                rt288x_gpio_reserve(1, 2);
 
index 70f548a..5916888 100644 (file)
@@ -43,6 +43,77 @@ void __init rt305x_detect_sys_type(void)
                (id & CHIP_ID_REV_MASK));
 }
 
+static struct ramips_gpio_chip rt305x_gpio_chips[] = {
+       {
+               .chip = {
+                       .label  = "RT305X-GPIO0",
+                       .base   = 0,
+                       .ngpio  = 24,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x00,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x04,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x08,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x0c,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x20,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x24,
+                       [RAMIPS_GPIO_REG_POL]   = 0x28,
+                       [RAMIPS_GPIO_REG_SET]   = 0x2c,
+                       [RAMIPS_GPIO_REG_RESET] = 0x30,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
+               },
+               .map_base = RT305X_PIO_BASE,
+               .map_size = RT305X_PIO_SIZE,
+       },
+       {
+               .chip = {
+                       .label  = "RT305X-GPIO1",
+                       .base   = 24,
+                       .ngpio  = 16,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x38,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x40,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x44,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x48,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x4c,
+                       [RAMIPS_GPIO_REG_POL]   = 0x50,
+                       [RAMIPS_GPIO_REG_SET]   = 0x54,
+                       [RAMIPS_GPIO_REG_RESET] = 0x58,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
+               },
+               .map_base = RT305X_PIO_BASE,
+               .map_size = RT305X_PIO_SIZE,
+       },
+       {
+               .chip = {
+                       .label  = "RT305X-GPIO2",
+                       .base   = 40,
+                       .ngpio  = 12,
+               },
+               .regs = {
+                       [RAMIPS_GPIO_REG_INT]   = 0x60,
+                       [RAMIPS_GPIO_REG_EDGE]  = 0x64,
+                       [RAMIPS_GPIO_REG_RENA]  = 0x68,
+                       [RAMIPS_GPIO_REG_FENA]  = 0x6c,
+                       [RAMIPS_GPIO_REG_DATA]  = 0x70,
+                       [RAMIPS_GPIO_REG_DIR]   = 0x74,
+                       [RAMIPS_GPIO_REG_POL]   = 0x78,
+                       [RAMIPS_GPIO_REG_SET]   = 0x7c,
+                       [RAMIPS_GPIO_REG_RESET] = 0x80,
+                       [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
+               },
+               .map_base = RT305X_PIO_BASE,
+               .map_size = RT305X_PIO_SIZE,
+       },
+};
+
+static struct ramips_gpio_data rt305x_gpio_data = {
+       .chips = rt305x_gpio_chips,
+       .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
+};
+
 static void rt305x_gpio_reserve(int first, int last)
 {
        for (; first <= last; first++)
@@ -55,7 +126,7 @@ void __init rt305x_gpio_init(u32 mode)
 
        rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 
-       ramips_gpio_init();
+       ramips_gpio_init(&rt305x_gpio_data);
        if ((mode & RT305X_GPIO_MODE_I2C) == 0)
                rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);