mac80211: update to wireless-testing 2012-05-29
authorFelix Fietkau <nbd@openwrt.org>
Wed, 30 May 2012 01:01:06 +0000 (01:01 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Wed, 30 May 2012 01:01:06 +0000 (01:01 +0000)
SVN-Revision: 32002

59 files changed:
package/mac80211/Makefile
package/mac80211/patches/000-disable_ethernet.patch
package/mac80211/patches/001-disable_b44.patch
package/mac80211/patches/002-disable_rfkill.patch
package/mac80211/patches/003-disable_bt.patch
package/mac80211/patches/005-disable_ssb_build.patch
package/mac80211/patches/006-disable_bcma_build.patch
package/mac80211/patches/007-remove_misc_drivers.patch
package/mac80211/patches/008-disable_mesh.patch
package/mac80211/patches/010-no_pcmcia.patch
package/mac80211/patches/011-no_sdio.patch
package/mac80211/patches/013-disable_b43_nphy.patch
package/mac80211/patches/015-remove-rt2x00-options.patch
package/mac80211/patches/016-remove_pid_algo.patch
package/mac80211/patches/017-remove_ath9k_rc.patch
package/mac80211/patches/019-remove_ath5k_pci_option.patch
package/mac80211/patches/022-remove_crc8_and_cordic.patch
package/mac80211/patches/023-ath9k_disable_btcoex.patch
package/mac80211/patches/050-compat_firmware.patch
package/mac80211/patches/060-compat_add_module_pci_driver.patch
package/mac80211/patches/070-disable_codel.patch [new file with mode: 0644]
package/mac80211/patches/071-add_codel_ifdef.patch [new file with mode: 0644]
package/mac80211/patches/110-disable_usb_compat.patch
package/mac80211/patches/120-pr_fmt_warnings.patch
package/mac80211/patches/201-ath5k-WAR-for-AR71xx-PCI-bug.patch
package/mac80211/patches/300-pending_work.patch
package/mac80211/patches/401-ath9k_blink_default.patch
package/mac80211/patches/403-ath_regd_optional.patch
package/mac80211/patches/404-world_regd_fixup.patch
package/mac80211/patches/410-ath9k_allow_adhoc_and_ap.patch
package/mac80211/patches/411-ath5k_allow_adhoc_and_ap.patch
package/mac80211/patches/412-mac80211_allow_adhoc_and_ap.patch
package/mac80211/patches/420-ath5k_disable_fast_cc.patch
package/mac80211/patches/431-add_platform_eeprom_support_to_ath5k.patch
package/mac80211/patches/432-ath5k_add_pciids.patch
package/mac80211/patches/501-ath9k-eeprom_endianess.patch
package/mac80211/patches/502-ath9k_ahb_init.patch
package/mac80211/patches/510-ath9k_intr_mitigation_tweak.patch
package/mac80211/patches/512-ath9k_channelbw_debugfs.patch
package/mac80211/patches/520-mac80211_cur_txpower.patch
package/mac80211/patches/521-ath9k_cur_txpower.patch
package/mac80211/patches/522-ath9k_per_chain_signal_strength.patch
package/mac80211/patches/530-ath9k_limit_qlen.patch
package/mac80211/patches/540-ath9k_extra_leds.patch
package/mac80211/patches/550-mac80211_optimize_mcs_rate_mask.patch
package/mac80211/patches/560-ath9k_fix_rx_tx_stop.patch [deleted file]
package/mac80211/patches/561-ath9k_fix_tid_buffer_free.patch [deleted file]
package/mac80211/patches/562-ath9k_update_ar9330_initvals.patch [deleted file]
package/mac80211/patches/563-ath9k_fix_ar9330_internal_regulator.patch [deleted file]
package/mac80211/patches/820-b43-add-antenna-control.patch
package/mac80211/patches/840-b43-backport.patch [deleted file]
package/mac80211/patches/840-brcmsmac-add-device-found-on-some-SoCs-like-the-bcm4.patch [new file with mode: 0644]
package/mac80211/patches/841-brcmsmac-add-support-for-BCM43224.patch [new file with mode: 0644]
package/mac80211/patches/842-brcmsmac-add-some-conditions-for-the-bcm4716-again.patch [new file with mode: 0644]
package/mac80211/patches/860-brcmsmac-backport.patch [deleted file]
package/mac80211/patches/870-brcmsmac-add-device-found-on-some-SoCs-like-the-bcm4.patch [deleted file]
package/mac80211/patches/871-brcmsmac-add-support-for-BCM43224.patch [deleted file]
package/mac80211/patches/872-brcmsmac-add-some-conditions-for-the-bcm4716-again.patch [deleted file]
package/mac80211/patches/890-brcmfmac-fix-memory-allocation.patch [deleted file]

index 489c338..a0388bb 100644 (file)
@@ -10,10 +10,10 @@ include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=mac80211
 
-PKG_VERSION:=2012-04-17
-PKG_RELEASE:=2
+PKG_VERSION:=2012-05-29
+PKG_RELEASE:=1
 PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
-PKG_MD5SUM:=2607092b22b5cb552dc3c79921c85369
+PKG_MD5SUM:=a98eedfcb1690405626217e040deec1a
 
 PKG_SOURCE:=compat-wireless-$(PKG_VERSION).tar.bz2
 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/compat-wireless-$(PKG_VERSION)
index f89fa53..2c5e3d0 100644 (file)
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -29,9 +29,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
+@@ -44,9 +44,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
  
  obj-$(CONFIG_COMPAT_NET_USB_MODULES) += drivers/net/usb/
  
index e73cf99..aaebab1 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -362,8 +362,8 @@ export CONFIG_B43_BCMA_EXTRA=y
+@@ -370,8 +370,8 @@ export CONFIG_B43_BCMA_EXTRA=y
  
  export CONFIG_P54_PCI=m
  
index 5eebf69..1bd9fc3 100644 (file)
@@ -9,7 +9,7 @@
  
  ifeq ($(CONFIG_MAC80211),y)
  $(error "ERROR: you have MAC80211 compiled into the kernel, CONFIG_MAC80211=y, as such you cannot replace its mac80211 driver. You need this set to CONFIG_MAC80211=m. If you are using Fedora upgrade your kernel as later version should this set as modular. For further information on Fedora see https://bugzilla.redhat.com/show_bug.cgi?id=470143. If you are using your own kernel recompile it and make mac80211 modular")
-@@ -668,10 +668,10 @@ endif #CONFIG_COMPAT_KERNEL_2_6_27
+@@ -675,10 +675,10 @@ endif #CONFIG_COMPAT_KERNEL_2_6_27
  # We need the backported rfkill module on kernel < 2.6.31.
  # In more recent kernel versions use the in kernel rfkill module.
  ifdef CONFIG_COMPAT_KERNEL_2_6_31
index 025f9dc..499c823 100644 (file)
@@ -1,13 +1,15 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -99,8 +99,8 @@ ifndef CONFIG_COMPAT_KERNEL_2_6_27
+@@ -99,9 +99,9 @@ ifndef CONFIG_COMPAT_KERNEL_2_6_27
  ifeq ($(CONFIG_BT),y)
  # we'll ignore compiling bluetooth
  else
 - export CONFIG_COMPAT_BLUETOOTH=y
 - export CONFIG_COMPAT_BLUETOOTH_MODULES=m
+- export CONFIG_HID_GENERIC=m
 +# export CONFIG_COMPAT_BLUETOOTH=y
 +# export CONFIG_COMPAT_BLUETOOTH_MODULES=m
++# export CONFIG_HID_GENERIC=m
  endif
  endif #CONFIG_COMPAT_KERNEL_2_6_27
  
index 442ed25..996d7b1 100644 (file)
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -29,7 +29,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
+@@ -44,7 +44,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
  
  obj-$(CONFIG_COMPAT_NET_USB_MODULES) += drivers/net/usb/
  
@@ -19,7 +19,7 @@
  else
  include $(KLIB_BUILD)/.config
  endif
-@@ -338,7 +338,8 @@ export CONFIG_IPW2200_QOS=y
+@@ -346,7 +346,8 @@ export CONFIG_IPW2200_QOS=y
  # % echo 1 > /sys/bus/pci/drivers/ipw2200/*/rtap_iface
  endif #CONFIG_WIRELESS_EXT
  
@@ -29,7 +29,7 @@
  # Sonics Silicon Backplane
  export CONFIG_SSB_SPROM=y
  
-@@ -351,7 +352,7 @@ endif #CONFIG_PCMCIA
+@@ -359,7 +360,7 @@ endif #CONFIG_PCMCIA
  # export CONFIG_SSB_DEBUG=y
  export CONFIG_SSB_DRIVER_PCICORE=y
  export CONFIG_B43_SSB=y
@@ -38,7 +38,7 @@
  
  export CONFIG_BCMA=m
  export CONFIG_BCMA_BLOCKIO=y
-@@ -562,7 +563,7 @@ endif #CONFIG_SPI_MASTER end of SPI driv
+@@ -574,7 +575,7 @@ endif #CONFIG_SPI_MASTER end of SPI driv
  
  ifdef CONFIG_MMC
  
index e5395e0..fd05385 100644 (file)
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -29,7 +29,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
+@@ -44,7 +44,6 @@ obj-$(CONFIG_COMPAT_WIRELESS_MODULES) +=
  
  obj-$(CONFIG_COMPAT_NET_USB_MODULES) += drivers/net/usb/
  
@@ -10,7 +10,7 @@
  ifeq ($(CONFIG_STAGING_EXCLUDE_BUILD),)
 --- a/config.mk
 +++ b/config.mk
-@@ -354,12 +354,12 @@ export CONFIG_SSB_DRIVER_PCICORE=y
+@@ -362,12 +362,12 @@ export CONFIG_SSB_DRIVER_PCICORE=y
  export CONFIG_B43_SSB=y
  endif #__CONFIG_SSB
  
index 99cfe73..f5bd351 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -237,7 +237,7 @@ $(warning "WARNING: CONFIG_CFG80211_WEXT
+@@ -240,7 +240,7 @@ $(warning "WARNING: CONFIG_CFG80211_WEXT
  endif #CONFIG_WIRELESS_EXT
  
  ifdef CONFIG_STAGING
@@ -9,7 +9,7 @@
  endif #CONFIG_STAGING
  
  # mac80211 test driver
-@@ -391,15 +391,15 @@ endif #CONFIG_CRC_ITU_T
+@@ -399,15 +399,15 @@ endif #CONFIG_CRC_ITU_T
  export CONFIG_MWL8K=m
  
  # Ethernet drivers go here
 +# export CONFIG_ATL1=m
 +# export CONFIG_ATL2=m
 +# export CONFIG_ATL1E=m
- ifdef CONFIG_COMPAT_KERNEL_2_6_27
+ ifdef CONFIG_COMPAT_KERNEL_2_6_28
+-export CONFIG_ATL1C=m
+-export CONFIG_ALX=n
++# export CONFIG_ATL1C=m
++# export CONFIG_ALX=n
+ else #CONFIG_COMPAT_KERNEL_2_6_28
 -export CONFIG_ATL1C=n
 -export CONFIG_ALX=m
 +# export CONFIG_ATL1C=n
 +# export CONFIG_ALX=m
- else #CONFIG_COMPAT_KERNEL_2_6_27
--export CONFIG_ATL1C=n
--export CONFIG_ALX=m
-+# export CONFIG_ATL1C=n
-+# export CONFIG_ALX=m
- endif #CONFIG_COMPAT_KERNEL_2_6_27
+ endif #CONFIG_COMPAT_KERNEL_2_6_28
  
  ifdef CONFIG_WIRELESS_EXT
-@@ -460,21 +460,21 @@ endif #CONFIG_COMPAT_KERNEL_2_6_29
+@@ -468,21 +468,21 @@ endif #CONFIG_COMPAT_KERNEL_2_6_29
  # Note: this depends on CONFIG_USB_NET_RNDIS_HOST and CONFIG_USB_NET_CDCETHER
  # it also requires new RNDIS_HOST and CDC_ETHER modules which we add
  ifdef CONFIG_COMPAT_KERNEL_2_6_29
index 097ceb4..2f2cea8 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -175,7 +175,7 @@ export CONFIG_MAC80211_LEDS=y
+@@ -176,7 +176,7 @@ export CONFIG_MAC80211_LEDS=y
  endif #CONFIG_LEDS_TRIGGERS
  
  # enable mesh networking too
index 07a7abb..9d94b8d 100644 (file)
@@ -9,7 +9,7 @@
  # export CONFIG_SSB=m
  else
  include $(KLIB_BUILD)/.config
-@@ -289,7 +289,7 @@ export CONFIG_B43=m
+@@ -297,7 +297,7 @@ export CONFIG_B43=m
  export CONFIG_B43_HWRNG=y
  export CONFIG_B43_PCI_AUTOSELECT=y
  ifdef CONFIG_PCMCIA
index 1d7c59b..58c3ba9 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -564,7 +564,7 @@ endif #CONFIG_SPI_MASTER end of SPI driv
+@@ -576,7 +576,7 @@ endif #CONFIG_SPI_MASTER end of SPI driv
  ifdef CONFIG_MMC
  
  # export CONFIG_SSB_SDIOHOST=y
index 72a5778..10ee794 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -295,8 +295,8 @@ ifdef CONFIG_MAC80211_LEDS
+@@ -303,8 +303,8 @@ ifdef CONFIG_MAC80211_LEDS
  export CONFIG_B43_LEDS=y
  endif #CONFIG_MAC80211_LEDS
  export CONFIG_B43_PHY_LP=y
index 629c34b..bd27913 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -370,7 +370,7 @@ export CONFIG_RTL8180=m
+@@ -378,7 +378,7 @@ export CONFIG_RTL8180=m
  
  export CONFIG_ADM8211=m
  
@@ -9,7 +9,7 @@
  export CONFIG_RT2400PCI=m
  export CONFIG_RT2500PCI=m
  ifdef CONFIG_CRC_CCITT
-@@ -512,7 +512,7 @@ export CONFIG_RT2800USB_RT35XX=y
+@@ -524,7 +524,7 @@ export CONFIG_RT2800USB_RT35XX=y
  export CONFIG_RT2800USB_RT53XX=y
  export CONFIG_RT2800USB_UNKNOWN=y
  endif #CONFIG_CRC_CCITT
index 70d1a4c..19bbb2a 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -167,7 +167,7 @@ export CONFIG_MAC80211_RC_DEFAULT_MINSTR
+@@ -168,7 +168,7 @@ export CONFIG_MAC80211_RC_DEFAULT_MINSTR
  # This is the one used by our compat-wireless net/mac80211/rate.c
  # in case you have and old kernel which is overriding this to pid.
  export CONFIG_COMPAT_MAC80211_RC_DEFAULT=minstrel_ht
index c33e1d0..933aec5 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -261,7 +261,7 @@ export CONFIG_ATH9K_COMMON=m
+@@ -264,7 +264,7 @@ export CONFIG_ATH9K_COMMON=m
  # as default once we get minstrel properly tested and blessed by
  # our systems engineering team. CCK rates also need to be used
  # for long range considerations.
index c83874b..581fbfc 100644 (file)
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -268,7 +268,7 @@ export CONFIG_ATH9K_BTCOEX_SUPPORT=y
+@@ -276,7 +276,7 @@ endif #CONFIG_COMPAT_KERNEL_2_6_27
  # PCI Drivers
  ifdef CONFIG_PCI
  
index f5505d9..56721f3 100644 (file)
@@ -1,8 +1,8 @@
 --- a/compat/Makefile
 +++ b/compat/Makefile
-@@ -38,8 +38,6 @@ compat-$(CONFIG_COMPAT_KERNEL_3_2) += co
compat-$(CONFIG_COMPAT_KERNEL_3_3) += compat-3.3.o
- compat-$(CONFIG_COMPAT_KERNEL_3_5) += compat-3.5.o
+@@ -43,8 +43,6 @@ compat-$(CONFIG_COMPAT_KERNEL_3_3) += \
      flow_dissector.o
+ compat-$(CONFIG_COMPAT_KERNEL_3_4) += compat-3.4.o
  
 -compat-$(CONFIG_COMPAT_CORDIC) += cordic.o
 -compat-$(CONFIG_COMPAT_CRC8) += crc8.o
index c603e87..36645fc 100644 (file)
@@ -1,11 +1,11 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -263,7 +263,7 @@ export CONFIG_ATH9K_COMMON=m
+@@ -266,7 +266,7 @@ export CONFIG_ATH9K_COMMON=m
  # for long range considerations.
  # export CONFIG_COMPAT_ATH9K_RATE_CONTROL=y
  
 -export CONFIG_ATH9K_BTCOEX_SUPPORT=y
 +# export CONFIG_ATH9K_BTCOEX_SUPPORT=y
  
- # PCI Drivers
- ifdef CONFIG_PCI
+ ifndef CONFIG_COMPAT_KERNEL_2_6_27
+ export CONFIG_ATH6KL=m
index 4fd5011..602e82d 100644 (file)
@@ -1,20 +1,17 @@
 --- a/compat/Makefile
 +++ b/compat/Makefile
-@@ -1,10 +1,13 @@
+@@ -1,7 +1,10 @@
  obj-m += compat.o
  #compat-objs :=
  
 -obj-$(CONFIG_COMPAT_FIRMWARE_CLASS) += compat_firmware_class.o
- compat-y += main.o
 +ifdef CONFIG_COMPAT_FIRMWARE_CLASS
 +  compat-y += compat_firmware_class.o
 +endif
 +
- # Compat kernel compatibility code
compat-$(CONFIG_COMPAT_KERNEL_2_6_14) += compat-2.6.14.o
- compat-$(CONFIG_COMPAT_KERNEL_2_6_18) += compat-2.6.18.o
+ obj-$(CONFIG_COMPAT_NET_SCH_CODEL) += sch_codel.o
obj-$(CONFIG_COMPAT_NET_SCH_FQ_CODEL) += sch_fq_codel.o
 --- a/compat/compat_firmware_class.c
 +++ b/compat/compat_firmware_class.c
 @@ -741,19 +741,16 @@ compat_request_firmware_nowait(
  EXPORT_SYMBOL_GPL(request_firmware_nowait);
 --- a/compat/main.c
 +++ b/compat/main.c
-@@ -37,6 +37,17 @@ void compat_dependency_symbol(void)
- }
+@@ -47,6 +47,17 @@ void compat_dependency_symbol(void)
  EXPORT_SYMBOL_GPL(compat_dependency_symbol);
  
 +#if defined(CONFIG_FW_LOADER) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
 +int __init firmware_class_init(void);
 +void __exit firmware_class_exit(void);
 +
  static int __init compat_init(void)
  {
-       /* pm-qos for kernels <= 2.6.24, this is a no-op on newer kernels */
-@@ -51,7 +62,8 @@ static int __init compat_init(void)
-              COMPAT_BASE_TREE " " COMPAT_BASE_TREE_VERSION
-              "\n");
+       compat_pm_qos_power_init();
+@@ -63,7 +74,8 @@ static int __init compat_init(void)
+       printk(KERN_INFO "compat.git: "
+              COMPAT_BASE_TREE "\n");
  
 -        return 0;
 +      firmware_class_init();
@@ -69,7 +66,7 @@
  }
  module_init(compat_init);
  
-@@ -60,7 +72,8 @@ static void __exit compat_exit(void)
+@@ -72,7 +84,8 @@ static void __exit compat_exit(void)
        compat_pm_qos_power_deinit();
        compat_system_workqueue_destroy();
  
index 7d51e9a..6ddfc7d 100644 (file)
@@ -1,8 +1,8 @@
 --- a/include/linux/compat-3.4.h
 +++ b/include/linux/compat-3.4.h
-@@ -62,6 +62,19 @@ static inline void eth_hw_addr_random(st
- #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) */
- #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12)) */
+@@ -77,6 +77,19 @@ static inline void eth_hw_addr_random(st
+       module_driver(__pci_driver, pci_register_driver, \
+                      pci_unregister_driver)
  
 +/* source include/linux/pci.h */
 +/**
diff --git a/package/mac80211/patches/070-disable_codel.patch b/package/mac80211/patches/070-disable_codel.patch
new file mode 100644 (file)
index 0000000..1ec7409
--- /dev/null
@@ -0,0 +1,19 @@
+--- a/compat/scripts/gen-compat-config.sh
++++ b/compat/scripts/gen-compat-config.sh
+@@ -62,16 +62,3 @@ fi
+ if [[ ${CONFIG_COMPAT_KERNEL_2_6_36} = "y" ]]; then
+       echo "export CONFIG_COMPAT_KFIFO=y"
+ fi
+-
+-if [[ ${CONFIG_COMPAT_KERNEL_3_5} = "y" ]]; then
+-      # We don't have 2.6.24 backport support yet for Codel / FQ CoDel
+-      # For those who want to try this is what is required that I can tell
+-      # so far:
+-      #  * struct Qdisc_ops
+-      #       - init and change callback ops use a different argument dataype
+-      #       - you need to parse data received from userspace differently
+-      if [[ ${CONFIG_COMPAT_KERNEL_2_6_25} != "y" ]]; then
+-              echo "export CONFIG_COMPAT_NET_SCH_CODEL=m"
+-              echo "export CONFIG_COMPAT_NET_SCH_FQ_CODEL=m"
+-      fi
+-fi
diff --git a/package/mac80211/patches/071-add_codel_ifdef.patch b/package/mac80211/patches/071-add_codel_ifdef.patch
new file mode 100644 (file)
index 0000000..b69fdd7
--- /dev/null
@@ -0,0 +1,19 @@
+--- a/include/linux/compat-3.5.h
++++ b/include/linux/compat-3.5.h
+@@ -10,6 +10,8 @@
+ #include <linux/pkt_sched.h>
++#ifndef TCA_CODEL_MAX
++
+ /*
+  * This backports:
+  *
+@@ -107,6 +109,7 @@ struct tc_fq_codel_xstats {
+       };
+ };
++#endif /* TCA_CODEL_MAX */
+ /* Backports tty_lock: Localise the lock */
+ #define tty_lock(__tty) tty_lock()
index eee924c..6108989 100644 (file)
@@ -33,7 +33,7 @@
  #endif
 --- a/config.mk
 +++ b/config.mk
-@@ -498,7 +498,7 @@ endif #CONFIG_COMPAT_KERNEL_2_6_29
+@@ -506,7 +506,7 @@ endif #CONFIG_COMPAT_KERNEL_2_6_29
  # This activates a threading fix for usb urb.
  # this is mainline commit: b3e670443b7fb8a2d29831b62b44a039c283e351
  # This fix will be included in some stable releases.
index ffde0f8..8014707 100644 (file)
@@ -1,33 +1,3 @@
---- a/drivers/net/wireless/ath/ath5k/ani.c
-+++ b/drivers/net/wireless/ath/ath5k/ani.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "ath5k.h"
---- a/drivers/net/wireless/ath/ath5k/attach.c
-+++ b/drivers/net/wireless/ath/ath5k/attach.c
-@@ -20,6 +20,7 @@
- * Attach/Detach Functions and helpers *
- \*************************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/pci.h>
---- a/drivers/net/wireless/ath/ath5k/base.c
-+++ b/drivers/net/wireless/ath/ath5k/base.c
-@@ -40,6 +40,7 @@
-  *
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/module.h>
 --- a/drivers/net/wireless/ath/ath5k/debug.c
 +++ b/drivers/net/wireless/ath/ath5k/debug.c
 @@ -58,6 +58,7 @@
  #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  
  #include <linux/export.h>
---- a/drivers/net/wireless/ath/ath5k/desc.c
-+++ b/drivers/net/wireless/ath/ath5k/desc.c
-@@ -21,6 +21,7 @@
-  Hardware Descriptor Functions
- \******************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "ath5k.h"
---- a/drivers/net/wireless/ath/ath5k/dma.c
-+++ b/drivers/net/wireless/ath/ath5k/dma.c
-@@ -29,6 +29,7 @@
-  * status registers (ISR).
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "ath5k.h"
---- a/drivers/net/wireless/ath/ath5k/eeprom.c
-+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
-@@ -21,6 +21,7 @@
- * EEPROM access functions and helpers *
- \*************************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/slab.h>
---- a/drivers/net/wireless/ath/ath5k/initvals.c
-+++ b/drivers/net/wireless/ath/ath5k/initvals.c
-@@ -19,6 +19,7 @@
-  *
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "ath5k.h"
---- a/drivers/net/wireless/ath/ath5k/led.c
-+++ b/drivers/net/wireless/ath/ath5k/led.c
-@@ -39,6 +39,7 @@
-  *
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/pci.h>
---- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
-+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
-@@ -41,6 +41,7 @@
-  *
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <net/mac80211.h>
---- a/drivers/net/wireless/ath/ath5k/pci.c
-+++ b/drivers/net/wireless/ath/ath5k/pci.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/nl80211.h>
---- a/drivers/net/wireless/ath/ath5k/phy.c
-+++ b/drivers/net/wireless/ath/ath5k/phy.c
-@@ -22,6 +22,7 @@
- * PHY related functions *
- \***********************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/delay.h>
---- a/drivers/net/wireless/ath/ath5k/qcu.c
-+++ b/drivers/net/wireless/ath/ath5k/qcu.c
-@@ -20,6 +20,7 @@
- Queue Control Unit, DCF Control Unit Functions
- \********************************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "ath5k.h"
---- a/drivers/net/wireless/ath/ath5k/reset.c
-+++ b/drivers/net/wireless/ath/ath5k/reset.c
-@@ -23,6 +23,7 @@
-   Reset function and helpers
- \****************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <asm/unaligned.h>
---- a/drivers/net/wireless/ath/ath5k/sysfs.c
-+++ b/drivers/net/wireless/ath/ath5k/sysfs.c
-@@ -1,3 +1,4 @@
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/device.h>
---- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
-+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
-@@ -15,6 +15,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/moduleparam.h>
---- a/drivers/net/wireless/ath/ath6kl/init.c
-+++ b/drivers/net/wireless/ath/ath6kl/init.c
-@@ -16,6 +16,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/moduleparam.h>
---- a/drivers/net/wireless/ath/ath6kl/main.c
-+++ b/drivers/net/wireless/ath/ath6kl/main.c
-@@ -15,6 +15,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "core.h"
---- a/drivers/net/wireless/ath/ath6kl/txrx.c
-+++ b/drivers/net/wireless/ath/ath6kl/txrx.c
-@@ -15,6 +15,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "core.h"
---- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
-+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "htc.h"
---- a/drivers/net/wireless/ath/ath9k/htc_hst.c
-+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include "htc.h"
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/dma-mapping.h>
---- a/drivers/net/wireless/ath/ath9k/pci.c
-+++ b/drivers/net/wireless/ath/ath9k/pci.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/nl80211.h>
---- a/drivers/net/wireless/ath/main.c
-+++ b/drivers/net/wireless/ath/main.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/kernel.h>
---- a/drivers/net/wireless/ath/regd.c
-+++ b/drivers/net/wireless/ath/regd.c
-@@ -14,6 +14,7 @@
-  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-  */
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/kernel.h>
---- a/drivers/net/wireless/iwlwifi/iwl-agn.c
-+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
-@@ -27,6 +27,7 @@
-  *
-  *****************************************************************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/kernel.h>
---- a/drivers/net/wireless/iwlwifi/iwl-pci.c
-+++ b/drivers/net/wireless/iwlwifi/iwl-pci.c
-@@ -61,6 +61,7 @@
-  *
-  *****************************************************************************/
-+#undef pr_fmt
- #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
- #include <linux/module.h>
index eb5547b..9e08a08 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/initvals.c
 +++ b/drivers/net/wireless/ath/ath5k/initvals.c
-@@ -63,8 +63,14 @@ static const struct ath5k_ini ar5210_ini
+@@ -65,8 +65,14 @@ static const struct ath5k_ini ar5210_ini
        { AR5K_IMR,             0 },
        { AR5K_IER,             AR5K_IER_DISABLE },
        { AR5K_BSR,             0, AR5K_INI_READ },
@@ -17,7 +17,7 @@
        { AR5K_RXNOFRM,         8 },
 --- a/drivers/net/wireless/ath/ath5k/dma.c
 +++ b/drivers/net/wireless/ath/ath5k/dma.c
-@@ -861,10 +861,18 @@ ath5k_hw_dma_init(struct ath5k_hw *ah)
+@@ -863,10 +863,18 @@ ath5k_hw_dma_init(struct ath5k_hw *ah)
         * guess we can tweak it and see how it goes ;-)
         */
        if (ah->ah_version != AR5K_AR5210) {
index fab677f..245a5db 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/base.c
 +++ b/drivers/net/wireless/ath/ath5k/base.c
-@@ -2416,6 +2416,22 @@ ath5k_tx_complete_poll_work(struct work_
+@@ -2417,6 +2417,22 @@ ath5k_tx_complete_poll_work(struct work_
  * Initialization routines *
  \*************************/
  
@@ -23,7 +23,7 @@
  int __devinit
  ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
  {
-@@ -2437,6 +2453,9 @@ ath5k_init_ah(struct ath5k_hw *ah, const
+@@ -2438,6 +2454,9 @@ ath5k_init_ah(struct ath5k_hw *ah, const
                BIT(NL80211_IFTYPE_ADHOC) |
                BIT(NL80211_IFTYPE_MESH_POINT);
  
        /* SW support for IBSS_RSN is provided by mac80211 */
        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
  
---- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-@@ -618,19 +618,10 @@ static void ar5008_hw_init_bb(struct ath
-       u32 synthDelay;
-       synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
--      if (IS_CHAN_B(chan))
--              synthDelay = (4 * synthDelay) / 22;
--      else
--              synthDelay /= 10;
--
--      if (IS_CHAN_HALF_RATE(chan))
--              synthDelay *= 2;
--      else if (IS_CHAN_QUARTER_RATE(chan))
--              synthDelay *= 4;
-       REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
--      udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+      ath9k_hw_synth_delay(ah, chan, synthDelay);
- }
- static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
-@@ -868,7 +859,7 @@ static int ar5008_hw_process_ini(struct 
-       ar5008_hw_set_channel_regs(ah, chan);
-       ar5008_hw_init_chain_masks(ah);
-       ath9k_olc_init(ah);
--      ath9k_hw_apply_txpower(ah, chan);
-+      ath9k_hw_apply_txpower(ah, chan, false);
-       /* Write analog registers */
-       if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-@@ -948,12 +939,8 @@ static bool ar5008_hw_rfbus_req(struct a
- static void ar5008_hw_rfbus_done(struct ath_hw *ah)
- {
-       u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
--      if (IS_CHAN_B(ah->curchan))
--              synthDelay = (4 * synthDelay) / 22;
--      else
--              synthDelay /= 10;
--      udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+      ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
-       REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
- }
---- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-@@ -1000,10 +1000,12 @@ static bool ar9003_hw_init_cal(struct at
-       if (mci && IS_CHAN_2GHZ(chan) && run_agc_cal)
-               ar9003_mci_init_cal_req(ah, &is_reusable);
--      txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
--      REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
--      udelay(5);
--      REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-+      if (!(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))) {
-+              txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
-+              REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-+              udelay(5);
-+              REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-+      }
- skip_tx_iqcal:
-       if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -4281,18 +4281,10 @@ static int ar9003_hw_tx_power_regwrite(s
- #undef POW_SM
- }
--static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
--                                            u8 *targetPowerValT2)
-+static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
-+                                             u8 *targetPowerValT2,
-+                                             bool is2GHz)
- {
--      /* XXX: hard code for now, need to get from eeprom struct */
--      u8 ht40PowerIncForPdadc = 0;
--      bool is2GHz = false;
--      unsigned int i = 0;
--      struct ath_common *common = ath9k_hw_common(ah);
--
--      if (freq < 4000)
--              is2GHz = true;
--
-       targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
-           ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
-                                        is2GHz);
-@@ -4305,6 +4297,11 @@ static void ar9003_hw_set_target_power_e
-       targetPowerValT2[ALL_TARGET_LEGACY_54] =
-           ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
-                                        is2GHz);
-+}
-+
-+static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
-+                                          u8 *targetPowerValT2)
-+{
-       targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
-           ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
-                                            freq);
-@@ -4314,6 +4311,11 @@ static void ar9003_hw_set_target_power_e
-           ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
-       targetPowerValT2[ALL_TARGET_LEGACY_11S] =
-           ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
-+}
-+
-+static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
-+                                           u8 *targetPowerValT2, bool is2GHz)
-+{
-       targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
-           ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
-                                             is2GHz);
-@@ -4356,6 +4358,16 @@ static void ar9003_hw_set_target_power_e
-       targetPowerValT2[ALL_TARGET_HT20_23] =
-           ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
-                                             is2GHz);
-+}
-+
-+static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
-+                                                 u16 freq,
-+                                                 u8 *targetPowerValT2,
-+                                                 bool is2GHz)
-+{
-+      /* XXX: hard code for now, need to get from eeprom struct */
-+      u8 ht40PowerIncForPdadc = 0;
-+
-       targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
-           ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
-                                             is2GHz) + ht40PowerIncForPdadc;
-@@ -4399,6 +4411,26 @@ static void ar9003_hw_set_target_power_e
-       targetPowerValT2[ALL_TARGET_HT40_23] =
-           ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
-                                             is2GHz) + ht40PowerIncForPdadc;
-+}
-+
-+static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
-+                                            struct ath9k_channel *chan,
-+                                            u8 *targetPowerValT2)
-+{
-+      bool is2GHz = IS_CHAN_2GHZ(chan);
-+      unsigned int i = 0;
-+      struct ath_common *common = ath9k_hw_common(ah);
-+      u16 freq = chan->channel;
-+
-+      if (is2GHz)
-+              ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
-+
-+      ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
-+      ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
-+
-+      if (IS_CHAN_HT40(chan))
-+              ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
-+                                               is2GHz);
-       for (i = 0; i < ar9300RateSize; i++) {
-               ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
-@@ -4778,9 +4810,6 @@ static void ar9003_hw_set_power_per_rate
-       scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
-                                               antenna_reduction);
--      /*
--       * Get target powers from EEPROM - our baseline for TX Power
--       */
-       if (is2ghz) {
-               /* Setup for CTL modes */
-               /* CTL_11B, CTL_11G, CTL_2GHT20 */
-@@ -4952,7 +4981,12 @@ static void ath9k_hw_ar9300_set_txpower(
-       unsigned int i = 0, paprd_scale_factor = 0;
-       u8 pwr_idx, min_pwridx = 0;
--      ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
-+      memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
-+
-+      /*
-+       * Get target powers from EEPROM - our baseline for TX Power
-+       */
-+      ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
-       if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
-               if (IS_CHAN_2GHZ(chan))
---- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
-@@ -54,7 +54,7 @@ void ar9003_paprd_enable(struct ath_hw *
-       if (val) {
-               ah->paprd_table_write_done = true;
--              ath9k_hw_apply_txpower(ah, chan);
-+              ath9k_hw_apply_txpower(ah, chan, false);
-       }
-       REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-@@ -373,7 +373,7 @@ static void ar9003_hw_spur_ofdm_work(str
-                       else
-                               spur_subchannel_sd = 0;
--                      spur_freq_sd = (freq_offset << 9) / 11;
-+                      spur_freq_sd = ((freq_offset + 10) << 9) / 11;
-               } else {
-                       if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
-@@ -382,7 +382,7 @@ static void ar9003_hw_spur_ofdm_work(str
-                       else
-                               spur_subchannel_sd = 1;
--                      spur_freq_sd = (freq_offset << 9) / 11;
-+                      spur_freq_sd = ((freq_offset - 10) << 9) / 11;
-               }
-@@ -526,22 +526,10 @@ static void ar9003_hw_init_bb(struct ath
-        * Value is in 100ns increments.
-        */
-       synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
--      if (IS_CHAN_B(chan))
--              synthDelay = (4 * synthDelay) / 22;
--      else
--              synthDelay /= 10;
-       /* Activate the PHY (includes baseband activate + synthesizer on) */
-       REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
--
--      /*
--       * There is an issue if the AP starts the calibration before
--       * the base band timeout completes.  This could result in the
--       * rx_clear false triggering.  As a workaround we add delay an
--       * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
--       * does not happen.
--       */
--      udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+      ath9k_hw_synth_delay(ah, chan, synthDelay);
- }
- static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
-@@ -692,7 +680,7 @@ static int ar9003_hw_process_ini(struct 
-       ar9003_hw_override_ini(ah);
-       ar9003_hw_set_channel_regs(ah, chan);
-       ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
--      ath9k_hw_apply_txpower(ah, chan);
-+      ath9k_hw_apply_txpower(ah, chan, false);
-       if (AR_SREV_9462(ah)) {
-               if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
-@@ -723,6 +711,14 @@ static void ar9003_hw_set_rfmode(struct 
-       if (IS_CHAN_A_FAST_CLOCK(ah, chan))
-               rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
-+      if (IS_CHAN_QUARTER_RATE(chan))
-+              rfMode |= AR_PHY_MODE_QUARTER;
-+      if (IS_CHAN_HALF_RATE(chan))
-+              rfMode |= AR_PHY_MODE_HALF;
-+
-+      if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
-+              REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
-+                            AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
-       REG_WRITE(ah, AR_PHY_MODE, rfMode);
- }
-@@ -793,12 +789,8 @@ static bool ar9003_hw_rfbus_req(struct a
- static void ar9003_hw_rfbus_done(struct ath_hw *ah)
- {
-       u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
--      if (IS_CHAN_B(ah->curchan))
--              synthDelay = (4 * synthDelay) / 22;
--      else
--              synthDelay /= 10;
--      udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+      ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
-       REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
- }
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
-@@ -468,6 +468,9 @@
- #define AR_PHY_ADDAC_PARA_CTL    (AR_SM_BASE + 0x150)
- #define AR_PHY_XPA_CFG           (AR_SM_BASE + 0x158)
-+#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW  3
-+#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S    0
-+
- #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A           0x0001FC00
- #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S         10
- #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A                       0x3FF
---- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
-+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
-@@ -798,6 +798,8 @@ static void ath9k_hw_ar9287_set_txpower(
-                       regulatory->max_power_level = ratesArray[i];
-       }
-+      ath9k_hw_update_regulatory_maxpower(ah);
-+
-       if (test)
-               return;
---- a/drivers/net/wireless/ath/ath9k/hw.c
-+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -191,6 +191,22 @@ bool ath9k_hw_wait(struct ath_hw *ah, u3
- }
- EXPORT_SYMBOL(ath9k_hw_wait);
-+void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
-+                        int hw_delay)
-+{
-+      if (IS_CHAN_B(chan))
-+              hw_delay = (4 * hw_delay) / 22;
-+      else
-+              hw_delay /= 10;
-+
-+      if (IS_CHAN_HALF_RATE(chan))
-+              hw_delay *= 2;
-+      else if (IS_CHAN_QUARTER_RATE(chan))
-+              hw_delay *= 4;
-+
-+      udelay(hw_delay + BASE_ACTIVATE_DELAY);
-+}
-+
- void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
-                         int column, unsigned int *writecnt)
- {
-@@ -1020,7 +1036,7 @@ void ath9k_hw_init_global_settings(struc
-       struct ath_common *common = ath9k_hw_common(ah);
-       struct ieee80211_conf *conf = &common->hw->conf;
-       const struct ath9k_channel *chan = ah->curchan;
--      int acktimeout, ctstimeout;
-+      int acktimeout, ctstimeout, ack_offset = 0;
-       int slottime;
-       int sifstime;
-       int rx_lat = 0, tx_lat = 0, eifs = 0;
-@@ -1041,6 +1057,11 @@ void ath9k_hw_init_global_settings(struc
-               rx_lat = 37;
-       tx_lat = 54;
-+      if (IS_CHAN_5GHZ(chan))
-+              sifstime = 16;
-+      else
-+              sifstime = 10;
-+
-       if (IS_CHAN_HALF_RATE(chan)) {
-               eifs = 175;
-               rx_lat *= 2;
-@@ -1048,8 +1069,9 @@ void ath9k_hw_init_global_settings(struc
-               if (IS_CHAN_A_FAST_CLOCK(ah, chan))
-                   tx_lat += 11;
-+              sifstime *= 2;
-+              ack_offset = 16;
-               slottime = 13;
--              sifstime = 32;
-       } else if (IS_CHAN_QUARTER_RATE(chan)) {
-               eifs = 340;
-               rx_lat = (rx_lat * 4) - 1;
-@@ -1057,8 +1079,9 @@ void ath9k_hw_init_global_settings(struc
-               if (IS_CHAN_A_FAST_CLOCK(ah, chan))
-                   tx_lat += 22;
-+              sifstime *= 4;
-+              ack_offset = 32;
-               slottime = 21;
--              sifstime = 64;
-       } else {
-               if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
-                       eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
-@@ -1072,14 +1095,10 @@ void ath9k_hw_init_global_settings(struc
-               tx_lat = MS(reg, AR_USEC_TX_LAT);
-               slottime = ah->slottime;
--              if (IS_CHAN_5GHZ(chan))
--                      sifstime = 16;
--              else
--                      sifstime = 10;
-       }
-       /* As defined by IEEE 802.11-2007 17.3.8.6 */
--      acktimeout = slottime + sifstime + 3 * ah->coverage_class;
-+      acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
-       ctstimeout = acktimeout;
-       /*
-@@ -1089,7 +1108,8 @@ void ath9k_hw_init_global_settings(struc
-        * BA frames in some implementations, but it has been found to fix ACK
-        * timeout issues in other cases as well.
-        */
--      if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) {
-+      if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
-+          !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
-               acktimeout += 64 - sifstime - ah->slottime;
-               ctstimeout += 48 - sifstime - ah->slottime;
-       }
-@@ -1469,6 +1489,10 @@ static bool ath9k_hw_channel_change(stru
-                                                   CHANNEL_5GHZ));
-       mode_diff = (chan->chanmode != ah->curchan->chanmode);
-+      if ((ah->curchan->channelFlags | chan->channelFlags) &
-+          (CHANNEL_HALF | CHANNEL_QUARTER))
-+              return false;
-+
-       for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
-               if (ath9k_hw_numtxpending(ah, qnum)) {
-                       ath_dbg(common, QUEUE,
-@@ -1502,7 +1526,7 @@ static bool ath9k_hw_channel_change(stru
-               return false;
-       }
-       ath9k_hw_set_clockrate(ah);
--      ath9k_hw_apply_txpower(ah, chan);
-+      ath9k_hw_apply_txpower(ah, chan, false);
-       ath9k_hw_rfbus_done(ah);
-       if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
-@@ -2773,7 +2797,8 @@ static int get_antenna_gain(struct ath_h
-       return ah->eep_ops->get_eeprom(ah, gain_param);
- }
--void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
-+void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
-+                          bool test)
- {
-       struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
-       struct ieee80211_channel *channel;
-@@ -2794,7 +2819,7 @@ void ath9k_hw_apply_txpower(struct ath_h
-       ah->eep_ops->set_txpower(ah, chan,
-                                ath9k_regd_get_ctl(reg, chan),
--                               ant_reduction, new_pwr, false);
-+                               ant_reduction, new_pwr, test);
- }
- void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
-@@ -2807,7 +2832,7 @@ void ath9k_hw_set_txpowerlimit(struct at
-       if (test)
-               channel->max_power = MAX_RATE_POWER / 2;
--      ath9k_hw_apply_txpower(ah, chan);
-+      ath9k_hw_apply_txpower(ah, chan, test);
-       if (test)
-               channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
---- a/drivers/net/wireless/ath/ath9k/hw.h
-+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -923,6 +923,8 @@ void ath9k_hw_set_gpio(struct ath_hw *ah
- void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
- /* General Operation */
-+void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
-+                        int hw_delay);
- bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
- void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
-                         int column, unsigned int *writecnt);
-@@ -982,7 +984,8 @@ void ath9k_hw_name(struct ath_hw *ah, ch
- /* PHY */
- void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
-                                  u32 *coef_mantissa, u32 *coef_exponent);
--void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
-+void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
-+                          bool test);
- /*
-  * Code Specific to AR5008, AR9001 or AR9002,
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -647,6 +647,24 @@ void ath9k_reload_chainmask_settings(str
-               setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
- }
-+static const struct ieee80211_iface_limit if_limits[] = {
-+      { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) |
-+                               BIT(NL80211_IFTYPE_P2P_CLIENT) |
-+                               BIT(NL80211_IFTYPE_WDS) },
-+      { .max = 8,     .types =
-+#ifdef CONFIG_MAC80211_MESH
-+                               BIT(NL80211_IFTYPE_MESH_POINT) |
-+#endif
-+                               BIT(NL80211_IFTYPE_AP) |
-+                               BIT(NL80211_IFTYPE_P2P_GO) },
-+};
-+
-+static const struct ieee80211_iface_combination if_comb = {
-+      .limits = if_limits,
-+      .n_limits = ARRAY_SIZE(if_limits),
-+      .max_interfaces = 2048,
-+      .num_different_channels = 1,
-+};
- void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
- {
-@@ -676,6 +694,9 @@ void ath9k_set_hw_capab(struct ath_softc
-               BIT(NL80211_IFTYPE_ADHOC) |
-               BIT(NL80211_IFTYPE_MESH_POINT);
-+      hw->wiphy->iface_combinations = &if_comb;
-+      hw->wiphy->n_iface_combinations = 1;
-+
-       if (AR_SREV_5416(sc->sc_ah))
-               hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
---- a/drivers/net/wireless/ath/ath9k/mac.c
-+++ b/drivers/net/wireless/ath/ath9k/mac.c
-@@ -133,8 +133,16 @@ EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel
- void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
- {
-+      int maxdelay = 1000;
-       int i, q;
-+      if (ah->curchan) {
-+              if (IS_CHAN_HALF_RATE(ah->curchan))
-+                      maxdelay *= 2;
-+              else if (IS_CHAN_QUARTER_RATE(ah->curchan))
-+                      maxdelay *= 4;
-+      }
-+
-       REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
-       REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
-@@ -142,7 +150,7 @@ void ath9k_hw_abort_tx_dma(struct ath_hw
-       REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
-       for (q = 0; q < AR_NUM_QCU; q++) {
--              for (i = 0; i < 1000; i++) {
-+              for (i = 0; i < maxdelay; i++) {
-                       if (i)
-                               udelay(5);
 --- a/net/mac80211/agg-rx.c
 +++ b/net/mac80211/agg-rx.c
 @@ -200,6 +200,8 @@ static void ieee80211_send_addba_resp(st
                memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
        else if (sdata->vif.type == NL80211_IFTYPE_STATION)
                memcpy(mgmt->bssid, sdata->u.mgd.bssid, ETH_ALEN);
-@@ -484,6 +485,7 @@ int ieee80211_start_tx_ba_session(struct
+@@ -490,6 +491,7 @@ int ieee80211_start_tx_ba_session(struct
            sdata->vif.type != NL80211_IFTYPE_MESH_POINT &&
            sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
            sdata->vif.type != NL80211_IFTYPE_AP &&
                            TEST(TDLS_PEER_AUTH), TEST(4ADDR_EVENT),
 --- a/net/mac80211/iface.c
 +++ b/net/mac80211/iface.c
-@@ -206,8 +206,10 @@ static void ieee80211_set_default_queues
-       for (i = 0; i < IEEE80211_NUM_ACS; i++) {
-               if (local->hw.flags & IEEE80211_HW_QUEUE_CONTROL)
-                       sdata->vif.hw_queue[i] = IEEE80211_INVAL_HW_QUEUE;
--              else
-+              else if (local->hw.queues >= IEEE80211_NUM_ACS)
-                       sdata->vif.hw_queue[i] = i;
-+              else
-+                      sdata->vif.hw_queue[i] = 0;
-       }
-       sdata->vif.cab_queue = IEEE80211_INVAL_HW_QUEUE;
- }
-@@ -282,7 +284,6 @@ static int ieee80211_do_open(struct net_
+@@ -284,7 +284,6 @@ static int ieee80211_do_open(struct net_
  {
        struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);
        struct ieee80211_local *local = sdata->local;
        u32 changed = 0;
        int res;
        u32 hw_reconf_flags = 0;
-@@ -428,28 +429,6 @@ static int ieee80211_do_open(struct net_
+@@ -430,28 +429,6 @@ static int ieee80211_do_open(struct net_
  
        set_bit(SDATA_STATE_RUNNING, &sdata->state);
  
        /*
         * set_multicast_list will be invoked by the networking core
         * which will check whether any increments here were done in
-@@ -846,6 +825,72 @@ static void ieee80211_if_setup(struct ne
+@@ -848,6 +825,72 @@ static void ieee80211_if_setup(struct ne
        dev->destructor = free_netdev;
  }
  
  static void ieee80211_iface_work(struct work_struct *work)
  {
        struct ieee80211_sub_if_data *sdata =
-@@ -950,6 +995,9 @@ static void ieee80211_iface_work(struct 
+@@ -952,6 +995,9 @@ static void ieee80211_iface_work(struct 
                                break;
                        ieee80211_mesh_rx_queued_mgmt(sdata, skb);
                        break;
                        break;
 --- a/net/mac80211/rx.c
 +++ b/net/mac80211/rx.c
-@@ -2283,6 +2283,7 @@ ieee80211_rx_h_action(struct ieee80211_r
+@@ -2284,6 +2284,7 @@ ieee80211_rx_h_action(struct ieee80211_r
                    sdata->vif.type != NL80211_IFTYPE_MESH_POINT &&
                    sdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
                    sdata->vif.type != NL80211_IFTYPE_AP &&
                    sdata->vif.type != NL80211_IFTYPE_ADHOC)
                        break;
  
-@@ -2497,14 +2498,15 @@ ieee80211_rx_h_mgmt(struct ieee80211_rx_
+@@ -2498,14 +2499,15 @@ ieee80211_rx_h_mgmt(struct ieee80211_rx_
  
        if (!ieee80211_vif_is_mesh(&sdata->vif) &&
            sdata->vif.type != NL80211_IFTYPE_ADHOC &&
                break;
        case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
        case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
-@@ -2838,10 +2840,16 @@ static int prepare_for_handlers(struct i
+@@ -2839,10 +2841,16 @@ static int prepare_for_handlers(struct i
                }
                break;
        case NL80211_IFTYPE_WDS:
        WLAN_STA_CLEAR_PS_FILT,
        WLAN_STA_MFP,
        WLAN_STA_BLOCK_BA,
---- a/drivers/net/wireless/iwlwifi/iwl-agn.h
-+++ b/drivers/net/wireless/iwlwifi/iwl-agn.h
-@@ -425,6 +425,7 @@ void iwl_testmode_cleanup(struct iwl_pri
- #ifdef CONFIG_IWLWIFI_DEBUG
- void iwl_print_rx_config_cmd(struct iwl_priv *priv,
-                            enum iwl_rxon_context_id ctxid);
-+int iwl_alloc_traffic_mem(struct iwl_priv *priv);
- #else
- static inline void iwl_print_rx_config_cmd(struct iwl_priv *priv,
-                                          enum iwl_rxon_context_id ctxid)
-@@ -510,7 +511,6 @@ void iwl_setup_deferred_work(struct iwl_
- int iwl_send_wimax_coex(struct iwl_priv *priv);
- int iwl_send_bt_env(struct iwl_priv *priv, u8 action, u8 type);
- void iwl_debug_config(struct iwl_priv *priv);
--int iwl_alloc_traffic_mem(struct iwl_priv *priv);
- void iwl_set_hw_params(struct iwl_priv *priv);
- void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags);
- int iwl_init_drv(struct iwl_priv *priv);
---- a/drivers/net/wireless/libertas/firmware.c
-+++ b/drivers/net/wireless/libertas/firmware.c
-@@ -5,6 +5,7 @@
- #include <linux/firmware.h>
- #include <linux/firmware.h>
- #include <linux/module.h>
-+#include <linux/sched.h>
- #include "dev.h"
- #include "decl.h"
---- a/drivers/net/wireless/ath/ath9k/recv.c
-+++ b/drivers/net/wireless/ath/ath9k/recv.c
-@@ -812,6 +812,7 @@ static bool ath9k_rx_accept(struct ath_c
-       is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
-               test_bit(rx_stats->rs_keyix, common->tkip_keymap);
-       strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
-+              ieee80211_has_protected(fc) &&
-               !(rx_stats->rs_status &
-               (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
-                ATH9K_RXERR_KEYMISS));
---- a/net/mac80211/cfg.c
-+++ b/net/mac80211/cfg.c
-@@ -1005,6 +1005,9 @@ static int ieee80211_change_station(stru
-       }
-       if (params->vlan && params->vlan != sta->sdata->dev) {
-+              bool prev_4addr = false;
-+              bool new_4addr = false;
-+
-               vlansdata = IEEE80211_DEV_TO_SUB_IF(params->vlan);
-               if (vlansdata->vif.type != NL80211_IFTYPE_AP_VLAN &&
-@@ -1020,9 +1023,25 @@ static int ieee80211_change_station(stru
-                       }
-                       rcu_assign_pointer(vlansdata->u.vlan.sta, sta);
-+                      new_4addr = true;
-+              }
-+
-+              if (sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN &&
-+                  sta->sdata->u.vlan.sta) {
-+                      rcu_assign_pointer(sta->sdata->u.vlan.sta, NULL);
-+                      prev_4addr = true;
-               }
-               sta->sdata = vlansdata;
-+
-+              if (sta->sta_state == IEEE80211_STA_AUTHORIZED &&
-+                  prev_4addr != new_4addr) {
-+                      if (new_4addr)
-+                              atomic_dec(&sta->sdata->bss->num_mcast_sta);
-+                      else
-+                              atomic_inc(&sta->sdata->bss->num_mcast_sta);
-+              }
-+
-               ieee80211_send_layer2_update(sta);
-       }
---- a/net/mac80211/debugfs_netdev.c
-+++ b/net/mac80211/debugfs_netdev.c
-@@ -394,7 +394,7 @@ static ssize_t ieee80211_if_parse_uapsd_
- __IEEE80211_IF_FILE_W(uapsd_max_sp_len);
- /* AP attributes */
--IEEE80211_IF_FILE(num_sta_authorized, u.ap.num_sta_authorized, ATOMIC);
-+IEEE80211_IF_FILE(num_mcast_sta, u.ap.num_mcast_sta, ATOMIC);
- IEEE80211_IF_FILE(num_sta_ps, u.ap.num_sta_ps, ATOMIC);
- IEEE80211_IF_FILE(dtim_count, u.ap.dtim_count, DEC);
-@@ -540,7 +540,7 @@ static void add_sta_files(struct ieee802
- static void add_ap_files(struct ieee80211_sub_if_data *sdata)
- {
--      DEBUGFS_ADD(num_sta_authorized);
-+      DEBUGFS_ADD(num_mcast_sta);
-       DEBUGFS_ADD(num_sta_ps);
-       DEBUGFS_ADD(dtim_count);
-       DEBUGFS_ADD(num_buffered_multicast);
---- a/net/mac80211/ieee80211_i.h
-+++ b/net/mac80211/ieee80211_i.h
-@@ -282,7 +282,7 @@ struct ieee80211_if_ap {
-       u8 tim[sizeof(unsigned long) * BITS_TO_LONGS(IEEE80211_MAX_AID + 1)];
-       struct sk_buff_head ps_bc_buf;
-       atomic_t num_sta_ps; /* number of stations in PS mode */
--      atomic_t num_sta_authorized; /* number of authorized stations */
-+      atomic_t num_mcast_sta; /* number of stations receiving multicast */
-       int dtim_count;
-       bool dtim_bc_mc;
- };
---- a/net/mac80211/sta_info.c
-+++ b/net/mac80211/sta_info.c
-@@ -1417,15 +1417,19 @@ int sta_info_move_state(struct sta_info 
-               if (sta->sta_state == IEEE80211_STA_AUTH) {
-                       set_bit(WLAN_STA_ASSOC, &sta->_flags);
-               } else if (sta->sta_state == IEEE80211_STA_AUTHORIZED) {
--                      if (sta->sdata->vif.type == NL80211_IFTYPE_AP)
--                              atomic_dec(&sta->sdata->u.ap.num_sta_authorized);
-+                      if (sta->sdata->vif.type == NL80211_IFTYPE_AP ||
-+                          (sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN &&
-+                           !sta->sdata->u.vlan.sta))
-+                              atomic_dec(&sta->sdata->bss->num_mcast_sta);
-                       clear_bit(WLAN_STA_AUTHORIZED, &sta->_flags);
-               }
-               break;
-       case IEEE80211_STA_AUTHORIZED:
-               if (sta->sta_state == IEEE80211_STA_ASSOC) {
--                      if (sta->sdata->vif.type == NL80211_IFTYPE_AP)
--                              atomic_inc(&sta->sdata->u.ap.num_sta_authorized);
-+                      if (sta->sdata->vif.type == NL80211_IFTYPE_AP ||
-+                          (sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN &&
-+                           !sta->sdata->u.vlan.sta))
-+                              atomic_inc(&sta->sdata->bss->num_mcast_sta);
-                       set_bit(WLAN_STA_AUTHORIZED, &sta->_flags);
-               }
-               break;
---- a/net/mac80211/tx.c
-+++ b/net/mac80211/tx.c
-@@ -306,7 +306,7 @@ ieee80211_tx_h_check_assoc(struct ieee80
-               }
-       } else if (unlikely(tx->sdata->vif.type == NL80211_IFTYPE_AP &&
-                           ieee80211_is_data(hdr->frame_control) &&
--                          !atomic_read(&tx->sdata->u.ap.num_sta_authorized))) {
-+                          !atomic_read(&tx->sdata->u.ap.num_mcast_sta))) {
-               /*
-                * No associated STAs - no need to send multicast
-                * frames.
-@@ -1159,7 +1159,8 @@ ieee80211_tx_prepare(struct ieee80211_su
-               tx->sta = rcu_dereference(sdata->u.vlan.sta);
-               if (!tx->sta && sdata->dev->ieee80211_ptr->use_4addr)
-                       return TX_DROP;
--      } else if (info->flags & IEEE80211_TX_CTL_INJECTED) {
-+      } else if (info->flags & IEEE80211_TX_CTL_INJECTED ||
-+                 tx->sdata->control_port_protocol == tx->skb->protocol) {
-               tx->sta = sta_info_get_bss(sdata, hdr->addr1);
-       }
-       if (!tx->sta)
---- a/net/wireless/scan.c
-+++ b/net/wireless/scan.c
-@@ -378,7 +378,11 @@ static int cmp_bss_core(struct cfg80211_
-                              b->len_information_elements);
-       }
--      return compare_ether_addr(a->bssid, b->bssid);
-+      /*
-+       * we can't use compare_ether_addr here since we need a < > operator.
-+       * The binary return value of compare_ether_addr isn't enough
-+       */
-+      return memcmp(a->bssid, b->bssid, sizeof(a->bssid));
- }
- static int cmp_bss(struct cfg80211_bss *a,
index 270f669..10c7636 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/init.c
 +++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -39,7 +39,7 @@ int ath9k_modparam_nohwcrypt;
+@@ -40,7 +40,7 @@ int ath9k_modparam_nohwcrypt;
  module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
  MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  
index 21cb519..1854c27 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/regd.c
 +++ b/drivers/net/wireless/ath/regd.c
-@@ -199,6 +199,10 @@ ath_reg_apply_beaconing_flags(struct wip
+@@ -200,6 +200,10 @@ ath_reg_apply_beaconing_flags(struct wip
        u32 bandwidth = 0;
        int r;
  
@@ -11,7 +11,7 @@
        for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
  
                if (!wiphy->bands[band])
-@@ -258,6 +262,10 @@ ath_reg_apply_active_scan_flags(struct w
+@@ -259,6 +263,10 @@ ath_reg_apply_active_scan_flags(struct w
        u32 bandwidth = 0;
        int r;
  
@@ -22,7 +22,7 @@
        sband = wiphy->bands[IEEE80211_BAND_2GHZ];
        if (!sband)
                return;
-@@ -307,6 +315,10 @@ static void ath_reg_apply_radar_flags(st
+@@ -308,6 +316,10 @@ static void ath_reg_apply_radar_flags(st
        struct ieee80211_channel *ch;
        unsigned int i;
  
@@ -33,7 +33,7 @@
        if (!wiphy->bands[IEEE80211_BAND_5GHZ])
                return;
  
-@@ -513,6 +525,10 @@ ath_regd_init_wiphy(struct ath_regulator
+@@ -514,6 +526,10 @@ ath_regd_init_wiphy(struct ath_regulator
  {
        const struct ieee80211_regdomain *regd;
  
index 6a8d1f4..d609b55 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/regd.c
 +++ b/drivers/net/wireless/ath/regd.c
-@@ -43,7 +43,8 @@ static int __ath_regd_init(struct ath_re
+@@ -44,7 +44,8 @@ static int __ath_regd_init(struct ath_re
                                NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
  
  /* We allow IBSS on these on a case by case basis by regulatory domain */
@@ -10,7 +10,7 @@
                                NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
  #define ATH9K_5GHZ_5470_5850  REG_RULE(5470-10, 5850+10, 40, 0, 30,\
                                NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
-@@ -61,57 +62,56 @@ static int __ath_regd_init(struct ath_re
+@@ -62,57 +63,56 @@ static int __ath_regd_init(struct ath_re
  #define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \
                                ATH9K_5GHZ_5725_5850
  
index d23edd3..0a5f694 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/main.c
 +++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -1445,15 +1445,6 @@ static int ath9k_add_interface(struct ie
+@@ -1443,15 +1443,6 @@ static int ath9k_add_interface(struct ie
                }
        }
  
@@ -16,7 +16,7 @@
        ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  
        sc->nvifs++;
-@@ -1478,15 +1469,6 @@ static int ath9k_change_interface(struct
+@@ -1476,15 +1467,6 @@ static int ath9k_change_interface(struct
        mutex_lock(&sc->mutex);
        ath9k_ps_wakeup(sc);
  
@@ -34,7 +34,7 @@
                if (sc->nbcnvifs >= ATH_BCBUF) {
 --- a/drivers/net/wireless/ath/ath9k/init.c
 +++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -655,6 +655,7 @@ static const struct ieee80211_iface_limi
+@@ -656,6 +656,7 @@ static const struct ieee80211_iface_limi
  #ifdef CONFIG_MAC80211_MESH
                                 BIT(NL80211_IFTYPE_MESH_POINT) |
  #endif
index ab8d6dc..6f745fc 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
 +++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
-@@ -86,13 +86,8 @@ ath5k_add_interface(struct ieee80211_hw 
+@@ -88,13 +88,8 @@ ath5k_add_interface(struct ieee80211_hw 
                goto end;
        }
  
@@ -18,7 +18,7 @@
                goto end;
 --- a/drivers/net/wireless/ath/ath5k/base.c
 +++ b/drivers/net/wireless/ath/ath5k/base.c
-@@ -1871,7 +1871,7 @@ ath5k_beacon_send(struct ath5k_hw *ah)
+@@ -1872,7 +1872,7 @@ ath5k_beacon_send(struct ath5k_hw *ah)
        }
  
        if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
@@ -27,7 +27,7 @@
                        ah->opmode == NL80211_IFTYPE_MESH_POINT) {
                u64 tsf = ath5k_hw_get_tsf64(ah);
                u32 tsftu = TSF_TO_TU(tsf);
-@@ -1957,7 +1957,7 @@ ath5k_beacon_update_timers(struct ath5k_
+@@ -1958,7 +1958,7 @@ ath5k_beacon_update_timers(struct ath5k_
  
        intval = ah->bintval & AR5K_BEACON_PERIOD;
        if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
@@ -36,7 +36,7 @@
                intval /= ATH_BCBUF;    /* staggered multi-bss beacons */
                if (intval < 15)
                        ATH5K_WARN(ah, "intval %u is too low, min 15\n",
-@@ -2422,6 +2422,7 @@ static const struct ieee80211_iface_limi
+@@ -2423,6 +2423,7 @@ static const struct ieee80211_iface_limi
  #ifdef CONFIG_MAC80211_MESH
                                 BIT(NL80211_IFTYPE_MESH_POINT) |
  #endif
index 9055964..6f30be5 100644 (file)
@@ -1,6 +1,6 @@
 --- a/net/mac80211/main.c
 +++ b/net/mac80211/main.c
-@@ -766,17 +766,11 @@ int ieee80211_register_hw(struct ieee802
+@@ -771,17 +771,11 @@ int ieee80211_register_hw(struct ieee802
         */
        for (i = 0; i < hw->wiphy->n_iface_combinations; i++) {
                const struct ieee80211_iface_combination *c;
index b63382e..bd661c6 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/reset.c
 +++ b/drivers/net/wireless/ath/ath5k/reset.c
-@@ -1155,6 +1155,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum
+@@ -1156,6 +1156,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum
        tsf_lo = 0;
        mode = 0;
  
@@ -8,7 +8,7 @@
        /*
         * Sanity check for fast flag
         * Fast channel change only available
-@@ -1162,6 +1163,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum
+@@ -1163,6 +1164,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum
         */
        if (fast && (ah->ah_radio != AR5K_RF2413) &&
        (ah->ah_radio != AR5K_RF5413))
index 474b012..6cafa23 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/pci.c
 +++ b/drivers/net/wireless/ath/ath5k/pci.c
-@@ -22,6 +22,7 @@
+@@ -23,6 +23,7 @@
  #include <linux/pci-aspm.h>
  #include <linux/etherdevice.h>
  #include <linux/module.h>
@@ -8,7 +8,7 @@
  #include "../ath.h"
  #include "ath5k.h"
  #include "debug.h"
-@@ -73,7 +74,7 @@ static void ath5k_pci_read_cachesize(str
+@@ -74,7 +75,7 @@ static void ath5k_pci_read_cachesize(str
  }
  
  /*
@@ -17,7 +17,7 @@
   */
  static bool
  ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
-@@ -81,6 +82,19 @@ ath5k_pci_eeprom_read(struct ath_common 
+@@ -82,6 +83,19 @@ ath5k_pci_eeprom_read(struct ath_common 
        struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
        u32 status, timeout;
  
@@ -37,7 +37,7 @@
        /*
         * Initialize EEPROM access
         */
-@@ -124,6 +138,16 @@ static int ath5k_pci_eeprom_read_mac(str
+@@ -125,6 +139,16 @@ static int ath5k_pci_eeprom_read_mac(str
        u16 data;
        int octet;
  
index 15977db..8db5e1b 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath5k/pci.c
 +++ b/drivers/net/wireless/ath/ath5k/pci.c
-@@ -49,6 +49,8 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci
+@@ -50,6 +50,8 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci
        { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
        { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
        { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
index 452e10a..4571fe2 100644 (file)
@@ -71,7 +71,7 @@
                        ath_err(common, "Reading Magic # failed\n");
 --- a/drivers/net/wireless/ath/ath9k/hw.h
 +++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -662,6 +662,7 @@ enum ath_cal_list {
+@@ -657,6 +657,7 @@ enum ath_cal_list {
  #define AH_USE_EEPROM   0x1
  #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
  #define AH_FASTCC       0x4
@@ -81,7 +81,7 @@
        struct ath_ops reg_ops;
 --- a/drivers/net/wireless/ath/ath9k/init.c
 +++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -534,6 +534,8 @@ static int ath9k_init_softc(u16 devid, s
+@@ -535,6 +535,8 @@ static int ath9k_init_softc(u16 devid, s
                ah->is_clk_25mhz = pdata->is_clk_25mhz;
                ah->get_mac_revision = pdata->get_mac_revision;
                ah->external_reset = pdata->external_reset;
index 78bd237..d2e7331 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/init.c
 +++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -904,23 +904,23 @@ static int __init ath9k_init(void)
+@@ -905,23 +905,23 @@ static int __init ath9k_init(void)
                goto err_out;
        }
  
index bc0a731..429d443 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/hw.c
 +++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1936,8 +1936,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1939,8 +1939,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
        REG_WRITE(ah, AR_OBS, 8);
  
        if (ah->config.rx_intr_mitigation) {
index 348ab21..637fada 100644 (file)
@@ -80,8 +80,8 @@
  }
 --- a/drivers/net/wireless/ath/ath9k/main.c
 +++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -1550,7 +1550,7 @@ static void ath9k_disable_ps(struct ath_
+@@ -1551,7 +1551,7 @@ static void ath9k_disable_ps(struct ath_
+       ath_dbg(common, PS, "PowerSave disabled\n");
  }
  
 -static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
@@ -89,7 +89,7 @@
  {
        struct ath_softc *sc = hw->priv;
        struct ath_hw *ah = sc->sc_ah;
-@@ -1601,9 +1601,11 @@ static int ath9k_config(struct ieee80211
+@@ -1602,9 +1602,11 @@ static int ath9k_config(struct ieee80211
  
        if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
                struct ieee80211_channel *curchan = hw->conf.channel;
  
                if (ah->curchan)
                        old_pos = ah->curchan - &ah->channels[0];
-@@ -1651,7 +1653,23 @@ static int ath9k_config(struct ieee80211
+@@ -1652,7 +1654,23 @@ static int ath9k_config(struct ieee80211
                        memset(&sc->survey[pos], 0, sizeof(struct survey_info));
                }
  
index f1bd0bc..e8893fb 100644 (file)
@@ -1,6 +1,6 @@
 --- a/include/net/mac80211.h
 +++ b/include/net/mac80211.h
-@@ -825,7 +825,7 @@ enum ieee80211_smps_mode {
+@@ -829,7 +829,7 @@ enum ieee80211_smps_mode {
   */
  struct ieee80211_conf {
        u32 flags;
@@ -11,7 +11,7 @@
        u16 listen_interval;
 --- a/net/mac80211/cfg.c
 +++ b/net/mac80211/cfg.c
-@@ -1757,7 +1757,7 @@ static int ieee80211_get_tx_power(struct
+@@ -1936,7 +1936,7 @@ static int ieee80211_get_tx_power(struct
  {
        struct ieee80211_local *local = wiphy_priv(wiphy);
  
@@ -22,7 +22,7 @@
  }
 --- a/net/mac80211/main.c
 +++ b/net/mac80211/main.c
-@@ -165,6 +165,7 @@ int ieee80211_hw_config(struct ieee80211
+@@ -167,6 +167,7 @@ int ieee80211_hw_config(struct ieee80211
  
        if (local->hw.conf.power_level != power) {
                changed |= IEEE80211_CONF_CHANGE_POWER;
index 5a59bbf..24437ac 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/net/wireless/ath/ath9k/main.c
 +++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -1675,6 +1675,8 @@ int ath9k_config(struct ieee80211_hw *hw
+@@ -1676,6 +1676,8 @@ int ath9k_config(struct ieee80211_hw *hw
                        return -EINVAL;
                }
  
@@ -9,7 +9,7 @@
                /*
                 * The most recent snapshot of channel->noisefloor for the old
                 * channel is only available after the hardware reset. Copy it to
-@@ -1689,6 +1691,7 @@ int ath9k_config(struct ieee80211_hw *hw
+@@ -1690,6 +1692,7 @@ int ath9k_config(struct ieee80211_hw *hw
                sc->config.txpowlimit = 2 * conf->power_level;
                ath9k_cmn_update_txpow(ah, sc->curtxpow,
                                       sc->config.txpowlimit, &sc->curtxpow);
index d8e46df..7aa72ab 100644 (file)
@@ -1,6 +1,6 @@
 --- a/include/net/mac80211.h
 +++ b/include/net/mac80211.h
-@@ -693,6 +693,9 @@ enum mac80211_rx_flags {
+@@ -697,6 +697,9 @@ enum mac80211_rx_flags {
   * @mactime: value in microseconds of the 64-bit Time Synchronization Function
   *    (TSF) timer when the first data symbol (MPDU) arrived at the hardware.
   * @band: the active band when this frame was received
@@ -10,7 +10,7 @@
   * @freq: frequency the radio was tuned to when receiving this frame, in MHz
   * @signal: signal strength when receiving this frame, either in dBm, in dB or
   *    unspecified depending on the hardware capabilities flags
-@@ -706,6 +709,10 @@ enum mac80211_rx_flags {
+@@ -710,6 +713,10 @@ enum mac80211_rx_flags {
  struct ieee80211_rx_status {
        u64 mactime;
        enum ieee80211_band band;
@@ -37,7 +37,7 @@
  
 --- a/net/mac80211/rx.c
 +++ b/net/mac80211/rx.c
-@@ -1262,6 +1262,7 @@ ieee80211_rx_h_sta_process(struct ieee80
+@@ -1263,6 +1263,7 @@ ieee80211_rx_h_sta_process(struct ieee80
        struct sk_buff *skb = rx->skb;
        struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
@@ -45,7 +45,7 @@
  
        if (!sta)
                return RX_CONTINUE;
-@@ -1306,6 +1307,19 @@ ieee80211_rx_h_sta_process(struct ieee80
+@@ -1307,6 +1308,19 @@ ieee80211_rx_h_sta_process(struct ieee80
                ewma_add(&sta->avg_signal, -status->signal);
        }
  
        RX_SAMP_DBG(rate) = rs->rs_rate;
 --- a/include/linux/nl80211.h
 +++ b/include/linux/nl80211.h
-@@ -1693,6 +1693,8 @@ enum nl80211_sta_bss_param {
+@@ -1695,6 +1695,8 @@ enum nl80211_sta_bss_param {
   * @NL80211_STA_INFO_STA_FLAGS: Contains a struct nl80211_sta_flag_update.
   * @NL80211_STA_INFO_BEACON_LOSS: count of times beacon loss was detected (u32)
   * @NL80211_STA_INFO_T_OFFSET: timing offset with respect to this STA (s64)
   * @__NL80211_STA_INFO_AFTER_LAST: internal
   * @NL80211_STA_INFO_MAX: highest possible station info attribute
   */
-@@ -1717,6 +1719,8 @@ enum nl80211_sta_info {
+@@ -1719,6 +1721,8 @@ enum nl80211_sta_info {
        NL80211_STA_INFO_STA_FLAGS,
        NL80211_STA_INFO_BEACON_LOSS,
        NL80211_STA_INFO_T_OFFSET,
        __NL80211_STA_INFO_AFTER_LAST,
 --- a/net/wireless/nl80211.c
 +++ b/net/wireless/nl80211.c
-@@ -2406,6 +2406,33 @@ nla_put_failure:
+@@ -2467,6 +2467,33 @@ nla_put_failure:
        return false;
  }
  
  static int nl80211_send_station(struct sk_buff *msg, u32 pid, u32 seq,
                                int flags,
                                struct cfg80211_registered_device *rdev,
-@@ -2460,6 +2487,18 @@ static int nl80211_send_station(struct s
+@@ -2528,6 +2555,18 @@ static int nl80211_send_station(struct s
        default:
                break;
        }
index 5a9275b..22b4102 100644 (file)
@@ -33,7 +33,7 @@
        debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
 --- a/drivers/net/wireless/ath/ath9k/xmit.c
 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -392,6 +392,14 @@ static void ath_tx_count_frames(struct a
+@@ -393,6 +393,14 @@ static void ath_tx_count_frames(struct a
        }
  }
  
@@ -48,7 +48,7 @@
  
  static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                 struct ath_buf *bf, struct list_head *bf_q,
-@@ -486,6 +494,8 @@ static void ath_tx_complete_aggr(struct 
+@@ -487,6 +495,8 @@ static void ath_tx_complete_aggr(struct 
        __skb_queue_head_init(&bf_pending);
  
        ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
@@ -57,7 +57,7 @@
        while (bf) {
                u16 seqno = bf->bf_state.seqno;
  
-@@ -884,6 +894,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
+@@ -885,6 +895,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
                        ath_tx_addto_baw(sc, tid, seqno);
                bf->bf_state.ndelim = ndelim;
  
@@ -65,7 +65,7 @@
                __skb_unlink(skb, &tid->buf_q);
                list_add_tail(&bf->list, bf_q);
                if (bf_prev)
-@@ -1737,6 +1748,8 @@ static void ath_tx_send_ampdu(struct ath
+@@ -1738,6 +1749,8 @@ static void ath_tx_send_ampdu(struct ath
        /* Add sub-frame to BAW */
        ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
  
@@ -74,7 +74,7 @@
        /* Queue to h/w without aggregation */
        TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
        bf->bf_lastbf = bf;
-@@ -1869,22 +1882,11 @@ error:
+@@ -1873,22 +1886,11 @@ error:
  
  /* FIXME: tx power */
  static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
@@ -99,7 +99,7 @@
  
        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
                /*
-@@ -1916,6 +1918,7 @@ int ath_tx_start(struct ieee80211_hw *hw
+@@ -1920,6 +1922,7 @@ int ath_tx_start(struct ieee80211_hw *hw
        struct ieee80211_vif *vif = info->control.vif;
        struct ath_softc *sc = hw->priv;
        struct ath_txq *txq = txctl->txq;
        int padpos, padsize;
        int frmlen = skb->len + FCS_LEN;
        int q;
-@@ -1958,6 +1961,24 @@ int ath_tx_start(struct ieee80211_hw *hw
+@@ -1962,6 +1965,24 @@ int ath_tx_start(struct ieee80211_hw *hw
  
        setup_frame_info(hw, skb, frmlen);
  
        /*
         * At this point, the vif, hw_key and sta pointers in the tx control
         * info are no longer valid (overwritten by the ath_frame_info data.
-@@ -1972,7 +1993,7 @@ int ath_tx_start(struct ieee80211_hw *hw
+@@ -1976,7 +1997,7 @@ int ath_tx_start(struct ieee80211_hw *hw
                txq->stopped = true;
        }
  
index 30094cd..a34a4e1 100644 (file)
  
 --- a/drivers/net/wireless/ath/ath9k/init.c
 +++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -781,7 +781,7 @@ int ath9k_init_device(u16 devid, struct 
+@@ -782,7 +782,7 @@ int ath9k_init_device(u16 devid, struct 
  
  #ifdef CONFIG_MAC80211_LEDS
        /* must be initialized before ieee80211_register_hw */
index 71dae84..f7f66be 100644 (file)
@@ -11,7 +11,7 @@
        union {
 --- a/net/mac80211/cfg.c
 +++ b/net/mac80211/cfg.c
-@@ -1933,9 +1933,20 @@ static int ieee80211_set_bitrate_mask(st
+@@ -2112,9 +2112,20 @@ static int ieee80211_set_bitrate_mask(st
        }
  
        for (i = 0; i < IEEE80211_NUM_BANDS; i++) {
@@ -34,7 +34,7 @@
        return 0;
 --- a/include/net/mac80211.h
 +++ b/include/net/mac80211.h
-@@ -3645,7 +3645,7 @@ void ieee80211_send_bar(struct ieee80211
+@@ -3672,7 +3672,7 @@ void ieee80211_send_bar(struct ieee80211
   *    (deprecated; this will be removed once drivers get updated to use
   *    rate_idx_mask)
   * @rate_idx_mask: user-requested (legacy) rate mask
@@ -43,7 +43,7 @@
   * @bss: whether this frame is sent out in AP or IBSS mode
   */
  struct ieee80211_tx_rate_control {
-@@ -3657,7 +3657,7 @@ struct ieee80211_tx_rate_control {
+@@ -3684,7 +3684,7 @@ struct ieee80211_tx_rate_control {
        bool rts, short_preamble;
        u8 max_rate_idx;
        u32 rate_idx_mask;
diff --git a/package/mac80211/patches/560-ath9k_fix_rx_tx_stop.patch b/package/mac80211/patches/560-ath9k_fix_rx_tx_stop.patch
deleted file mode 100644 (file)
index 8a98f91..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -235,7 +235,7 @@ static bool ath_prepare_reset(struct ath
- {
-       struct ath_hw *ah = sc->sc_ah;
-       struct ath_common *common = ath9k_hw_common(ah);
--      bool ret;
-+      bool ret = true;
-       ieee80211_stop_queues(sc->hw);
-@@ -246,11 +246,12 @@ static bool ath_prepare_reset(struct ath
-       ath9k_debug_samp_bb_mac(sc);
-       ath9k_hw_disable_interrupts(ah);
--      ret = ath_drain_all_txq(sc, retry_tx);
--
-       if (!ath_stoprecv(sc))
-               ret = false;
-+      if (!ath_drain_all_txq(sc, retry_tx))
-+              ret = false;
-+
-       if (!flush) {
-               if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
-                       ath_rx_tasklet(sc, 1, true);
diff --git a/package/mac80211/patches/561-ath9k_fix_tid_buffer_free.patch b/package/mac80211/patches/561-ath9k_fix_tid_buffer_free.patch
deleted file mode 100644 (file)
index fd0bfa9..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -64,7 +64,8 @@ static void ath_tx_update_baw(struct ath
- static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
-                                          struct ath_txq *txq,
-                                          struct ath_atx_tid *tid,
--                                         struct sk_buff *skb);
-+                                         struct sk_buff *skb,
-+                                         bool dequeue);
- enum {
-       MCS_HT20,
-@@ -821,7 +822,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
-               fi = get_frame_info(skb);
-               bf = fi->bf;
-               if (!fi->bf)
--                      bf = ath_tx_setup_buffer(sc, txq, tid, skb);
-+                      bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
-               if (!bf)
-                       continue;
-@@ -1737,7 +1738,7 @@ static void ath_tx_send_ampdu(struct ath
-               return;
-       }
--      bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
-+      bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
-       if (!bf)
-               return;
-@@ -1766,7 +1767,7 @@ static void ath_tx_send_normal(struct at
-       bf = fi->bf;
-       if (!bf)
--              bf = ath_tx_setup_buffer(sc, txq, tid, skb);
-+              bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
-       if (!bf)
-               return;
-@@ -1827,7 +1828,8 @@ u8 ath_txchainmask_reduction(struct ath_
- static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
-                                          struct ath_txq *txq,
-                                          struct ath_atx_tid *tid,
--                                         struct sk_buff *skb)
-+                                         struct sk_buff *skb,
-+                                         bool dequeue)
- {
-       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-       struct ath_frame_info *fi = get_frame_info(skb);
-@@ -1876,6 +1878,8 @@ static struct ath_buf *ath_tx_setup_buff
-       return bf;
- error:
-+      if (dequeue)
-+              __skb_unlink(skb, &tid->buf_q);
-       dev_kfree_skb_any(skb);
-       return NULL;
- }
-@@ -1895,7 +1899,7 @@ static void ath_tx_start_dma(struct ath_
-                */
-               ath_tx_send_ampdu(sc, tid, skb, txctl);
-       } else {
--              bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
-+              bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
-               if (!bf)
-                       return;
diff --git a/package/mac80211/patches/562-ath9k_update_ar9330_initvals.patch b/package/mac80211/patches/562-ath9k_update_ar9330_initvals.patch
deleted file mode 100644 (file)
index 99093bc..0000000
+++ /dev/null
@@ -1,301 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
-+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
-@@ -1,5 +1,6 @@
- /*
-- * Copyright (c) 2011 Atheros Communications Inc.
-+ * Copyright (c) 2010-2011 Atheros Communications Inc.
-+ * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
-  *
-  * Permission to use, copy, modify, and/or distribute this software for any
-  * purpose with or without fee is hereby granted, provided that the above
-@@ -18,7 +19,7 @@
- #define INITVALS_9330_1P1_H
- static const u32 ar9331_1p1_baseband_postamble[][5] = {
--      /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
-       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
-       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
-@@ -27,10 +28,10 @@ static const u32 ar9331_1p1_baseband_pos
-       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
-       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
-       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
--      {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
-+      {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
-       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
-       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
--      {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
-+      {0x00009e14, 0x31365d5e, 0x3136605e, 0x3136605e, 0x31365d5e},
-       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
-       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
-@@ -55,7 +56,7 @@ static const u32 ar9331_1p1_baseband_pos
-       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
--      {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
-+      {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
-       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
-       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
-@@ -63,7 +64,7 @@ static const u32 ar9331_1p1_baseband_pos
- };
- static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p1[][5] = {
--      /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
-       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
-       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
-@@ -155,7 +156,7 @@ static const u32 ar9331_modes_lowest_ob_
- };
- static const u32 ar9331_modes_high_ob_db_tx_gain_1p1[][5] = {
--      /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
-       {0x0000a2dc, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52},
-       {0x0000a2e0, 0xffb31c84, 0xffb31c84, 0xffb31c84, 0xffb31c84},
-@@ -245,7 +246,7 @@ static const u32 ar9331_modes_high_ob_db
- };
- static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
--      /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
-       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
-       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
-@@ -377,14 +378,14 @@ static const u32 ar9331_1p1_radio_core[]
-       {0x000160b4, 0x92480040},
-       {0x000160c0, 0x006db6db},
-       {0x000160c4, 0x0186db60},
--      {0x000160c8, 0x6db6db6c},
-+      {0x000160c8, 0x6db4db6c},
-       {0x000160cc, 0x6de6c300},
-       {0x000160d0, 0x14500820},
-       {0x00016100, 0x04cb0001},
-       {0x00016104, 0xfff80015},
-       {0x00016108, 0x00080010},
-       {0x0001610c, 0x00170000},
--      {0x00016140, 0x10804000},
-+      {0x00016140, 0x10800000},
-       {0x00016144, 0x01884080},
-       {0x00016148, 0x000080c0},
-       {0x00016280, 0x01000015},
-@@ -417,7 +418,7 @@ static const u32 ar9331_1p1_radio_core[]
- };
- static const u32 ar9331_1p1_soc_postamble[][5] = {
--      /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
- };
-@@ -691,7 +692,7 @@ static const u32 ar9331_1p1_baseband_cor
- };
- static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
--      /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
-       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
-       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
-@@ -783,7 +784,7 @@ static const u32 ar9331_modes_high_power
- };
- static const u32 ar9331_1p1_mac_postamble[][5] = {
--      /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
-+      /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
-       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
-       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
-@@ -973,26 +974,27 @@ static const u32 ar9331_1p1_mac_core[][2
- static const u32 ar9331_common_rx_gain_1p1[][2] = {
-       /* Addr      allmodes  */
--      {0x0000a000, 0x00010000},
--      {0x0000a004, 0x00030002},
--      {0x0000a008, 0x00050004},
--      {0x0000a00c, 0x00810080},
--      {0x0000a010, 0x00830082},
--      {0x0000a014, 0x01810180},
--      {0x0000a018, 0x01830182},
--      {0x0000a01c, 0x01850184},
--      {0x0000a020, 0x01890188},
--      {0x0000a024, 0x018b018a},
--      {0x0000a028, 0x018d018c},
--      {0x0000a02c, 0x01910190},
--      {0x0000a030, 0x01930192},
--      {0x0000a034, 0x01950194},
--      {0x0000a038, 0x038a0196},
--      {0x0000a03c, 0x038c038b},
--      {0x0000a040, 0x0390038d},
--      {0x0000a044, 0x03920391},
--      {0x0000a048, 0x03940393},
--      {0x0000a04c, 0x03960395},
-+      {0x00009e18, 0x05000000},
-+      {0x0000a000, 0x00060005},
-+      {0x0000a004, 0x00810080},
-+      {0x0000a008, 0x00830082},
-+      {0x0000a00c, 0x00850084},
-+      {0x0000a010, 0x01820181},
-+      {0x0000a014, 0x01840183},
-+      {0x0000a018, 0x01880185},
-+      {0x0000a01c, 0x018a0189},
-+      {0x0000a020, 0x02850284},
-+      {0x0000a024, 0x02890288},
-+      {0x0000a028, 0x028b028a},
-+      {0x0000a02c, 0x03850384},
-+      {0x0000a030, 0x03890388},
-+      {0x0000a034, 0x038b038a},
-+      {0x0000a038, 0x038d038c},
-+      {0x0000a03c, 0x03910390},
-+      {0x0000a040, 0x03930392},
-+      {0x0000a044, 0x03950394},
-+      {0x0000a048, 0x00000396},
-+      {0x0000a04c, 0x00000000},
-       {0x0000a050, 0x00000000},
-       {0x0000a054, 0x00000000},
-       {0x0000a058, 0x00000000},
-@@ -1005,15 +1007,15 @@ static const u32 ar9331_common_rx_gain_1
-       {0x0000a074, 0x00000000},
-       {0x0000a078, 0x00000000},
-       {0x0000a07c, 0x00000000},
--      {0x0000a080, 0x22222229},
--      {0x0000a084, 0x1d1d1d1d},
--      {0x0000a088, 0x1d1d1d1d},
--      {0x0000a08c, 0x1d1d1d1d},
--      {0x0000a090, 0x171d1d1d},
--      {0x0000a094, 0x11111717},
--      {0x0000a098, 0x00030311},
--      {0x0000a09c, 0x00000000},
--      {0x0000a0a0, 0x00000000},
-+      {0x0000a080, 0x28282828},
-+      {0x0000a084, 0x28282828},
-+      {0x0000a088, 0x28282828},
-+      {0x0000a08c, 0x28282828},
-+      {0x0000a090, 0x28282828},
-+      {0x0000a094, 0x24242428},
-+      {0x0000a098, 0x171e1e1e},
-+      {0x0000a09c, 0x02020b0b},
-+      {0x0000a0a0, 0x02020202},
-       {0x0000a0a4, 0x00000000},
-       {0x0000a0a8, 0x00000000},
-       {0x0000a0ac, 0x00000000},
-@@ -1021,27 +1023,27 @@ static const u32 ar9331_common_rx_gain_1
-       {0x0000a0b4, 0x00000000},
-       {0x0000a0b8, 0x00000000},
-       {0x0000a0bc, 0x00000000},
--      {0x0000a0c0, 0x001f0000},
--      {0x0000a0c4, 0x01000101},
--      {0x0000a0c8, 0x011e011f},
--      {0x0000a0cc, 0x011c011d},
--      {0x0000a0d0, 0x02030204},
--      {0x0000a0d4, 0x02010202},
--      {0x0000a0d8, 0x021f0200},
--      {0x0000a0dc, 0x0302021e},
--      {0x0000a0e0, 0x03000301},
--      {0x0000a0e4, 0x031e031f},
--      {0x0000a0e8, 0x0402031d},
--      {0x0000a0ec, 0x04000401},
--      {0x0000a0f0, 0x041e041f},
--      {0x0000a0f4, 0x0502041d},
--      {0x0000a0f8, 0x05000501},
--      {0x0000a0fc, 0x051e051f},
--      {0x0000a100, 0x06010602},
--      {0x0000a104, 0x061f0600},
--      {0x0000a108, 0x061d061e},
--      {0x0000a10c, 0x07020703},
--      {0x0000a110, 0x07000701},
-+      {0x0000a0c0, 0x22072208},
-+      {0x0000a0c4, 0x22052206},
-+      {0x0000a0c8, 0x22032204},
-+      {0x0000a0cc, 0x22012202},
-+      {0x0000a0d0, 0x221f2200},
-+      {0x0000a0d4, 0x221d221e},
-+      {0x0000a0d8, 0x33023303},
-+      {0x0000a0dc, 0x33003301},
-+      {0x0000a0e0, 0x331e331f},
-+      {0x0000a0e4, 0x4402331d},
-+      {0x0000a0e8, 0x44004401},
-+      {0x0000a0ec, 0x441e441f},
-+      {0x0000a0f0, 0x55025503},
-+      {0x0000a0f4, 0x55005501},
-+      {0x0000a0f8, 0x551e551f},
-+      {0x0000a0fc, 0x6602551d},
-+      {0x0000a100, 0x66006601},
-+      {0x0000a104, 0x661e661f},
-+      {0x0000a108, 0x7703661d},
-+      {0x0000a10c, 0x77017702},
-+      {0x0000a110, 0x00007700},
-       {0x0000a114, 0x00000000},
-       {0x0000a118, 0x00000000},
-       {0x0000a11c, 0x00000000},
-@@ -1054,26 +1056,26 @@ static const u32 ar9331_common_rx_gain_1
-       {0x0000a138, 0x00000000},
-       {0x0000a13c, 0x00000000},
-       {0x0000a140, 0x001f0000},
--      {0x0000a144, 0x01000101},
--      {0x0000a148, 0x011e011f},
--      {0x0000a14c, 0x011c011d},
--      {0x0000a150, 0x02030204},
--      {0x0000a154, 0x02010202},
--      {0x0000a158, 0x021f0200},
--      {0x0000a15c, 0x0302021e},
--      {0x0000a160, 0x03000301},
--      {0x0000a164, 0x031e031f},
--      {0x0000a168, 0x0402031d},
--      {0x0000a16c, 0x04000401},
--      {0x0000a170, 0x041e041f},
--      {0x0000a174, 0x0502041d},
--      {0x0000a178, 0x05000501},
--      {0x0000a17c, 0x051e051f},
--      {0x0000a180, 0x06010602},
--      {0x0000a184, 0x061f0600},
--      {0x0000a188, 0x061d061e},
--      {0x0000a18c, 0x07020703},
--      {0x0000a190, 0x07000701},
-+      {0x0000a144, 0x111f1100},
-+      {0x0000a148, 0x111d111e},
-+      {0x0000a14c, 0x111b111c},
-+      {0x0000a150, 0x22032204},
-+      {0x0000a154, 0x22012202},
-+      {0x0000a158, 0x221f2200},
-+      {0x0000a15c, 0x221d221e},
-+      {0x0000a160, 0x33013302},
-+      {0x0000a164, 0x331f3300},
-+      {0x0000a168, 0x4402331e},
-+      {0x0000a16c, 0x44004401},
-+      {0x0000a170, 0x441e441f},
-+      {0x0000a174, 0x55015502},
-+      {0x0000a178, 0x551f5500},
-+      {0x0000a17c, 0x6602551e},
-+      {0x0000a180, 0x66006601},
-+      {0x0000a184, 0x661e661f},
-+      {0x0000a188, 0x7703661d},
-+      {0x0000a18c, 0x77017702},
-+      {0x0000a190, 0x00007700},
-       {0x0000a194, 0x00000000},
-       {0x0000a198, 0x00000000},
-       {0x0000a19c, 0x00000000},
-@@ -1100,14 +1102,14 @@ static const u32 ar9331_common_rx_gain_1
-       {0x0000a1f0, 0x00000396},
-       {0x0000a1f4, 0x00000396},
-       {0x0000a1f8, 0x00000396},
--      {0x0000a1fc, 0x00000196},
-+      {0x0000a1fc, 0x00000296},
- };
- static const u32 ar9331_common_tx_gain_offset1_1[][1] = {
--      {0},
--      {3},
--      {0},
--      {0},
-+      {0x00000000},
-+      {0x00000003},
-+      {0x00000000},
-+      {0x00000000},
- };
- static const u32 ar9331_1p1_chansel_xtal_25M[] = {
diff --git a/package/mac80211/patches/563-ath9k_fix_ar9330_internal_regulator.patch b/package/mac80211/patches/563-ath9k_fix_ar9330_internal_regulator.patch
deleted file mode 100644 (file)
index 8df5e73..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -3809,7 +3809,7 @@ static bool is_pmu_set(struct ath_hw *ah
-       return true;
- }
--static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
-+void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
- {
-       int internal_regulator =
-               ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
-@@ -334,4 +334,7 @@ u8 *ar9003_get_spur_chan_ptr(struct ath_
- unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
-                                          struct ath9k_channel *chan);
-+
-+void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
-+
- #endif
---- a/drivers/net/wireless/ath/ath9k/hw.c
-+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1477,6 +1477,9 @@ static bool ath9k_hw_chip_reset(struct a
-               return false;
-       ah->chip_fullsleep = false;
-+
-+      if (AR_SREV_9330(ah))
-+              ar9003_hw_internal_regulator_apply(ah);
-       ath9k_hw_init_pll(ah, chan);
-       ath9k_hw_set_rfmode(ah, chan);
index 82908ab..be6b683 100644 (file)
@@ -42,7 +42,7 @@
  
        if (wl->radio_enabled != phy->radio_on) {
                if (wl->radio_enabled) {
-@@ -4934,6 +4931,47 @@ static int b43_op_get_survey(struct ieee
+@@ -4940,6 +4937,47 @@ static int b43_op_get_survey(struct ieee
        return 0;
  }
  
@@ -90,7 +90,7 @@
  static const struct ieee80211_ops b43_hw_ops = {
        .tx                     = b43_op_tx,
        .conf_tx                = b43_op_conf_tx,
-@@ -4955,6 +4993,8 @@ static const struct ieee80211_ops b43_hw
+@@ -4961,6 +4999,8 @@ static const struct ieee80211_ops b43_hw
        .sw_scan_complete       = b43_op_sw_scan_complete_notifier,
        .get_survey             = b43_op_get_survey,
        .rfkill_poll            = b43_rfkill_poll,
@@ -99,7 +99,7 @@
  };
  
  /* Hard-reset the chip. Do not call this directly.
-@@ -5201,6 +5241,8 @@ static int b43_one_core_attach(struct b4
+@@ -5207,6 +5247,8 @@ static int b43_one_core_attach(struct b4
        if (!wldev)
                goto out;
  
        wldev->use_pio = b43_modparam_pio;
        wldev->dev = dev;
        wldev->wl = wl;
-@@ -5291,6 +5333,9 @@ static struct b43_wl *b43_wireless_init(
+@@ -5297,6 +5339,9 @@ static struct b43_wl *b43_wireless_init(
  
        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
  
diff --git a/package/mac80211/patches/840-b43-backport.patch b/package/mac80211/patches/840-b43-backport.patch
deleted file mode 100644 (file)
index b2bb22a..0000000
+++ /dev/null
@@ -1,159 +0,0 @@
---- a/drivers/net/wireless/b43/bus.c
-+++ b/drivers/net/wireless/b43/bus.c
-@@ -107,11 +107,9 @@ struct b43_bus_dev *b43_bus_dev_bcma_ini
-       dev->dma_dev = core->dma_dev;
-       dev->irq = core->irq;
--      /*
-       dev->board_vendor = core->bus->boardinfo.vendor;
-       dev->board_type = core->bus->boardinfo.type;
--      dev->board_rev = core->bus->boardinfo.rev;
--      */
-+      dev->board_rev = core->bus->sprom.board_rev;
-       dev->chip_id = core->bus->chipinfo.id;
-       dev->chip_rev = core->bus->chipinfo.rev;
-@@ -210,7 +208,7 @@ struct b43_bus_dev *b43_bus_dev_ssb_init
-       dev->board_vendor = sdev->bus->boardinfo.vendor;
-       dev->board_type = sdev->bus->boardinfo.type;
--      dev->board_rev = sdev->bus->boardinfo.rev;
-+      dev->board_rev = sdev->bus->sprom.board_rev;
-       dev->chip_id = sdev->bus->chip_id;
-       dev->chip_rev = sdev->bus->chip_rev;
---- a/drivers/net/wireless/b43/dma.c
-+++ b/drivers/net/wireless/b43/dma.c
-@@ -1109,7 +1109,7 @@ static bool b43_dma_translation_in_low_w
- #ifdef CONFIG_B43_SSB
-       if (dev->dev->bus_type == B43_BUS_SSB &&
-           dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
--          !(dev->dev->sdev->bus->host_pci->is_pcie &&
-+          !(pci_is_pcie(dev->dev->sdev->bus->host_pci) &&
-             ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
-                       return 1;
- #endif
---- a/drivers/net/wireless/b43/main.c
-+++ b/drivers/net/wireless/b43/main.c
-@@ -4834,8 +4834,14 @@ static int b43_op_start(struct ieee80211
-  out_mutex_unlock:
-       mutex_unlock(&wl->mutex);
--      /* reload configuration */
--      b43_op_config(hw, ~0);
-+      /*
-+       * Configuration may have been overwritten during initialization.
-+       * Reload the configuration, but only if initialization was
-+       * successful. Reloading the configuration after a failed init
-+       * may hang the system.
-+       */
-+      if (!err)
-+              b43_op_config(hw, ~0);
-       return err;
- }
-@@ -5279,10 +5285,10 @@ static void b43_sprom_fixup(struct ssb_b
-       /* boardflags workarounds */
-       if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
--          bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
-+          bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
-               bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
-       if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
--          bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
-+          bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
-               bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
-       if (bus->bustype == SSB_BUSTYPE_PCI) {
-               pdev = bus->host_pci;
---- a/drivers/net/wireless/b43/sdio.c
-+++ b/drivers/net/wireless/b43/sdio.c
-@@ -193,7 +193,7 @@ static struct sdio_driver b43_sdio_drive
-       .name           = "b43-sdio",
-       .id_table       = b43_sdio_ids,
-       .probe          = b43_sdio_probe,
--      .remove         = b43_sdio_remove,
-+      .remove         = __devexit_p(b43_sdio_remove),
- };
- int b43_sdio_init(void)
---- a/drivers/net/wireless/b43legacy/main.c
-+++ b/drivers/net/wireless/b43legacy/main.c
-@@ -1550,8 +1550,6 @@ static void b43legacy_request_firmware(s
-       const char *filename;
-       int err;
--      /* do dummy read */
--      ssb_read32(dev->dev, SSB_TMSHIGH);
-       if (!fw->ucode) {
-               if (rev == 2)
-                       filename = "ucode2";
-@@ -3758,7 +3756,7 @@ static void b43legacy_sprom_fixup(struct
-       /* boardflags workarounds */
-       if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
-           bus->boardinfo.type == 0x4E &&
--          bus->boardinfo.rev > 0x40)
-+          bus->sprom.board_rev > 0x40)
-               bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
- }
---- a/drivers/net/wireless/b43legacy/phy.c
-+++ b/drivers/net/wireless/b43legacy/phy.c
-@@ -408,7 +408,7 @@ static void b43legacy_phy_setupg(struct
-               if (is_bcm_board_vendor(dev) &&
-                   (dev->dev->bus->boardinfo.type == 0x0416) &&
--                  (dev->dev->bus->boardinfo.rev == 0x0017))
-+                  (dev->dev->bus->sprom.board_rev == 0x0017))
-                       return;
-               b43legacy_ilt_write(dev, 0x5001, 0x0002);
-@@ -424,7 +424,7 @@ static void b43legacy_phy_setupg(struct
-               if (is_bcm_board_vendor(dev) &&
-                   (dev->dev->bus->boardinfo.type == 0x0416) &&
--                  (dev->dev->bus->boardinfo.rev == 0x0017))
-+                  (dev->dev->bus->sprom.board_rev == 0x0017))
-                       return;
-               b43legacy_ilt_write(dev, 0x0401, 0x0002);
---- a/drivers/net/wireless/b43legacy/radio.c
-+++ b/drivers/net/wireless/b43legacy/radio.c
-@@ -1998,7 +1998,7 @@ u16 b43legacy_default_radio_attenuation(
-                       if (phy->type == B43legacy_PHYTYPE_G) {
-                               if (is_bcm_board_vendor(dev) &&
-                                   dev->dev->bus->boardinfo.type == 0x421 &&
--                                  dev->dev->bus->boardinfo.rev >= 30)
-+                                  dev->dev->bus->sprom.board_rev >= 30)
-                                       att = 3;
-                               else if (is_bcm_board_vendor(dev) &&
-                                        dev->dev->bus->boardinfo.type == 0x416)
-@@ -2008,7 +2008,7 @@ u16 b43legacy_default_radio_attenuation(
-                       } else {
-                               if (is_bcm_board_vendor(dev) &&
-                                   dev->dev->bus->boardinfo.type == 0x421 &&
--                                  dev->dev->bus->boardinfo.rev >= 30)
-+                                  dev->dev->bus->sprom.board_rev >= 30)
-                                       att = 7;
-                               else
-                                       att = 6;
-@@ -2018,7 +2018,7 @@ u16 b43legacy_default_radio_attenuation(
-                       if (phy->type == B43legacy_PHYTYPE_G) {
-                               if (is_bcm_board_vendor(dev) &&
-                                   dev->dev->bus->boardinfo.type == 0x421 &&
--                                  dev->dev->bus->boardinfo.rev >= 30)
-+                                  dev->dev->bus->sprom.board_rev >= 30)
-                                       att = 3;
-                               else if (is_bcm_board_vendor(dev) &&
-                                        dev->dev->bus->boardinfo.type ==
-@@ -2052,9 +2052,9 @@ u16 b43legacy_default_radio_attenuation(
-       }
-       if (is_bcm_board_vendor(dev) &&
-           dev->dev->bus->boardinfo.type == 0x421) {
--              if (dev->dev->bus->boardinfo.rev < 0x43)
-+              if (dev->dev->bus->sprom.board_rev < 0x43)
-                       att = 2;
--              else if (dev->dev->bus->boardinfo.rev < 0x51)
-+              else if (dev->dev->bus->sprom.board_rev < 0x51)
-                       att = 3;
-       }
-       if (att == 0xFFFF)
diff --git a/package/mac80211/patches/840-brcmsmac-add-device-found-on-some-SoCs-like-the-bcm4.patch b/package/mac80211/patches/840-brcmsmac-add-device-found-on-some-SoCs-like-the-bcm4.patch
new file mode 100644 (file)
index 0000000..df48e1e
--- /dev/null
@@ -0,0 +1,39 @@
+--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+@@ -94,6 +94,7 @@ MODULE_LICENSE("Dual BSD/GPL");
+ static struct bcma_device_id brcms_coreid_table[] = {
+       BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 23, BCMA_ANY_CLASS),
+       BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 24, BCMA_ANY_CLASS),
++//    BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 17, BCMA_ANY_CLASS),
+       BCMA_CORETABLE_END
+ };
+ MODULE_DEVICE_TABLE(bcma, brcms_coreid_table);
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -719,7 +719,7 @@ static void brcms_c_ucode_bsinit(struct 
+       brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
+       /* do band-specific ucode IHR, SHM, and SCR inits */
+-      if (D11REV_IS(wlc_hw->corerev, 23)) {
++      if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
+               if (BRCMS_ISNPHY(wlc_hw->band))
+                       brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
+               else
+@@ -2242,7 +2242,7 @@ static void brcms_ucode_download(struct 
+       if (wlc_hw->ucode_loaded)
+               return;
+-      if (D11REV_IS(wlc_hw->corerev, 23)) {
++      if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
+               if (BRCMS_ISNPHY(wlc_hw->band)) {
+                       brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
+                                         ucode->bcm43xx_16_mimosz);
+@@ -3218,7 +3218,7 @@ static void brcms_b_coreinit(struct brcm
+       sflags = bcma_aread32(core, BCMA_IOST);
+-      if (D11REV_IS(wlc_hw->corerev, 23)) {
++      if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
+               if (BRCMS_ISNPHY(wlc_hw->band))
+                       brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
+               else
diff --git a/package/mac80211/patches/841-brcmsmac-add-support-for-BCM43224.patch b/package/mac80211/patches/841-brcmsmac-add-support-for-BCM43224.patch
new file mode 100644 (file)
index 0000000..56fd1eb
--- /dev/null
@@ -0,0 +1,29 @@
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -4132,6 +4132,7 @@ void brcms_c_wme_setparams(struct brcms_
+                                         M_EDCF_QINFO +
+                                         wme_ac2fifo[aci] * M_EDCF_QLEN + i,
+                                         *shm_entry++);
++              printk("dummy\n");
+       }
+       if (suspend) {
+@@ -4537,7 +4538,8 @@ static int brcms_b_attach(struct brcms_c
+       /* check device id(srom, nvram etc.) to set bands */
+       if (wlc_hw->deviceid == BCM43224_D11N_ID ||
+-          wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
++          wlc_hw->deviceid == BCM43224_D11N_ID_VEN1||
++          wlc_hw->deviceid == BCM43224_CHIP_ID)
+               /* Dualband boards */
+               wlc_hw->_nbands = 2;
+       else
+@@ -5791,7 +5793,7 @@ bool brcms_c_chipmatch(u16 vendor, u16 d
+               return false;
+       }
+-      if (device == BCM43224_D11N_ID_VEN1)
++      if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
+               return true;
+       if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
+               return true;
diff --git a/package/mac80211/patches/842-brcmsmac-add-some-conditions-for-the-bcm4716-again.patch b/package/mac80211/patches/842-brcmsmac-add-some-conditions-for-the-bcm4716-again.patch
new file mode 100644 (file)
index 0000000..40ccde9
--- /dev/null
@@ -0,0 +1,202 @@
+--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
+@@ -1943,7 +1943,8 @@ static bool brcms_b_radio_read_hwdisable
+                * accesses phyreg throughput mac. This can be skipped since
+                * only mac reg is accessed below
+                */
+-              flags |= SICF_PCLKE;
++              if (D11REV_GE(wlc_hw->corerev, 18))
++                      flags |= SICF_PCLKE;
+               /*
+                * TODO: test suspend/resume
+@@ -2024,7 +2025,8 @@ void brcms_b_corereset(struct brcms_hard
+        * phyreg throughput mac, AND phy_reset is skipped at early stage when
+        * band->pi is invalid. need to enable PHY CLK
+        */
+-      flags |= SICF_PCLKE;
++      if (D11REV_GE(wlc_hw->corerev, 18))
++              flags |= SICF_PCLKE;
+       /*
+        * reset the core
+--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
++++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
+@@ -17895,6 +17895,9 @@ static u32 *wlc_phy_get_ipa_gaintbl_nphy
+                                       nphy_tpc_txgain_ipa_2g_2057rev7;
+               } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
+                       tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
++                      if (pi->sh->chip == BCM47162_CHIP_ID) {
++                              tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
++                      }
+               } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+                       tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
+               } else {
+@@ -19256,8 +19259,14 @@ static void wlc_phy_spurwar_nphy(struct 
+                       case 38:
+                       case 102:
+                       case 118:
+-                              nphy_adj_tone_id_buf[0] = 0;
+-                              nphy_adj_noise_var_buf[0] = 0x0;
++                              if ((pi->sh->chip == BCM4716_CHIP_ID) &&
++                                  (pi->sh->chippkg == BCM4717_PKG_ID)) {
++                                      nphy_adj_tone_id_buf[0] = 32;
++                                      nphy_adj_noise_var_buf[0] = 0x21f;
++                              } else {
++                                      nphy_adj_tone_id_buf[0] = 0;
++                                      nphy_adj_noise_var_buf[0] = 0x0;
++                              }
+                               break;
+                       case 134:
+                               nphy_adj_tone_id_buf[0] = 32;
+@@ -20697,12 +20706,22 @@ wlc_phy_chanspec_radio2056_setup(struct 
+                       write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
+                                       RADIO_2056_SYN, 0x1f);
+-                      write_radio_reg(pi,
+-                                      RADIO_2056_SYN_PLL_LOOPFILTER4 |
+-                                      RADIO_2056_SYN, 0xb);
+-                      write_radio_reg(pi,
+-                                      RADIO_2056_SYN_PLL_CP2 |
+-                                      RADIO_2056_SYN, 0x14);
++                      if ((pi->sh->chip == BCM4716_CHIP_ID) ||
++                          (pi->sh->chip == BCM47162_CHIP_ID)) {
++                              write_radio_reg(pi,
++                                              RADIO_2056_SYN_PLL_LOOPFILTER4 |
++                                              RADIO_2056_SYN, 0x14);
++                              write_radio_reg(pi,
++                                              RADIO_2056_SYN_PLL_CP2 |
++                                              RADIO_2056_SYN, 0x00);
++                      } else {
++                              write_radio_reg(pi,
++                                              RADIO_2056_SYN_PLL_LOOPFILTER4 |
++                                              RADIO_2056_SYN, 0xb);
++                              write_radio_reg(pi,
++                                              RADIO_2056_SYN_PLL_CP2 |
++                                              RADIO_2056_SYN, 0x14);
++                      }
+               }
+       }
+@@ -20749,24 +20768,33 @@ wlc_phy_chanspec_radio2056_setup(struct 
+                               WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+                                                PADG_IDAC, 0xcc);
+-                              bias = 0x25;
+-                              cascbias = 0x20;
++                              if ((pi->sh->chip == BCM4716_CHIP_ID) ||
++                                  (pi->sh->chip ==
++                                   BCM47162_CHIP_ID)) {
++                                      bias = 0x40;
++                                      cascbias = 0x45;
++                                      pag_boost_tune = 0x5;
++                                      pgag_boost_tune = 0x33;
++                                      padg_boost_tune = 0x77;
++                                      mixg_boost_tune = 0x55;
++                              } else {
++                                      bias = 0x25;
++                                      cascbias = 0x20;
+-                              if ((pi->sh->chip ==
+-                                   BCM43224_CHIP_ID)
+-                                  || (pi->sh->chip ==
+-                                      BCM43225_CHIP_ID)) {
+-                                      if (pi->sh->chippkg ==
+-                                          BCM43224_FAB_SMIC) {
+-                                              bias = 0x2a;
+-                                              cascbias = 0x38;
++                                      if ((pi->sh->chip == BCM43224_CHIP_ID)
++                                          || (pi->sh->chip == BCM43225_CHIP_ID)) {
++                                              if (pi->sh->chippkg ==
++                                                  BCM43224_FAB_SMIC) {
++                                                      bias = 0x2a;
++                                                      cascbias = 0x38;
++                                              }
+                                       }
+-                              }
+-                              pag_boost_tune = 0x4;
+-                              pgag_boost_tune = 0x03;
+-                              padg_boost_tune = 0x77;
+-                              mixg_boost_tune = 0x65;
++                                      pag_boost_tune = 0x4;
++                                      pgag_boost_tune = 0x03;
++                                      padg_boost_tune = 0x77;
++                                      mixg_boost_tune = 0x65;
++                              }
+                               WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+                                                INTPAG_IMAIN_STAT, bias);
+@@ -21180,19 +21208,27 @@ wlc_phy_chanspec_nphy_setup(struct brcms
+               } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+                       if (val == 54)
+                               spuravoid = 1;
+-              } else {
+-                      if (pi->nphy_aband_spurwar_en &&
+-                          ((val == 38) || (val == 102)
+-                           || (val == 118)))
++              } else if (pi->nphy_aband_spurwar_en &&
++                          ((val == 38) || (val == 102) || (val == 118))) {
++                      if ((pi->sh->chip == BCM4716_CHIP_ID)
++                          && (pi->sh->chippkg == BCM4717_PKG_ID)) {
++                              spuravoid = 0;
++                      } else {
+                               spuravoid = 1;
++                      }
+               }
+               if (pi->phy_spuravoid == SPURAVOID_FORCEON)
+                       spuravoid = 1;
+-              wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
+-              si_pmu_spuravoid_pllupdate(pi->sh->sih, spuravoid);
+-              wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
++              if ((pi->sh->chip == BCM4716_CHIP_ID) ||
++                  (pi->sh->chip == BCM47162_CHIP_ID)) {
++                      si_pmu_spuravoid_pllupdate(pi->sh->sih, spuravoid);
++              } else {
++                      wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
++                      si_pmu_spuravoid_pllupdate(pi->sh->sih, spuravoid);
++                      wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
++              }
+               if ((pi->sh->chip == BCM43224_CHIP_ID) ||
+                   (pi->sh->chip == BCM43225_CHIP_ID)) {
+@@ -21211,7 +21247,10 @@ wlc_phy_chanspec_nphy_setup(struct brcms
+                       }
+               }
+-              wlapi_bmac_core_phypll_reset(pi->sh->physhim);
++              if (!((pi->sh->chip == BCM4716_CHIP_ID) ||
++                    (pi->sh->chip == BCM47162_CHIP_ID))) {
++                      wlapi_bmac_core_phypll_reset(pi->sh->physhim);
++              }
+               mod_phy_reg(pi, 0x01, (0x1 << 15),
+                           ((spuravoid > 0) ? (0x1 << 15) : 0));
+@@ -24925,14 +24964,20 @@ wlc_phy_a2_nphy(struct brcms_phy *pi, st
+                       if (txgains->useindex) {
+                               phy_a4 = 15 - ((txgains->index) >> 3);
+                               if (CHSPEC_IS2G(pi->radio_chanspec)) {
+-                                      if (NREV_GE(pi->pubpi.phy_rev, 6))
++                                      if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+                                               phy_a5 = 0x00f7 | (phy_a4 << 8);
+-
+-                                      else
+-                                      if (NREV_IS(pi->pubpi.phy_rev, 5))
++                                              if (pi->sh->chip ==
++                                                  BCM47162_CHIP_ID) {
++                                                      phy_a5 =
++                                                          0x10f7 | (phy_a4 <<
++                                                                    8);
++                                              }
++                                      } else
++                                      if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+                                               phy_a5 = 0x10f7 | (phy_a4 << 8);
+-                                      else
++                                      } else {
+                                               phy_a5 = 0x50f7 | (phy_a4 << 8);
++                                      }
+                               } else {
+                                       phy_a5 = 0x70f7 | (phy_a4 << 8);
+                               }
diff --git a/package/mac80211/patches/860-brcmsmac-backport.patch b/package/mac80211/patches/860-brcmsmac-backport.patch
deleted file mode 100644 (file)
index af3ae07..0000000
+++ /dev/null
@@ -1,4465 +0,0 @@
---- a/drivers/net/wireless/brcm80211/brcmsmac/Makefile
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/Makefile
-@@ -39,10 +39,7 @@ BRCMSMAC_OFILES := \
-       phy/phytbl_lcn.o \
-       phy/phytbl_n.o \
-       phy/phy_qmath.o \
--      otp.o \
--      srom.o \
-       dma.o \
--      nicpci.o \
-       brcms_trace_events.o
- MODULEPFX := brcmsmac
---- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
-@@ -22,7 +22,6 @@
- #include <linux/kernel.h>
- #include <linux/printk.h>
- #include <linux/delay.h>
--#include <linux/pci.h>
- #include <defs.h>
- #include <chipcommon.h>
-@@ -32,8 +31,6 @@
- #include "types.h"
- #include "pub.h"
- #include "pmu.h"
--#include "srom.h"
--#include "nicpci.h"
- #include "aiutils.h"
- /* slow_clk_ctl */
-@@ -324,7 +321,6 @@
- #define       IS_SIM(chippkg) \
-       ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
--#define PCI(sih)      (ai_get_buscoretype(sih) == PCI_CORE_ID)
- #define PCIE(sih)     (ai_get_buscoretype(sih) == PCIE_CORE_ID)
- #define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
-@@ -457,36 +453,9 @@ struct aidmp {
-       u32 componentid3;       /* 0xffc */
- };
--/* return true if PCIE capability exists in the pci config space */
--static bool ai_ispcie(struct si_info *sii)
--{
--      u8 cap_ptr;
--
--      cap_ptr =
--          pcicore_find_pci_capability(sii->pcibus, PCI_CAP_ID_EXP, NULL,
--                                      NULL);
--      if (!cap_ptr)
--              return false;
--
--      return true;
--}
--
--static bool ai_buscore_prep(struct si_info *sii)
--{
--      /* kludge to enable the clock on the 4306 which lacks a slowclock */
--      if (!ai_ispcie(sii))
--              ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
--      return true;
--}
--
- static bool
- ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
- {
--      struct bcma_device *pci = NULL;
--      struct bcma_device *pcie = NULL;
--      struct bcma_device *core;
--
--
-       /* no cores found, bail out */
-       if (cc->bus->nr_cores == 0)
-               return false;
-@@ -495,8 +464,7 @@ ai_buscore_setup(struct si_info *sii, st
-       sii->pub.ccrev = cc->id.rev;
-       /* get chipcommon chipstatus */
--      if (ai_get_ccrev(&sii->pub) >= 11)
--              sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
-+      sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
-       /* get chipcommon capabilites */
-       sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
-@@ -509,64 +477,18 @@ ai_buscore_setup(struct si_info *sii, st
-       }
-       /* figure out buscore */
--      list_for_each_entry(core, &cc->bus->cores, list) {
--              uint cid, crev;
--
--              cid = core->id.id;
--              crev = core->id.rev;
--
--              if (cid == PCI_CORE_ID) {
--                      pci = core;
--              } else if (cid == PCIE_CORE_ID) {
--                      pcie = core;
--              }
--      }
--
--      if (pci && pcie) {
--              if (ai_ispcie(sii))
--                      pci = NULL;
--              else
--                      pcie = NULL;
--      }
--      if (pci) {
--              sii->buscore = pci;
--      } else if (pcie) {
--              sii->buscore = pcie;
--      }
--
--      /* fixup necessary chip/core configurations */
--      if (!sii->pch) {
--              sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
--              if (sii->pch == NULL)
--                      return false;
--      }
--      if (ai_pci_fixcfg(&sii->pub))
--              return false;
-+      sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
-       return true;
- }
--/*
-- * get boardtype and boardrev
-- */
--static __used void ai_nvram_process(struct si_info *sii)
--{
--      uint w = 0;
--
--      /* do a pci config read to get subsystem id and subvendor id */
--      pci_read_config_dword(sii->pcibus, PCI_SUBSYSTEM_VENDOR_ID, &w);
--
--      sii->pub.boardvendor = w & 0xffff;
--      sii->pub.boardtype = (w >> 16) & 0xffff;
--}
--
- static struct si_info *ai_doattach(struct si_info *sii,
-                                  struct bcma_bus *pbus)
- {
-       struct si_pub *sih = &sii->pub;
-       u32 w, savewin;
-       struct bcma_device *cc;
--      uint socitype;
-+      struct ssb_sprom *sprom = &pbus->sprom;
-       savewin = 0;
-@@ -576,38 +498,15 @@ static struct si_info *ai_doattach(struc
-       /* switch to Chipcommon core */
-       cc = pbus->drv_cc.core;
--      /* bus/core/clk setup for register access */
--      if (!ai_buscore_prep(sii))
--              return NULL;
-+      sih->chip = pbus->chipinfo.id;
-+      sih->chiprev = pbus->chipinfo.rev;
-+      sih->chippkg = pbus->chipinfo.pkg;
-+      sih->boardvendor = pbus->boardinfo.vendor;
-+      sih->boardtype = pbus->boardinfo.type;
--      /*
--       * ChipID recognition.
--       *   We assume we can read chipid at offset 0 from the regs arg.
--       *   If we add other chiptypes (or if we need to support old sdio
--       *   hosts w/o chipcommon), some way of recognizing them needs to
--       *   be added here.
--       */
--      w = bcma_read32(cc, CHIPCREGOFFS(chipid));
--      socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
--      /* Might as wll fill in chip id rev & pkg */
--      sih->chip = w & CID_ID_MASK;
--      sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
--      sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
--
--      /* scan for cores */
--      if (socitype != SOCI_AI)
--              return NULL;
--
--      SI_MSG("Found chip type AI (0x%08x)\n", w);
-       if (!ai_buscore_setup(sii, cc))
-               goto exit;
--      /* Init nvram from sprom/otp if they exist */
--      if (srom_var_init(&sii->pub))
--              goto exit;
--
--      ai_nvram_process(sii);
--
-       /* === NVRAM, clock is ready === */
-       bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
-       bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
-@@ -620,15 +519,13 @@ static struct si_info *ai_doattach(struc
-       }
-       /* setup the GPIO based LED powersave register */
--      w = getintvar(sih, BRCMS_SROM_LEDDC);
-+      w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
-+               (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
-       if (w == 0)
-               w = DEFAULT_GPIOTIMERVAL;
-       ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
-                 ~0, w);
--      if (PCIE(sih))
--              pcicore_attach(sii->pch, SI_DOATTACH);
--
-       if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
-               /*
-                * enable 12 mA drive strenth for 43224 and
-@@ -662,9 +559,6 @@ static struct si_info *ai_doattach(struc
-       return sii;
-  exit:
--      if (sii->pch)
--              pcicore_deinit(sii->pch);
--      sii->pch = NULL;
-       return NULL;
- }
-@@ -703,11 +597,6 @@ void ai_detach(struct si_pub *sih)
-       if (sii == NULL)
-               return;
--      if (sii->pch)
--              pcicore_deinit(sii->pch);
--      sii->pch = NULL;
--
--      srom_free_vars(sih);
-       kfree(sii);
- }
-@@ -758,21 +647,7 @@ uint ai_cc_reg(struct si_pub *sih, uint
- /* return the slow clock source - LPO, XTAL, or PCI */
- static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
- {
--      struct si_info *sii;
--      u32 val;
--
--      sii = (struct si_info *)sih;
--      if (ai_get_ccrev(&sii->pub) < 6) {
--              pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
--                                    &val);
--              if (val & PCI_CFG_GPIO_SCS)
--                      return SCC_SS_PCI;
--              return SCC_SS_XTAL;
--      } else if (ai_get_ccrev(&sii->pub) < 10) {
--              return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
--                     SCC_SS_MASK;
--      } else                  /* Insta-clock */
--              return SCC_SS_XTAL;
-+      return SCC_SS_XTAL;
- }
- /*
-@@ -782,36 +657,12 @@ static uint ai_slowclk_src(struct si_pub
- static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
-                           struct bcma_device *cc)
- {
--      u32 slowclk;
-       uint div;
--      slowclk = ai_slowclk_src(sih, cc);
--      if (ai_get_ccrev(sih) < 6) {
--              if (slowclk == SCC_SS_PCI)
--                      return max_freq ? (PCIMAXFREQ / 64)
--                              : (PCIMINFREQ / 64);
--              else
--                      return max_freq ? (XTALMAXFREQ / 32)
--                              : (XTALMINFREQ / 32);
--      } else if (ai_get_ccrev(sih) < 10) {
--              div = 4 *
--                  (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
--                    SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
--              if (slowclk == SCC_SS_LPO)
--                      return max_freq ? LPOMAXFREQ : LPOMINFREQ;
--              else if (slowclk == SCC_SS_XTAL)
--                      return max_freq ? (XTALMAXFREQ / div)
--                              : (XTALMINFREQ / div);
--              else if (slowclk == SCC_SS_PCI)
--                      return max_freq ? (PCIMAXFREQ / div)
--                              : (PCIMINFREQ / div);
--      } else {
--              /* Chipc rev 10 is InstaClock */
--              div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
--              div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
--              return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
--      }
--      return 0;
-+      /* Chipc rev 10 is InstaClock */
-+      div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
-+      div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
-+      return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
- }
- static void
-@@ -834,8 +685,7 @@ ai_clkctl_setdelay(struct si_pub *sih, s
-       /* Starting with 4318 it is ILP that is used for the delays */
-       slowmaxfreq =
--          ai_slowclk_freq(sih,
--                          (ai_get_ccrev(sih) >= 10) ? false : true, cc);
-+          ai_slowclk_freq(sih, false, cc);
-       pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
-       fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
-@@ -857,9 +707,8 @@ void ai_clkctl_init(struct si_pub *sih)
-               return;
-       /* set all Instaclk chip ILP to 1 MHz */
--      if (ai_get_ccrev(sih) >= 10)
--              bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
--                             (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
-+      bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
-+                     (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
-       ai_clkctl_setdelay(sih, cc);
- }
-@@ -894,140 +743,6 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
-       return fpdelay;
- }
--/* turn primary xtal and/or pll off/on */
--int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
--{
--      struct si_info *sii;
--      u32 in, out, outen;
--
--      sii = (struct si_info *)sih;
--
--      /* pcie core doesn't have any mapping to control the xtal pu */
--      if (PCIE(sih))
--              return -1;
--
--      pci_read_config_dword(sii->pcibus, PCI_GPIO_IN, &in);
--      pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, &out);
--      pci_read_config_dword(sii->pcibus, PCI_GPIO_OUTEN, &outen);
--
--      /*
--       * Avoid glitching the clock if GPRS is already using it.
--       * We can't actually read the state of the PLLPD so we infer it
--       * by the value of XTAL_PU which *is* readable via gpioin.
--       */
--      if (on && (in & PCI_CFG_GPIO_XTAL))
--              return 0;
--
--      if (what & XTAL)
--              outen |= PCI_CFG_GPIO_XTAL;
--      if (what & PLL)
--              outen |= PCI_CFG_GPIO_PLL;
--
--      if (on) {
--              /* turn primary xtal on */
--              if (what & XTAL) {
--                      out |= PCI_CFG_GPIO_XTAL;
--                      if (what & PLL)
--                              out |= PCI_CFG_GPIO_PLL;
--                      pci_write_config_dword(sii->pcibus,
--                                             PCI_GPIO_OUT, out);
--                      pci_write_config_dword(sii->pcibus,
--                                             PCI_GPIO_OUTEN, outen);
--                      udelay(XTAL_ON_DELAY);
--              }
--
--              /* turn pll on */
--              if (what & PLL) {
--                      out &= ~PCI_CFG_GPIO_PLL;
--                      pci_write_config_dword(sii->pcibus,
--                                             PCI_GPIO_OUT, out);
--                      mdelay(2);
--              }
--      } else {
--              if (what & XTAL)
--                      out &= ~PCI_CFG_GPIO_XTAL;
--              if (what & PLL)
--                      out |= PCI_CFG_GPIO_PLL;
--              pci_write_config_dword(sii->pcibus,
--                                     PCI_GPIO_OUT, out);
--              pci_write_config_dword(sii->pcibus,
--                                     PCI_GPIO_OUTEN, outen);
--      }
--
--      return 0;
--}
--
--/* clk control mechanism through chipcommon, no policy checking */
--static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
--{
--      struct bcma_device *cc;
--      u32 scc;
--
--      /* chipcommon cores prior to rev6 don't support dynamic clock control */
--      if (ai_get_ccrev(&sii->pub) < 6)
--              return false;
--
--      cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
--
--      if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
--          (ai_get_ccrev(&sii->pub) < 20))
--              return mode == CLK_FAST;
--
--      switch (mode) {
--      case CLK_FAST:          /* FORCEHT, fast (pll) clock */
--              if (ai_get_ccrev(&sii->pub) < 10) {
--                      /*
--                       * don't forget to force xtal back
--                       * on before we clear SCC_DYN_XTAL..
--                       */
--                      ai_clkctl_xtal(&sii->pub, XTAL, ON);
--                      bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
--                                     (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
--              } else if (ai_get_ccrev(&sii->pub) < 20) {
--                      bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
--              } else {
--                      bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
--              }
--
--              /* wait for the PLL */
--              if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
--                      u32 htavail = CCS_HTAVAIL;
--                      SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) &
--                                 htavail) == 0), PMU_MAX_TRANSITION_DLY);
--              } else {
--                      udelay(PLL_DELAY);
--              }
--              break;
--
--      case CLK_DYNAMIC:       /* enable dynamic clock control */
--              if (ai_get_ccrev(&sii->pub) < 10) {
--                      scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
--                      scc &= ~(SCC_FS | SCC_IP | SCC_XC);
--                      if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
--                              scc |= SCC_XC;
--                      bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
--
--                      /*
--                       * for dynamic control, we have to
--                       * release our xtal_pu "force on"
--                       */
--                      if (scc & SCC_XC)
--                              ai_clkctl_xtal(&sii->pub, XTAL, OFF);
--              } else if (ai_get_ccrev(&sii->pub) < 20) {
--                      /* Instaclock */
--                      bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
--              } else {
--                      bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
--              }
--              break;
--
--      default:
--              break;
--      }
--
--      return mode == CLK_FAST;
--}
--
- /*
-  *  clock control policy function throught chipcommon
-  *
-@@ -1036,133 +751,53 @@ static bool _ai_clkctl_cc(struct si_info
-  *    this is a wrapper over the next internal function
-  *      to allow flexible policy settings for outside caller
-  */
--bool ai_clkctl_cc(struct si_pub *sih, uint mode)
-+bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode)
- {
-       struct si_info *sii;
-+      struct bcma_device *cc;
-       sii = (struct si_info *)sih;
--      /* chipcommon cores prior to rev6 don't support dynamic clock control */
--      if (ai_get_ccrev(sih) < 6)
--              return false;
--
-       if (PCI_FORCEHT(sih))
--              return mode == CLK_FAST;
-+              return mode == BCMA_CLKMODE_FAST;
--      return _ai_clkctl_cc(sii, mode);
-+      cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
-+      bcma_core_set_clockmode(cc, mode);
-+      return mode == BCMA_CLKMODE_FAST;
- }
- void ai_pci_up(struct si_pub *sih)
- {
-       struct si_info *sii;
-+      struct bcma_device *cc;
-       sii = (struct si_info *)sih;
--      if (PCI_FORCEHT(sih))
--              _ai_clkctl_cc(sii, CLK_FAST);
-+      if (PCI_FORCEHT(sih)) {
-+              cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
-+              bcma_core_set_clockmode(cc, BCMA_CLKMODE_FAST);
-+      }
-       if (PCIE(sih))
--              pcicore_up(sii->pch, SI_PCIUP);
--
--}
--
--/* Unconfigure and/or apply various WARs when system is going to sleep mode */
--void ai_pci_sleep(struct si_pub *sih)
--{
--      struct si_info *sii;
--
--      sii = (struct si_info *)sih;
--
--      pcicore_sleep(sii->pch);
-+              bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
- }
- /* Unconfigure and/or apply various WARs when going down */
- void ai_pci_down(struct si_pub *sih)
- {
-       struct si_info *sii;
-+      struct bcma_device *cc;
-       sii = (struct si_info *)sih;
-       /* release FORCEHT since chip is going to "down" state */
--      if (PCI_FORCEHT(sih))
--              _ai_clkctl_cc(sii, CLK_DYNAMIC);
--
--      pcicore_down(sii->pch, SI_PCIDOWN);
--}
--
--/*
-- * Configure the pci core for pci client (NIC) action
-- * coremask is the bitvec of cores by index to be enabled.
-- */
--void ai_pci_setup(struct si_pub *sih, uint coremask)
--{
--      struct si_info *sii;
--      u32 w;
--
--      sii = (struct si_info *)sih;
--
--      /*
--       * Enable sb->pci interrupts.  Assume
--       * PCI rev 2.3 support was added in pci core rev 6 and things changed..
--       */
--      if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
--              /* pci config write to set this core bit in PCIIntMask */
--              pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
--              w |= (coremask << PCI_SBIM_SHIFT);
--              pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
--      }
--
--      if (PCI(sih)) {
--              pcicore_pci_setup(sii->pch);
-+      if (PCI_FORCEHT(sih)) {
-+              cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
-+              bcma_core_set_clockmode(cc, BCMA_CLKMODE_DYNAMIC);
-       }
--}
--
--/*
-- * Fixup SROMless PCI device's configuration.
-- * The current core may be changed upon return.
-- */
--int ai_pci_fixcfg(struct si_pub *sih)
--{
--      struct si_info *sii = (struct si_info *)sih;
--
--      /* Fixup PI in SROM shadow area to enable the correct PCI core access */
--      /* check 'pi' is correct and fix it if not */
--      pcicore_fixcfg(sii->pch);
--      pcicore_hwup(sii->pch);
--      return 0;
--}
--
--/* mask&set gpiocontrol bits */
--u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
--{
--      uint regoff;
--
--      regoff = offsetof(struct chipcregs, gpiocontrol);
--      return ai_cc_reg(sih, regoff, mask, val);
--}
--
--void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
--{
--      struct bcma_device *cc;
--      u32 val;
--
--      cc = ai_findcore(sih, CC_CORE_ID, 0);
--      if (on) {
--              if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
--                      /* Ext PA Controls for 4331 12x9 Package */
--                      bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
--                                 CCTRL4331_EXTPA_EN |
--                                 CCTRL4331_EXTPA_ON_GPIO2_5);
--              else
--                      /* Ext PA Controls for 4331 12x12 Package */
--                      bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
--                                 CCTRL4331_EXTPA_EN);
--      } else {
--              val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
--              bcma_mask32(cc, CHIPCREGOFFS(chipcontrol),
--                          ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5));
--      }
-+      if (PCIE(sih))
-+              bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
- }
- /* Enable BT-COEX & Ex-PA for 4313 */
-@@ -1184,6 +819,9 @@ bool ai_deviceremoved(struct si_pub *sih
-       sii = (struct si_info *)sih;
-+      if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
-+              return false;
-+
-       pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);
-       if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
-               return true;
-@@ -1191,45 +829,6 @@ bool ai_deviceremoved(struct si_pub *sih
-       return false;
- }
--bool ai_is_sprom_available(struct si_pub *sih)
--{
--      struct si_info *sii = (struct si_info *)sih;
--
--      if (ai_get_ccrev(sih) >= 31) {
--              struct bcma_device *cc;
--              u32 sromctrl;
--
--              if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
--                      return false;
--
--              cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
--              sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol));
--              return sromctrl & SRC_PRESENT;
--      }
--
--      switch (ai_get_chip_id(sih)) {
--      case BCM4313_CHIP_ID:
--              return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
--      default:
--              return true;
--      }
--}
--
--bool ai_is_otp_disabled(struct si_pub *sih)
--{
--      struct si_info *sii = (struct si_info *)sih;
--
--      switch (ai_get_chip_id(sih)) {
--      case BCM4313_CHIP_ID:
--              return (sii->chipst & CST4313_OTP_PRESENT) == 0;
--              /* These chips always have their OTP on */
--      case BCM43224_CHIP_ID:
--      case BCM43225_CHIP_ID:
--      default:
--              return false;
--      }
--}
--
- uint ai_get_buscoretype(struct si_pub *sih)
- {
-       struct si_info *sii = (struct si_info *)sih;
---- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
-@@ -113,10 +113,6 @@
- #define       XTAL                    0x1     /* primary crystal oscillator (2050) */
- #define       PLL                     0x2     /* main chip pll */
--/* clkctl clk mode */
--#define       CLK_FAST                0       /* force fast (pll) clock */
--#define       CLK_DYNAMIC             2       /* enable dynamic clock control */
--
- /* GPIO usage priorities */
- #define GPIO_DRV_PRIORITY     0       /* Driver */
- #define GPIO_APP_PRIORITY     1       /* Application */
-@@ -172,9 +168,7 @@ struct si_info {
-       struct si_pub pub;      /* back plane public state (must be first) */
-       struct bcma_bus *icbus; /* handle to soc interconnect bus */
-       struct pci_dev *pcibus; /* handle to pci bus */
--      struct pcicore_info *pch; /* PCI/E core handle */
-       struct bcma_device *buscore;
--      struct list_head var_list; /* list of srom variables */
-       u32 chipst;             /* chip status */
- };
-@@ -197,38 +191,20 @@ extern u32 ai_core_cflags(struct bcma_de
- extern struct si_pub *ai_attach(struct bcma_bus *pbus);
- extern void ai_detach(struct si_pub *sih);
- extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
--extern void ai_pci_setup(struct si_pub *sih, uint coremask);
- extern void ai_clkctl_init(struct si_pub *sih);
- extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
- extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
--extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
- extern bool ai_deviceremoved(struct si_pub *sih);
--extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
--                           u8 priority);
--
--/* OTP status */
--extern bool ai_is_otp_disabled(struct si_pub *sih);
--
--/* SPROM availability */
--extern bool ai_is_sprom_available(struct si_pub *sih);
--extern void ai_pci_sleep(struct si_pub *sih);
- extern void ai_pci_down(struct si_pub *sih);
- extern void ai_pci_up(struct si_pub *sih);
--extern int ai_pci_fixcfg(struct si_pub *sih);
--extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
- /* Enable Ex-PA for 4313 */
- extern void ai_epa_4313war(struct si_pub *sih);
- extern uint ai_get_buscoretype(struct si_pub *sih);
- extern uint ai_get_buscorerev(struct si_pub *sih);
--static inline int ai_get_ccrev(struct si_pub *sih)
--{
--      return sih->ccrev;
--}
--
- static inline u32 ai_get_cccaps(struct si_pub *sih)
- {
-       return sih->cccaps;
---- a/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
-@@ -108,7 +108,7 @@ brcms_c_antsel_init_cfg(struct antsel_in
- struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
- {
-       struct antsel_info *asi;
--      struct si_pub *sih = wlc->hw->sih;
-+      struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
-       asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
-       if (!asi)
-@@ -118,7 +118,7 @@ struct antsel_info *brcms_c_antsel_attac
-       asi->pub = wlc->pub;
-       asi->antsel_type = ANTSEL_NA;
-       asi->antsel_avail = false;
--      asi->antsel_antswitch = (u8) getintvar(sih, BRCMS_SROM_ANTSWITCH);
-+      asi->antsel_antswitch = sprom->antswitch;
-       if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
-               switch (asi->antsel_antswitch) {
-@@ -128,12 +128,12 @@ struct antsel_info *brcms_c_antsel_attac
-                       /* 4321/2 board with 2x3 switch logic */
-                       asi->antsel_type = ANTSEL_2x3;
-                       /* Antenna selection availability */
--                      if (((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) ||
--                          ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 7)) {
-+                      if ((sprom->ant_available_bg == 7) ||
-+                          (sprom->ant_available_a == 7)) {
-                               asi->antsel_avail = true;
-                       } else if (
--                              (u16) getintvar(sih, BRCMS_SROM_AA2G) == 3 ||
--                              (u16) getintvar(sih, BRCMS_SROM_AA5G) == 3) {
-+                              sprom->ant_available_bg == 3 ||
-+                              sprom->ant_available_a == 3) {
-                               asi->antsel_avail = false;
-                       } else {
-                               asi->antsel_avail = false;
-@@ -146,8 +146,8 @@ struct antsel_info *brcms_c_antsel_attac
-                       break;
-               }
-       } else if ((asi->pub->sromrev == 4) &&
--                 ((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) &&
--                 ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 0)) {
-+                 (sprom->ant_available_bg == 7) &&
-+                 (sprom->ant_available_a == 0)) {
-               /* hack to match old 4321CB2 cards with 2of3 antenna switch */
-               asi->antsel_type = ANTSEL_2x3;
-               asi->antsel_avail = true;
---- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
-@@ -1110,7 +1110,7 @@ struct brcms_cm_info *brcms_c_channel_mg
-       char country_abbrev[BRCM_CNTRY_BUF_SZ];
-       const struct country_info *country;
-       struct brcms_pub *pub = wlc->pub;
--      char *ccode;
-+      struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
-       BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-@@ -1122,9 +1122,8 @@ struct brcms_cm_info *brcms_c_channel_mg
-       wlc->cmi = wlc_cm;
-       /* store the country code for passing up as a regulatory hint */
--      ccode = getvar(wlc->hw->sih, BRCMS_SROM_CCODE);
--      if (ccode && brcms_c_country_valid(ccode))
--              strncpy(wlc->pub->srom_ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
-+      if (sprom->alpha2 && brcms_c_country_valid(sprom->alpha2))
-+              strncpy(wlc->pub->srom_ccode, sprom->alpha2, sizeof(sprom->alpha2));
-       /*
-        * internal country information which must match
---- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
-@@ -28,7 +28,6 @@
- #include <linux/bcma/bcma.h>
- #include <net/mac80211.h>
- #include <defs.h>
--#include "nicpci.h"
- #include "phy/phy_int.h"
- #include "d11.h"
- #include "channel.h"
-@@ -773,7 +772,7 @@ void brcms_dpc(unsigned long data)
-  * Precondition: Since this function is called in brcms_pci_probe() context,
-  * no locking is required.
-  */
--static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev)
-+static int brcms_request_fw(struct brcms_info *wl, struct bcma_device *pdev)
- {
-       int status;
-       struct device *device = &pdev->dev;
-@@ -1025,7 +1024,7 @@ static struct brcms_info *brcms_attach(s
-       spin_lock_init(&wl->isr_lock);
-       /* prepare ucode */
--      if (brcms_request_fw(wl, pdev->bus->host_pci) < 0) {
-+      if (brcms_request_fw(wl, pdev) < 0) {
-               wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
-                         "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
-               brcms_release_fw(wl);
-@@ -1046,12 +1045,12 @@ static struct brcms_info *brcms_attach(s
-       wl->pub->ieee_hw = hw;
-       /* register our interrupt handler */
--      if (request_irq(pdev->bus->host_pci->irq, brcms_isr,
-+      if (request_irq(pdev->irq, brcms_isr,
-                       IRQF_SHARED, KBUILD_MODNAME, wl)) {
-               wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
-               goto fail;
-       }
--      wl->irq = pdev->bus->host_pci->irq;
-+      wl->irq = pdev->irq;
-       /* register module */
-       brcms_c_module_register(wl->pub, "linux", wl, NULL);
-@@ -1101,7 +1100,7 @@ static int __devinit brcms_bcma_probe(st
-       dev_info(&pdev->dev, "mfg %x core %x rev %d class %d irq %d\n",
-                pdev->id.manuf, pdev->id.id, pdev->id.rev, pdev->id.class,
--               pdev->bus->host_pci->irq);
-+               pdev->irq);
-       if ((pdev->id.manuf != BCMA_MANUF_BCM) ||
-           (pdev->id.id != BCMA_CORE_80211))
---- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
-@@ -850,8 +850,7 @@ brcms_c_dotxstatus(struct brcms_c_info *
-        */
-       if (!(txs->status & TX_STATUS_AMPDU)
-           && (txs->status & TX_STATUS_INTERMEDIATE)) {
--              wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
--                        __func__);
-+              BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
-               return false;
-       }
-@@ -1223,7 +1222,7 @@ static void brcms_b_wait_for_wake(struct
- }
- /* control chip clock to save power, enable dynamic clock or force fast clock */
--static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
-+static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
- {
-       if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
-               /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
-@@ -1233,7 +1232,7 @@ static void brcms_b_clkctl_clk(struct br
-                */
-               if (wlc_hw->clk) {
--                      if (mode == CLK_FAST) {
-+                      if (mode == BCMA_CLKMODE_FAST) {
-                               bcma_set32(wlc_hw->d11core,
-                                          D11REGOFFS(clk_ctl_st),
-                                          CCS_FORCEHT);
-@@ -1264,7 +1263,7 @@ static void brcms_b_clkctl_clk(struct br
-                                       ~CCS_FORCEHT);
-                       }
-               }
--              wlc_hw->forcefastclk = (mode == CLK_FAST);
-+              wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
-       } else {
-               /* old chips w/o PMU, force HT through cc,
-@@ -1571,7 +1570,7 @@ void brcms_b_bw_set(struct brcms_hardwar
-       /* request FAST clock if not on */
-       fastclk = wlc_hw->forcefastclk;
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
-@@ -1580,7 +1579,7 @@ void brcms_b_bw_set(struct brcms_hardwar
-       /* restore the clk */
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
- }
- static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
-@@ -1886,27 +1885,20 @@ static bool brcms_c_validboardtype(struc
-       return true;
- }
--static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
-+static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
- {
--      enum brcms_srom_id var_id = BRCMS_SROM_MACADDR;
--      char *macaddr;
-+      struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
-       /* If macaddr exists, use it (Sromrev4, CIS, ...). */
--      macaddr = getvar(wlc_hw->sih, var_id);
--      if (macaddr != NULL)
--              return macaddr;
-+      if (!is_zero_ether_addr(sprom->il0mac)) {
-+              memcpy(etheraddr, sprom->il0mac, 6);
-+              return;
-+      }
-       if (wlc_hw->_nbands > 1)
--              var_id = BRCMS_SROM_ET1MACADDR;
-+              memcpy(etheraddr, sprom->et1mac, 6);
-       else
--              var_id = BRCMS_SROM_IL0MACADDR;
--
--      macaddr = getvar(wlc_hw->sih, var_id);
--      if (macaddr == NULL)
--              wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
--                        "getvar(%d) not found\n", wlc_hw->unit, var_id);
--
--      return macaddr;
-+              memcpy(etheraddr, sprom->il0mac, 6);
- }
- /* power both the pll and external oscillator on/off */
-@@ -1921,9 +1913,6 @@ static void brcms_b_xtal(struct brcms_ha
-       if (!want && wlc_hw->pllreq)
-               return;
--      if (wlc_hw->sih)
--              ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
--
-       wlc_hw->sbclk = want;
-       if (!wlc_hw->sbclk) {
-               wlc_hw->clk = false;
-@@ -2008,7 +1997,7 @@ void brcms_b_corereset(struct brcms_hard
-       /* request FAST clock if not on  */
-       fastclk = wlc_hw->forcefastclk;
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       /* reset the dma engines except first time thru */
-       if (bcma_core_is_enabled(wlc_hw->d11core)) {
-@@ -2057,7 +2046,7 @@ void brcms_b_corereset(struct brcms_hard
-       brcms_c_mctrl_reset(wlc_hw);
-       if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
--              brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       brcms_b_phy_reset(wlc_hw);
-@@ -2069,7 +2058,7 @@ void brcms_b_corereset(struct brcms_hard
-       /* restore the clk setting */
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
- }
- /* txfifo sizes needs to be modified(increased) since the newer cores
-@@ -2222,7 +2211,7 @@ static void brcms_c_gpio_init(struct brc
-               gm |= gc |= BOARD_GPIO_PACTRL;
-       /* apply to gpiocontrol register */
--      ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
-+      bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
- }
- static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
-@@ -3375,7 +3364,7 @@ static brcms_b_init(struct brcms_hardwar
-       /* request FAST clock if not on */
-       fastclk = wlc_hw->forcefastclk;
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       /* disable interrupts */
-       macintmask = brcms_intrsoff(wlc->wl);
-@@ -3409,7 +3398,7 @@ static brcms_b_init(struct brcms_hardwar
-       /* restore the clk */
-       if (!fastclk)
--              brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
- }
- static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
-@@ -4440,17 +4429,22 @@ static int brcms_b_attach(struct brcms_c
-                         uint unit, bool piomode)
- {
-       struct brcms_hardware *wlc_hw;
--      char *macaddr = NULL;
-       uint err = 0;
-       uint j;
-       bool wme = false;
-       struct shared_phy_params sha_params;
-       struct wiphy *wiphy = wlc->wiphy;
-       struct pci_dev *pcidev = core->bus->host_pci;
-+      struct ssb_sprom *sprom = &core->bus->sprom;
--      BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
--             pcidev->vendor,
--             pcidev->device);
-+      if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
-+              BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
-+                     pcidev->vendor,
-+                     pcidev->device);
-+      else
-+              BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
-+                     core->bus->boardinfo.vendor,
-+                     core->bus->boardinfo.type);
-       wme = true;
-@@ -4476,7 +4470,8 @@ static int brcms_b_attach(struct brcms_c
-       }
-       /* verify again the device is supported */
--      if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
-+      if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
-+          !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
-               wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
-                       "vendor/device (0x%x/0x%x)\n",
-                        unit, pcidev->vendor, pcidev->device);
-@@ -4484,8 +4479,13 @@ static int brcms_b_attach(struct brcms_c
-               goto fail;
-       }
--      wlc_hw->vendorid = pcidev->vendor;
--      wlc_hw->deviceid = pcidev->device;
-+      if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
-+              wlc_hw->vendorid = pcidev->vendor;
-+              wlc_hw->deviceid = pcidev->device;
-+      } else {
-+              wlc_hw->vendorid = core->bus->boardinfo.vendor;
-+              wlc_hw->deviceid = core->bus->boardinfo.type;
-+      }
-       wlc_hw->d11core = core;
-       wlc_hw->corerev = core->id.rev;
-@@ -4505,7 +4505,7 @@ static int brcms_b_attach(struct brcms_c
-        *   is still false; But it will be called again inside wlc_corereset,
-        *   after d11 is out of reset.
-        */
--      brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+      brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
-       if (!brcms_b_validate_chip_access(wlc_hw)) {
-@@ -4516,7 +4516,7 @@ static int brcms_b_attach(struct brcms_c
-       }
-       /* get the board rev, used just below */
--      j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV);
-+      j = sprom->board_rev;
-       /* promote srom boardrev of 0xFF to 1 */
-       if (j == BOARDREV_PROMOTABLE)
-               j = BOARDREV_PROMOTED;
-@@ -4529,11 +4529,9 @@ static int brcms_b_attach(struct brcms_c
-               err = 15;
-               goto fail;
-       }
--      wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV);
--      wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih,
--                                           BRCMS_SROM_BOARDFLAGS);
--      wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
--                                            BRCMS_SROM_BOARDFLAGS2);
-+      wlc_hw->sromrev = sprom->revision;
-+      wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
-+      wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
-       if (wlc_hw->boardflags & BFL_NOPLLDOWN)
-               brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
-@@ -4706,25 +4704,18 @@ static int brcms_b_attach(struct brcms_c
-        */
-       /* init etheraddr state variables */
--      macaddr = brcms_c_get_macaddr(wlc_hw);
--      if (macaddr == NULL) {
--              wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
--                        unit);
--              err = 21;
--              goto fail;
--      }
--      if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
--          is_broadcast_ether_addr(wlc_hw->etheraddr) ||
-+      brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
-+
-+      if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
-           is_zero_ether_addr(wlc_hw->etheraddr)) {
--              wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
--                        unit, macaddr);
-+              wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
-+                        unit);
-               err = 22;
-               goto fail;
-       }
--      BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
--             wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih),
--             macaddr);
-+      BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
-+             wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
-       return err;
-@@ -4774,16 +4765,16 @@ static bool brcms_c_attach_stf_ant_init(
-       int aa;
-       uint unit;
-       int bandtype;
--      struct si_pub *sih = wlc->hw->sih;
-+      struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
-       unit = wlc->pub->unit;
-       bandtype = wlc->band->bandtype;
-       /* get antennas available */
-       if (bandtype == BRCM_BAND_5G)
--              aa = (s8) getintvar(sih, BRCMS_SROM_AA5G);
-+              aa = sprom->ant_available_a;
-       else
--              aa = (s8) getintvar(sih, BRCMS_SROM_AA2G);
-+              aa = sprom->ant_available_bg;
-       if ((aa < 1) || (aa > 15)) {
-               wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
-@@ -4803,9 +4794,9 @@ static bool brcms_c_attach_stf_ant_init(
-       /* Compute Antenna Gain */
-       if (bandtype == BRCM_BAND_5G)
--              wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1);
-+              wlc->band->antgain = sprom->antenna_gain.a1;
-       else
--              wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0);
-+              wlc->band->antgain = sprom->antenna_gain.a0;
-       brcms_c_attach_antgain_init(wlc);
-@@ -4956,15 +4947,6 @@ static int brcms_b_detach(struct brcms_c
-       callbacks = 0;
--      if (wlc_hw->sih) {
--              /*
--               * detach interrupt sync mechanism since interrupt is disabled
--               * and per-port interrupt object may has been freed. this must
--               * be done before sb core switch
--               */
--              ai_pci_sleep(wlc_hw->sih);
--      }
--
-       brcms_b_detach_dmapio(wlc_hw);
-       band = wlc_hw->band;
-@@ -5051,9 +5033,7 @@ static void brcms_b_hw_up(struct brcms_h
-        */
-       brcms_b_xtal(wlc_hw, ON);
-       ai_clkctl_init(wlc_hw->sih);
--      brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
--
--      ai_pci_fixcfg(wlc_hw->sih);
-+      brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       /*
-        * TODO: test suspend/resume
-@@ -5082,8 +5062,6 @@ static void brcms_b_hw_up(struct brcms_h
- static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
- {
--      uint coremask;
--
-       BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-       /*
-@@ -5092,15 +5070,14 @@ static int brcms_b_up_prep(struct brcms_
-        */
-       brcms_b_xtal(wlc_hw, ON);
-       ai_clkctl_init(wlc_hw->sih);
--      brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+      brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       /*
-        * Configure pci/pcmcia here instead of in brcms_c_attach()
-        * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
-        */
--      coremask = (1 << wlc_hw->wlc->core->coreidx);
--
--      ai_pci_setup(wlc_hw->sih, coremask);
-+      bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
-+                            true);
-       /*
-        * Need to read the hwradio status here to cover the case where the
-@@ -5130,7 +5107,7 @@ static int brcms_b_up_finish(struct brcm
-       wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
-       /* FULLY enable dynamic power control and d11 core interrupt */
--      brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-+      brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
-       brcms_intrson(wlc_hw->wlc->wl);
-       return 0;
- }
-@@ -5271,7 +5248,7 @@ static int brcms_b_bmac_down_prep(struct
-               brcms_intrsoff(wlc_hw->wlc->wl);
-               /* ensure we're running on the pll clock again */
--              brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
-+              brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
-       }
-       /* down phy at the last of this stage */
-       callbacks += wlc_phy_down(wlc_hw->band->pi);
---- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
-+++ /dev/null
-@@ -1,826 +0,0 @@
--/*
-- * Copyright (c) 2010 Broadcom Corporation
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
-- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- */
--
--#include <linux/slab.h>
--#include <linux/delay.h>
--#include <linux/pci.h>
--
--#include <defs.h>
--#include <soc.h>
--#include <chipcommon.h>
--#include "aiutils.h"
--#include "pub.h"
--#include "nicpci.h"
--
--/* SPROM offsets */
--#define SRSH_ASPM_OFFSET              4       /* word 4 */
--#define SRSH_ASPM_ENB                 0x18    /* bit 3, 4 */
--#define SRSH_ASPM_L1_ENB              0x10    /* bit 4 */
--#define SRSH_ASPM_L0s_ENB             0x8     /* bit 3 */
--
--#define SRSH_PCIE_MISC_CONFIG         5       /* word 5 */
--#define SRSH_L23READY_EXIT_NOPERST    0x8000  /* bit 15 */
--#define SRSH_CLKREQ_OFFSET_REV5               20      /* word 20 for srom rev <= 5 */
--#define SRSH_CLKREQ_ENB                       0x0800  /* bit 11 */
--#define SRSH_BD_OFFSET                  6     /* word 6 */
--
--/* chipcontrol */
--#define CHIPCTRL_4321_PLL_DOWN                0x800000/* serdes PLL down override */
--
--/* MDIO control */
--#define MDIOCTL_DIVISOR_MASK          0x7f    /* clock to be used on MDIO */
--#define MDIOCTL_DIVISOR_VAL           0x2
--#define MDIOCTL_PREAM_EN              0x80    /* Enable preamble sequnce */
--#define MDIOCTL_ACCESS_DONE           0x100   /* Transaction complete */
--
--/* MDIO Data */
--#define MDIODATA_MASK                 0x0000ffff      /* data 2 bytes */
--#define MDIODATA_TA                   0x00020000      /* Turnaround */
--
--#define MDIODATA_REGADDR_SHF          18              /* Regaddr shift */
--#define MDIODATA_REGADDR_MASK         0x007c0000      /* Regaddr Mask */
--#define MDIODATA_DEVADDR_SHF          23      /* Physmedia devaddr shift */
--#define MDIODATA_DEVADDR_MASK         0x0f800000
--                                              /* Physmedia devaddr Mask */
--
--/* MDIO Data for older revisions < 10 */
--#define MDIODATA_REGADDR_SHF_OLD      18      /* Regaddr shift */
--#define MDIODATA_REGADDR_MASK_OLD     0x003c0000
--                                              /* Regaddr Mask */
--#define MDIODATA_DEVADDR_SHF_OLD      22      /* Physmedia devaddr shift  */
--#define MDIODATA_DEVADDR_MASK_OLD     0x0fc00000
--                                              /* Physmedia devaddr Mask */
--
--/* Transactions flags */
--#define MDIODATA_WRITE                        0x10000000
--#define MDIODATA_READ                 0x20000000
--#define MDIODATA_START                        0x40000000
--
--#define MDIODATA_DEV_ADDR             0x0     /* dev address for serdes */
--#define       MDIODATA_BLK_ADDR               0x1F    /* blk address for serdes */
--
--/* serdes regs (rev < 10) */
--#define MDIODATA_DEV_PLL              0x1d    /* SERDES PLL Dev */
--#define MDIODATA_DEV_TX                       0x1e    /* SERDES TX Dev */
--#define MDIODATA_DEV_RX                       0x1f    /* SERDES RX Dev */
--
--/* SERDES RX registers */
--#define SERDES_RX_CTRL                        1       /* Rx cntrl */
--#define SERDES_RX_TIMER1              2       /* Rx Timer1 */
--#define SERDES_RX_CDR                 6       /* CDR */
--#define SERDES_RX_CDRBW                       7       /* CDR BW */
--/* SERDES RX control register */
--#define SERDES_RX_CTRL_FORCE          0x80    /* rxpolarity_force */
--#define SERDES_RX_CTRL_POLARITY               0x40    /* rxpolarity_value */
--
--/* SERDES PLL registers */
--#define SERDES_PLL_CTRL                 1     /* PLL control reg */
--#define PLL_CTRL_FREQDET_EN             0x4000        /* bit 14 is FREQDET on */
--
--/* Linkcontrol reg offset in PCIE Cap */
--#define PCIE_CAP_LINKCTRL_OFFSET      16      /* offset in pcie cap */
--#define PCIE_CAP_LCREG_ASPML0s                0x01    /* ASPM L0s in linkctrl */
--#define PCIE_CAP_LCREG_ASPML1         0x02    /* ASPM L1 in linkctrl */
--#define PCIE_CLKREQ_ENAB              0x100   /* CLKREQ Enab in linkctrl */
--
--#define PCIE_ASPM_ENAB                        3       /* ASPM L0s & L1 in linkctrl */
--#define PCIE_ASPM_L1_ENAB             2       /* ASPM L0s & L1 in linkctrl */
--#define PCIE_ASPM_L0s_ENAB            1       /* ASPM L0s & L1 in linkctrl */
--#define PCIE_ASPM_DISAB                       0       /* ASPM L0s & L1 in linkctrl */
--
--/* Power management threshold */
--#define PCIE_L1THRESHOLDTIME_MASK       0xFF00        /* bits 8 - 15 */
--#define PCIE_L1THRESHOLDTIME_SHIFT      8     /* PCIE_L1THRESHOLDTIME_SHIFT */
--#define PCIE_L1THRESHOLD_WARVAL         0x72  /* WAR value */
--#define PCIE_ASPMTIMER_EXTEND         0x01000000
--                                              /* > rev7:
--                                               * enable extend ASPM timer
--                                               */
--
--/* different register spaces to access thru pcie indirect access */
--#define PCIE_CONFIGREGS               1       /* Access to config space */
--#define PCIE_PCIEREGS         2       /* Access to pcie registers */
--
--/* PCIE protocol PHY diagnostic registers */
--#define       PCIE_PLP_STATUSREG              0x204   /* Status */
--
--/* Status reg PCIE_PLP_STATUSREG */
--#define PCIE_PLP_POLARITYINV_STAT     0x10
--
--/* PCIE protocol DLLP diagnostic registers */
--#define PCIE_DLLP_LCREG                       0x100   /* Link Control */
--#define PCIE_DLLP_PMTHRESHREG         0x128   /* Power Management Threshold */
--
--/* PCIE protocol TLP diagnostic registers */
--#define PCIE_TLP_WORKAROUNDSREG               0x004   /* TLP Workarounds */
--
--/* Sonics to PCI translation types */
--#define       SBTOPCI_PREF    0x4             /* prefetch enable */
--#define       SBTOPCI_BURST   0x8             /* burst enable */
--#define       SBTOPCI_RC_READMULTI    0x20    /* memory read multiple */
--
--#define PCI_CLKRUN_DSBL       0x8000  /* Bit 15 forceClkrun */
--
--/* PCI core index in SROM shadow area */
--#define SRSH_PI_OFFSET        0       /* first word */
--#define SRSH_PI_MASK  0xf000  /* bit 15:12 */
--#define SRSH_PI_SHIFT 12      /* bit 15:12 */
--
--#define PCIREGOFFS(field)     offsetof(struct sbpciregs, field)
--#define PCIEREGOFFS(field)    offsetof(struct sbpcieregs, field)
--
--/* Sonics side: PCI core and host control registers */
--struct sbpciregs {
--      u32 control;            /* PCI control */
--      u32 PAD[3];
--      u32 arbcontrol;         /* PCI arbiter control */
--      u32 clkrun;             /* Clkrun Control (>=rev11) */
--      u32 PAD[2];
--      u32 intstatus;          /* Interrupt status */
--      u32 intmask;            /* Interrupt mask */
--      u32 sbtopcimailbox;     /* Sonics to PCI mailbox */
--      u32 PAD[9];
--      u32 bcastaddr;          /* Sonics broadcast address */
--      u32 bcastdata;          /* Sonics broadcast data */
--      u32 PAD[2];
--      u32 gpioin;             /* ro: gpio input (>=rev2) */
--      u32 gpioout;            /* rw: gpio output (>=rev2) */
--      u32 gpioouten;          /* rw: gpio output enable (>= rev2) */
--      u32 gpiocontrol;        /* rw: gpio control (>= rev2) */
--      u32 PAD[36];
--      u32 sbtopci0;           /* Sonics to PCI translation 0 */
--      u32 sbtopci1;           /* Sonics to PCI translation 1 */
--      u32 sbtopci2;           /* Sonics to PCI translation 2 */
--      u32 PAD[189];
--      u32 pcicfg[4][64];      /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
--      u16 sprom[36];          /* SPROM shadow Area */
--      u32 PAD[46];
--};
--
--/* SB side: PCIE core and host control registers */
--struct sbpcieregs {
--      u32 control;            /* host mode only */
--      u32 PAD[2];
--      u32 biststatus;         /* bist Status: 0x00C */
--      u32 gpiosel;            /* PCIE gpio sel: 0x010 */
--      u32 gpioouten;          /* PCIE gpio outen: 0x14 */
--      u32 PAD[2];
--      u32 intstatus;          /* Interrupt status: 0x20 */
--      u32 intmask;            /* Interrupt mask: 0x24 */
--      u32 sbtopcimailbox;     /* sb to pcie mailbox: 0x028 */
--      u32 PAD[53];
--      u32 sbtopcie0;          /* sb to pcie translation 0: 0x100 */
--      u32 sbtopcie1;          /* sb to pcie translation 1: 0x104 */
--      u32 sbtopcie2;          /* sb to pcie translation 2: 0x108 */
--      u32 PAD[5];
--
--      /* pcie core supports in direct access to config space */
--      u32 configaddr; /* pcie config space access: Address field: 0x120 */
--      u32 configdata; /* pcie config space access: Data field: 0x124 */
--
--      /* mdio access to serdes */
--      u32 mdiocontrol;        /* controls the mdio access: 0x128 */
--      u32 mdiodata;           /* Data to the mdio access: 0x12c */
--
--      /* pcie protocol phy/dllp/tlp register indirect access mechanism */
--      u32 pcieindaddr;        /* indirect access to
--                               * the internal register: 0x130
--                               */
--      u32 pcieinddata;        /* Data to/from the internal regsiter: 0x134 */
--
--      u32 clkreqenctrl;       /* >= rev 6, Clkreq rdma control : 0x138 */
--      u32 PAD[177];
--      u32 pciecfg[4][64];     /* 0x400 - 0x7FF, PCIE Cfg Space */
--      u16 sprom[64];          /* SPROM shadow Area */
--};
--
--struct pcicore_info {
--      struct bcma_device *core;
--      struct si_pub *sih;     /* System interconnect handle */
--      struct pci_dev *dev;
--      u8 pciecap_lcreg_offset;/* PCIE capability LCreg offset
--                               * in the config space
--                               */
--      bool pcie_pr42767;
--      u8 pcie_polarity;
--      u8 pcie_war_aspm_ovr;   /* Override ASPM/Clkreq settings */
--
--      u8 pmecap_offset;       /* PM Capability offset in the config space */
--      bool pmecap;            /* Capable of generating PME */
--};
--
--#define PCIE_ASPM(sih)                                                        \
--      ((ai_get_buscoretype(sih) == PCIE_CORE_ID) &&                   \
--       ((ai_get_buscorerev(sih) >= 3) &&                              \
--        (ai_get_buscorerev(sih) <= 5)))
--
--
--/* delay needed between the mdio control/ mdiodata register data access */
--static void pr28829_delay(void)
--{
--      udelay(10);
--}
--
--/* Initialize the PCI core.
-- * It's caller's responsibility to make sure that this is done only once
-- */
--struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
--{
--      struct pcicore_info *pi;
--
--      /* alloc struct pcicore_info */
--      pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
--      if (pi == NULL)
--              return NULL;
--
--      pi->sih = sih;
--      pi->dev = core->bus->host_pci;
--      pi->core = core;
--
--      if (core->id.id == PCIE_CORE_ID) {
--              u8 cap_ptr;
--              cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
--                                                    NULL, NULL);
--              pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
--      }
--      return pi;
--}
--
--void pcicore_deinit(struct pcicore_info *pch)
--{
--      kfree(pch);
--}
--
--/* return cap_offset if requested capability exists in the PCI config space */
--/* Note that it's caller's responsibility to make sure it's a pci bus */
--u8
--pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
--                          unsigned char *buf, u32 *buflen)
--{
--      u8 cap_id;
--      u8 cap_ptr = 0;
--      u32 bufsize;
--      u8 byte_val;
--
--      /* check for Header type 0 */
--      pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
--      if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
--              goto end;
--
--      /* check if the capability pointer field exists */
--      pci_read_config_byte(dev, PCI_STATUS, &byte_val);
--      if (!(byte_val & PCI_STATUS_CAP_LIST))
--              goto end;
--
--      pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
--      /* check if the capability pointer is 0x00 */
--      if (cap_ptr == 0x00)
--              goto end;
--
--      /* loop thru the capability list
--       * and see if the pcie capability exists
--       */
--
--      pci_read_config_byte(dev, cap_ptr, &cap_id);
--
--      while (cap_id != req_cap_id) {
--              pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
--              if (cap_ptr == 0x00)
--                      break;
--              pci_read_config_byte(dev, cap_ptr, &cap_id);
--      }
--      if (cap_id != req_cap_id)
--              goto end;
--
--      /* found the caller requested capability */
--      if (buf != NULL && buflen != NULL) {
--              u8 cap_data;
--
--              bufsize = *buflen;
--              if (!bufsize)
--                      goto end;
--              *buflen = 0;
--              /* copy the capability data excluding cap ID and next ptr */
--              cap_data = cap_ptr + 2;
--              if ((bufsize + cap_data) > PCI_SZPCR)
--                      bufsize = PCI_SZPCR - cap_data;
--              *buflen = bufsize;
--              while (bufsize--) {
--                      pci_read_config_byte(dev, cap_data, buf);
--                      cap_data++;
--                      buf++;
--              }
--      }
--end:
--      return cap_ptr;
--}
--
--/* ***** Register Access API */
--static uint
--pcie_readreg(struct bcma_device *core, uint addrtype, uint offset)
--{
--      uint retval = 0xFFFFFFFF;
--
--      switch (addrtype) {
--      case PCIE_CONFIGREGS:
--              bcma_write32(core, PCIEREGOFFS(configaddr), offset);
--              (void)bcma_read32(core, PCIEREGOFFS(configaddr));
--              retval = bcma_read32(core, PCIEREGOFFS(configdata));
--              break;
--      case PCIE_PCIEREGS:
--              bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
--              (void)bcma_read32(core, PCIEREGOFFS(pcieindaddr));
--              retval = bcma_read32(core, PCIEREGOFFS(pcieinddata));
--              break;
--      }
--
--      return retval;
--}
--
--static uint pcie_writereg(struct bcma_device *core, uint addrtype,
--                        uint offset, uint val)
--{
--      switch (addrtype) {
--      case PCIE_CONFIGREGS:
--              bcma_write32(core, PCIEREGOFFS(configaddr), offset);
--              bcma_write32(core, PCIEREGOFFS(configdata), val);
--              break;
--      case PCIE_PCIEREGS:
--              bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
--              bcma_write32(core, PCIEREGOFFS(pcieinddata), val);
--              break;
--      default:
--              break;
--      }
--      return 0;
--}
--
--static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
--{
--      uint mdiodata, i = 0;
--      uint pcie_serdes_spinwait = 200;
--
--      mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
--                  (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
--                  (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
--                  (blk << 4));
--      bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
--
--      pr28829_delay();
--      /* retry till the transaction is complete */
--      while (i < pcie_serdes_spinwait) {
--              if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
--                  MDIOCTL_ACCESS_DONE)
--                      break;
--
--              udelay(1000);
--              i++;
--      }
--
--      if (i >= pcie_serdes_spinwait)
--              return false;
--
--      return true;
--}
--
--static int
--pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
--          uint *val)
--{
--      uint mdiodata;
--      uint i = 0;
--      uint pcie_serdes_spinwait = 10;
--
--      /* enable mdio access to SERDES */
--      bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol),
--                   MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
--
--      if (ai_get_buscorerev(pi->sih) >= 10) {
--              /* new serdes is slower in rw,
--               * using two layers of reg address mapping
--               */
--              if (!pcie_mdiosetblock(pi, physmedia))
--                      return 1;
--              mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
--                          (regaddr << MDIODATA_REGADDR_SHF));
--              pcie_serdes_spinwait *= 20;
--      } else {
--              mdiodata = ((physmedia << MDIODATA_DEVADDR_SHF_OLD) |
--                          (regaddr << MDIODATA_REGADDR_SHF_OLD));
--      }
--
--      if (!write)
--              mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
--      else
--              mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
--                           *val);
--
--      bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
--
--      pr28829_delay();
--
--      /* retry till the transaction is complete */
--      while (i < pcie_serdes_spinwait) {
--              if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
--                  MDIOCTL_ACCESS_DONE) {
--                      if (!write) {
--                              pr28829_delay();
--                              *val = (bcma_read32(pi->core,
--                                                  PCIEREGOFFS(mdiodata)) &
--                                      MDIODATA_MASK);
--                      }
--                      /* Disable mdio access to SERDES */
--                      bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
--                      return 0;
--              }
--              udelay(1000);
--              i++;
--      }
--
--      /* Timed out. Disable mdio access to SERDES. */
--      bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
--      return 1;
--}
--
--/* use the mdio interface to read from mdio slaves */
--static int
--pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint regaddr,
--            uint *regval)
--{
--      return pcie_mdioop(pi, physmedia, regaddr, false, regval);
--}
--
--/* use the mdio interface to write to mdio slaves */
--static int
--pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
--{
--      return pcie_mdioop(pi, physmedia, regaddr, true, &val);
--}
--
--/* ***** Support functions ***** */
--static u8 pcie_clkreq(struct pcicore_info *pi, u32 mask, u32 val)
--{
--      u32 reg_val;
--      u8 offset;
--
--      offset = pi->pciecap_lcreg_offset;
--      if (!offset)
--              return 0;
--
--      pci_read_config_dword(pi->dev, offset, &reg_val);
--      /* set operation */
--      if (mask) {
--              if (val)
--                      reg_val |= PCIE_CLKREQ_ENAB;
--              else
--                      reg_val &= ~PCIE_CLKREQ_ENAB;
--              pci_write_config_dword(pi->dev, offset, reg_val);
--              pci_read_config_dword(pi->dev, offset, &reg_val);
--      }
--      if (reg_val & PCIE_CLKREQ_ENAB)
--              return 1;
--      else
--              return 0;
--}
--
--static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
--{
--      u32 w;
--      struct si_pub *sih = pi->sih;
--
--      if (ai_get_buscoretype(sih) != PCIE_CORE_ID ||
--          ai_get_buscorerev(sih) < 7)
--              return;
--
--      w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
--      if (extend)
--              w |= PCIE_ASPMTIMER_EXTEND;
--      else
--              w &= ~PCIE_ASPMTIMER_EXTEND;
--      pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
--      w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
--}
--
--/* centralized clkreq control policy */
--static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
--{
--      struct si_pub *sih = pi->sih;
--
--      switch (state) {
--      case SI_DOATTACH:
--              if (PCIE_ASPM(sih))
--                      pcie_clkreq(pi, 1, 0);
--              break;
--      case SI_PCIDOWN:
--              /* turn on serdes PLL down */
--              if (ai_get_buscorerev(sih) == 6) {
--                      ai_cc_reg(sih,
--                                offsetof(struct chipcregs, chipcontrol_addr),
--                                ~0, 0);
--                      ai_cc_reg(sih,
--                                offsetof(struct chipcregs, chipcontrol_data),
--                                ~0x40, 0);
--              } else if (pi->pcie_pr42767) {
--                      pcie_clkreq(pi, 1, 1);
--              }
--              break;
--      case SI_PCIUP:
--              /* turn off serdes PLL down */
--              if (ai_get_buscorerev(sih) == 6) {
--                      ai_cc_reg(sih,
--                                offsetof(struct chipcregs, chipcontrol_addr),
--                                ~0, 0);
--                      ai_cc_reg(sih,
--                                offsetof(struct chipcregs, chipcontrol_data),
--                                ~0x40, 0x40);
--              } else if (PCIE_ASPM(sih)) {    /* disable clkreq */
--                      pcie_clkreq(pi, 1, 0);
--              }
--              break;
--      }
--}
--
--/* ***** PCI core WARs ***** */
--/* Done only once at attach time */
--static void pcie_war_polarity(struct pcicore_info *pi)
--{
--      u32 w;
--
--      if (pi->pcie_polarity != 0)
--              return;
--
--      w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
--
--      /* Detect the current polarity at attach and force that polarity and
--       * disable changing the polarity
--       */
--      if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
--              pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
--      else
--              pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
--                                   SERDES_RX_CTRL_POLARITY);
--}
--
--/* enable ASPM and CLKREQ if srom doesn't have it */
--/* Needs to happen when update to shadow SROM is needed
-- *   : Coming out of 'standby'/'hibernate'
-- *   : If pcie_war_aspm_ovr state changed
-- */
--static void pcie_war_aspm_clkreq(struct pcicore_info *pi)
--{
--      struct si_pub *sih = pi->sih;
--      u16 val16;
--      u32 w;
--
--      if (!PCIE_ASPM(sih))
--              return;
--
--      /* bypass this on QT or VSIM */
--      val16 = bcma_read16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]));
--
--      val16 &= ~SRSH_ASPM_ENB;
--      if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
--              val16 |= SRSH_ASPM_ENB;
--      else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
--              val16 |= SRSH_ASPM_L1_ENB;
--      else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
--              val16 |= SRSH_ASPM_L0s_ENB;
--
--      bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]), val16);
--
--      pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
--      w &= ~PCIE_ASPM_ENAB;
--      w |= pi->pcie_war_aspm_ovr;
--      pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
--
--      val16 = bcma_read16(pi->core,
--                          PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]));
--
--      if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
--              val16 |= SRSH_CLKREQ_ENB;
--              pi->pcie_pr42767 = true;
--      } else
--              val16 &= ~SRSH_CLKREQ_ENB;
--
--      bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]),
--                   val16);
--}
--
--/* Apply the polarity determined at the start */
--/* Needs to happen when coming out of 'standby'/'hibernate' */
--static void pcie_war_serdes(struct pcicore_info *pi)
--{
--      u32 w = 0;
--
--      if (pi->pcie_polarity != 0)
--              pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
--                             pi->pcie_polarity);
--
--      pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
--      if (w & PLL_CTRL_FREQDET_EN) {
--              w &= ~PLL_CTRL_FREQDET_EN;
--              pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
--      }
--}
--
--/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
--/* Needs to happen when coming out of 'standby'/'hibernate' */
--static void pcie_misc_config_fixup(struct pcicore_info *pi)
--{
--      u16 val16;
--
--      val16 = bcma_read16(pi->core,
--                          PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]));
--
--      if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
--              val16 |= SRSH_L23READY_EXIT_NOPERST;
--              bcma_write16(pi->core,
--                           PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]), val16);
--      }
--}
--
--/* quick hack for testing */
--/* Needs to happen when coming out of 'standby'/'hibernate' */
--static void pcie_war_noplldown(struct pcicore_info *pi)
--{
--      /* turn off serdes PLL down */
--      ai_cc_reg(pi->sih, offsetof(struct chipcregs, chipcontrol),
--                CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
--
--      /* clear srom shadow backdoor */
--      bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_BD_OFFSET]), 0);
--}
--
--/* Needs to happen when coming out of 'standby'/'hibernate' */
--static void pcie_war_pci_setup(struct pcicore_info *pi)
--{
--      struct si_pub *sih = pi->sih;
--      u32 w;
--
--      if (ai_get_buscorerev(sih) == 0 || ai_get_buscorerev(sih) == 1) {
--              w = pcie_readreg(pi->core, PCIE_PCIEREGS,
--                               PCIE_TLP_WORKAROUNDSREG);
--              w |= 0x8;
--              pcie_writereg(pi->core, PCIE_PCIEREGS,
--                            PCIE_TLP_WORKAROUNDSREG, w);
--      }
--
--      if (ai_get_buscorerev(sih) == 1) {
--              w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
--              w |= 0x40;
--              pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
--      }
--
--      if (ai_get_buscorerev(sih) == 0) {
--              pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
--              pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
--              pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
--      } else if (PCIE_ASPM(sih)) {
--              /* Change the L1 threshold for better performance */
--              w = pcie_readreg(pi->core, PCIE_PCIEREGS,
--                               PCIE_DLLP_PMTHRESHREG);
--              w &= ~PCIE_L1THRESHOLDTIME_MASK;
--              w |= PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT;
--              pcie_writereg(pi->core, PCIE_PCIEREGS,
--                            PCIE_DLLP_PMTHRESHREG, w);
--
--              pcie_war_serdes(pi);
--
--              pcie_war_aspm_clkreq(pi);
--      } else if (ai_get_buscorerev(pi->sih) == 7)
--              pcie_war_noplldown(pi);
--
--      /* Note that the fix is actually in the SROM,
--       * that's why this is open-ended
--       */
--      if (ai_get_buscorerev(pi->sih) >= 6)
--              pcie_misc_config_fixup(pi);
--}
--
--/* ***** Functions called during driver state changes ***** */
--void pcicore_attach(struct pcicore_info *pi, int state)
--{
--      struct si_pub *sih = pi->sih;
--      u32 bfl2 = (u32)getintvar(sih, BRCMS_SROM_BOARDFLAGS2);
--
--      /* Determine if this board needs override */
--      if (PCIE_ASPM(sih)) {
--              if (bfl2 & BFL2_PCIEWAR_OVR)
--                      pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
--              else
--                      pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
--      }
--
--      /* These need to happen in this order only */
--      pcie_war_polarity(pi);
--
--      pcie_war_serdes(pi);
--
--      pcie_war_aspm_clkreq(pi);
--
--      pcie_clkreq_upd(pi, state);
--
--}
--
--void pcicore_hwup(struct pcicore_info *pi)
--{
--      if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
--              return;
--
--      pcie_war_pci_setup(pi);
--}
--
--void pcicore_up(struct pcicore_info *pi, int state)
--{
--      if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
--              return;
--
--      /* Restore L1 timer for better performance */
--      pcie_extendL1timer(pi, true);
--
--      pcie_clkreq_upd(pi, state);
--}
--
--/* When the device is going to enter D3 state
-- * (or the system is going to enter S3/S4 states)
-- */
--void pcicore_sleep(struct pcicore_info *pi)
--{
--      u32 w;
--
--      if (!pi || !PCIE_ASPM(pi->sih))
--              return;
--
--      pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
--      w &= ~PCIE_CAP_LCREG_ASPML1;
--      pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
--
--      pi->pcie_pr42767 = false;
--}
--
--void pcicore_down(struct pcicore_info *pi, int state)
--{
--      if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
--              return;
--
--      pcie_clkreq_upd(pi, state);
--
--      /* Reduce L1 timer for better power savings */
--      pcie_extendL1timer(pi, false);
--}
--
--void pcicore_fixcfg(struct pcicore_info *pi)
--{
--      struct bcma_device *core = pi->core;
--      u16 val16;
--      uint regoff;
--
--      switch (pi->core->id.id) {
--      case BCMA_CORE_PCI:
--              regoff = PCIREGOFFS(sprom[SRSH_PI_OFFSET]);
--              break;
--
--      case BCMA_CORE_PCIE:
--              regoff = PCIEREGOFFS(sprom[SRSH_PI_OFFSET]);
--              break;
--
--      default:
--              return;
--      }
--
--      val16 = bcma_read16(pi->core, regoff);
--      if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) !=
--          (u16)core->core_index) {
--              val16 = ((u16)core->core_index << SRSH_PI_SHIFT) |
--                      (val16 & ~SRSH_PI_MASK);
--              bcma_write16(pi->core, regoff, val16);
--      }
--}
--
--/* precondition: current core is pci core */
--void
--pcicore_pci_setup(struct pcicore_info *pi)
--{
--      bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
--                 SBTOPCI_PREF | SBTOPCI_BURST);
--
--      if (pi->core->id.rev >= 11) {
--              bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
--                         SBTOPCI_RC_READMULTI);
--              bcma_set32(pi->core, PCIREGOFFS(clkrun), PCI_CLKRUN_DSBL);
--              (void)bcma_read32(pi->core, PCIREGOFFS(clkrun));
--      }
--}
---- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
-+++ /dev/null
-@@ -1,77 +0,0 @@
--/*
-- * Copyright (c) 2010 Broadcom Corporation
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
-- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- */
--
--#ifndef       _BRCM_NICPCI_H_
--#define       _BRCM_NICPCI_H_
--
--#include "types.h"
--
--/* PCI configuration address space size */
--#define PCI_SZPCR             256
--
--/* Brcm PCI configuration registers */
--/* backplane address space accessed by BAR0 */
--#define PCI_BAR0_WIN          0x80
--/* sprom property control */
--#define PCI_SPROM_CONTROL     0x88
--/* mask of PCI and other cores interrupts */
--#define PCI_INT_MASK          0x94
--/* backplane core interrupt mask bits offset */
--#define  PCI_SBIM_SHIFT               8
--/* backplane address space accessed by second 4KB of BAR0 */
--#define PCI_BAR0_WIN2         0xac
--/* pci config space gpio input (>=rev3) */
--#define PCI_GPIO_IN           0xb0
--/* pci config space gpio output (>=rev3) */
--#define PCI_GPIO_OUT          0xb4
--/* pci config space gpio output enable (>=rev3) */
--#define PCI_GPIO_OUTEN                0xb8
--
--/* bar0 + 4K accesses external sprom */
--#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
--/* bar0 + 6K accesses pci core registers */
--#define PCI_BAR0_PCIREGS_OFFSET       (6 * 1024)
--/*
-- * pci core SB registers are at the end of the
-- * 8KB window, so their address is the "regular"
-- * address plus 4K
-- */
--#define PCI_BAR0_PCISBR_OFFSET        (4 * 1024)
--/* bar0 window size Match with corerev 13 */
--#define PCI_BAR0_WINSZ                (16 * 1024)
--/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
--/* bar0 + 8K accesses pci/pcie core registers */
--#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
--/* bar0 + 12K accesses chipc core registers */
--#define PCI_16KB0_CCREGS_OFFSET       (12 * 1024)
--
--struct sbpciregs;
--struct sbpcieregs;
--
--extern struct pcicore_info *pcicore_init(struct si_pub *sih,
--                                       struct bcma_device *core);
--extern void pcicore_deinit(struct pcicore_info *pch);
--extern void pcicore_attach(struct pcicore_info *pch, int state);
--extern void pcicore_hwup(struct pcicore_info *pch);
--extern void pcicore_up(struct pcicore_info *pch, int state);
--extern void pcicore_sleep(struct pcicore_info *pch);
--extern void pcicore_down(struct pcicore_info *pch, int state);
--extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
--                                    unsigned char *buf, u32 *buflen);
--extern void pcicore_fixcfg(struct pcicore_info *pch);
--extern void pcicore_pci_setup(struct pcicore_info *pch);
--
--#endif /* _BRCM_NICPCI_H_ */
---- a/drivers/net/wireless/brcm80211/brcmsmac/otp.c
-+++ /dev/null
-@@ -1,410 +0,0 @@
--/*
-- * Copyright (c) 2010 Broadcom Corporation
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
-- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- */
--
--#include <linux/io.h>
--#include <linux/errno.h>
--#include <linux/string.h>
--
--#include <brcm_hw_ids.h>
--#include <chipcommon.h>
--#include "aiutils.h"
--#include "otp.h"
--
--#define OTPS_GUP_MASK         0x00000f00
--#define OTPS_GUP_SHIFT                8
--/* h/w subregion is programmed */
--#define OTPS_GUP_HW           0x00000100
--/* s/w subregion is programmed */
--#define OTPS_GUP_SW           0x00000200
--/* chipid/pkgopt subregion is programmed */
--#define OTPS_GUP_CI           0x00000400
--/* fuse subregion is programmed */
--#define OTPS_GUP_FUSE         0x00000800
--
--/* Fields in otpprog in rev >= 21 */
--#define OTPP_COL_MASK         0x000000ff
--#define OTPP_COL_SHIFT                0
--#define OTPP_ROW_MASK         0x0000ff00
--#define OTPP_ROW_SHIFT                8
--#define OTPP_OC_MASK          0x0f000000
--#define OTPP_OC_SHIFT         24
--#define OTPP_READERR          0x10000000
--#define OTPP_VALUE_MASK               0x20000000
--#define OTPP_VALUE_SHIFT      29
--#define OTPP_START_BUSY               0x80000000
--#define       OTPP_READ               0x40000000
--
--/* Opcodes for OTPP_OC field */
--#define OTPPOC_READ           0
--#define OTPPOC_BIT_PROG               1
--#define OTPPOC_VERIFY         3
--#define OTPPOC_INIT           4
--#define OTPPOC_SET            5
--#define OTPPOC_RESET          6
--#define OTPPOC_OCST           7
--#define OTPPOC_ROW_LOCK               8
--#define OTPPOC_PRESCN_TEST    9
--
--#define OTPTYPE_IPX(ccrev)    ((ccrev) == 21 || (ccrev) >= 23)
--
--#define OTPP_TRIES    10000000        /* # of tries for OTPP */
--
--#define MAXNUMRDES            9       /* Maximum OTP redundancy entries */
--
--/* Fixed size subregions sizes in words */
--#define OTPGU_CI_SZ           2
--
--struct otpinfo;
--
--/* OTP function struct */
--struct otp_fn_s {
--      int (*init)(struct si_pub *sih, struct otpinfo *oi);
--      int (*read_region)(struct otpinfo *oi, int region, u16 *data,
--                         uint *wlen);
--};
--
--struct otpinfo {
--      struct bcma_device *core; /* chipc core */
--      const struct otp_fn_s *fn;      /* OTP functions */
--      struct si_pub *sih;             /* Saved sb handle */
--
--      /* IPX OTP section */
--      u16 wsize;              /* Size of otp in words */
--      u16 rows;               /* Geometry */
--      u16 cols;               /* Geometry */
--      u32 status;             /* Flag bits (lock/prog/rv).
--                               * (Reflected only when OTP is power cycled)
--                               */
--      u16 hwbase;             /* hardware subregion offset */
--      u16 hwlim;              /* hardware subregion boundary */
--      u16 swbase;             /* software subregion offset */
--      u16 swlim;              /* software subregion boundary */
--      u16 fbase;              /* fuse subregion offset */
--      u16 flim;               /* fuse subregion boundary */
--      int otpgu_base;         /* offset to General Use Region */
--};
--
--/* OTP layout */
--/* CC revs 21, 24 and 27 OTP General Use Region word offset */
--#define REVA4_OTPGU_BASE      12
--
--/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
--#define REVB8_OTPGU_BASE      20
--
--/* CC rev 36 OTP General Use Region word offset */
--#define REV36_OTPGU_BASE      12
--
--/* Subregion word offsets in General Use region */
--#define OTPGU_HSB_OFF         0
--#define OTPGU_SFB_OFF         1
--#define OTPGU_CI_OFF          2
--#define OTPGU_P_OFF           3
--#define OTPGU_SROM_OFF                4
--
--/* Flag bit offsets in General Use region  */
--#define OTPGU_HWP_OFF         60
--#define OTPGU_SWP_OFF         61
--#define OTPGU_CIP_OFF         62
--#define OTPGU_FUSEP_OFF               63
--#define OTPGU_CIP_MSK         0x4000
--#define OTPGU_P_MSK           0xf000
--#define OTPGU_P_SHIFT         (OTPGU_HWP_OFF % 16)
--
--/* OTP Size */
--#define OTP_SZ_FU_324         ((roundup(324, 8))/8)   /* 324 bits */
--#define OTP_SZ_FU_288         (288/8) /* 288 bits */
--#define OTP_SZ_FU_216         (216/8) /* 216 bits */
--#define OTP_SZ_FU_72          (72/8)  /* 72 bits */
--#define OTP_SZ_CHECKSUM               (16/8)  /* 16 bits */
--#define OTP4315_SWREG_SZ      178     /* 178 bytes */
--#define OTP_SZ_FU_144         (144/8) /* 144 bits */
--
--static u16
--ipxotp_otpr(struct otpinfo *oi, uint wn)
--{
--      return bcma_read16(oi->core,
--                         CHIPCREGOFFS(sromotp[wn]));
--}
--
--/*
-- * Calculate max HW/SW region byte size by subtracting fuse region
-- * and checksum size, osizew is oi->wsize (OTP size - GU size) in words
-- */
--static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
--{
--      int ret = 0;
--
--      switch (ai_get_chip_id(sih)) {
--      case BCM43224_CHIP_ID:
--      case BCM43225_CHIP_ID:
--              ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
--              break;
--      case BCM4313_CHIP_ID:
--              ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
--              break;
--      default:
--              break;  /* Don't know about this chip */
--      }
--
--      return ret;
--}
--
--static void _ipxotp_init(struct otpinfo *oi)
--{
--      uint k;
--      u32 otpp, st;
--      int ccrev = ai_get_ccrev(oi->sih);
--
--
--      /*
--       * record word offset of General Use Region
--       * for various chipcommon revs
--       */
--      if (ccrev == 21 || ccrev == 24
--          || ccrev == 27) {
--              oi->otpgu_base = REVA4_OTPGU_BASE;
--      } else if (ccrev == 36) {
--              /*
--               * OTP size greater than equal to 2KB (128 words),
--               * otpgu_base is similar to rev23
--               */
--              if (oi->wsize >= 128)
--                      oi->otpgu_base = REVB8_OTPGU_BASE;
--              else
--                      oi->otpgu_base = REV36_OTPGU_BASE;
--      } else if (ccrev == 23 || ccrev >= 25) {
--              oi->otpgu_base = REVB8_OTPGU_BASE;
--      }
--
--      /* First issue an init command so the status is up to date */
--      otpp =
--          OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
--
--      bcma_write32(oi->core, CHIPCREGOFFS(otpprog), otpp);
--      st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
--      for (k = 0; (st & OTPP_START_BUSY) && (k < OTPP_TRIES); k++)
--              st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
--      if (k >= OTPP_TRIES)
--              return;
--
--      /* Read OTP lock bits and subregion programmed indication bits */
--      oi->status = bcma_read32(oi->core, CHIPCREGOFFS(otpstatus));
--
--      if ((ai_get_chip_id(oi->sih) == BCM43224_CHIP_ID)
--          || (ai_get_chip_id(oi->sih) == BCM43225_CHIP_ID)) {
--              u32 p_bits;
--              p_bits = (ipxotp_otpr(oi, oi->otpgu_base + OTPGU_P_OFF) &
--                        OTPGU_P_MSK) >> OTPGU_P_SHIFT;
--              oi->status |= (p_bits << OTPS_GUP_SHIFT);
--      }
--
--      /*
--       * h/w region base and fuse region limit are fixed to
--       * the top and the bottom of the general use region.
--       * Everything else can be flexible.
--       */
--      oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
--      oi->hwlim = oi->wsize;
--      if (oi->status & OTPS_GUP_HW) {
--              oi->hwlim =
--                  ipxotp_otpr(oi, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
--              oi->swbase = oi->hwlim;
--      } else
--              oi->swbase = oi->hwbase;
--
--      /* subtract fuse and checksum from beginning */
--      oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
--
--      if (oi->status & OTPS_GUP_SW) {
--              oi->swlim =
--                  ipxotp_otpr(oi, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
--              oi->fbase = oi->swlim;
--      } else
--              oi->fbase = oi->swbase;
--
--      oi->flim = oi->wsize;
--}
--
--static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
--{
--      /* Make sure we're running IPX OTP */
--      if (!OTPTYPE_IPX(ai_get_ccrev(sih)))
--              return -EBADE;
--
--      /* Make sure OTP is not disabled */
--      if (ai_is_otp_disabled(sih))
--              return -EBADE;
--
--      /* Check for otp size */
--      switch ((ai_get_cccaps(sih) & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
--      case 0:
--              /* Nothing there */
--              return -EBADE;
--      case 1:         /* 32x64 */
--              oi->rows = 32;
--              oi->cols = 64;
--              oi->wsize = 128;
--              break;
--      case 2:         /* 64x64 */
--              oi->rows = 64;
--              oi->cols = 64;
--              oi->wsize = 256;
--              break;
--      case 5:         /* 96x64 */
--              oi->rows = 96;
--              oi->cols = 64;
--              oi->wsize = 384;
--              break;
--      case 7:         /* 16x64 *//* 1024 bits */
--              oi->rows = 16;
--              oi->cols = 64;
--              oi->wsize = 64;
--              break;
--      default:
--              /* Don't know the geometry */
--              return -EBADE;
--      }
--
--      /* Retrieve OTP region info */
--      _ipxotp_init(oi);
--      return 0;
--}
--
--static int
--ipxotp_read_region(struct otpinfo *oi, int region, u16 *data, uint *wlen)
--{
--      uint base, i, sz;
--
--      /* Validate region selection */
--      switch (region) {
--      case OTP_HW_RGN:
--              sz = (uint) oi->hwlim - oi->hwbase;
--              if (!(oi->status & OTPS_GUP_HW)) {
--                      *wlen = sz;
--                      return -ENODATA;
--              }
--              if (*wlen < sz) {
--                      *wlen = sz;
--                      return -EOVERFLOW;
--              }
--              base = oi->hwbase;
--              break;
--      case OTP_SW_RGN:
--              sz = ((uint) oi->swlim - oi->swbase);
--              if (!(oi->status & OTPS_GUP_SW)) {
--                      *wlen = sz;
--                      return -ENODATA;
--              }
--              if (*wlen < sz) {
--                      *wlen = sz;
--                      return -EOVERFLOW;
--              }
--              base = oi->swbase;
--              break;
--      case OTP_CI_RGN:
--              sz = OTPGU_CI_SZ;
--              if (!(oi->status & OTPS_GUP_CI)) {
--                      *wlen = sz;
--                      return -ENODATA;
--              }
--              if (*wlen < sz) {
--                      *wlen = sz;
--                      return -EOVERFLOW;
--              }
--              base = oi->otpgu_base + OTPGU_CI_OFF;
--              break;
--      case OTP_FUSE_RGN:
--              sz = (uint) oi->flim - oi->fbase;
--              if (!(oi->status & OTPS_GUP_FUSE)) {
--                      *wlen = sz;
--                      return -ENODATA;
--              }
--              if (*wlen < sz) {
--                      *wlen = sz;
--                      return -EOVERFLOW;
--              }
--              base = oi->fbase;
--              break;
--      case OTP_ALL_RGN:
--              sz = ((uint) oi->flim - oi->hwbase);
--              if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
--                      *wlen = sz;
--                      return -ENODATA;
--              }
--              if (*wlen < sz) {
--                      *wlen = sz;
--                      return -EOVERFLOW;
--              }
--              base = oi->hwbase;
--              break;
--      default:
--              return -EINVAL;
--      }
--
--      /* Read the data */
--      for (i = 0; i < sz; i++)
--              data[i] = ipxotp_otpr(oi, base + i);
--
--      *wlen = sz;
--      return 0;
--}
--
--static const struct otp_fn_s ipxotp_fn = {
--      (int (*)(struct si_pub *, struct otpinfo *)) ipxotp_init,
--      (int (*)(struct otpinfo *, int, u16 *, uint *)) ipxotp_read_region,
--};
--
--static int otp_init(struct si_pub *sih, struct otpinfo *oi)
--{
--      int ret;
--
--      memset(oi, 0, sizeof(struct otpinfo));
--
--      oi->core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
--
--      if (OTPTYPE_IPX(ai_get_ccrev(sih)))
--              oi->fn = &ipxotp_fn;
--
--      if (oi->fn == NULL)
--              return -EBADE;
--
--      oi->sih = sih;
--
--      ret = (oi->fn->init)(sih, oi);
--
--      return ret;
--}
--
--int
--otp_read_region(struct si_pub *sih, int region, u16 *data, uint *wlen) {
--      struct otpinfo otpinfo;
--      struct otpinfo *oi = &otpinfo;
--      int err = 0;
--
--      if (ai_is_otp_disabled(sih)) {
--              err = -EPERM;
--              goto out;
--      }
--
--      err = otp_init(sih, oi);
--      if (err)
--              goto out;
--
--      err = ((oi)->fn->read_region)(oi, region, data, wlen);
--
-- out:
--      return err;
--}
---- a/drivers/net/wireless/brcm80211/brcmsmac/otp.h
-+++ /dev/null
-@@ -1,36 +0,0 @@
--/*
-- * Copyright (c) 2010 Broadcom Corporation
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
-- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- */
--
--#ifndef       _BRCM_OTP_H_
--#define       _BRCM_OTP_H_
--
--#include "types.h"
--
--/* OTP regions */
--#define OTP_HW_RGN    1
--#define OTP_SW_RGN    2
--#define OTP_CI_RGN    4
--#define OTP_FUSE_RGN  8
--/* From h/w region to end of OTP including checksum */
--#define OTP_ALL_RGN   0xf
--
--/* OTP Size */
--#define OTP_SZ_MAX            (6144/8)        /* maximum bytes in one CIS */
--
--extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
--                         uint *wlen);
--
--#endif                                /* _BRCM_OTP_H_ */
---- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
-@@ -4817,28 +4817,23 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-       s8 txpwr = 0;
-       int i;
-       struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
--      struct phy_shim_info *shim = pi->sh->physhim;
-+      struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
-       if (CHSPEC_IS2G(pi->radio_chanspec)) {
-               u16 cckpo = 0;
-               u32 offset_ofdm, offset_mcs;
--              pi_lcn->lcnphy_tr_isolation_mid =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
-+              pi_lcn->lcnphy_tr_isolation_mid = sprom->fem.ghz2.tr_iso;
--              pi_lcn->lcnphy_rx_power_offset =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_RXPO2G);
-+              pi_lcn->lcnphy_rx_power_offset = sprom->rxpo2g;
--              pi->txpa_2g[0] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B0);
--              pi->txpa_2g[1] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B1);
--              pi->txpa_2g[2] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B2);
--
--              pi_lcn->lcnphy_rssi_vf =
--                              (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMF2G);
--              pi_lcn->lcnphy_rssi_vc =
--                              (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMC2G);
--              pi_lcn->lcnphy_rssi_gs =
--                              (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISAV2G);
-+              pi->txpa_2g[0] = sprom->pa0b0;
-+              pi->txpa_2g[1] = sprom->pa0b1;
-+              pi->txpa_2g[2] = sprom->pa0b2;
-+
-+              pi_lcn->lcnphy_rssi_vf = sprom->rssismf2g;
-+              pi_lcn->lcnphy_rssi_vc = sprom->rssismc2g;
-+              pi_lcn->lcnphy_rssi_gs = sprom->rssisav2g;
-               pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
-               pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
-@@ -4848,7 +4843,7 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-               pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc;
-               pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs;
--              txpwr = (s8)wlapi_getintvar(shim, BRCMS_SROM_MAXP2GA0);
-+              txpwr = sprom->core_pwr_info[0].maxpwr_2g;
-               pi->tx_srom_max_2g = txpwr;
-               for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
-@@ -4856,8 +4851,8 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-                       pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
-               }
--              cckpo = (u16)wlapi_getintvar(shim, BRCMS_SROM_CCK2GPO);
--              offset_ofdm = (u32)wlapi_getintvar(shim, BRCMS_SROM_OFDM2GPO);
-+              cckpo = sprom->cck2gpo;
-+              offset_ofdm = sprom->ofdm2gpo;
-               if (cckpo) {
-                       uint max_pwr_chan = txpwr;
-@@ -4876,7 +4871,7 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-               } else {
-                       u8 opo = 0;
--                      opo = (u8)wlapi_getintvar(shim, BRCMS_SROM_OPO);
-+                      opo = sprom->opo;
-                       for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++)
-                               pi->tx_srom_max_rate_2g[i] = txpwr;
-@@ -4886,12 +4881,8 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-                                               ((offset_ofdm & 0xf) * 2);
-                               offset_ofdm >>= 4;
-                       }
--                      offset_mcs =
--                              wlapi_getintvar(shim,
--                                              BRCMS_SROM_MCS2GPO1) << 16;
--                      offset_mcs |=
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO0);
-+                      offset_mcs = sprom->mcs2gpo[1] << 16;
-+                      offset_mcs |= sprom->mcs2gpo[0];
-                       pi_lcn->lcnphy_mcs20_po = offset_mcs;
-                       for (i = TXP_FIRST_SISO_MCS_20;
-                            i <= TXP_LAST_SISO_MCS_20; i++) {
-@@ -4901,25 +4892,17 @@ static bool wlc_phy_txpwr_srom_read_lcnp
-                       }
-               }
--              pi_lcn->lcnphy_rawtempsense =
--                      (u16)wlapi_getintvar(shim, BRCMS_SROM_RAWTEMPSENSE);
--              pi_lcn->lcnphy_measPower =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_MEASPOWER);
--              pi_lcn->lcnphy_tempsense_slope =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_SLOPE);
--              pi_lcn->lcnphy_hw_iqcal_en =
--                      (bool)wlapi_getintvar(shim, BRCMS_SROM_HW_IQCAL_EN);
--              pi_lcn->lcnphy_iqcal_swp_dis =
--                      (bool)wlapi_getintvar(shim, BRCMS_SROM_IQCAL_SWP_DIS);
--              pi_lcn->lcnphy_tempcorrx =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPCORRX);
--              pi_lcn->lcnphy_tempsense_option =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_OPTION);
--              pi_lcn->lcnphy_freqoffset_corr =
--                      (u8)wlapi_getintvar(shim, BRCMS_SROM_FREQOFFSET_CORR);
--              if ((u8)wlapi_getintvar(shim, BRCMS_SROM_AA2G) > 1)
-+              pi_lcn->lcnphy_rawtempsense = sprom->rawtempsense;
-+              pi_lcn->lcnphy_measPower = sprom->measpower;
-+              pi_lcn->lcnphy_tempsense_slope = sprom->tempsense_slope;
-+              pi_lcn->lcnphy_hw_iqcal_en = sprom->hw_iqcal_en;
-+              pi_lcn->lcnphy_iqcal_swp_dis = sprom->iqcal_swp_dis;
-+              pi_lcn->lcnphy_tempcorrx = sprom->tempcorrx;
-+              pi_lcn->lcnphy_tempsense_option = sprom->tempsense_option;
-+              pi_lcn->lcnphy_freqoffset_corr = sprom->freqoffset_corr;
-+              if (sprom->ant_available_bg > 1)
-                       wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi,
--                              (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G));
-+                              sprom->ant_available_bg);
-       }
-       pi_lcn->lcnphy_cck_dig_filt_type = -1;
---- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
-@@ -14388,30 +14388,30 @@ static void wlc_phy_txpwr_srom_read_ppr_
- {
-       u16 bw40po, cddpo, stbcpo, bwduppo;
-       uint band_num;
--      struct phy_shim_info *shim = pi->sh->physhim;
-+      struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
-       if (pi->sh->sromrev >= 9)
-               return;
--      bw40po = (u16) wlapi_getintvar(shim, BRCMS_SROM_BW40PO);
-+      bw40po = sprom->bw40po;
-       pi->bw402gpo = bw40po & 0xf;
-       pi->bw405gpo = (bw40po & 0xf0) >> 4;
-       pi->bw405glpo = (bw40po & 0xf00) >> 8;
-       pi->bw405ghpo = (bw40po & 0xf000) >> 12;
--      cddpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_CDDPO);
-+      cddpo = sprom->cddpo;
-       pi->cdd2gpo = cddpo & 0xf;
-       pi->cdd5gpo = (cddpo & 0xf0) >> 4;
-       pi->cdd5glpo = (cddpo & 0xf00) >> 8;
-       pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
--      stbcpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_STBCPO);
-+      stbcpo = sprom->stbcpo;
-       pi->stbc2gpo = stbcpo & 0xf;
-       pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
-       pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
-       pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
--      bwduppo = (u16) wlapi_getintvar(shim, BRCMS_SROM_BWDUPPO);
-+      bwduppo = sprom->bwduppo;
-       pi->bwdup2gpo = bwduppo & 0xf;
-       pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
-       pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
-@@ -14421,242 +14421,137 @@ static void wlc_phy_txpwr_srom_read_ppr_
-            band_num++) {
-               switch (band_num) {
-               case 0:
--
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP2GA0);
-+                              sprom->core_pwr_info[0].maxpwr_2g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP2GA1);
-+                              sprom->core_pwr_info[1].maxpwr_2g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW0A0);
-+                              sprom->core_pwr_info[0].pa_2g[0];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW0A1);
-+                              sprom->core_pwr_info[1].pa_2g[0];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW1A0);
-+                              sprom->core_pwr_info[0].pa_2g[1];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW1A1);
-+                              sprom->core_pwr_info[1].pa_2g[1];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW2A0);
-+                              sprom->core_pwr_info[0].pa_2g[2];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA2GW2A1);
-+                              sprom->core_pwr_info[1].pa_2g[2];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
--                              (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA0);
-+                              sprom->core_pwr_info[0].itssi_2g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
--                              (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA1);
-+                              sprom->core_pwr_info[1].itssi_2g;
-+
-+                      pi->cck2gpo = sprom->cck2gpo;
--                      pi->cck2gpo = (u16) wlapi_getintvar(shim,
--                                                          BRCMS_SROM_CCK2GPO);
-+                      pi->ofdm2gpo = sprom->ofdm2gpo;
--                      pi->ofdm2gpo =
--                              (u32) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_OFDM2GPO);
--
--                      pi->mcs2gpo[0] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO0);
--                      pi->mcs2gpo[1] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO1);
--                      pi->mcs2gpo[2] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO2);
--                      pi->mcs2gpo[3] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO3);
--                      pi->mcs2gpo[4] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO4);
--                      pi->mcs2gpo[5] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO5);
--                      pi->mcs2gpo[6] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO6);
--                      pi->mcs2gpo[7] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS2GPO7);
-+                      pi->mcs2gpo[0] = sprom->mcs2gpo[0];
-+                      pi->mcs2gpo[1] = sprom->mcs2gpo[1];
-+                      pi->mcs2gpo[2] = sprom->mcs2gpo[2];
-+                      pi->mcs2gpo[3] = sprom->mcs2gpo[3];
-+                      pi->mcs2gpo[4] = sprom->mcs2gpo[4];
-+                      pi->mcs2gpo[5] = sprom->mcs2gpo[5];
-+                      pi->mcs2gpo[6] = sprom->mcs2gpo[6];
-+                      pi->mcs2gpo[7] = sprom->mcs2gpo[7];
-                       break;
-               case 1:
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
--                              (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0);
-+                              sprom->core_pwr_info[0].maxpwr_5g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP5GA1);
-+                              sprom->core_pwr_info[1].maxpwr_5g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW0A0);
-+                              sprom->core_pwr_info[0].pa_5g[0];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW0A1);
-+                              sprom->core_pwr_info[1].pa_5g[0];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW1A0);
-+                              sprom->core_pwr_info[0].pa_5g[1];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW1A1);
-+                              sprom->core_pwr_info[1].pa_5g[1];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW2A0);
-+                              sprom->core_pwr_info[0].pa_5g[2];
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GW2A1);
-+                              sprom->core_pwr_info[1].pa_5g[2];
-                       pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
--                              (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA0);
-+                              sprom->core_pwr_info[0].itssi_5g;
-                       pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
--                              (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA1);
-+                              sprom->core_pwr_info[1].itssi_5g;
-+
-+                      pi->ofdm5gpo = sprom->ofdm5gpo;
--                      pi->ofdm5gpo =
--                              (u32) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_OFDM5GPO);
--
--                      pi->mcs5gpo[0] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO0);
--                      pi->mcs5gpo[1] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO1);
--                      pi->mcs5gpo[2] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO2);
--                      pi->mcs5gpo[3] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO3);
--                      pi->mcs5gpo[4] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO4);
--                      pi->mcs5gpo[5] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO5);
--                      pi->mcs5gpo[6] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO6);
--                      pi->mcs5gpo[7] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GPO7);
-+                      pi->mcs5gpo[0] = sprom->mcs5gpo[0];
-+                      pi->mcs5gpo[1] = sprom->mcs5gpo[1];
-+                      pi->mcs5gpo[2] = sprom->mcs5gpo[2];
-+                      pi->mcs5gpo[3] = sprom->mcs5gpo[3];
-+                      pi->mcs5gpo[4] = sprom->mcs5gpo[4];
-+                      pi->mcs5gpo[5] = sprom->mcs5gpo[5];
-+                      pi->mcs5gpo[6] = sprom->mcs5gpo[6];
-+                      pi->mcs5gpo[7] = sprom->mcs5gpo[7];
-                       break;
-               case 2:
-                       pi->nphy_pwrctrl_info[0].max_pwr_5gl =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP5GLA0);
-+                              sprom->core_pwr_info[0].maxpwr_5gl;
-                       pi->nphy_pwrctrl_info[1].max_pwr_5gl =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP5GLA1);
-+                              sprom->core_pwr_info[1].maxpwr_5gl;
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW0A0);
-+                              sprom->core_pwr_info[0].pa_5gl[0];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW0A1);
-+                              sprom->core_pwr_info[1].pa_5gl[0];
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW1A0);
-+                              sprom->core_pwr_info[0].pa_5gl[1];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW1A1);
-+                              sprom->core_pwr_info[1].pa_5gl[1];
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW2A0);
-+                              sprom->core_pwr_info[0].pa_5gl[2];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GLW2A1);
-+                              sprom->core_pwr_info[1].pa_5gl[2];
-                       pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
-                       pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
--                      pi->ofdm5glpo =
--                              (u32) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_OFDM5GLPO);
--
--                      pi->mcs5glpo[0] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO0);
--                      pi->mcs5glpo[1] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO1);
--                      pi->mcs5glpo[2] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO2);
--                      pi->mcs5glpo[3] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO3);
--                      pi->mcs5glpo[4] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO4);
--                      pi->mcs5glpo[5] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO5);
--                      pi->mcs5glpo[6] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO6);
--                      pi->mcs5glpo[7] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GLPO7);
-+                      pi->ofdm5glpo = sprom->ofdm5glpo;
-+
-+                      pi->mcs5glpo[0] = sprom->mcs5glpo[0];
-+                      pi->mcs5glpo[1] = sprom->mcs5glpo[1];
-+                      pi->mcs5glpo[2] = sprom->mcs5glpo[2];
-+                      pi->mcs5glpo[3] = sprom->mcs5glpo[3];
-+                      pi->mcs5glpo[4] = sprom->mcs5glpo[4];
-+                      pi->mcs5glpo[5] = sprom->mcs5glpo[5];
-+                      pi->mcs5glpo[6] = sprom->mcs5glpo[6];
-+                      pi->mcs5glpo[7] = sprom->mcs5glpo[7];
-                       break;
-               case 3:
-                       pi->nphy_pwrctrl_info[0].max_pwr_5gh =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP5GHA0);
-+                              sprom->core_pwr_info[0].maxpwr_5gh;
-                       pi->nphy_pwrctrl_info[1].max_pwr_5gh =
--                              (s8) wlapi_getintvar(shim,
--                                                   BRCMS_SROM_MAXP5GHA1);
-+                              sprom->core_pwr_info[1].maxpwr_5gh;
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW0A0);
-+                              sprom->core_pwr_info[0].pa_5gh[0];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW0A1);
-+                              sprom->core_pwr_info[1].pa_5gh[0];
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW1A0);
-+                              sprom->core_pwr_info[0].pa_5gh[1];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW1A1);
-+                              sprom->core_pwr_info[1].pa_5gh[1];
-                       pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW2A0);
-+                              sprom->core_pwr_info[0].pa_5gh[2];
-                       pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
--                              (s16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_PA5GHW2A1);
-+                              sprom->core_pwr_info[1].pa_5gh[2];
-                       pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
-                       pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
--                      pi->ofdm5ghpo =
--                              (u32) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_OFDM5GHPO);
--
--                      pi->mcs5ghpo[0] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO0);
--                      pi->mcs5ghpo[1] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO1);
--                      pi->mcs5ghpo[2] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO2);
--                      pi->mcs5ghpo[3] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO3);
--                      pi->mcs5ghpo[4] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO4);
--                      pi->mcs5ghpo[5] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO5);
--                      pi->mcs5ghpo[6] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO6);
--                      pi->mcs5ghpo[7] =
--                              (u16) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_MCS5GHPO7);
-+                      pi->ofdm5ghpo = sprom->ofdm5ghpo;
-+
-+                      pi->mcs5ghpo[0] = sprom->mcs5ghpo[0];
-+                      pi->mcs5ghpo[1] = sprom->mcs5ghpo[1];
-+                      pi->mcs5ghpo[2] = sprom->mcs5ghpo[2];
-+                      pi->mcs5ghpo[3] = sprom->mcs5ghpo[3];
-+                      pi->mcs5ghpo[4] = sprom->mcs5ghpo[4];
-+                      pi->mcs5ghpo[5] = sprom->mcs5ghpo[5];
-+                      pi->mcs5ghpo[6] = sprom->mcs5ghpo[6];
-+                      pi->mcs5ghpo[7] = sprom->mcs5ghpo[7];
-                       break;
-               }
-       }
-@@ -14666,45 +14561,34 @@ static void wlc_phy_txpwr_srom_read_ppr_
- static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
- {
--      struct phy_shim_info *shim = pi->sh->physhim;
-+      struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
--      pi->antswitch = (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWITCH);
--      pi->aa2g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G);
--      pi->aa5g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA5G);
--
--      pi->srom_fem2g.tssipos = (u8) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_TSSIPOS2G);
--      pi->srom_fem2g.extpagain = (u8) wlapi_getintvar(shim,
--                                                      BRCMS_SROM_EXTPAGAIN2G);
--      pi->srom_fem2g.pdetrange = (u8) wlapi_getintvar(shim,
--                                                      BRCMS_SROM_PDETRANGE2G);
--      pi->srom_fem2g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
--      pi->srom_fem2g.antswctrllut =
--                      (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
--
--      pi->srom_fem5g.tssipos = (u8) wlapi_getintvar(shim,
--                                                    BRCMS_SROM_TSSIPOS5G);
--      pi->srom_fem5g.extpagain = (u8) wlapi_getintvar(shim,
--                                                      BRCMS_SROM_EXTPAGAIN5G);
--      pi->srom_fem5g.pdetrange = (u8) wlapi_getintvar(shim,
--                                                      BRCMS_SROM_PDETRANGE5G);
--      pi->srom_fem5g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO5G);
--      if (wlapi_getvar(shim, BRCMS_SROM_ANTSWCTL5G))
--              pi->srom_fem5g.antswctrllut =
--                      (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL5G);
-+      pi->antswitch = sprom->antswitch;
-+      pi->aa2g = sprom->ant_available_bg;
-+      pi->aa5g = sprom->ant_available_a;
-+
-+      pi->srom_fem2g.tssipos = sprom->fem.ghz2.tssipos;
-+      pi->srom_fem2g.extpagain = sprom->fem.ghz2.extpa_gain;
-+      pi->srom_fem2g.pdetrange = sprom->fem.ghz2.pdet_range;
-+      pi->srom_fem2g.triso = sprom->fem.ghz2.tr_iso;
-+      pi->srom_fem2g.antswctrllut = sprom->fem.ghz2.antswlut;
-+
-+      pi->srom_fem5g.tssipos = sprom->fem.ghz5.tssipos;
-+      pi->srom_fem5g.extpagain = sprom->fem.ghz5.extpa_gain;
-+      pi->srom_fem5g.pdetrange = sprom->fem.ghz5.pdet_range;
-+      pi->srom_fem5g.triso = sprom->fem.ghz5.tr_iso;
-+      if (sprom->fem.ghz5.antswlut)
-+              pi->srom_fem5g.antswctrllut = sprom->fem.ghz5.antswlut;
-       else
--              pi->srom_fem5g.antswctrllut =
--                      (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
-+              pi->srom_fem5g.antswctrllut = sprom->fem.ghz2.antswlut;
-       wlc_phy_txpower_ipa_upd(pi);
--      pi->phy_txcore_disable_temp =
--                      (s16) wlapi_getintvar(shim, BRCMS_SROM_TEMPTHRESH);
-+      pi->phy_txcore_disable_temp = sprom->tempthresh;
-       if (pi->phy_txcore_disable_temp == 0)
-               pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
--      pi->phy_tempsense_offset = (s8) wlapi_getintvar(shim,
--                                                      BRCMS_SROM_TEMPOFFSET);
-+      pi->phy_tempsense_offset = sprom->tempoffset;
-       if (pi->phy_tempsense_offset != 0) {
-               if (pi->phy_tempsense_offset >
-                   (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET))
-@@ -14719,8 +14603,7 @@ static bool wlc_phy_txpwr_srom_read_nphy
-       pi->phy_txcore_enable_temp =
-               pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
--      pi->phycal_tempdelta =
--                      (u8) wlapi_getintvar(shim, BRCMS_SROM_PHYCAL_TEMPDELTA);
-+      pi->phycal_tempdelta = sprom->phycal_tempdelta;
-       if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA)
-               pi->phycal_tempdelta = 0;
-@@ -21462,7 +21345,7 @@ void wlc_phy_antsel_init(struct brcms_ph
-               write_phy_reg(pi, 0xc8, 0x0);
-               write_phy_reg(pi, 0xc9, 0x0);
--              ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
-+              bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc, mask, mask);
-               mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
-               mc &= ~MCTL_GPOUT_SEL_MASK;
---- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
-@@ -214,12 +214,3 @@ wlapi_copyto_objmem(struct phy_shim_info
- {
-       brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
- }
--
--char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
--{
--      return getvar(physhim->wlc_hw->sih, id);
--}
--int wlapi_getintvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
--{
--      return getintvar(physhim->wlc_hw->sih, id);
--}
---- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
-@@ -175,8 +175,5 @@ extern void wlapi_copyto_objmem(struct p
- extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim,
-                                      u32 phy_mode);
- extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
--extern char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id);
--extern int wlapi_getintvar(struct phy_shim_info *physhim,
--                         enum brcms_srom_id id);
- #endif                                /* _BRCM_PHY_SHIM_H_ */
---- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
-+++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
-@@ -22,232 +22,6 @@
- #include "types.h"
- #include "defs.h"
--enum brcms_srom_id {
--      BRCMS_SROM_NULL,
--      BRCMS_SROM_CONT,
--      BRCMS_SROM_AA2G,
--      BRCMS_SROM_AA5G,
--      BRCMS_SROM_AG0,
--      BRCMS_SROM_AG1,
--      BRCMS_SROM_AG2,
--      BRCMS_SROM_AG3,
--      BRCMS_SROM_ANTSWCTL2G,
--      BRCMS_SROM_ANTSWCTL5G,
--      BRCMS_SROM_ANTSWITCH,
--      BRCMS_SROM_BOARDFLAGS2,
--      BRCMS_SROM_BOARDFLAGS,
--      BRCMS_SROM_BOARDNUM,
--      BRCMS_SROM_BOARDREV,
--      BRCMS_SROM_BOARDTYPE,
--      BRCMS_SROM_BW40PO,
--      BRCMS_SROM_BWDUPPO,
--      BRCMS_SROM_BXA2G,
--      BRCMS_SROM_BXA5G,
--      BRCMS_SROM_CC,
--      BRCMS_SROM_CCK2GPO,
--      BRCMS_SROM_CCKBW202GPO,
--      BRCMS_SROM_CCKBW20UL2GPO,
--      BRCMS_SROM_CCODE,
--      BRCMS_SROM_CDDPO,
--      BRCMS_SROM_DEVID,
--      BRCMS_SROM_ET1MACADDR,
--      BRCMS_SROM_EXTPAGAIN2G,
--      BRCMS_SROM_EXTPAGAIN5G,
--      BRCMS_SROM_FREQOFFSET_CORR,
--      BRCMS_SROM_HW_IQCAL_EN,
--      BRCMS_SROM_IL0MACADDR,
--      BRCMS_SROM_IQCAL_SWP_DIS,
--      BRCMS_SROM_LEDBH0,
--      BRCMS_SROM_LEDBH1,
--      BRCMS_SROM_LEDBH2,
--      BRCMS_SROM_LEDBH3,
--      BRCMS_SROM_LEDDC,
--      BRCMS_SROM_LEGOFDM40DUPPO,
--      BRCMS_SROM_LEGOFDMBW202GPO,
--      BRCMS_SROM_LEGOFDMBW205GHPO,
--      BRCMS_SROM_LEGOFDMBW205GLPO,
--      BRCMS_SROM_LEGOFDMBW205GMPO,
--      BRCMS_SROM_LEGOFDMBW20UL2GPO,
--      BRCMS_SROM_LEGOFDMBW20UL5GHPO,
--      BRCMS_SROM_LEGOFDMBW20UL5GLPO,
--      BRCMS_SROM_LEGOFDMBW20UL5GMPO,
--      BRCMS_SROM_MACADDR,
--      BRCMS_SROM_MCS2GPO0,
--      BRCMS_SROM_MCS2GPO1,
--      BRCMS_SROM_MCS2GPO2,
--      BRCMS_SROM_MCS2GPO3,
--      BRCMS_SROM_MCS2GPO4,
--      BRCMS_SROM_MCS2GPO5,
--      BRCMS_SROM_MCS2GPO6,
--      BRCMS_SROM_MCS2GPO7,
--      BRCMS_SROM_MCS32PO,
--      BRCMS_SROM_MCS5GHPO0,
--      BRCMS_SROM_MCS5GHPO1,
--      BRCMS_SROM_MCS5GHPO2,
--      BRCMS_SROM_MCS5GHPO3,
--      BRCMS_SROM_MCS5GHPO4,
--      BRCMS_SROM_MCS5GHPO5,
--      BRCMS_SROM_MCS5GHPO6,
--      BRCMS_SROM_MCS5GHPO7,
--      BRCMS_SROM_MCS5GLPO0,
--      BRCMS_SROM_MCS5GLPO1,
--      BRCMS_SROM_MCS5GLPO2,
--      BRCMS_SROM_MCS5GLPO3,
--      BRCMS_SROM_MCS5GLPO4,
--      BRCMS_SROM_MCS5GLPO5,
--      BRCMS_SROM_MCS5GLPO6,
--      BRCMS_SROM_MCS5GLPO7,
--      BRCMS_SROM_MCS5GPO0,
--      BRCMS_SROM_MCS5GPO1,
--      BRCMS_SROM_MCS5GPO2,
--      BRCMS_SROM_MCS5GPO3,
--      BRCMS_SROM_MCS5GPO4,
--      BRCMS_SROM_MCS5GPO5,
--      BRCMS_SROM_MCS5GPO6,
--      BRCMS_SROM_MCS5GPO7,
--      BRCMS_SROM_MCSBW202GPO,
--      BRCMS_SROM_MCSBW205GHPO,
--      BRCMS_SROM_MCSBW205GLPO,
--      BRCMS_SROM_MCSBW205GMPO,
--      BRCMS_SROM_MCSBW20UL2GPO,
--      BRCMS_SROM_MCSBW20UL5GHPO,
--      BRCMS_SROM_MCSBW20UL5GLPO,
--      BRCMS_SROM_MCSBW20UL5GMPO,
--      BRCMS_SROM_MCSBW402GPO,
--      BRCMS_SROM_MCSBW405GHPO,
--      BRCMS_SROM_MCSBW405GLPO,
--      BRCMS_SROM_MCSBW405GMPO,
--      BRCMS_SROM_MEASPOWER,
--      BRCMS_SROM_OFDM2GPO,
--      BRCMS_SROM_OFDM5GHPO,
--      BRCMS_SROM_OFDM5GLPO,
--      BRCMS_SROM_OFDM5GPO,
--      BRCMS_SROM_OPO,
--      BRCMS_SROM_PA0B0,
--      BRCMS_SROM_PA0B1,
--      BRCMS_SROM_PA0B2,
--      BRCMS_SROM_PA0ITSSIT,
--      BRCMS_SROM_PA0MAXPWR,
--      BRCMS_SROM_PA1B0,
--      BRCMS_SROM_PA1B1,
--      BRCMS_SROM_PA1B2,
--      BRCMS_SROM_PA1HIB0,
--      BRCMS_SROM_PA1HIB1,
--      BRCMS_SROM_PA1HIB2,
--      BRCMS_SROM_PA1HIMAXPWR,
--      BRCMS_SROM_PA1ITSSIT,
--      BRCMS_SROM_PA1LOB0,
--      BRCMS_SROM_PA1LOB1,
--      BRCMS_SROM_PA1LOB2,
--      BRCMS_SROM_PA1LOMAXPWR,
--      BRCMS_SROM_PA1MAXPWR,
--      BRCMS_SROM_PDETRANGE2G,
--      BRCMS_SROM_PDETRANGE5G,
--      BRCMS_SROM_PHYCAL_TEMPDELTA,
--      BRCMS_SROM_RAWTEMPSENSE,
--      BRCMS_SROM_REGREV,
--      BRCMS_SROM_REV,
--      BRCMS_SROM_RSSISAV2G,
--      BRCMS_SROM_RSSISAV5G,
--      BRCMS_SROM_RSSISMC2G,
--      BRCMS_SROM_RSSISMC5G,
--      BRCMS_SROM_RSSISMF2G,
--      BRCMS_SROM_RSSISMF5G,
--      BRCMS_SROM_RXCHAIN,
--      BRCMS_SROM_RXPO2G,
--      BRCMS_SROM_RXPO5G,
--      BRCMS_SROM_STBCPO,
--      BRCMS_SROM_TEMPCORRX,
--      BRCMS_SROM_TEMPOFFSET,
--      BRCMS_SROM_TEMPSENSE_OPTION,
--      BRCMS_SROM_TEMPSENSE_SLOPE,
--      BRCMS_SROM_TEMPTHRESH,
--      BRCMS_SROM_TRI2G,
--      BRCMS_SROM_TRI5GH,
--      BRCMS_SROM_TRI5GL,
--      BRCMS_SROM_TRI5G,
--      BRCMS_SROM_TRISO2G,
--      BRCMS_SROM_TRISO5G,
--      BRCMS_SROM_TSSIPOS2G,
--      BRCMS_SROM_TSSIPOS5G,
--      BRCMS_SROM_TXCHAIN,
--      /*
--       * per-path identifiers (see srom.c)
--       */
--      BRCMS_SROM_ITT2GA0,
--      BRCMS_SROM_ITT2GA1,
--      BRCMS_SROM_ITT2GA2,
--      BRCMS_SROM_ITT2GA3,
--      BRCMS_SROM_ITT5GA0,
--      BRCMS_SROM_ITT5GA1,
--      BRCMS_SROM_ITT5GA2,
--      BRCMS_SROM_ITT5GA3,
--      BRCMS_SROM_MAXP2GA0,
--      BRCMS_SROM_MAXP2GA1,
--      BRCMS_SROM_MAXP2GA2,
--      BRCMS_SROM_MAXP2GA3,
--      BRCMS_SROM_MAXP5GA0,
--      BRCMS_SROM_MAXP5GA1,
--      BRCMS_SROM_MAXP5GA2,
--      BRCMS_SROM_MAXP5GA3,
--      BRCMS_SROM_MAXP5GHA0,
--      BRCMS_SROM_MAXP5GHA1,
--      BRCMS_SROM_MAXP5GHA2,
--      BRCMS_SROM_MAXP5GHA3,
--      BRCMS_SROM_MAXP5GLA0,
--      BRCMS_SROM_MAXP5GLA1,
--      BRCMS_SROM_MAXP5GLA2,
--      BRCMS_SROM_MAXP5GLA3,
--      BRCMS_SROM_PA2GW0A0,
--      BRCMS_SROM_PA2GW0A1,
--      BRCMS_SROM_PA2GW0A2,
--      BRCMS_SROM_PA2GW0A3,
--      BRCMS_SROM_PA2GW1A0,
--      BRCMS_SROM_PA2GW1A1,
--      BRCMS_SROM_PA2GW1A2,
--      BRCMS_SROM_PA2GW1A3,
--      BRCMS_SROM_PA2GW2A0,
--      BRCMS_SROM_PA2GW2A1,
--      BRCMS_SROM_PA2GW2A2,
--      BRCMS_SROM_PA2GW2A3,
--      BRCMS_SROM_PA5GHW0A0,
--      BRCMS_SROM_PA5GHW0A1,
--      BRCMS_SROM_PA5GHW0A2,
--      BRCMS_SROM_PA5GHW0A3,
--      BRCMS_SROM_PA5GHW1A0,
--      BRCMS_SROM_PA5GHW1A1,
--      BRCMS_SROM_PA5GHW1A2,
--      BRCMS_SROM_PA5GHW1A3,
--      BRCMS_SROM_PA5GHW2A0,
--      BRCMS_SROM_PA5GHW2A1,
--      BRCMS_SROM_PA5GHW2A2,
--      BRCMS_SROM_PA5GHW2A3,
--      BRCMS_SROM_PA5GLW0A0,
--      BRCMS_SROM_PA5GLW0A1,
--      BRCMS_SROM_PA5GLW0A2,
--      BRCMS_SROM_PA5GLW0A3,
--      BRCMS_SROM_PA5GLW1A0,
--      BRCMS_SROM_PA5GLW1A1,
--      BRCMS_SROM_PA5GLW1A2,
--      BRCMS_SROM_PA5GLW1A3,
--      BRCMS_SROM_PA5GLW2A0,
--      BRCMS_SROM_PA5GLW2A1,
--      BRCMS_SROM_PA5GLW2A2,
--      BRCMS_SROM_PA5GLW2A3,
--      BRCMS_SROM_PA5GW0A0,
--      BRCMS_SROM_PA5GW0A1,
--      BRCMS_SROM_PA5GW0A2,
--      BRCMS_SROM_PA5GW0A3,
--      BRCMS_SROM_PA5GW1A0,
--      BRCMS_SROM_PA5GW1A1,
--      BRCMS_SROM_PA5GW1A2,
--      BRCMS_SROM_PA5GW1A3,
--      BRCMS_SROM_PA5GW2A0,
--      BRCMS_SROM_PA5GW2A1,
--      BRCMS_SROM_PA5GW2A2,
--      BRCMS_SROM_PA5GW2A3,
--};
--
- #define       BRCMS_NUMRATES  16      /* max # of rates in a rateset */
- /* phy types */
-@@ -565,8 +339,6 @@ extern void brcms_c_ampdu_flush(struct b
-                           struct ieee80211_sta *sta, u16 tid);
- extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
-                                        u8 ba_wsize, uint max_rx_ampdu_bytes);
--extern char *getvar(struct si_pub *sih, enum brcms_srom_id id);
--extern int getintvar(struct si_pub *sih, enum brcms_srom_id id);
- extern int brcms_c_module_register(struct brcms_pub *pub,
-                                  const char *name, struct brcms_info *hdl,
-                                  int (*down_fn)(void *handle));
---- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
-+++ /dev/null
-@@ -1,980 +0,0 @@
--/*
-- * Copyright (c) 2010 Broadcom Corporation
-- *
-- * Permission to use, copy, modify, and/or distribute this software for any
-- * purpose with or without fee is hereby granted, provided that the above
-- * copyright notice and this permission notice appear in all copies.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
-- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-- */
--
--#include <linux/kernel.h>
--#include <linux/string.h>
--#include <linux/io.h>
--#include <linux/etherdevice.h>
--#include <linux/crc8.h>
--#include <stdarg.h>
--
--#include <chipcommon.h>
--#include <brcmu_utils.h>
--#include "pub.h"
--#include "nicpci.h"
--#include "aiutils.h"
--#include "otp.h"
--#include "srom.h"
--#include "soc.h"
--
--/*
-- * SROM CRC8 polynomial value:
-- *
-- * x^8 + x^7 +x^6 + x^4 + x^2 + 1
-- */
--#define SROM_CRC8_POLY                0xAB
--
--/* Maximum srom: 6 Kilobits == 768 bytes */
--#define       SROM_MAX                768
--
--/* PCI fields */
--#define PCI_F0DEVID           48
--
--#define       SROM_WORDS              64
--
--#define       SROM_SSID               2
--
--#define       SROM_WL1LHMAXP          29
--
--#define       SROM_WL1LPAB0           30
--#define       SROM_WL1LPAB1           31
--#define       SROM_WL1LPAB2           32
--
--#define       SROM_WL1HPAB0           33
--#define       SROM_WL1HPAB1           34
--#define       SROM_WL1HPAB2           35
--
--#define       SROM_MACHI_IL0          36
--#define       SROM_MACMID_IL0         37
--#define       SROM_MACLO_IL0          38
--#define       SROM_MACHI_ET1          42
--#define       SROM_MACMID_ET1         43
--#define       SROM_MACLO_ET1          44
--
--#define       SROM_BXARSSI2G          40
--#define       SROM_BXARSSI5G          41
--
--#define       SROM_TRI52G             42
--#define       SROM_TRI5GHL            43
--
--#define       SROM_RXPO52G            45
--
--#define       SROM_AABREV             46
--/* Fields in AABREV */
--#define       SROM_BR_MASK            0x00ff
--#define       SROM_CC_MASK            0x0f00
--#define       SROM_CC_SHIFT           8
--#define       SROM_AA0_MASK           0x3000
--#define       SROM_AA0_SHIFT          12
--#define       SROM_AA1_MASK           0xc000
--#define       SROM_AA1_SHIFT          14
--
--#define       SROM_WL0PAB0            47
--#define       SROM_WL0PAB1            48
--#define       SROM_WL0PAB2            49
--
--#define       SROM_LEDBH10            50
--#define       SROM_LEDBH32            51
--
--#define       SROM_WL10MAXP           52
--
--#define       SROM_WL1PAB0            53
--#define       SROM_WL1PAB1            54
--#define       SROM_WL1PAB2            55
--
--#define       SROM_ITT                56
--
--#define       SROM_BFL                57
--#define       SROM_BFL2               28
--
--#define       SROM_AG10               58
--
--#define       SROM_CCODE              59
--
--#define       SROM_OPO                60
--
--#define       SROM_CRCREV             63
--
--#define       SROM4_WORDS             220
--
--#define SROM4_TXCHAIN_MASK    0x000f
--#define SROM4_RXCHAIN_MASK    0x00f0
--#define SROM4_SWITCH_MASK     0xff00
--
--/* Per-path fields */
--#define       MAX_PATH_SROM           4
--
--#define       SROM4_CRCREV            219
--
--/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
-- * This is acombined srom for both MIMO and SISO boards, usable in
-- * the .130 4Kilobit OTP with hardware redundancy.
-- */
--#define       SROM8_BREV              65
--
--#define       SROM8_BFL0              66
--#define       SROM8_BFL1              67
--#define       SROM8_BFL2              68
--#define       SROM8_BFL3              69
--
--#define       SROM8_MACHI             70
--#define       SROM8_MACMID            71
--#define       SROM8_MACLO             72
--
--#define       SROM8_CCODE             73
--#define       SROM8_REGREV            74
--
--#define       SROM8_LEDBH10           75
--#define       SROM8_LEDBH32           76
--
--#define       SROM8_LEDDC             77
--
--#define       SROM8_AA                78
--
--#define       SROM8_AG10              79
--#define       SROM8_AG32              80
--
--#define       SROM8_TXRXC             81
--
--#define       SROM8_BXARSSI2G         82
--#define       SROM8_BXARSSI5G         83
--#define       SROM8_TRI52G            84
--#define       SROM8_TRI5GHL           85
--#define       SROM8_RXPO52G           86
--
--#define SROM8_FEM2G           87
--#define SROM8_FEM5G           88
--#define SROM8_FEM_ANTSWLUT_MASK               0xf800
--#define SROM8_FEM_ANTSWLUT_SHIFT      11
--#define SROM8_FEM_TR_ISO_MASK         0x0700
--#define SROM8_FEM_TR_ISO_SHIFT                8
--#define SROM8_FEM_PDET_RANGE_MASK     0x00f8
--#define SROM8_FEM_PDET_RANGE_SHIFT    3
--#define SROM8_FEM_EXTPA_GAIN_MASK     0x0006
--#define SROM8_FEM_EXTPA_GAIN_SHIFT    1
--#define SROM8_FEM_TSSIPOS_MASK                0x0001
--#define SROM8_FEM_TSSIPOS_SHIFT               0
--
--#define SROM8_THERMAL         89
--
--/* Temp sense related entries */
--#define SROM8_MPWR_RAWTS              90
--#define SROM8_TS_SLP_OPT_CORRX        91
--/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
-- * IQSWP: IQ CAL swap disable */
--#define SROM8_FOC_HWIQ_IQSWP  92
--
--/* Temperature delta for PHY calibration */
--#define SROM8_PHYCAL_TEMPDELTA        93
--
--/* Per-path offsets & fields */
--#define       SROM8_PATH0             96
--#define       SROM8_PATH1             112
--#define       SROM8_PATH2             128
--#define       SROM8_PATH3             144
--
--#define       SROM8_2G_ITT_MAXP       0
--#define       SROM8_2G_PA             1
--#define       SROM8_5G_ITT_MAXP       4
--#define       SROM8_5GLH_MAXP         5
--#define       SROM8_5G_PA             6
--#define       SROM8_5GL_PA            9
--#define       SROM8_5GH_PA            12
--
--/* All the miriad power offsets */
--#define       SROM8_2G_CCKPO          160
--
--#define       SROM8_2G_OFDMPO         161
--#define       SROM8_5G_OFDMPO         163
--#define       SROM8_5GL_OFDMPO        165
--#define       SROM8_5GH_OFDMPO        167
--
--#define       SROM8_2G_MCSPO          169
--#define       SROM8_5G_MCSPO          177
--#define       SROM8_5GL_MCSPO         185
--#define       SROM8_5GH_MCSPO         193
--
--#define       SROM8_CDDPO             201
--#define       SROM8_STBCPO            202
--#define       SROM8_BW40PO            203
--#define       SROM8_BWDUPPO           204
--
--/* SISO PA parameters are in the path0 spaces */
--#define       SROM8_SISO              96
--
--/* Legacy names for SISO PA paramters */
--#define       SROM8_W0_ITTMAXP        (SROM8_SISO + SROM8_2G_ITT_MAXP)
--#define       SROM8_W0_PAB0           (SROM8_SISO + SROM8_2G_PA)
--#define       SROM8_W0_PAB1           (SROM8_SISO + SROM8_2G_PA + 1)
--#define       SROM8_W0_PAB2           (SROM8_SISO + SROM8_2G_PA + 2)
--#define       SROM8_W1_ITTMAXP        (SROM8_SISO + SROM8_5G_ITT_MAXP)
--#define       SROM8_W1_MAXP_LCHC      (SROM8_SISO + SROM8_5GLH_MAXP)
--#define       SROM8_W1_PAB0           (SROM8_SISO + SROM8_5G_PA)
--#define       SROM8_W1_PAB1           (SROM8_SISO + SROM8_5G_PA + 1)
--#define       SROM8_W1_PAB2           (SROM8_SISO + SROM8_5G_PA + 2)
--#define       SROM8_W1_PAB0_LC        (SROM8_SISO + SROM8_5GL_PA)
--#define       SROM8_W1_PAB1_LC        (SROM8_SISO + SROM8_5GL_PA + 1)
--#define       SROM8_W1_PAB2_LC        (SROM8_SISO + SROM8_5GL_PA + 2)
--#define       SROM8_W1_PAB0_HC        (SROM8_SISO + SROM8_5GH_PA)
--#define       SROM8_W1_PAB1_HC        (SROM8_SISO + SROM8_5GH_PA + 1)
--#define       SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
--
--/* SROM REV 9 */
--#define SROM9_2GPO_CCKBW20    160
--#define SROM9_2GPO_CCKBW20UL  161
--#define SROM9_2GPO_LOFDMBW20  162
--#define SROM9_2GPO_LOFDMBW20UL        164
--
--#define SROM9_5GLPO_LOFDMBW20 166
--#define SROM9_5GLPO_LOFDMBW20UL       168
--#define SROM9_5GMPO_LOFDMBW20 170
--#define SROM9_5GMPO_LOFDMBW20UL       172
--#define SROM9_5GHPO_LOFDMBW20 174
--#define SROM9_5GHPO_LOFDMBW20UL       176
--
--#define SROM9_2GPO_MCSBW20    178
--#define SROM9_2GPO_MCSBW20UL  180
--#define SROM9_2GPO_MCSBW40    182
--
--#define SROM9_5GLPO_MCSBW20   184
--#define SROM9_5GLPO_MCSBW20UL 186
--#define SROM9_5GLPO_MCSBW40   188
--#define SROM9_5GMPO_MCSBW20   190
--#define SROM9_5GMPO_MCSBW20UL 192
--#define SROM9_5GMPO_MCSBW40   194
--#define SROM9_5GHPO_MCSBW20   196
--#define SROM9_5GHPO_MCSBW20UL 198
--#define SROM9_5GHPO_MCSBW40   200
--
--#define SROM9_PO_MCS32                202
--#define SROM9_PO_LOFDM40DUP   203
--
--/* SROM flags (see sromvar_t) */
--
--/* value continues as described by the next entry */
--#define SRFL_MORE     1
--#define       SRFL_NOFFS      2       /* value bits can't be all one's */
--#define       SRFL_PRHEX      4       /* value is in hexdecimal format */
--#define       SRFL_PRSIGN     8       /* value is in signed decimal format */
--#define       SRFL_CCODE      0x10    /* value is in country code format */
--#define       SRFL_ETHADDR    0x20    /* value is an Ethernet address */
--#define SRFL_LEDDC    0x40    /* value is an LED duty cycle */
--/* do not generate a nvram param, entry is for mfgc */
--#define SRFL_NOVAR    0x80
--
--/* Max. nvram variable table size */
--#define       MAXSZ_NVRAM_VARS        4096
--
--/*
-- * indicates type of value.
-- */
--enum brcms_srom_var_type {
--      BRCMS_SROM_STRING,
--      BRCMS_SROM_SNUMBER,
--      BRCMS_SROM_UNUMBER
--};
--
--/*
-- * storage type for srom variable.
-- *
-- * var_list: for linked list operations.
-- * varid: identifier of the variable.
-- * var_type: type of variable.
-- * buf: variable value when var_type == BRCMS_SROM_STRING.
-- * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
-- * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
-- */
--struct brcms_srom_list_head {
--      struct list_head var_list;
--      enum brcms_srom_id varid;
--      enum brcms_srom_var_type var_type;
--      union {
--              char buf[0];
--              u32 uval;
--              s32 sval;
--      };
--};
--
--struct brcms_sromvar {
--      enum brcms_srom_id varid;
--      u32 revmask;
--      u32 flags;
--      u16 off;
--      u16 mask;
--};
--
--struct brcms_varbuf {
--      char *base;             /* pointer to buffer base */
--      char *buf;              /* pointer to current position */
--      unsigned int size;      /* current (residual) size in bytes */
--};
--
--/*
-- * Assumptions:
-- * - Ethernet address spans across 3 consecutive words
-- *
-- * Table rules:
-- * - Add multiple entries next to each other if a value spans across multiple
-- *   words (even multiple fields in the same word) with each entry except the
-- *   last having it's SRFL_MORE bit set.
-- * - Ethernet address entry does not follow above rule and must not have
-- *   SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
-- * - The last entry's name field must be NULL to indicate the end of the table.
-- *   Other entries must have non-NULL name.
-- */
--static const struct brcms_sromvar pci_sromvars[] = {
--      {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
--       0xffff},
--      {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
--      {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
--      {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
--      {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
--      {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
--      {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
--      {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
--      {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
--      {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
--      {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
--      {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
--      {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
--      {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
--      {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
--      {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
--      {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
--      {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
--      {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
--      {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
--      {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
--      {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
--      {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
--      {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
--      {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
--      {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
--      {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
--      {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
--      {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
--      {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
--      {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
--      {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
--      {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
--      {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
--      {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
--      {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
--      {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
--      {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
--      {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
--      {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
--      {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
--      {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
--      {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
--      {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
--      {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
--      {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
--      {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
--      {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
--      {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
--      {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
--      {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
--       SROM4_TXCHAIN_MASK},
--      {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
--       SROM4_RXCHAIN_MASK},
--      {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
--       SROM4_SWITCH_MASK},
--      {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
--       SROM8_FEM_TSSIPOS_MASK},
--      {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
--       SROM8_FEM_EXTPA_GAIN_MASK},
--      {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
--       SROM8_FEM_PDET_RANGE_MASK},
--      {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
--      {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
--       SROM8_FEM_ANTSWLUT_MASK},
--      {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
--       SROM8_FEM_TSSIPOS_MASK},
--      {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
--       SROM8_FEM_EXTPA_GAIN_MASK},
--      {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
--       SROM8_FEM_PDET_RANGE_MASK},
--      {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
--      {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
--       SROM8_FEM_ANTSWLUT_MASK},
--      {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
--      {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
--
--      {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
--      {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
--      {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
--       0xffff},
--      {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
--       0x01ff},
--      {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
--       0xfe00},
--      {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
--       SROM8_TS_SLP_OPT_CORRX, 0x00ff},
--      {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
--       0xfc00},
--      {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
--       SROM8_TS_SLP_OPT_CORRX, 0x0300},
--      {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
--       SROM8_FOC_HWIQ_IQSWP, 0x000f},
--      {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
--       0x0010},
--      {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
--       0x0020},
--      {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
--       0x00ff},
--
--      {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
--      {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
--      {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
--      {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
--      {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
--      {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
--      {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
--      {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
--      {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
--      {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
--      {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
--      {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
--      {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
--      {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
--      {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
--      {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
--      {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
--      {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
--      {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
--      {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
--      {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
--      {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
--      {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
--      {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
--      {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
--      {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
--      {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
--      {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
--      {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
--      {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
--      {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
--      {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
--      {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
--      {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
--      {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
--      {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
--      {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
--      {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
--      {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
--      {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
--      {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
--
--      /* power per rate from sromrev 9 */
--      {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
--      {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
--       SROM9_2GPO_LOFDMBW20, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
--       SROM9_2GPO_LOFDMBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GLPO_LOFDMBW20, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GLPO_LOFDMBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GMPO_LOFDMBW20, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GMPO_LOFDMBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GHPO_LOFDMBW20, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
--      {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GHPO_LOFDMBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
--      {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
--      {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GLPO_MCSBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
--      {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GMPO_MCSBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
--      {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
--      {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
--       SROM9_5GHPO_MCSBW20UL, 0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
--      {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
--       0xffff},
--      {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
--      {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
--      {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
--
--      {BRCMS_SROM_NULL, 0, 0, 0, 0}
--};
--
--static const struct brcms_sromvar perpath_pci_sromvars[] = {
--      {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
--      {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
--      {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
--      {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
--      {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
--      {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
--      {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
--      {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
--      {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
--      {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
--      {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
--      {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
--      {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
--      {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
--       0xffff},
--      {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
--       0xffff},
--      {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
--      {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
--       0xffff},
--      {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
--       0xffff},
--      {BRCMS_SROM_NULL, 0, 0, 0, 0}
--};
--
--/* crc table has the same contents for every device instance, so it can be
-- * shared between devices. */
--static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
--
--static uint mask_shift(u16 mask)
--{
--      uint i;
--      for (i = 0; i < (sizeof(mask) << 3); i++) {
--              if (mask & (1 << i))
--                      return i;
--      }
--      return 0;
--}
--
--static uint mask_width(u16 mask)
--{
--      int i;
--      for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
--              if (mask & (1 << i))
--                      return (uint) (i - mask_shift(mask) + 1);
--      }
--      return 0;
--}
--
--static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
--{
--      while (nwords--)
--              *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
--}
--
--static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
--{
--      while (nwords--)
--              *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
--}
--
--/*
-- * convert binary srom data into linked list of srom variable items.
-- */
--static int
--_initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
--{
--      struct brcms_srom_list_head *entry;
--      enum brcms_srom_id id;
--      u16 w;
--      u32 val = 0;
--      const struct brcms_sromvar *srv;
--      uint width;
--      uint flags;
--      u32 sr = (1 << sromrev);
--      uint p;
--      uint pb =  SROM8_PATH0;
--      const uint psz = SROM8_PATH1 - SROM8_PATH0;
--
--      /* first store the srom revision */
--      entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
--      if (!entry)
--              return -ENOMEM;
--
--      entry->varid = BRCMS_SROM_REV;
--      entry->var_type = BRCMS_SROM_UNUMBER;
--      entry->uval = sromrev;
--      list_add(&entry->var_list, var_list);
--
--      for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
--              enum brcms_srom_var_type type;
--              u8 ea[ETH_ALEN];
--              u8 extra_space = 0;
--
--              if ((srv->revmask & sr) == 0)
--                      continue;
--
--              flags = srv->flags;
--              id = srv->varid;
--
--              /* This entry is for mfgc only. Don'