ar71xx: add AR933X GMAC register defines
authorGabor Juhos <juhosg@openwrt.org>
Tue, 1 Nov 2011 11:20:50 +0000 (11:20 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Tue, 1 Nov 2011 11:20:50 +0000 (11:20 +0000)
SVN-Revision: 28705

target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

index 4a732e2..97ac835 100644 (file)
@@ -72,6 +72,8 @@
 
 #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
 #define AR933X_UART_SIZE       0x14
+#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE       0x04
 #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
 #define AR933X_WMAC_SIZE       0x20000
 
@@ -768,6 +770,23 @@ void ar71xx_flash_release(void);
 #define MII1_CTRL_IF_RGMII     0
 #define MII1_CTRL_IF_RMII      1
 
+/*
+ * AR933X GMAC
+ */
+#define AR933X_GMAC_REG_ETH_CFG                0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
+#define AR933X_ETH_CFG_MII_GE0         BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* __ASM_MACH_AR71XX_H */