ifdef CONFIG_MODVERSIONS
diff -urN linux.old/Rules.make linux.dev/Rules.make
---- linux.old/Rules.make 2004-02-18 14:36:30.000000000 +0100
-+++ linux.dev/Rules.make 2005-08-26 13:44:34.252400640 +0200
+--- linux.old/Rules.make 2005-11-07 23:12:50.538884250 +0100
++++ linux.dev/Rules.make 2005-11-07 21:57:07.837585250 +0100
@@ -176,7 +176,14 @@
_modinst__: dummy
ifneq "$(strip $(ALL_MOBJS))" ""
.PHONY: modules_install
diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
---- linux.old/arch/mips/Makefile 2005-08-26 13:41:41.690634016 +0200
-+++ linux.dev/arch/mips/Makefile 2005-08-26 13:44:34.253400488 +0200
+--- linux.old/arch/mips/Makefile 2005-11-07 23:12:50.582887000 +0100
++++ linux.dev/arch/mips/Makefile 2005-11-07 21:57:08.537629000 +0100
@@ -46,10 +46,10 @@
GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
@$(MAKEBOOT) mrproper
diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
--- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/Makefile 2005-08-26 13:44:34.262399120 +0200
++++ linux.dev/arch/mips/bcm947xx/Makefile 2005-11-08 00:55:04.392074500 +0100
@@ -0,0 +1,15 @@
+#
+# Makefile for the BCM947xx specific kernel interface routines
+
+export-objs := nvram_linux.o setup.o
+obj-y := prom.o setup.o time.o sbmips.o gpio.o
-+obj-y += nvram.o nvram_linux.o
++obj-y += nvram.o nvram_linux.o sflash.o
+obj-$(CONFIG_PCI) += sbpci.o pcibios.o
+
+include $(TOPDIR)/Rules.make
diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
--- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-08-26 13:44:34.262399120 +0200
++++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-11-07 21:57:07.841585500 +0100
@@ -0,0 +1,33 @@
+#
+# Makefile for Broadcom BCM947XX boards
+ rm -f vmlinuz piggy
diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
--- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-08-26 13:44:34.263398968 +0200
++++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-11-07 21:57:07.841585500 +0100
@@ -0,0 +1,15 @@
+#
+# Makefile for the BCM947xx specific kernel interface routines
+include $(TOPDIR)/Rules.make
diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
--- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-08-26 13:44:34.263398968 +0200
++++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-11-07 21:57:07.841585500 +0100
@@ -0,0 +1,51 @@
+/*
+ * Generic interrupt handler for Broadcom MIPS boards
+ END(brcmIRQ)
diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
--- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-08-26 13:44:34.263398968 +0200
++++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-11-07 21:57:07.841585500 +0100
@@ -0,0 +1,130 @@
+/*
+ * Generic interrupt control functions for Broadcom MIPS boards
+}
diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
--- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-08-26 13:44:34.264398816 +0200
++++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-11-07 23:58:34.968754500 +0100
@@ -0,0 +1,158 @@
+/*
+ * GPIO char driver
+ *
-+ * Copyright 2004, Broadcom Corporation
++ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
-+ * $Id: gpio.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
++ * $Id$
+ */
+
+#include <linux/module.h>
+#include <sbutils.h>
+#include <bcmdevs.h>
+
-+static void *gpio_sbh;
++static sb_t *gpio_sbh;
+static int gpio_major;
+static devfs_handle_t gpio_dir;
+static struct {
+ val = sb_gpioin(gpio_sbh);
+ break;
+ case 1:
-+ val = sb_gpioout(gpio_sbh, 0, 0);
++ val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
+ break;
+ case 2:
-+ val = sb_gpioouten(gpio_sbh, 0, 0);
++ val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
+ break;
+ case 3:
-+ val = sb_gpiocontrol(gpio_sbh, 0, 0);
++ val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
+ break;
+ default:
+ return -ENODEV;
+ case 0:
+ return -EACCES;
+ case 1:
-+ sb_gpioout(gpio_sbh, ~0, val);
++ sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
+ break;
+ case 2:
-+ sb_gpioouten(gpio_sbh, ~0, val);
++ sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
+ break;
+ case 3:
-+ sb_gpiocontrol(gpio_sbh, ~0, val);
++ sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
+ break;
+ default:
+ return -ENODEV;
+module_exit(gpio_exit);
diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
--- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-08-26 13:44:34.265398664 +0200
-@@ -0,0 +1,369 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-11-07 22:51:38.772725750 +0100
+@@ -0,0 +1,391 @@
+/*
+ * Broadcom device-specific manifest constants.
+ *
+#define BCM4310_USB_ID 0x4315 /* 4310 usb */
+
+#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
++#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
++
+
+#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
+#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
+#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
+#define BFL_HGPA 0x2000 /* This board has a high gain PA */
+#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
++#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
+
+/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
+#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
+#endif
+
+/* power control defines */
-+#define PLL_DELAY 150 /* 150us pll on delay */
-+#define FREF_DELAY 200 /* 200us fref change delay */
-+#define MIN_SLOW_CLK 32 /* 32us Slow clock period */
++#define PLL_DELAY 150 /* us pll on delay */
++#define FREF_DELAY 200 /* us fref change delay */
++#define MIN_SLOW_CLK 32 /* us Slow clock period */
++#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
+
+/* Reference Board Types */
+
+#define MP4318_BOARD 0x044a
+#define SD4318_BOARD 0x044b
+
++/* BCM63XX boards */
++#define BCM96338_BOARD 0x6338
++#define BCM96345_BOARD 0x6345
++#define BCM96348_BOARD 0x6348
++
+/* Another mp4306 with SiGe */
+#define BCM94306P_BOARD 0x044c
+
+/* 4306mplna */
+#define BCM94306MPLNA_BOARD 0x0457
+
++/* 4320 boards */
++#define BU4320_BOARD 0x0458
++#define BU4320S_BOARD 0x0459
++#define BCM94320PH_BOARD 0x045a
+
+/* 4306mph */
+#define BCM94306MPH_BOARD 0x045b
+
+#define BU4712SD_BOARD 0x045d
+
++#define BCM94320PFLSH_BOARD 0x045e
+
+#define BU4712L_BOARD 0x045f
+#define BCM94712LGR_BOARD 0x0460
++#define BCM94320R_BOARD 0x0461
+
+#define BU5352_BOARD 0x0462
++
++#define BCM94318MPGH_BOARD 0x0463
++
++
+#define BCM95352GR_BOARD 0x0467
+
++/* bcm95351agr */
++#define BCM95351AGR_BOARD 0x0470
++
+/* # of GPIO pins */
+#define GPIO_NUMPINS 16
+
+#endif /* _BCMDEVS_H */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
--- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-08-26 13:44:34.269398056 +0200
-@@ -0,0 +1,168 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-11-07 22:51:38.772725750 +0100
+@@ -0,0 +1,152 @@
+/*
+ * local version of endian.h - byte order defines
+ *
+ (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
+ (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
+ (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
++
++/* 2 Byte swap a 32 bit value */
++#define BCMSWAP32BY16(val) \
++ ((uint32)( \
++ (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
++ (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
++
+
+static INLINE uint16
+bcmswap16(uint16 val)
+ return BCMSWAP32(val);
+}
+
++static INLINE uint32
++bcmswap32by16(uint32 val)
++{
++ return BCMSWAP32BY16(val);
++}
++
+/* buf - start of buffer of shorts to swap */
+/* len - byte length of buffer */
+static INLINE void
+ return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
+}
+
-+/* get_ua adapted from Linux asm-mips/unaligned.h */
-+#ifdef IL_BIGENDIAN
-+#define get_ua(ptr) \
-+({ \
-+ __typeof__(*(ptr)) __val; \
-+ \
-+ switch (sizeof(*(ptr))) { \
-+ case 1: \
-+ __val = *(uint8 *)ptr; \
-+ break; \
-+ case 2: \
-+ __val = ntoh16_ua((uint8 *)ptr); \
-+ break; \
-+ case 4: \
-+ __val = ntoh32_ua((uint8 *)ptr); \
-+ break; \
-+ } \
-+ \
-+ __val; \
-+})
-+#else
-+#define get_ua(ptr) \
-+({ \
-+ __typeof__(*(ptr)) __val; \
-+ \
-+ switch (sizeof(*(ptr))) { \
-+ case 1: \
-+ __val = *(uint8 *)ptr; \
-+ break; \
-+ case 2: \
-+ __val = ltoh16_ua((uint8 *)ptr); \
-+ break; \
-+ case 4: \
-+ __val = ltoh32_ua((uint8 *)ptr); \
-+ break; \
-+ } \
-+ \
-+ __val; \
-+})
-+#endif
++#define ltoh_ua(ptr) ( \
++ sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
++ sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
++ (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
++)
++
++#define ntoh_ua(ptr) ( \
++ sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
++ sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
++ (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
++)
+
+#endif /* _BCMENDIAN_H_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
--- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-08-26 13:44:34.270397904 +0200
++++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-11-07 22:51:38.772725750 +0100
@@ -0,0 +1,229 @@
+/*
+ * Hardware-specific definitions for
+ uint32 PAD[63];
+
+ /* DMA engine */
-+ dmaregs_t dmaregs;
-+ dmafifo_t dmafifo;
++ dma32regp_t dmaregs;
++ dma32diag_t dmafifo;
+ uint32 PAD[116];
+
+ /* EMAC Registers */
+#endif /* _bcmenet_47xx_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
--- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-08-26 13:44:34.278396688 +0200
++++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-11-07 21:57:07.845585750 +0100
@@ -0,0 +1,81 @@
+/*
+ * Hardware-specific MIB definition for
+#endif /* _bcmenetmib_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
--- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-08-26 13:44:34.278396688 +0200
++++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-11-07 21:57:07.845585750 +0100
@@ -0,0 +1,58 @@
+/*
+ * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
+#endif /* _bcmenetphy_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
--- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-08-26 13:44:34.278396688 +0200
++++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-11-07 21:57:07.845585750 +0100
@@ -0,0 +1,43 @@
+/*
+ * Hardware-specific Receive Data Header for the
+#endif /* _bcmenetrxh_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
--- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-08-26 13:44:34.279396536 +0200
-@@ -0,0 +1,132 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-11-07 22:51:38.772725750 +0100
+@@ -0,0 +1,141 @@
+/*
+ * NVRAM variable manipulation
+ *
+struct nvram_header {
+ uint32 magic;
+ uint32 len;
-+ uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
-+ uint32 config_refresh; /* 0:15 config, 16:31 refresh */
++ uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
++ uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
+ uint32 config_ncdl; /* ncdl values for memc */
+};
+
+ * Disable NVRAM access. May be unnecessary or undefined on certain
+ * platforms.
+ */
-+extern void BCMINIT(nvram_exit)(void);
++extern void BCMINIT(nvram_exit)(void *sbh);
+
+/*
+ * Get the value of an NVRAM variable. The pointer returned may be
+extern char * BCMINIT(nvram_get)(const char *name);
+
+/*
++ * Read the reset GPIO value from the nvram and set the GPIO
++ * as input
++ */
++extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
++
++/*
+ * Get the value of an NVRAM variable.
+ * @param name name of variable to get
+ * @return value of variable or NUL if undefined
+#define NVRAM_HEADER_SIZE 20
+#define NVRAM_SPACE 0x8000
+
++#define NVRAM_MAX_VALUE_LEN 255
++#define NVRAM_MAX_PARAM_LEN 64
++
+#endif /* _bcmnvram_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
--- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-08-26 13:44:34.279396536 +0200
-@@ -0,0 +1,23 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,25 @@
+/*
+ * Misc system wide parameters.
+ *
+
+#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
+
++#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
++
+#endif
diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
--- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-08-26 13:44:34.280396384 +0200
-@@ -0,0 +1,22 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,23 @@
+/*
+ * Misc useful routines to access NIC local SROM/OTP .
+ *
+#ifndef _bcmsrom_h_
+#define _bcmsrom_h_
+
-+extern int srom_var_init(void *sbh, uint bus, void *curmap, void *osh, char **vars, int *count);
-+extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
-+extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
-+
++extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
++
++extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
++extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
++
+#endif /* _bcmsrom_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
--- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-08-26 13:44:34.280396384 +0200
-@@ -0,0 +1,239 @@
++++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,313 @@
+/*
+ * Misc useful os-independent macros and functions.
+ *
+#define _BCM_X 0x40 /* hex digit */
+#define _BCM_SP 0x80 /* hard space (0x20) */
+
++#define GPIO_PIN_NOTDEFINED 0x20
++
+extern unsigned char bcm_ctype[];
+#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
+
+
+/* externs */
+/* packet */
-+extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
-+extern uint pkttotlen(void *drv, void *);
++extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
++extern uint pkttotlen(osl_t *osh, void *);
+extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
+extern void pktenq(struct pktq *q, void *p, bool lifo);
+extern void *pktdeq(struct pktq *q);
+#define bcmlog(fmt, a1, a2)
+#define bcmdumplog(buf, size) *buf = '\0'
+#define bcmdumplogent(buf, idx) -1
++
+#endif /* #ifdef BCMDRIVER */
+
+/*** driver/apps-shared section ***/
++
++#define BCME_STRLEN 64
++#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
++
++
++/*
++ * error codes could be added but the defined ones shouldn't be changed/deleted
++ * these error codes are exposed to the user code
++ * when ever a new error code is added to this list
++ * please update errorstring table with the related error string and
++ * update osl files with os specific errorcode map
++*/
++
++#define BCME_ERROR -1 /* Error generic */
++#define BCME_BADARG -2 /* Bad Argument */
++#define BCME_BADOPTION -3 /* Bad option */
++#define BCME_NOTUP -4 /* Not up */
++#define BCME_NOTDOWN -5 /* Not down */
++#define BCME_NOTAP -6 /* Not AP */
++#define BCME_NOTSTA -7 /* Not STA */
++#define BCME_BADKEYIDX -8 /* BAD Key Index */
++#define BCME_RADIOOFF -9 /* Radio Off */
++#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
++#define BCME_NOCLK -11 /* No Clock*/
++#define BCME_BADRATESET -12 /* BAD RateSet*/
++#define BCME_BADBAND -13 /* BAD Band */
++#define BCME_BUFTOOSHORT -14 /* Buffer too short */
++#define BCME_BUFTOOLONG -15 /* Buffer too Long */
++#define BCME_BUSY -16 /* Busy*/
++#define BCME_NOTASSOCIATED -17 /* Not associated*/
++#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
++#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
++#define BCME_BADCHAN -20 /* BAD Channel */
++#define BCME_BADADDR -21 /* BAD Address*/
++#define BCME_NORESOURCE -22 /* No resources*/
++#define BCME_UNSUPPORTED -23 /* Unsupported*/
++#define BCME_BADLEN -24 /* Bad Length*/
++#define BCME_NOTREADY -25 /* Not ready Yet*/
++#define BCME_EPERM -26 /* Not Permitted */
++#define BCME_NOMEM -27 /* No Memory */
++#define BCME_ASSOCIATED -28 /* Associated */
++#define BCME_RANGE -29 /* Range Error*/
++#define BCME_NOTFOUND -30 /* Not found */
++#define BCME_LAST BCME_NOTFOUND
++
++#ifndef ABS
++#define ABS(a) (((a)<0)?-(a):(a))
++#endif
++
+#ifndef MIN
+#define MIN(a, b) (((a)<(b))?(a):(b))
+#endif
+#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
+#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
+#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
++#define VALID_MASK(mask) !((mask) & ((mask) + 1))
+#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
+#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
+
+#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
+#endif
+
-+#define NBITS(type) (sizeof (type) * 8)
++#define NBITS(type) (sizeof(type) * 8)
++#define NBITVAL(bits) (1 << (bits))
++#define MAXBITVAL(bits) ((1 << (bits)) - 1)
+
+/* crc defines */
+#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
+} bcm_tlv_t;
+
+/* Check that bcm_tlv_t fits into the given buflen */
-+#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (buflen) >= 2 + (elt)->len)
++#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
+
+/* buffer length for ethernet address from bcm_ether_ntoa() */
+#define ETHER_ADDR_STR_LEN 18
+extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
+extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
+
++/* bcmerror*/
++extern const char *bcmerrorstr(int bcmerror);
++
+/* multi-bool data type: set of bools, mbool is true if any is set */
+typedef uint32 mbool;
+#define mboolset(mb, bit) (mb |= bit) /* set one bool */
+#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
+#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
+
++/* power conversion */
++extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
++extern uint8 bcm_mw_to_qdbm(uint16 mw);
++
++/* generic datastruct to help dump routines */
++struct fielddesc {
++ char *nameandfmt;
++ uint32 offset;
++ uint32 len;
++};
++
++typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
++extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
++
++extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
++
+#endif /* _bcmutils_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
--- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-08-26 13:44:34.281396232 +0200
++++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-11-07 21:57:07.849586000 +0100
@@ -0,0 +1,85 @@
+/*
+ * bit manipulation utility functions
+#endif /* _BITFUNCS_H */
diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
--- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-08-26 13:44:34.281396232 +0200
-@@ -0,0 +1,184 @@
++++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,191 @@
+/*
+ * CFE boot loader OS Abstraction Layer.
+ *
+#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
+ do {} while (0)
+
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) (0)
++#define OSL_PCI_SLOT(osh) (0)
++
+/* register access macros */
+#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
+#define rreg32(r) (*(volatile uint32*)(r))
+/* bcopy, bcmp, and bzero */
+#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
+
-+#define osl_attach(pdev) (pdev)
++#define osl_attach(pdev) ((osl_t*)pdev)
+#define osl_detach(osh)
+
+/* general purpose memory allocation */
+/* microsecond delay */
+#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
+
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++
+/* map/unmap physical to virtual I/O */
+#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
+#define REG_UNMAP(va) do {} while (0)
+#define PKTBUFSZ 2048
+
+/* packet primitives */
-+#define PKTGET(drv, len, send) ((void*)osl_pktget((len)))
-+#define PKTFREE(drv, lb, send) osl_pktfree((struct lbuf*)(lb))
-+#define PKTDATA(drv, lb) (((struct lbuf*)(lb))->data)
-+#define PKTLEN(drv, lb) (((struct lbuf*)(lb))->len)
-+#define PKTHEADROOM(drv, lb) (PKTDATA(drv,lb)-(((struct lbuf*)(lb))->head))
-+#define PKTTAILROOM(drv, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
-+#define PKTNEXT(drv, lb) (((struct lbuf*)(lb))->next)
++#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
++#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
++#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
++#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
++#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
++#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
++#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
+#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
-+#define PKTSETLEN(drv, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
-+#define PKTPUSH(drv, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
-+#define PKTPULL(drv, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
-+#define PKTDUP(drv, lb) osl_pktdup((struct lbuf*)(lb))
++#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
++#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
++#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
++#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
+#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
+#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
+#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
+extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
+extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
+extern struct lbuf *osl_pktdup(struct lbuf *lb);
++extern int osl_error(int bcmerror);
+
+#endif /* _cfe_osl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
--- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-08-26 13:44:34.282396080 +0200
++++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-11-07 22:51:38.776726000 +0100
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2005, Broadcom Corporation
+
+#define EPI_MAJOR_VERSION 3
+
-+#define EPI_MINOR_VERSION 90
++#define EPI_MINOR_VERSION 130
+
-+#define EPI_RC_NUMBER 23
++#define EPI_RC_NUMBER 20
+
+#define EPI_INCREMENTAL_NUMBER 0
+
+#define EPI_BUILD_NUMBER 0
+
-+#define EPI_VERSION 3,90,23,0
++#define EPI_VERSION 3,130,20,0
+
-+#define EPI_VERSION_NUM 0x035a1700
++#define EPI_VERSION_NUM 0x03821400
+
+/* Driver Version String, ASCII, 32 chars max */
-+#define EPI_VERSION_STR "3.90.23.0"
-+#define EPI_ROUTER_VERSION_STR "3.91.23.0"
++#define EPI_VERSION_STR "3.130.20.0"
++#define EPI_ROUTER_VERSION_STR "3.131.20.0"
+
+#endif /* _epivers_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
--- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-08-26 13:44:34.282396080 +0200
++++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-11-07 21:57:07.849586000 +0100
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2005, Broadcom Corporation
+#endif /* _epivers_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
--- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-08-26 13:44:34.283395928 +0200
++++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-11-07 21:57:07.861586750 +0100
@@ -0,0 +1,59 @@
+/*
+ * Driver-specific socket ioctls
+#endif
diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
--- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-08-27 02:56:56.458670688 +0200
++++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-11-07 21:57:07.861586750 +0100
@@ -0,0 +1,188 @@
+/*
+ * flash.h: Common definitions for flash access.
+#endif
diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
--- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-08-26 13:44:34.284395776 +0200
++++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-11-07 21:57:07.861586750 +0100
@@ -0,0 +1,27 @@
+/*
+ * BCM47XX FLASH driver interface
+#endif /* _flashutl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
--- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-08-26 13:44:34.284395776 +0200
-@@ -0,0 +1,184 @@
++++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,71 @@
+/*
-+ * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
++ * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
+ * This supports the following chips: BCM42xx, 44xx, 47xx .
+ *
+ * Copyright 2005, Broadcom Corporation
+#ifndef _hnddma_h_
+#define _hnddma_h_
+
-+/*
-+ * Each DMA processor consists of a transmit channel and a receive channel.
-+ */
-+typedef volatile struct {
-+ /* transmit channel */
-+ uint32 xmtcontrol; /* enable, et al */
-+ uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
-+ uint32 xmtptr; /* last descriptor posted to chip */
-+ uint32 xmtstatus; /* current active descriptor, et al */
-+
-+ /* receive channel */
-+ uint32 rcvcontrol; /* enable, et al */
-+ uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
-+ uint32 rcvptr; /* last descriptor posted to chip */
-+ uint32 rcvstatus; /* current active descriptor, et al */
-+} dmaregs_t;
-+
-+typedef volatile struct {
-+ /* diag access */
-+ uint32 fifoaddr; /* diag address */
-+ uint32 fifodatalow; /* low 32bits of data */
-+ uint32 fifodatahigh; /* high 32bits of data */
-+ uint32 pad; /* reserved */
-+} dmafifo_t;
-+
-+/* transmit channel control */
-+#define XC_XE ((uint32)1 << 0) /* transmit enable */
-+#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
-+#define XC_LE ((uint32)1 << 2) /* loopback enable */
-+#define XC_FL ((uint32)1 << 4) /* flush request */
-+
-+/* transmit descriptor table pointer */
-+#define XP_LD_MASK 0xfff /* last valid descriptor */
-+
-+/* transmit channel status */
-+#define XS_CD_MASK 0x0fff /* current descriptor pointer */
-+#define XS_XS_MASK 0xf000 /* transmit state */
-+#define XS_XS_SHIFT 12
-+#define XS_XS_DISABLED 0x0000 /* disabled */
-+#define XS_XS_ACTIVE 0x1000 /* active */
-+#define XS_XS_IDLE 0x2000 /* idle wait */
-+#define XS_XS_STOPPED 0x3000 /* stopped */
-+#define XS_XS_SUSP 0x4000 /* suspend pending */
-+#define XS_XE_MASK 0xf0000 /* transmit errors */
-+#define XS_XE_SHIFT 16
-+#define XS_XE_NOERR 0x00000 /* no error */
-+#define XS_XE_DPE 0x10000 /* descriptor protocol error */
-+#define XS_XE_DFU 0x20000 /* data fifo underrun */
-+#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
-+#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
-+#define XS_AD_MASK 0xfff00000 /* active descriptor */
-+#define XS_AD_SHIFT 20
-+
-+/* receive channel control */
-+#define RC_RE ((uint32)1 << 0) /* receive enable */
-+#define RC_RO_MASK 0xfe /* receive frame offset */
-+#define RC_RO_SHIFT 1
-+#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
-+
-+/* receive descriptor table pointer */
-+#define RP_LD_MASK 0xfff /* last valid descriptor */
-+
-+/* receive channel status */
-+#define RS_CD_MASK 0x0fff /* current descriptor pointer */
-+#define RS_RS_MASK 0xf000 /* receive state */
-+#define RS_RS_SHIFT 12
-+#define RS_RS_DISABLED 0x0000 /* disabled */
-+#define RS_RS_ACTIVE 0x1000 /* active */
-+#define RS_RS_IDLE 0x2000 /* idle wait */
-+#define RS_RS_STOPPED 0x3000 /* reserved */
-+#define RS_RE_MASK 0xf0000 /* receive errors */
-+#define RS_RE_SHIFT 16
-+#define RS_RE_NOERR 0x00000 /* no error */
-+#define RS_RE_DPE 0x10000 /* descriptor protocol error */
-+#define RS_RE_DFO 0x20000 /* data fifo overflow */
-+#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
-+#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
-+#define RS_AD_MASK 0xfff00000 /* active descriptor */
-+#define RS_AD_SHIFT 20
-+
-+/* fifoaddr */
-+#define FA_OFF_MASK 0xffff /* offset */
-+#define FA_SEL_MASK 0xf0000 /* select */
-+#define FA_SEL_SHIFT 16
-+#define FA_SEL_XDD 0x00000 /* transmit dma data */
-+#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
-+#define FA_SEL_RDD 0x40000 /* receive dma data */
-+#define FA_SEL_RDP 0x50000 /* receive dma pointers */
-+#define FA_SEL_XFD 0x80000 /* transmit fifo data */
-+#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
-+#define FA_SEL_RFD 0xc0000 /* receive fifo data */
-+#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
-+
-+/*
-+ * DMA Descriptor
-+ * Descriptors are only read by the hardware, never written back.
-+ */
-+typedef volatile struct {
-+ uint32 ctrl; /* misc control bits & bufcount */
-+ uint32 addr; /* data buffer address */
-+} dmadd_t;
-+
-+/*
-+ * Each descriptor ring must be 4096byte aligned
-+ * and fit within a single 4096byte page.
-+ */
-+#define DMAMAXRINGSZ 4096
-+#define DMARINGALIGN 4096
-+
-+/* control flags */
-+#define CTRL_BC_MASK 0x1fff /* buffer byte count */
-+#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
-+#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
-+#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
-+#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
-+
-+/* control flags in the range [27:20] are core-specific and not defined here */
-+#define CTRL_CORE_MASK 0x0ff00000
-+
+/* export structure */
+typedef volatile struct {
+ /* rx error counters */
+#define di_t void
+#endif
+
++#ifndef osl_t
++#define osl_t void
++#endif
++
+/* externs */
-+extern void * dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
-+ uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
-+ uint ddoffset, uint dataoffset, uint *msg_level);
++extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
++ uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
+extern void dma_detach(di_t *di);
+extern void dma_txreset(di_t *di);
+extern void dma_rxreset(di_t *di);
+extern void dma_txsuspend(di_t *di);
+extern void dma_txresume(di_t *di);
+extern bool dma_txsuspended(di_t *di);
++extern bool dma_txsuspendedidle(di_t *di);
+extern bool dma_txstopped(di_t *di);
+extern bool dma_rxstopped(di_t *di);
+extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
-+extern int dma_tx(di_t *di, void *p, uint32 coreflags);
+extern void dma_fifoloopbackenable(di_t *di);
+extern void *dma_rx(di_t *di);
+extern void dma_rxfill(di_t *di);
+extern uint dma_txactive(di_t *di);
+extern void dma_txrotate(di_t *di);
+
++extern void dma_rxpiomode(dma32regs_t *);
++extern void dma_txpioloopback(dma32regs_t *);
++
+
+#endif /* _hnddma_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
--- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-08-26 13:44:34.285395624 +0200
++++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-11-07 21:57:07.861586750 +0100
@@ -0,0 +1,16 @@
+/*
+ * Alternate include file for HND sbmips.h since CFE also ships with
+#include "sbmips.h"
diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
--- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-08-26 13:44:34.286395472 +0200
-@@ -0,0 +1,341 @@
++++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-11-07 22:51:38.776726000 +0100
+@@ -0,0 +1,371 @@
+/*
+ * Linux OS Independent Layer
+ *
+#include <linuxver.h>
+
+/* assert and panic */
++#ifdef __GNUC__
++#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
++#if GCC_VERSION > 30100
+#define ASSERT(exp) do {} while (0)
++#else
++/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
++#define ASSERT(exp)
++#endif
++#endif
++
++/* microsecond delay */
++#define OSL_DELAY(usec) osl_delay(usec)
++extern void osl_delay(uint usec);
+
+/* PCMCIA attribute space access macros */
+#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
+ osl_pcmcia_read_attr((osh), (offset), (buf), (size))
+#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
+ osl_pcmcia_write_attr((osh), (offset), (buf), (size))
-+extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
-+extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
++extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
++extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
+
+/* PCI configuration space access macros */
+#define OSL_PCI_READ_CONFIG(osh, offset, size) \
+ osl_pci_read_config((osh), (offset), (size))
+#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
+ osl_pci_write_config((osh), (offset), (size), (val))
-+extern uint32 osl_pci_read_config(void *osh, uint size, uint offset);
-+extern void osl_pci_write_config(void *osh, uint offset, uint size, uint val);
++extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
++extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
++
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
++#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
++extern uint osl_pci_bus(osl_t *osh);
++extern uint osl_pci_slot(osl_t *osh);
+
+/* OSL initialization */
-+extern void *osl_attach(void *pdev);
-+extern void osl_detach(void *osh);
++extern osl_t *osl_attach(void *pdev);
++extern void osl_detach(osl_t *osh);
+
+/* host/bus architecture-specific byte swap */
+#define BUS_SWAP32(v) (v)
+#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
+#define MALLOCED(osh) osl_malloced((osh))
+#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
-+extern void *osl_debug_malloc(void *osh, uint size, int line, char* file);
-+extern void osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file);
-+extern char *osl_debug_memdump(void *osh, char *buf, uint sz);
++extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
++extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
++extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
+
+#else
+
+
+#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
+
-+extern void *osl_malloc(void *osh, uint size);
-+extern void osl_mfree(void *osh, void *addr, uint size);
-+extern uint osl_malloced(void *osh);
-+extern uint osl_malloc_failed(void *osh);
++extern void *osl_malloc(osl_t *osh, uint size);
++extern void osl_mfree(osl_t *osh, void *addr, uint size);
++extern uint osl_malloced(osl_t *osh);
++extern uint osl_malloc_failed(osl_t *osh);
+
+/* allocate/free shared (dma-able) consistent memory */
+#define DMA_CONSISTENT_ALIGN PAGE_SIZE
+ osl_dma_alloc_consistent((osh), (size), (pap))
+#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
+ osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
-+extern void *osl_dma_alloc_consistent(void *osh, uint size, ulong *pap);
-+extern void osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa);
++extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
++extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
+
+/* map/unmap direction */
+#define DMA_TX 1
+ osl_dma_map((osh), (va), (size), (direction))
+#define DMA_UNMAP(osh, pa, size, direction, p) \
+ osl_dma_unmap((osh), (pa), (size), (direction))
-+extern uint osl_dma_map(void *osh, void *va, uint size, int direction);
-+extern void osl_dma_unmap(void *osh, uint pa, uint size, int direction);
++extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
++extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
+
+/* register access macros */
+#if defined(BCMJTAG)
-+struct bcmjtag_info;
-+extern uint32 bcmjtag_read(struct bcmjtag_info *ejh, uint32 addr, uint size);
-+extern void bcmjtag_write(struct bcmjtag_info *ejh, uint32 addr, uint32 val, uint size);
++#include <bcmjtag.h>
+#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
+#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
+#endif
+
+/* register access macros */
+#if !defined(BCMJTAG)
++#ifndef IL_BIGENDIAN
+#define R_REG(r) ( \
+ sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
+ sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
+ case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
+ } \
+} while (0)
++#else /* IL_BIGENDIAN */
++#define R_REG(r) ({ \
++ __typeof(*(r)) __osl_v; \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
++ case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
++ case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
++ } \
++ __osl_v; \
++})
++#define W_REG(r, v) do { \
++ switch (sizeof(*(r))) { \
++ case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
++ case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
++ case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
++ } \
++} while (0)
++#endif
+#endif
+
+#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
+#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
+#define REG_UNMAP(va) iounmap((void *)(va))
+
-+/* microsecond delay */
-+#define OSL_DELAY(usec) udelay(usec)
-+#include <linux/delay.h>
-+
+/* shared (dma-able) memory access macros */
+#define R_SM(r) *(r)
+#define W_SM(r, v) (*(r) = (v))
+#define BZERO_SM(r, len) memset((r), '\0', (len))
+
+/* packet primitives */
-+#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
-+#define PKTFREE(drv, skb, send) osl_pktfree((skb))
-+#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
-+#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
-+#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
-+#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
-+#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
++#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
++#define PKTFREE(osh, skb, send) osl_pktfree((skb))
++#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
++#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
++#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
++#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
++#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
+#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
-+#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
-+#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
-+#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
-+#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
++#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
++#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
++#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
++#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
+#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
+#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
+#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
+#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
+#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
+#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
-+extern void *osl_pktget(void *drv, uint len, bool send);
++extern void *osl_pktget(osl_t *osh, uint len, bool send);
+extern void osl_pktfree(void *skb);
+
+#else /* BINOSL */
+extern int osl_sprintf(char *buf, const char *format, ...);
+extern int osl_strcmp(const char *s1, const char *s2);
+extern int osl_strncmp(const char *s1, const char *s2, uint n);
-+extern int osl_strlen(char *s);
++extern int osl_strlen(const char *s);
+extern char* osl_strcpy(char *d, const char *s);
+extern char* osl_strncpy(char *d, const char *s, uint n);
+
+extern void *osl_reg_map(uint32 pa, uint size);
+extern void osl_reg_unmap(void *va);
+
-+/* microsecond delay */
-+#define OSL_DELAY(usec) osl_delay((usec))
-+extern void osl_delay(uint usec);
-+
+/* shared (dma-able) memory access macros */
+#define R_SM(r) *(r)
+#define W_SM(r, v) (*(r) = (v))
+#define BZERO_SM(r, len) bzero((r), (len))
+
+/* packet primitives */
-+#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
-+#define PKTFREE(drv, skb, send) osl_pktfree((skb))
-+#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
-+#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
-+#define PKTHEADROOM(drv, skb) osl_pktheadroom((drv), (skb))
-+#define PKTTAILROOM(drv, skb) osl_pkttailroom((drv), (skb))
-+#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
++#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
++#define PKTFREE(osh, skb, send) osl_pktfree((skb))
++#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
++#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
++#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
++#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
++#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
+#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
-+#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
-+#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
-+#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
-+#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
++#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
++#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
++#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
++#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
+#define PKTCOOKIE(skb) osl_pktcookie((skb))
+#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
+#define PKTLINK(skb) osl_pktlink((skb))
+#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
+#define PKTPRIO(skb) osl_pktprio((skb))
+#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
-+extern void *osl_pktget(void *drv, uint len, bool send);
++extern void *osl_pktget(osl_t *osh, uint len, bool send);
+extern void osl_pktfree(void *skb);
-+extern uchar *osl_pktdata(void *drv, void *skb);
-+extern uint osl_pktlen(void *drv, void *skb);
-+extern uint osl_pktheadroom(void *drv, void *skb);
-+extern uint osl_pkttailroom(void *drv, void *skb);
-+extern void *osl_pktnext(void *drv, void *skb);
++extern uchar *osl_pktdata(osl_t *osh, void *skb);
++extern uint osl_pktlen(osl_t *osh, void *skb);
++extern uint osl_pktheadroom(osl_t *osh, void *skb);
++extern uint osl_pkttailroom(osl_t *osh, void *skb);
++extern void *osl_pktnext(osl_t *osh, void *skb);
+extern void osl_pktsetnext(void *skb, void *x);
-+extern void osl_pktsetlen(void *drv, void *skb, uint len);
-+extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
-+extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
-+extern void *osl_pktdup(void *drv, void *skb);
++extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
++extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
++extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
++extern void *osl_pktdup(osl_t *osh, void *skb);
+extern void *osl_pktcookie(void *skb);
+extern void osl_pktsetcookie(void *skb, void *x);
+extern void *osl_pktlink(void *skb);
+
+#endif /* BINOSL */
+
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++extern int osl_error(int bcmerror);
++
+/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
+#define PKTBUFSZ 2048
+
+#endif /* _linux_osl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
--- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-08-26 13:44:34.287395320 +0200
-@@ -0,0 +1,399 @@
++++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-11-07 22:51:38.780726250 +0100
+@@ -0,0 +1,411 @@
+/*
+ * Linux-specific abstractions to gain some independence from linux kernel versions.
+ * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
+#include <linux/modversions.h>
+#endif
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
++#include <linux/moduleparam.h>
++#endif
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
++#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
++#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
++#endif
++
+/* linux/malloc.h is deprecated, use linux/slab.h instead. */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
+#include <linux/malloc.h>
+#define IRQ_HANDLED
+#define IRQ_RETVAL(x)
+#endif
++#else
++typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
+#endif
+
+#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
+#endif /* _linuxver_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
--- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-08-26 13:44:34.287395320 +0200
-@@ -0,0 +1,120 @@
++++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-11-07 22:51:38.780726250 +0100
+@@ -0,0 +1,126 @@
+/*
+ * HND Minimal OS Abstraction Layer.
+ *
+
+#include <typedefs.h>
+#include <sbconfig.h>
++#include <mipsinc.h>
+
+/* Cache support */
+extern void caches_on(void);
+#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
+ do {} while (0)
+
++/* PCI device bus # and slot # */
++#define OSL_PCI_BUS(osh) (0)
++#define OSL_PCI_SLOT(osh) (0)
++
+/* register access macros */
+#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
+#define rreg32(r) (*(volatile uint32*)(r))
+#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
+
+/* Misc stubs */
-+#define osl_attach(pdev) (pdev)
++#define osl_attach(pdev) ((osl_t*)pdev)
+#define osl_detach(osh)
+extern void *osl_init(void);
-+extern int getintvar(char *vars, char *name);
++#define OSL_ERROR(bcmerror) osl_error(bcmerror)
++extern int osl_error(int);
+
+#endif /* _min_osl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
--- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-08-26 13:44:34.288395168 +0200
-@@ -0,0 +1,524 @@
++++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-11-07 22:51:38.780726250 +0100
+@@ -0,0 +1,552 @@
+/*
+ * HND Run Time Environment for standalone MIPS programs.
+ *
+ */
+
+#ifndef _MISPINC_H
-+#define _MISPINC_H
++#define _MISPINC_H
+
+
+/* MIPS defines */
+#define ra $31 /* return address */
+
+
-+/* *********************************************************************
-+ * CP0 Registers
-+ ********************************************************************* */
++/*
++ * CP0 Registers
++ */
+
+#define C0_INX $0
+#define C0_RAND $1
+#define C0_XCTEXT $20
+#define C0_DIAGNOSTIC $22
+#define C0_BROADCOM C0_DIAGNOSTIC
++#define C0_PERFORMANCE $25
+#define C0_ECC $26
+#define C0_CACHEERR $27
+#define C0_TAGLO $28
+/*
+ * LEAF - declare leaf routine
+ */
-+#define LEAF(symbol) \
++#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol,@function; \
+/*
+ * END - mark end of function
+ */
-+#define END(function) \
++#define END(function) \
+ .end function; \
+ .size function,.-function
+
-+#define _ULCAST_
++#define _ULCAST_
+
+#else
+
+#define STR(x) __STR(x)
+#endif
+
-+#define _ULCAST_ (unsigned long)
++#define _ULCAST_ (unsigned long)
+
+
-+/* *********************************************************************
-+ * CP0 Registers
-+ ********************************************************************* */
++/*
++ * CP0 Registers
++ */
+
+#define C0_INX 0 /* CP0: TLB Index */
+#define C0_RAND 1 /* CP0: TLB Random */
+#define C0_XCTEXT 20 /* CP0: XContext */
+#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
+#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
++#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
+#define C0_ECC 26 /* CP0: ECC */
+#define C0_CACHEERR 27 /* CP0: CacheErr */
+#define C0_TAGLO 28 /* CP0: TagLo */
+/*
+ * Cache Operations
+ */
-+#define Index_Invalidate_I 0x00
-+#define Index_Writeback_Inv_D 0x01
-+#define Index_Invalidate_SI 0x02
-+#define Index_Writeback_Inv_SD 0x03
++#define Index_Invalidate_I 0x00
++#define Index_Writeback_Inv_D 0x01
++#define Index_Invalidate_SI 0x02
++#define Index_Writeback_Inv_SD 0x03
+#define Index_Load_Tag_I 0x04
+#define Index_Load_Tag_D 0x05
+#define Index_Load_Tag_SI 0x06
+#define Hit_Set_Virtual_SD 0x1f
+#endif
+
-+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
-+ * Macros to access the system control coprocessor
++ * R4x00 interrupt enable / cause bits
+ */
-+
-+#define MFC0(source, sel) \
-+({ \
-+ int __res; \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
-+ "move\t%0,$1\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ :"=r" (__res) \
-+ : \
-+ :"$1"); \
-+ __res; \
-+})
-+
-+#define MTC0(source, sel, value) \
-+do { \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ "move\t$1,%z0\n\t" \
-+ ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ : \
-+ :"jr" (value) \
-+ :"$1"); \
-+} while (0)
-+
-+#define get_c0_count() \
-+({ \
-+ int __res; \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ "mfc0\t%0,$9\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ :"=r" (__res)); \
-+ __res; \
-+})
-+
-+static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
-+{
-+ uint lsz, sets, ways;
-+
-+ /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
-+ if ((lsz = ((config1 >> 19) & 7)))
-+ lsz = 2 << lsz;
-+ sets = 64 << ((config1 >> 22) & 7);
-+ ways = 1 + ((config1 >> 16) & 7);
-+ *size = lsz * sets * ways;
-+ *lsize = lsz;
-+}
-+
-+static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
-+{
-+ uint lsz, sets, ways;
-+
-+ /* Data Cache Size = Associativity * Line Size * Sets Per Way */
-+ if ((lsz = ((config1 >> 10) & 7)))
-+ lsz = 2 << lsz;
-+ sets = 64 << ((config1 >> 13) & 7);
-+ ways = 1 + ((config1 >> 7) & 7);
-+ *size = lsz * sets * ways;
-+ *lsize = lsz;
-+}
-+
-+#define cache_unroll(base,op) \
-+ __asm__ __volatile__(" \
-+ .set noreorder; \
-+ .set mips3; \
-+ cache %1, (%0); \
-+ .set mips0; \
-+ .set reorder" \
-+ : \
-+ : "r" (base), \
-+ "i" (op));
-+
-+#endif /* !_LANGUAGE_ASSEMBLY */
-+
-+
-+/*
-+ * R4x00 interrupt enable / cause bits
-+ */
-+#undef IE_SW0
-+#undef IE_SW1
-+#undef IE_IRQ0
-+#undef IE_IRQ1
-+#undef IE_IRQ2
-+#undef IE_IRQ3
-+#undef IE_IRQ4
-+#undef IE_IRQ5
-+#define IE_SW0 (1<< 8)
-+#define IE_SW1 (1<< 9)
-+#define IE_IRQ0 (1<<10)
-+#define IE_IRQ1 (1<<11)
-+#define IE_IRQ2 (1<<12)
-+#define IE_IRQ3 (1<<13)
-+#define IE_IRQ4 (1<<14)
-+#define IE_IRQ5 (1<<15)
-+
-+/*
-+ * Bitfields in the mips32 cp0 status register
-+ */
-+#define ST0_IE 0x00000001
-+#define ST0_EXL 0x00000002
-+#define ST0_ERL 0x00000004
-+/* already defined
-+#define ST0_UM 0x00000010
-+#define ST0_SWINT0 0x00000100
-+#define ST0_SWINT1 0x00000200
-+*/
-+#define ST0_HWINT0 0x00000400
-+#define ST0_HWINT1 0x00000800
-+#define ST0_HWINT2 0x00001000
-+#define ST0_HWINT3 0x00002000
-+#define ST0_HWINT4 0x00004000
-+#define ST0_HWINT5 0x00008000
-+#define ST0_IM 0x0000ff00
-+#define ST0_NMI 0x00080000
-+#define ST0_SR 0x00100000
-+#define ST0_TS 0x00200000
-+#define ST0_BEV 0x00400000
-+#define ST0_RE 0x02000000
-+#define ST0_RP 0x08000000
-+#define ST0_CU 0xf0000000
-+#define ST0_CU0 0x10000000
-+#define ST0_CU1 0x20000000
-+#define ST0_CU2 0x40000000
-+#define ST0_CU3 0x80000000
++#define IE_SW0 (_ULCAST_(1) << 8)
++#define IE_SW1 (_ULCAST_(1) << 9)
++#define IE_IRQ0 (_ULCAST_(1) << 10)
++#define IE_IRQ1 (_ULCAST_(1) << 11)
++#define IE_IRQ2 (_ULCAST_(1) << 12)
++#define IE_IRQ3 (_ULCAST_(1) << 13)
++#define IE_IRQ4 (_ULCAST_(1) << 14)
++#define IE_IRQ5 (_ULCAST_(1) << 15)
++
++#ifndef ST0_UM
++/*
++ * Bitfields in the mips32 cp0 status register
++ */
++#define ST0_IE 0x00000001
++#define ST0_EXL 0x00000002
++#define ST0_ERL 0x00000004
++#define ST0_UM 0x00000010
++#define ST0_SWINT0 0x00000100
++#define ST0_SWINT1 0x00000200
++#define ST0_HWINT0 0x00000400
++#define ST0_HWINT1 0x00000800
++#define ST0_HWINT2 0x00001000
++#define ST0_HWINT3 0x00002000
++#define ST0_HWINT4 0x00004000
++#define ST0_HWINT5 0x00008000
++#define ST0_IM 0x0000ff00
++#define ST0_NMI 0x00080000
++#define ST0_SR 0x00100000
++#define ST0_TS 0x00200000
++#define ST0_BEV 0x00400000
++#define ST0_RE 0x02000000
++#define ST0_RP 0x08000000
++#define ST0_CU 0xf0000000
++#define ST0_CU0 0x10000000
++#define ST0_CU1 0x20000000
++#define ST0_CU2 0x40000000
++#define ST0_CU3 0x80000000
++#endif
+
+
+/*
+#define C_EXC_SHIFT 2
+#define C_INT 0x0000ff00
+#define C_INT_SHIFT 8
-+/* already defined
-+#define C_SW0 0x00000100
-+#define C_SW1 0x00000200
-+#define C_IRQ0 0x00000400
-+#define C_IRQ1 0x00000800
-+#define C_IRQ2 0x00001000
-+#define C_IRQ3 0x00002000
-+#define C_IRQ4 0x00004000
-+#define C_IRQ5 0x00008000
-+*/
++#define C_SW0 (_ULCAST_(1) << 8)
++#define C_SW1 (_ULCAST_(1) << 9)
++#define C_IRQ0 (_ULCAST_(1) << 10)
++#define C_IRQ1 (_ULCAST_(1) << 11)
++#define C_IRQ2 (_ULCAST_(1) << 12)
++#define C_IRQ3 (_ULCAST_(1) << 13)
++#define C_IRQ4 (_ULCAST_(1) << 14)
++#define C_IRQ5 (_ULCAST_(1) << 15)
+#define C_WP 0x00400000
+#define C_IV 0x00800000
+#define C_CE 0x30000000
+/*
+ * Bits in the cp0 config register select 1.
+ */
-+#define CONF1_FP 0x00000001 /* FPU present */
-+#define CONF1_EP 0x00000002 /* EJTAG present */
-+#define CONF1_CA 0x00000004 /* mips16 implemented */
-+#define CONF1_WR 0x00000008 /* Watch registers present */
-+#define CONF1_PC 0x00000010 /* Performance counters present */
-+#define CONF1_DA_SHIFT 7 /* D$ associativity */
-+#define CONF1_DA_MASK 0x00000380
-+#define CONF1_DA_BASE 1
-+#define CONF1_DL_SHIFT 10 /* D$ line size */
-+#define CONF1_DL_MASK 0x00001c00
-+#define CONF1_DL_BASE 2
-+#define CONF1_DS_SHIFT 13 /* D$ sets/way */
-+#define CONF1_DS_MASK 0x0000e000
-+#define CONF1_DS_BASE 64
-+#define CONF1_IA_SHIFT 16 /* I$ associativity */
-+#define CONF1_IA_MASK 0x00070000
-+#define CONF1_IA_BASE 1
-+#define CONF1_IL_SHIFT 19 /* I$ line size */
-+#define CONF1_IL_MASK 0x00380000
-+#define CONF1_IL_BASE 2
-+#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
-+#define CONF1_IS_MASK 0x01c00000
-+#define CONF1_IS_BASE 64
-+#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
-+#define CONF1_MS_SHIFT 25
++#define CONF1_FP 0x00000001 /* FPU present */
++#define CONF1_EP 0x00000002 /* EJTAG present */
++#define CONF1_CA 0x00000004 /* mips16 implemented */
++#define CONF1_WR 0x00000008 /* Watch registers present */
++#define CONF1_PC 0x00000010 /* Performance counters present */
++#define CONF1_DA_SHIFT 7 /* D$ associativity */
++#define CONF1_DA_MASK 0x00000380
++#define CONF1_DA_BASE 1
++#define CONF1_DL_SHIFT 10 /* D$ line size */
++#define CONF1_DL_MASK 0x00001c00
++#define CONF1_DL_BASE 2
++#define CONF1_DS_SHIFT 13 /* D$ sets/way */
++#define CONF1_DS_MASK 0x0000e000
++#define CONF1_DS_BASE 64
++#define CONF1_IA_SHIFT 16 /* I$ associativity */
++#define CONF1_IA_MASK 0x00070000
++#define CONF1_IA_BASE 1
++#define CONF1_IL_SHIFT 19 /* I$ line size */
++#define CONF1_IL_MASK 0x00380000
++#define CONF1_IL_BASE 2
++#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
++#define CONF1_IS_MASK 0x01c00000
++#define CONF1_IS_BASE 64
++#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
++#define CONF1_MS_SHIFT 25
+
+/* PRID register */
+#define PRID_COPT_MASK 0xff000000
+#define PRID_IMP_BCM4710 0x4000
+#define PRID_IMP_BCM3302 0x9000
+#define PRID_IMP_BCM3303 0x9100
-+#define PRID_IMP_BCM3303 0x9100
+
+#define PRID_IMP_UNKNOWN 0xff00
+
-+#define BCM330X(id) \
++#define BCM330X(id) \
+ (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
+ || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
+
+/* Bits in C0_BROADCOM */
-+#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
-+#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
-+#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
-+#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
++#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
++#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
++#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
++#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
+
+/* PreFetch Cache aka Read Ahead Cache */
+
-+#define PFC_CR0 0xff400000 /* control reg 0 */
-+#define PFC_CR1 0xff400004 /* control reg 1 */
++#define PFC_CR0 0xff400000 /* control reg 0 */
++#define PFC_CR1 0xff400004 /* control reg 1 */
++
++/* PFC operations */
++#define PFC_I 0x00000001 /* Enable PFC use for instructions */
++#define PFC_D 0x00000002 /* Enable PFC use for data */
++#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
++#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
++#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
++#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
++#define PFC_DPF 0x00000040 /* Enable directional prefetching */
++#define PFC_FLUSH 0x00000100 /* Flush the PFC */
++#define PFC_BRR 0x40000000 /* Bus error indication */
++#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
++
++/* Handy defaults */
++#define PFC_DISABLED 0
++#define PFC_AUTO 0xffffffff /* auto select the default mode */
++#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
++#define PFC_INST_NOPF (PFC_I | PFC_CINV)
++#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
++#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
++#define PFC_I_AND_D (PFC_INST | PFC_DATA)
++#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
++
+
+/*
+ * These are the UART port assignments, expressed as offsets from the base
+#define UART_MSR 6 /* In: Modem Status Register */
+#define UART_SCR 7 /* I/O: Scratch Register */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-+#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
++#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
+#define UART_LSR_RXRDY 0x01 /* Receiver ready */
+
+
++#ifndef _LANGUAGE_ASSEMBLY
++
++/*
++ * Macros to access the system control coprocessor
++ */
++
++#define MFC0(source, sel) \
++({ \
++ int __res; \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
++ "move\t%0,$1\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ :"=r" (__res) \
++ : \
++ :"$1"); \
++ __res; \
++})
++
++#define MTC0(source, sel, value) \
++do { \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ "move\t$1,%z0\n\t" \
++ ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ : \
++ :"jr" (value) \
++ :"$1"); \
++} while (0)
++
++#define get_c0_count() \
++({ \
++ int __res; \
++ __asm__ __volatile__( \
++ ".set\tnoreorder\n\t" \
++ ".set\tnoat\n\t" \
++ "mfc0\t%0,$9\n\t" \
++ ".set\tat\n\t" \
++ ".set\treorder" \
++ :"=r" (__res)); \
++ __res; \
++})
++
++static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
++{
++ uint lsz, sets, ways;
++
++ /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
++ if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
++ lsz = CONF1_IL_BASE << lsz;
++ sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
++ ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
++ *size = lsz * sets * ways;
++ *lsize = lsz;
++}
++
++static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
++{
++ uint lsz, sets, ways;
++
++ /* Data Cache Size = Associativity * Line Size * Sets Per Way */
++ if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
++ lsz = CONF1_DL_BASE << lsz;
++ sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
++ ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
++ *size = lsz * sets * ways;
++ *lsize = lsz;
++}
++
++#define cache_op(base, op) \
++ __asm__ __volatile__(" \
++ .set noreorder; \
++ .set mips3; \
++ cache %1, (%0); \
++ .set mips0; \
++ .set reorder" \
++ : \
++ : "r" (base), \
++ "i" (op));
++
++#define cache_unroll4(base, delta, op) \
++ __asm__ __volatile__(" \
++ .set noreorder; \
++ .set mips3; \
++ cache %1,0(%0); \
++ cache %1,delta(%0); \
++ cache %1,(2 * delta)(%0); \
++ cache %1,(3 * delta)(%0); \
++ .set mips0; \
++ .set reorder" \
++ : \
++ : "r" (base), \
++ "i" (op));
++
++#endif /* !_LANGUAGE_ASSEMBLY */
++
+#endif /* _MISPINC_H */
diff -urN linux.old/arch/mips/bcm947xx/include/nvports.h linux.dev/arch/mips/bcm947xx/include/nvports.h
--- linux.old/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-08-26 13:44:34.291394712 +0200
++++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-11-07 21:57:07.865587000 +0100
@@ -0,0 +1,55 @@
+/*
+ * BCM53xx RoboSwitch utility functions
+
diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
--- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-08-26 13:44:34.291394712 +0200
-@@ -0,0 +1,39 @@
++++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-11-07 22:51:38.780726250 +0100
+@@ -0,0 +1,42 @@
+/*
-+ * OS Independent Layer
++ * OS Abstraction Layer
+ *
+ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+#ifndef _osl_h_
+#define _osl_h_
+
++/* osl handle type forward declaration */
++typedef struct os_handle osl_t;
++
+#if defined(linux)
+#include <linux_osl.h>
+#elif defined(NDIS)
+#endif /* _osl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
--- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-08-26 13:44:34.292394560 +0200
-@@ -0,0 +1,369 @@
++++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-11-07 22:51:38.780726250 +0100
+@@ -0,0 +1,451 @@
+/*
+ * pcicfg.h: PCI configuration constants and structures.
+ *
+#define PCICFG_BUS_SHIFT 16 /* Bus shift */
+#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
+#define PCICFG_FUN_SHIFT 8 /* Function shift */
-+#define PCICFG_OFF_SHIFT 0 /* Bus shift */
++#define PCICFG_OFF_SHIFT 0 /* Register shift */
+
+#define PCICFG_BUS_MASK 0xff /* Bus mask */
+#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
+#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
+#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
+
++/* PCIE Config space accessing MACROS*/
++
++#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
++#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
++#define PCIECFG_FUN_SHIFT 16 /* Function shift */
++#define PCIECFG_OFF_SHIFT 0 /* Register shift */
++
++#define PCIECFG_BUS_MASK 0xff /* Bus mask */
++#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
++#define PCIECFG_FUN_MASK 7 /* Function mask */
++#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
+
++#define PCIE_CONFIG_ADDR(b, s, f, o) \
++ ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
++ | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
++ | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
++ | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
++
++#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
++#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
++#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
++#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
++
++
+/* The actual config space */
+
+#define PCI_BAR_MAX 6
+
+#define PCR_RSVDA_MAX 2
+
++/* pci config status reg has a bit to indicate that capability ptr is present*/
++
++#define PCI_CAPPTR_PRESENT 0x0010
++
+typedef struct _pci_config_regs {
+ unsigned short vendor;
+ unsigned short device;
+#define PCI_CFG_SVID 0x2c
+#define PCI_CFG_SSID 0x2e
+#define PCI_CFG_ROMBAR 0x30
++#define PCI_CFG_CAPPTR 0x34
+#define PCI_CFG_INT 0x3c
+#define PCI_CFG_PIN 0x3d
+#define PCI_CFG_MINGNT 0x3e
+ unsigned char dev_dep[192];
+} ppb_config_regs;
+
-+/* Eveything below is BRCM HND proprietary */
++
++/* PCI CAPABILITY DEFINES */
++#define PCI_CAP_POWERMGMTCAP_ID 0x01
++#define PCI_CAP_MSICAP_ID 0x05
++#define PCI_CAP_PCIECAP_ID 0x10
++
++/* Data structure to define the Message Signalled Interrupt facility
++ * Valid for PCI and PCIE configurations */
++typedef struct _pciconfig_cap_msi {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short msgctrl;
++ unsigned int msgaddr;
++} pciconfig_cap_msi;
++
++/* Data structure to define the Power managment facility
++ * Valid for PCI and PCIE configurations */
++typedef struct _pciconfig_cap_pwrmgmt {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short pme_cap;
++ unsigned short pme_sts_ctrl;
++ unsigned char pme_bridge_ext;
++ unsigned char data;
++} pciconfig_cap_pwrmgmt;
++
++/* Data structure to define the PCIE capability */
++typedef struct _pciconfig_cap_pcie {
++ unsigned char capID;
++ unsigned char nextptr;
++ unsigned short pcie_cap;
++ unsigned int dev_cap;
++ unsigned short dev_ctrl;
++ unsigned short dev_status;
++ unsigned int link_cap;
++ unsigned short link_ctrl;
++ unsigned short link_status;
++} pciconfig_cap_pcie;
++
++/* PCIE Enhanced CAPABILITY DEFINES */
++#define PCIE_EXTCFG_OFFSET 0x100
++#define PCIE_ADVERRREP_CAPID 0x0001
++#define PCIE_VC_CAPID 0x0002
++#define PCIE_DEVSNUM_CAPID 0x0003
++#define PCIE_PWRBUDGET_CAPID 0x0004
++
++/* Header to define the PCIE specific capabilities in the extended config space */
++typedef struct _pcie_enhanced_caphdr {
++ unsigned short capID;
++ unsigned short cap_ver : 4;
++ unsigned short next_ptr : 12;
++} pcie_enhanced_caphdr;
++
++
++/* Everything below is BRCM HND proprietary */
+
+#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
+#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
+#endif
diff -urN linux.old/arch/mips/bcm947xx/include/pmon_osl.h linux.dev/arch/mips/bcm947xx/include/pmon_osl.h
--- linux.old/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-08-26 13:44:34.293394408 +0200
++++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-11-07 21:57:07.869587250 +0100
@@ -0,0 +1,126 @@
+/*
+ * MIPS PMON boot loader OS Abstraction Layer.
+#endif /* _pmon_osl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/proto/802.11.h linux.dev/arch/mips/bcm947xx/include/proto/802.11.h
--- linux.old/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-08-26 13:44:34.295394104 +0200
-@@ -0,0 +1,897 @@
++++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,930 @@
+/*
+ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ uint16 capability; /* capability information */
+ uint16 listen; /* listen interval */
+} PACKED;
++#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
++
++struct dot11_reassoc_req {
++ uint16 capability; /* capability information */
++ uint16 listen; /* listen interval */
++ struct ether_addr ap; /* Current AP address */
++} PACKED;
++#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
+
+struct dot11_assoc_resp {
+ uint16 capability; /* capability information */
+} PACKED;
+#define DOT11_ACTION_MEASURE_LEN 3
+
++struct dot11_action_switch_channel {
++ uint8 category;
++ uint8 action;
++ uint8 data[5]; /* for switch IE */
++} PACKED;
++
+/**************
+ 802.11h related definitions.
+**************/
+ uint8 num_channels;
+} dot11_supp_channels_t;
+
++/* csa mode type */
++#define DOT11_CSA_MODE_ADVISORY 0
++#define DOT11_CSA_MODE_NO_TX 1
+struct dot11_channel_switch {
+ uint8 id;
+ uint8 len;
+} PACKED;
+typedef struct dot11_channel_switch dot11_channel_switch_t;
+
++/* length of IE data, not including 2 byte header */
++#define DOT11_SWITCH_IE_LEN 3
++
+/* 802.11h Measurement Request/Report IEs */
+/* Measurement Type field */
+#define DOT11_MEASURE_TYPE_BASIC 0
+#define QOS_PRIO_MASK 0x0007
+#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
+
++#define QOS_TID_SHIFT 0
++#define QOS_TID_MASK 0x000f
++#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
++
+/* Ack Policy (0 means Acknowledge) */
+#define QOS_ACK_SHIFT 5
+#define QOS_ACK_MASK 0x0060
+#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
+#define DOT11_MNG_ERP_ID 42
+#define DOT11_MNG_NONERP_ID 47
++#ifdef BCMWPA2
+#define DOT11_MNG_RSN_ID 48
++#endif /* BCMWPA2 */
+#define DOT11_MNG_EXT_RATES_ID 50
+#define DOT11_MNG_WPA_ID 221
+#define DOT11_MNG_PROPR_ID 221
+#define BRF_ABCAP 0x1 /* afterburner capable */
+#define BRF_ABRQRD 0x2 /* afterburner requested */
+#define BRF_LZWDS 0x4 /* lazy wds enabled */
++#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
++#define BRF_ABCOUNTER_SHIFT 4
++
++#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
++#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
+
+
+/* OUI for BRCM proprietary IE */
+#define WPA_VERSION 1
+#define WPA_OUI "\x00\x50\xF2"
+
++#ifdef BCMWPA2
+#define WPA2_VERSION 1
+#define WPA2_VERSION_LEN 2
+#define WPA2_OUI "\x00\x0F\xAC"
++#endif /* BCMWPA2 */
+
+#define WPA_OUI_LEN 3
+
+#endif /* _802_11_H_ */
diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h
--- linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-08-26 13:44:34.295394104 +0200
-@@ -0,0 +1,97 @@
++++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,103 @@
+/*
+ * Broadcom Ethernettype protocol definitions
+ *
+
+
+#define BCMILCP_BCM_SUBTYPE_RESERVED 0
-+#define BCMILCP_BCM_SUBTYPE_WPA 1
-+#define BCMILCP_BCM_SUBTYPE_EAPOL 2
-+#define BCMILCP_BCM_SUBTYPE_SES 3
++#define BCMILCP_BCM_SUBTYPE_EVENT 1
++#define BCMILCP_BCM_SUBTYPE_SES 2
++/*
++The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
++within BCMILCP_BCM_SUBTYPE_EVENT type messages
++*/
++/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
+
+#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
+#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
+
-+typedef struct bcmeth_bcm_hdr
++/* These fields are stored in network order */
++typedef struct bcmeth_hdr
+{
+ uint16 subtype; /* Vendor specific..32769*/
+ uint16 length;
+ uint8 oui[3]; /* Broadcom OUI*/
+ /* user specific Data */
+ uint16 usr_subtype;
-+} PACKED bcmeth_bcm_hdr_t;
++} PACKED bcmeth_hdr_t;
++
+
+
+#undef PACKED
+#endif
+
+#endif
+diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmip.h linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h
+--- linux.old/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h 2005-11-08 00:15:47.881307500 +0100
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
++ * the contents of this file may not be disclosed to third parties, copied
++ * or duplicated in any form, in whole or in part, without the prior
++ * written permission of Broadcom Corporation.
++ *
++ * Fundamental constants relating to IP Protocol
++ *
++ * $Id$
++ */
++
++#ifndef _bcmip_h_
++#define _bcmip_h_
++
++/* IP header */
++#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
++#define IPV4_TOS_OFFSET 1 /* TOS offset */
++#define IPV4_PROT_OFFSET 9 /* protocol type offset */
++#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
++#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
++#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
++
++#define IPV4_VER_MASK 0xf0
++#define IPV4_IHL_MASK 0x0f
++
++#define IPV4_PROT_UDP 17 /* UDP protocol type */
++
++#define IPV4_ADDR_LEN 4 /* IP v4 address length */
++
++#define IPV4_VER_NUM 0x40 /* IP v4 version number */
++
++/* NULL IP address check */
++#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
++ ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
++
++#define IPV4_ADDR_STR_LEN 16
++
++#endif /* #ifndef _bcmip_h_ */
++
diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
--- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-08-26 13:44:34.296393952 +0200
-@@ -0,0 +1,161 @@
++++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,169 @@
+/*******************************************************************************
+ * $Id$
+ * Copyright 2005, Broadcom Corporation
+#endif
+
+/*
++ * Takes a pointer, sets locally admininistered
++ * address bit in the 48-bit Ethernet address.
++ */
++#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
++ (((uint8 *)(ea))[0] | 2) )
++
++/*
+ * Takes a pointer, returns true if a 48-bit multicast address
+ * (including broadcast, since it is all ones)
+ */
+#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
+
++
+/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
+#define ether_cmp(a, b) ( \
+ !(((short*)a)[0] == ((short*)b)[0]) | \
+#endif /* _NET_ETHERNET_H_ */
diff -urN linux.old/arch/mips/bcm947xx/include/proto/vlan.h linux.dev/arch/mips/bcm947xx/include/proto/vlan.h
--- linux.old/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-08-26 13:44:34.296393952 +0200
++++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-11-07 21:57:07.873587500 +0100
@@ -0,0 +1,50 @@
+/*
+ * 802.1Q VLAN protocol definitions
+#endif /* _vlan_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/proto/wpa.h linux.dev/arch/mips/bcm947xx/include/proto/wpa.h
--- linux.old/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-08-26 13:44:34.297393800 +0200
++++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-11-07 21:57:07.873587500 +0100
@@ -0,0 +1,140 @@
+/*
+ * Fundamental types and constants relating to WPA
+#endif /* _proto_wpa_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/rts/crc.h linux.dev/arch/mips/bcm947xx/include/rts/crc.h
--- linux.old/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-08-26 13:44:34.297393800 +0200
++++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-11-07 21:57:07.873587500 +0100
@@ -0,0 +1,69 @@
+/*******************************************************************************
+ * $Id$
+#endif /* _RTS_CRC_H_ */
diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
--- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-08-26 13:44:34.298393648 +0200
-@@ -0,0 +1,394 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,440 @@
+/*
+ * SiliconBackplane Chipcommon core hardware definitions.
+ *
+
+ /* Watchdog timer */
+ uint32 watchdog; /* 0x80 */
-+ uint32 PAD[3];
++ uint32 PAD[1];
++
++ /*GPIO based LED powersave registers corerev >= 16*/
++ uint32 gpiotimerval; /*0x88 */
++ uint32 gpiotimeroutmask;
+
+ /* clock control */
+ uint32 clockcontrol_n; /* 0x90 */
+#define CC_JTAGIR 0x34
+#define CC_JTAGDR 0x38
+#define CC_JTAGCTRL 0x3c
++#define CC_WATCHDOG 0x80
++#define CC_CLKC_N 0x90
++#define CC_CLKC_M0 0x94
++#define CC_CLKC_M1 0x98
++#define CC_CLKC_M2 0x9c
++#define CC_CLKC_M3 0xa0
+#define CC_CLKDIV 0xa4
++#define CC_SYS_CLK_CTL 0xc0
+#define CC_OTP 0x800
+
+/* chipid */
+#define CAP_PWR_CTL 0x00040000 /* Power control */
+#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
+#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
++#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
+#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
+#define CAP_ROM 0x00800000 /* Internal boot rom active */
+
+#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
+#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
+
++/* Fields in the otpstatus register */
++#define OTPS_PROGFAIL 0x80000000
++#define OTPS_PROTECT 0x00000007
++#define OTPS_HW_PROTECT 0x00000001
++#define OTPS_SW_PROTECT 0x00000002
++#define OTPS_CID_PROTECT 0x00000004
++
++/* Fields in the otpcontrol register */
++#define OTPC_RECWAIT 0xff000000
++#define OTPC_PROGWAIT 0x00ffff00
++#define OTPC_PRW_SHIFT 8
++#define OTPC_MAXFAIL 0x00000038
++#define OTPC_VSEL 0x00000006
++#define OTPC_SELVL 0x00000001
++
++/* Fields in otpprog */
++#define OTPP_COL_MASK 0x000000ff
++#define OTPP_ROW_MASK 0x0000ff00
++#define OTPP_ROW_SHIFT 8
++#define OTPP_READERR 0x10000000
++#define OTPP_VALUE 0x20000000
++#define OTPP_VALUE_SHIFT 29
++#define OTPP_READ 0x40000000
++#define OTPP_START 0x80000000
++#define OTPP_BUSY 0x80000000
++
+/* jtagcmd */
+#define JCMD_START 0x80000000
+#define JCMD_BUSY 0x80000000
+
+/* Fields in clkdiv */
+#define CLKD_SFLASH 0x0f000000
-+#define CLKD_SFLASH_SHIFT 24
++#define CLKD_SFLASH_SHIFT 24
+#define CLKD_OTP 0x000f0000
+#define CLKD_OTP_SHIFT 16
+#define CLKD_JTAG 0x00000f00
+#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
+#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
+#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
-+#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
-+#define SCC_CD_SHF 16 /* CLockDivider shift */
++#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
++#define SCC_CD_SHIFT 16
+
-+/* sys_clk_ctl */
++/* system_clk_ctl */
+#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
+#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
+#define SYCC_FP 0x00000004 /* ForcePLLOn */
+#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
+#define SYCC_HR 0x00000010 /* Force HT */
-+#define SYCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
-+#define SYCC_CD_SHF 16 /* CLockDivider shift */
++#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
++#define SYCC_CD_SHIFT 16
++
++/* gpiotimerval*/
++#define GPIO_ONTIME_SHIFT 16
+
+/* clockcontrol_n */
+#define CN_N1_MASK 0x3f /* n1 control */
+#define CC_MC_MASK 0x1f000000 /* mux control */
+#define CC_MC_SHIFT 24
+
-+/* N3M Clock control values for 125Mhz */
-+#define CC_125_N 0x0802 /* Default values for bcm4310 */
-+#define CC_125_M 0x04020009
-+#define CC_125_M25 0x11090009
-+#define CC_125_M33 0x11090005
-+
+/* N3M Clock control magic field values */
+#define CC_F6_2 0x02 /* A factor of 2 in */
+#define CC_F6_3 0x03 /* 6-bit fields like */
+#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
+#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
+
++/* Clock control values for 200Mhz in 5350 */
++#define CLKC_5350_N 0x0311
++#define CLKC_5350_M 0x04020009
++
+/* Flash types in the chipcommon capabilities register */
+#define FLASH_NONE 0x000 /* No flash */
+#define SFLASH_ST 0x100 /* ST serial flash */
+#define SFLASH_AT_ID_MASK 0x38
+#define SFLASH_AT_ID_SHIFT 3
+
-+/* OTP conventions */
-+#define OTP_HWBASE 0
-+#define OTP_SWLIM 256
-+#define OTP_CIDBASE 256
-+#define OTP_CIDLIM 260
++/* OTP regions */
++#define OTP_HW_REGION OTPS_HW_PROTECT
++#define OTP_SW_REGION OTPS_SW_PROTECT
++#define OTP_CID_REGION OTPS_CID_PROTECT
++
++/* OTP regions (Byte offsets from otp size) */
++#define OTP_SWLIM_OFF (-8)
++#define OTP_CIDBASE_OFF 0
++#define OTP_CIDLIM_OFF 8
+
-+#define OTP_BOUNDARY 252
-+#define OTP_HWSIGN 253
-+#define OTP_SWSIGN 254
-+#define OTP_CIDSIGN 255
++/* Predefined OTP words (Word offset from otp size) */
++#define OTP_BOUNDARY_OFF (-4)
++#define OTP_HWSIGN_OFF (-3)
++#define OTP_SWSIGN_OFF (-2)
++#define OTP_CIDSIGN_OFF (-1)
+
-+#define OTP_CID 256
-+#define OTP_PKG 257
-+#define OTP_FID 258
++#define OTP_CID_OFF 0
++#define OTP_PKG_OFF 1
++#define OTP_FID_OFF 2
++#define OTP_RSV_OFF 3
++#define OTP_LIM_OFF 4
+
+#define OTP_SIGNATURE 0x578a
+#define OTP_MAGIC 0x4e56
+#endif /* _SBCHIPC_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
--- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-08-26 13:44:34.299393496 +0200
-@@ -0,0 +1,324 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,342 @@
+/*
+ * Broadcom SiliconBackplane hardware register definitions.
+ *
+
+#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
+#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
++#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
++#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
+#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
+#define SB_LED (SB_EXTIF_BASE + 0x00900000)
+
++
+/* enumeration space related defs */
+#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
+#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
+
+/* sbtmstatelow */
+#define SBTML_RESET 0x1 /* reset */
-+#define SBTML_REJ 0x2 /* reject */
++#define SBTML_REJ_MASK 0x6 /* reject */
++#define SBTML_REJ_SHIFT 1
+#define SBTML_CLK 0x10000 /* clock enable */
+#define SBTML_FGC 0x20000 /* force gated clocks on */
+#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
+#define SBTMH_BUSY 0x4 /* busy */
+#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
+#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
++#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
+#define SBTMH_GCR 0x20000000 /* gated clock request */
+#define SBTMH_BISTF 0x40000000 /* bist failed */
+#define SBTMH_BISTD 0x80000000 /* bist done */
+
++
+/* sbbwa0 */
+#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
+#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
+#define SBIDL_IP_SHIFT 24
+#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
+#define SBIDL_RV_SHIFT 28
++#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
++#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
+
+/* sbidhigh */
-+#define SBIDH_RC_MASK 0xf /* revision code*/
-+#define SBIDH_CC_MASK 0xfff0 /* core code */
++#define SBIDH_RC_MASK 0x000f /* revision code */
++#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
++#define SBIDH_RCE_SHIFT 8
++#define SBCOREREV(sbidh) \
++ ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
++#define SBIDH_CC_MASK 0x8ff0 /* core code */
+#define SBIDH_CC_SHIFT 4
+#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
+#define SBIDH_VC_SHIFT 16
+#define SB_ATA100 0x81d /* parallel ATA core */
+#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
+#define SB_GIGETH 0x81f /* gigabit ethernet core */
++#define SB_PCIE 0x820 /* pci express core */
++#define SB_SRAMC 0x822 /* SRAM controller core */
++#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
++
++#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
+
+/* Not really related to Silicon Backplane, but a couple of software
+ * conventions for the use the flash space:
+#define BISZ_DATAEND_IDX 4 /* 4: text start */
+#define BISZ_BSSST_IDX 5 /* 5: text start */
+#define BISZ_BSSEND_IDX 6 /* 6: text start */
++#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
+
+#endif /* _SBCONFIG_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
--- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-08-26 13:44:34.300393344 +0200
++++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-11-07 21:57:07.877587750 +0100
@@ -0,0 +1,242 @@
+/*
+ * Hardware-specific External Interface I/O core definitions
+#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
+
+#endif /* _SBEXTIF_H */
-diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
---- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-08-26 13:44:34.300393344 +0200
-@@ -0,0 +1,147 @@
+diff -urN linux.old/arch/mips/bcm947xx/include/sbhnddma.h linux.dev/arch/mips/bcm947xx/include/sbhnddma.h
+--- linux.old/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/include/sbhnddma.h 2005-11-07 23:37:03.453685750 +0100
+@@ -0,0 +1,312 @@
+/*
-+ * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
++ * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
++ * This supports the following chips: BCM42xx, 44xx, 47xx .
+ *
+ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
+ * $Id$
+ */
+
-+#ifndef _SBMEMC_H
-+#define _SBMEMC_H
++#ifndef _sbhnddma_h_
++#define _sbhnddma_h_
+
-+#ifdef _LANGUAGE_ASSEMBLY
++
++/* 2byte-wide pio register set per channel(xmt or rcv) */
++typedef volatile struct {
++ uint16 fifocontrol;
++ uint16 fifodata;
++ uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
++ uint16 PAD;
++} pio2regs_t;
+
-+#define MEMC_CONTROL 0x00
-+#define MEMC_CONFIG 0x04
-+#define MEMC_REFRESH 0x08
-+#define MEMC_BISTSTAT 0x0c
-+#define MEMC_MODEBUF 0x10
-+#define MEMC_BKCLS 0x14
-+#define MEMC_PRIORINV 0x18
-+#define MEMC_DRAMTIM 0x1c
-+#define MEMC_INTSTAT 0x20
-+#define MEMC_INTMASK 0x24
-+#define MEMC_INTINFO 0x28
-+#define MEMC_NCDLCTL 0x30
-+#define MEMC_RDNCDLCOR 0x34
-+#define MEMC_WRNCDLCOR 0x38
-+#define MEMC_MISCDLYCTL 0x3c
-+#define MEMC_DQSGATENCDL 0x40
-+#define MEMC_SPARE 0x44
-+#define MEMC_TPADDR 0x48
-+#define MEMC_TPDATA 0x4c
-+#define MEMC_BARRIER 0x50
-+#define MEMC_CORE 0x54
++/* a pair of pio channels(tx and rx) */
++typedef volatile struct {
++ pio2regs_t tx;
++ pio2regs_t rx;
++} pio2regp_t;
+
++/* 4byte-wide pio register set per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 fifocontrol;
++ uint32 fifodata;
++} pio4regs_t;
+
-+#else
++/* a pair of pio channels(tx and rx) */
++typedef volatile struct {
++ pio4regs_t tx;
++ pio4regs_t rx;
++} pio4regp_t;
+
-+/* Sonics side: MEMC core registers */
-+typedef volatile struct sbmemcregs {
-+ uint32 control;
-+ uint32 config;
++
++
++/* DMA structure:
++ * support two DMA engines: 32 bits address or 64 bit addressing
++ * basic DMA register set is per channel(transmit or receive)
++ * a pair of channels is defined for convenience
++ */
++
++
++/*** 32 bits addressing ***/
++
++/* dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 control; /* enable, et al */
++ uint32 addr; /* descriptor ring base address (4K aligned) */
++ uint32 ptr; /* last descriptor posted to chip */
++ uint32 status; /* current active descriptor, et al */
++} dma32regs_t;
++
++typedef volatile struct {
++ dma32regs_t xmt; /* dma tx channel */
++ dma32regs_t rcv; /* dma rx channel */
++} dma32regp_t;
++
++typedef volatile struct { /* diag access */
++ uint32 fifoaddr; /* diag address */
++ uint32 fifodatalow; /* low 32bits of data */
++ uint32 fifodatahigh; /* high 32bits of data */
++ uint32 pad; /* reserved */
++} dma32diag_t;
++
++/*
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++ uint32 ctrl; /* misc control bits & bufcount */
++ uint32 addr; /* data buffer address */
++} dma32dd_t;
++
++/*
++ * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
++ */
++#define D32MAXRINGSZ 4096
++#define D32RINGALIGN 4096
++#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
++
++/* transmit channel control */
++#define XC_XE ((uint32)1 << 0) /* transmit enable */
++#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
++#define XC_LE ((uint32)1 << 2) /* loopback enable */
++#define XC_FL ((uint32)1 << 4) /* flush request */
++#define XC_AE ((uint32)3 << 16) /* address extension bits */
++#define XC_AE_SHIFT 16
++
++/* transmit descriptor table pointer */
++#define XP_LD_MASK 0xfff /* last valid descriptor */
++
++/* transmit channel status */
++#define XS_CD_MASK 0x0fff /* current descriptor pointer */
++#define XS_XS_MASK 0xf000 /* transmit state */
++#define XS_XS_SHIFT 12
++#define XS_XS_DISABLED 0x0000 /* disabled */
++#define XS_XS_ACTIVE 0x1000 /* active */
++#define XS_XS_IDLE 0x2000 /* idle wait */
++#define XS_XS_STOPPED 0x3000 /* stopped */
++#define XS_XS_SUSP 0x4000 /* suspend pending */
++#define XS_XE_MASK 0xf0000 /* transmit errors */
++#define XS_XE_SHIFT 16
++#define XS_XE_NOERR 0x00000 /* no error */
++#define XS_XE_DPE 0x10000 /* descriptor protocol error */
++#define XS_XE_DFU 0x20000 /* data fifo underrun */
++#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
++#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
++#define XS_AD_MASK 0xfff00000 /* active descriptor */
++#define XS_AD_SHIFT 20
++
++/* receive channel control */
++#define RC_RE ((uint32)1 << 0) /* receive enable */
++#define RC_RO_MASK 0xfe /* receive frame offset */
++#define RC_RO_SHIFT 1
++#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
++#define RC_AE ((uint32)3 << 16) /* address extension bits */
++#define RC_AE_SHIFT 16
++
++/* receive descriptor table pointer */
++#define RP_LD_MASK 0xfff /* last valid descriptor */
++
++/* receive channel status */
++#define RS_CD_MASK 0x0fff /* current descriptor pointer */
++#define RS_RS_MASK 0xf000 /* receive state */
++#define RS_RS_SHIFT 12
++#define RS_RS_DISABLED 0x0000 /* disabled */
++#define RS_RS_ACTIVE 0x1000 /* active */
++#define RS_RS_IDLE 0x2000 /* idle wait */
++#define RS_RS_STOPPED 0x3000 /* reserved */
++#define RS_RE_MASK 0xf0000 /* receive errors */
++#define RS_RE_SHIFT 16
++#define RS_RE_NOERR 0x00000 /* no error */
++#define RS_RE_DPE 0x10000 /* descriptor protocol error */
++#define RS_RE_DFO 0x20000 /* data fifo overflow */
++#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
++#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
++#define RS_AD_MASK 0xfff00000 /* active descriptor */
++#define RS_AD_SHIFT 20
++
++/* fifoaddr */
++#define FA_OFF_MASK 0xffff /* offset */
++#define FA_SEL_MASK 0xf0000 /* select */
++#define FA_SEL_SHIFT 16
++#define FA_SEL_XDD 0x00000 /* transmit dma data */
++#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
++#define FA_SEL_RDD 0x40000 /* receive dma data */
++#define FA_SEL_RDP 0x50000 /* receive dma pointers */
++#define FA_SEL_XFD 0x80000 /* transmit fifo data */
++#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
++#define FA_SEL_RFD 0xc0000 /* receive fifo data */
++#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
++#define FA_SEL_RSD 0xe0000 /* receive frame status data */
++#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
++
++/* descriptor control flags */
++#define CTRL_BC_MASK 0x1fff /* buffer byte count */
++#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
++#define CTRL_AE_SHIFT 16
++#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
++#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
++#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
++#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
++
++/* control flags in the range [27:20] are core-specific and not defined here */
++#define CTRL_CORE_MASK 0x0ff00000
++
++/*** 64 bits addressing ***/
++
++/* dma registers per channel(xmt or rcv) */
++typedef volatile struct {
++ uint32 control; /* enable, et al */
++ uint32 ptr; /* last descriptor posted to chip */
++ uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
++ uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
++ uint32 status0; /* current descriptor, xmt state */
++ uint32 status1; /* active descriptor, xmt error */
++} dma64regs_t;
++
++typedef volatile struct {
++ dma64regs_t tx; /* dma64 tx channel */
++ dma64regs_t rx; /* dma64 rx channel */
++} dma64regp_t;
++
++typedef volatile struct { /* diag access */
++ uint32 fifoaddr; /* diag address */
++ uint32 fifodatalow; /* low 32bits of data */
++ uint32 fifodatahigh; /* high 32bits of data */
++ uint32 pad; /* reserved */
++} dma64diag_t;
++
++/*
++ * DMA Descriptor
++ * Descriptors are only read by the hardware, never written back.
++ */
++typedef volatile struct {
++ uint32 ctrl1; /* misc control bits & bufcount */
++ uint32 ctrl2; /* buffer count and address extension */
++ uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
++ uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
++} dma64dd_t;
++
++/*
++ * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
++ */
++#define D64MAXRINGSZ 8192
++#define D64RINGALIGN 8192
++#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
++
++/* transmit channel control */
++#define D64_XC_XE 0x00000001 /* transmit enable */
++#define D64_XC_SE 0x00000002 /* transmit suspend request */
++#define D64_XC_LE 0x00000004 /* loopback enable */
++#define D64_XC_FL 0x00000010 /* flush request */
++#define D64_XC_AE 0x00110000 /* address extension bits */
++#define D64_XC_AE_SHIFT 16
++
++/* transmit descriptor table pointer */
++#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
++
++/* transmit channel status */
++#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
++#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
++#define D64_XS0_XS_SHIFT 28
++#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
++#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
++#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
++#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
++#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
++
++#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
++#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
++#define D64_XS1_XE_SHIFT 28
++#define D64_XS1_XE_NOERR 0x00000000 /* no error */
++#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
++#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
++#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
++#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
++#define D64_XS1_XE_COREE 0x50000000 /* core error */
++
++/* receive channel control */
++#define D64_RC_RE 0x00000001 /* receive enable */
++#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
++#define D64_RC_RO_SHIFT 1
++#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
++#define D64_RC_AE 0x00110000 /* address extension bits */
++#define D64_RC_AE_SHIFT 16
++
++/* receive descriptor table pointer */
++#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
++
++/* receive channel status */
++#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
++#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
++#define D64_RS0_RS_SHIFT 28
++#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
++#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
++#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
++#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
++#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
++
++#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
++#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
++#define D64_RS1_RE_SHIFT 28
++#define D64_RS1_RE_NOERR 0x00000000 /* no error */
++#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
++#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
++#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
++#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
++#define D64_RS1_RE_COREE 0x50000000 /* core error */
++
++/* fifoaddr */
++#define D64_FA_OFF_MASK 0xffff /* offset */
++#define D64_FA_SEL_MASK 0xf0000 /* select */
++#define D64_FA_SEL_SHIFT 16
++#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
++#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
++#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
++#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
++#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
++#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
++#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
++#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
++#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
++#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
++
++/* descriptor control flags 1 */
++#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
++#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
++#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
++#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
++
++/* descriptor control flags 2 */
++#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
++#define D64_CTRL2_AE 0x00110000 /* address extension bits */
++#define D64_CTRL2_AE_SHIFT 16
++
++/* control flags in the range [27:20] are core-specific and not defined here */
++#define D64_CTRL_CORE_MASK 0x0ff00000
++
++
++#endif /* _sbhnddma_h_ */
+diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
+--- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,148 @@
++/*
++ * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#ifndef _SBMEMC_H
++#define _SBMEMC_H
++
++#ifdef _LANGUAGE_ASSEMBLY
++
++#define MEMC_CONTROL 0x00
++#define MEMC_CONFIG 0x04
++#define MEMC_REFRESH 0x08
++#define MEMC_BISTSTAT 0x0c
++#define MEMC_MODEBUF 0x10
++#define MEMC_BKCLS 0x14
++#define MEMC_PRIORINV 0x18
++#define MEMC_DRAMTIM 0x1c
++#define MEMC_INTSTAT 0x20
++#define MEMC_INTMASK 0x24
++#define MEMC_INTINFO 0x28
++#define MEMC_NCDLCTL 0x30
++#define MEMC_RDNCDLCOR 0x34
++#define MEMC_WRNCDLCOR 0x38
++#define MEMC_MISCDLYCTL 0x3c
++#define MEMC_DQSGATENCDL 0x40
++#define MEMC_SPARE 0x44
++#define MEMC_TPADDR 0x48
++#define MEMC_TPDATA 0x4c
++#define MEMC_BARRIER 0x50
++#define MEMC_CORE 0x54
++
++
++#else
++
++/* Sonics side: MEMC core registers */
++typedef volatile struct sbmemcregs {
++ uint32 control;
++ uint32 config;
+ uint32 refresh;
+ uint32 biststat;
+ uint32 modebuf;
+#define MEMC_DRAMTIM2_INIT 0x000754d8
+#define MEMC_DRAMTIM25_INIT 0x000754d9
+#define MEMC_RDNCDLCOR_INIT 0x00000000
++#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
+#define MEMC_WRNCDLCOR_INIT 0x49351200
+#define MEMC_1_WRNCDLCOR_INIT 0x14500200
+#define MEMC_DQSGATENCDL_INIT 0x00030000
+#endif /* _SBMEMC_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
--- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-08-26 13:44:34.301393192 +0200
-@@ -0,0 +1,60 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-11-07 22:51:38.784726500 +0100
+@@ -0,0 +1,62 @@
+/*
+ * Broadcom SiliconBackplane MIPS definitions
+ *
+#ifndef _SBMIPS_H
+#define _SBMIPS_H
+
++#include <mipsinc.h>
++
+#ifndef _LANGUAGE_ASSEMBLY
+
+/* cpp contortions to concatenate w/arg prescan */
+ uint32 timer;
+} mipsregs_t;
+
-+extern uint32 sb_flag(void *sbh);
-+extern uint sb_irq(void *sbh);
++extern uint32 sb_flag(sb_t *sbh);
++extern uint sb_irq(sb_t *sbh);
+
-+extern void BCMINIT(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
++extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
+
-+extern void *sb_jtagm_init(void *sbh, uint clkd, bool exttap);
++extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
+extern void sb_jtagm_disable(void *h);
+extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
-+extern void BCMINIT(sb_mips_init)(void *sbh);
-+extern uint32 BCMINIT(sb_mips_clock)(void *sbh);
-+extern bool BCMINIT(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
++extern void BCMINIT(sb_mips_init)(sb_t *sbh);
++extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
++extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
++extern void BCMINIT(enable_pfc)(uint32 mode);
++extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
+
-+extern uint32 BCMINIT(sb_memc_get_ncdl)(void *sbh);
-+extern uint32 BCMINIT(sb_mips_get_pfc)(void *sbh);
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+#endif /* _SBMIPS_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
--- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-08-26 13:44:34.301393192 +0200
-@@ -0,0 +1,117 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-11-07 22:51:38.788726750 +0100
+@@ -0,0 +1,122 @@
+/*
+ * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
+ *
+#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
+#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
+
++/* PCI core index in SROM shadow area */
++#define SRSH_PI_OFFSET 0 /* first word */
++#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
++#define SRSH_PI_SHIFT 12 /* bit 15:12 */
++
+/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
+#define cap_list rsvd_a[0]
+#define bar0_window dev_dep[0x80 - 0x40]
+
+#ifndef _LANGUAGE_ASSEMBLY
+
-+extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
-+extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
++extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
++extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
+extern void sbpci_ban(uint16 core);
-+extern int sbpci_init(void *sbh);
-+extern void sbpci_check(void *sbh);
++extern int sbpci_init(sb_t *sbh);
++extern void sbpci_check(sb_t *sbh);
+
+#endif /* !_LANGUAGE_ASSEMBLY */
+
+#endif /* _SBPCI_H */
+diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
+--- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2005-11-07 23:39:41.403557000 +0100
+@@ -0,0 +1,199 @@
++/*
++ * BCM43XX SiliconBackplane PCIE core hardware definitions.
++ *
++ * $Id:
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ */
++
++#ifndef _SBPCIE_H
++#define _SBPCIE_H
++
++/* cpp contortions to concatenate w/arg prescan */
++#ifndef PAD
++#define _PADLINE(line) pad ## line
++#define _XSTR(line) _PADLINE(line)
++#define PAD _XSTR(__LINE__)
++#endif
++
++/* PCIE Enumeration space offsets*/
++#define PCIE_CORE_CONFIG_OFFSET 0x0
++#define PCIE_FUNC0_CONFIG_OFFSET 0x400
++#define PCIE_FUNC1_CONFIG_OFFSET 0x500
++#define PCIE_FUNC2_CONFIG_OFFSET 0x600
++#define PCIE_FUNC3_CONFIG_OFFSET 0x700
++#define PCIE_SPROM_SHADOW_OFFSET 0x800
++#define PCIE_SBCONFIG_OFFSET 0xE00
++
++/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
++#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
++#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
++#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
++#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
++
++/* SB side: PCIE core and host control registers */
++typedef struct sbpcieregs {
++
++ uint32 PAD[3];
++ uint32 biststatus; /* bist Status: 0x00C*/
++ uint32 PAD[6];
++ uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
++ uint32 PAD[54];
++ uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
++ uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
++ uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
++ uint32 PAD[4];
++
++ /* pcie core supports in direct access to config space */
++ uint32 configaddr; /* pcie config space access: Address field: 0x120*/
++ uint32 configdata; /* pcie config space access: Data field: 0x124*/
++
++ /* mdio access to serdes */
++ uint32 mdiocontrol; /* controls the mdio access: 0x128 */
++ uint32 mdiodata; /* Data to the mdio access: 0x12c */
++
++ /* pcie protocol phy/dllp/tlp register access mechanism*/
++ uint32 pcieaddr; /* address of the internal registeru: 0x130 */
++ uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
++
++ uint32 PAD[434];
++ uint16 sprom[36]; /* SPROM shadow Area */
++} sbpcieregs_t;
++
++/* SB to PCIE translation masks */
++#define SBTOPCIE0_MASK 0xfc000000
++#define SBTOPCIE1_MASK 0xfc000000
++#define SBTOPCIE2_MASK 0xc0000000
++
++/* Access type bits (0:1)*/
++#define SBTOPCIE_MEM 0
++#define SBTOPCIE_IO 1
++#define SBTOPCIE_CFG0 2
++#define SBTOPCIE_CFG1 3
++
++/*Prefetch enable bit 2*/
++#define SBTOPCIE_PF 4
++
++/*Write Burst enable for memory write bit 3*/
++#define SBTOPCIE_WR_BURST 8
++
++/* config access */
++#define CONFIGADDR_FUNC_MASK 0x7000
++#define CONFIGADDR_FUNC_SHF 12
++#define CONFIGADDR_REG_MASK 0x0FFF
++#define CONFIGADDR_REG_SHF 0
++
++/* PCIE protocol regs Indirect Address */
++#define PCIEADDR_PROT_MASK 0x300
++#define PCIEADDR_PROT_SHF 8
++#define PCIEADDR_PL_TLP 0
++#define PCIEADDR_PL_DLLP 1
++#define PCIEADDR_PL_PLP 2
++
++/* PCIE protocol PHY diagnostic registers */
++#define PCIE_PLP_MODEREG 0x200 /* Mode*/
++#define PCIE_PLP_STATUSREG 0x204 /* Status*/
++#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
++#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
++#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
++#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
++#define PCIE_PLP_ATTNREG 0x218 /* Attention */
++#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
++#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
++#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
++#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
++#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
++#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
++#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
++#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
++#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
++
++/* PCIE protocol DLLP diagnostic registers */
++#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
++#define PCIE_DLLP_LSREG 0x104 /* Link Status */
++#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
++#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
++#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
++#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
++#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
++#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
++#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
++#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
++#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
++#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
++#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
++#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
++#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
++#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
++#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
++#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
++#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
++#define PCIE_DLLP_TESTREG 0x14C /* Test */
++#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
++
++/* PCIE protocol TLP diagnostic registers */
++#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
++#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
++#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
++#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
++#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
++#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
++#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
++#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
++#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
++#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
++#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
++#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
++#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
++#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
++#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
++#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
++#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
++#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
++#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
++#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
++#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
++#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
++#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
++#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
++#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
++#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
++#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
++#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
++#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
++#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
++#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
++
++/* MDIO control */
++#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
++#define MDIOCTL_DIVISOR_VAL 0x2
++#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
++#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
++
++/* MDIO Data */
++#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
++#define MDIODATA_TA 0x00020000 /* Turnaround */
++#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
++#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
++#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
++#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
++#define MDIODATA_WRITE 0x10000000 /* write Transaction */
++#define MDIODATA_READ 0x20000000 /* Read Transaction */
++#define MDIODATA_START 0x40000000 /* start of Transaction */
++
++/* MDIO devices (SERDES modules) */
++#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
++#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
++#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
++
++/* SERDES registers */
++#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
++#define SERDES_RX_CDR 6 /* CDR */
++#define SERDES_RX_CDRBW 7 /* CDR BW */
++
++#endif /* _SBPCIE_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
--- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-08-26 13:44:34.302393040 +0200
-@@ -0,0 +1,139 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-11-07 22:51:38.788726750 +0100
+@@ -0,0 +1,146 @@
+/*
+ * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
+ *
+
+/* Subtypes of BRCM_HNBU: */
+
-+#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
++#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
++#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
+ * device id and chiprev
+ */
-+#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
-+#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
-+#define HNBU_OEM 0x04 /* Eight bytes OEM data */
-+#define HNBU_CC 0x05 /* Default country code */
++#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
++#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
++ * or 9 (sromrev > 1) bytes */
++#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
++#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
+#define HNBU_AA 0x06 /* Antennas available */
+#define HNBU_AG 0x07 /* Antenna gain */
-+#define HNBU_BOARDFLAGS 0x08 /* board flags */
-+#define HNBU_LED 0x09 /* LED set */
++#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
++#define HNBU_LEDS 0x09 /* LED set */
++#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
++ * in rev 2
++ */
++#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
++#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
+
+
+/* sbtmstatelow */
+#endif /* _SBPCMCIA_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
--- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-08-26 13:44:34.302393040 +0200
++++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-11-07 21:57:07.877587750 +0100
@@ -0,0 +1,75 @@
+/*
+ * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
+#endif /* _SBSDRAM_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
--- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-08-26 13:44:34.303392888 +0200
++++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-11-07 21:57:07.877587750 +0100
@@ -0,0 +1,37 @@
+/*
+ * BCM47XX Sonics SiliconBackplane embedded ram core
+#endif /* _SBSOCRAM_H */
diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
--- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-08-26 13:44:34.303392888 +0200
-@@ -0,0 +1,87 @@
++++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-11-07 22:51:38.788726750 +0100
+@@ -0,0 +1,140 @@
+/*
+ * Misc utility routines for accessing chip-specific features
+ * of Broadcom HNBU SiliconBackplane-based chips.
+#ifndef _sbutils_h_
+#define _sbutils_h_
+
++/*
++ * Datastructure to export all chip specific common variables
++ * public (read-only) portion of sbutils handle returned by
++ * sb_attach()/sb_kattach()
++*/
++
++struct sb_pub {
++
++ uint bustype; /* SB_BUS, PCI_BUS */
++ uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
++ uint buscorerev; /* buscore rev */
++ uint buscoreidx; /* buscore index */
++ int ccrev; /* chip common core rev */
++ uint boardtype; /* board type */
++ uint boardvendor; /* board vendor */
++ uint chip; /* chip number */
++ uint chiprev; /* chip revision */
++ uint chippkg; /* chip package option */
++ uint sonicsrev; /* sonics backplane rev */
++};
++
++typedef const struct sb_pub sb_t;
++
+/*
+ * Many of the routines below take an 'sbh' handle as their first arg.
+ * Allocate this by calling sb_attach(). Free it by calling sb_detach().
+ */
+
+/* exported externs */
-+extern void * BCMINIT(sb_attach)(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
-+extern void * BCMINIT(sb_kattach)(void);
-+extern void sb_detach(void *sbh);
-+extern uint BCMINIT(sb_chip)(void *sbh);
-+extern uint BCMINIT(sb_chiprev)(void *sbh);
-+extern uint BCMINIT(sb_chipcrev)(void *sbh);
-+extern uint BCMINIT(sb_chippkg)(void *sbh);
-+extern uint BCMINIT(sb_pcirev)(void *sbh);
-+extern uint BCMINIT(sb_pcmciarev)(void *sbh);
-+extern uint BCMINIT(sb_boardvendor)(void *sbh);
-+extern uint BCMINIT(sb_boardtype)(void *sbh);
-+extern uint sb_bus(void *sbh);
-+extern uint sb_corelist(void *sbh, uint coreid[]);
-+extern uint sb_coreid(void *sbh);
-+extern uint sb_coreidx(void *sbh);
-+extern uint sb_coreunit(void *sbh);
-+extern uint sb_corevendor(void *sbh);
-+extern uint sb_corerev(void *sbh);
-+extern void *sb_osh(void *sbh);
-+extern void *sb_coreregs(void *sbh);
-+extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
-+extern bool sb_iscoreup(void *sbh);
-+extern void *sb_setcoreidx(void *sbh, uint coreidx);
-+extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
-+extern void sb_commit(void *sbh);
++extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
++extern sb_t * BCMINIT(sb_kattach)(void);
++extern void sb_detach(sb_t *sbh);
++extern uint BCMINIT(sb_chip)(sb_t *sbh);
++extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
++extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
++extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
++extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
++extern bool BCMINIT(sb_war16165)(sb_t *sbh);
++extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
++extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
++extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
++extern uint sb_bus(sb_t *sbh);
++extern uint sb_buscoretype(sb_t *sbh);
++extern uint sb_buscorerev(sb_t *sbh);
++extern uint sb_corelist(sb_t *sbh, uint coreid[]);
++extern uint sb_coreid(sb_t *sbh);
++extern uint sb_coreidx(sb_t *sbh);
++extern uint sb_coreunit(sb_t *sbh);
++extern uint sb_corevendor(sb_t *sbh);
++extern uint sb_corerev(sb_t *sbh);
++extern void *sb_osh(sb_t *sbh);
++extern void *sb_coreregs(sb_t *sbh);
++extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
++extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
++extern bool sb_iscoreup(sb_t *sbh);
++extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
++extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
++extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
++extern void sb_commit(sb_t *sbh);
+extern uint32 sb_base(uint32 admatch);
+extern uint32 sb_size(uint32 admatch);
-+extern void sb_core_reset(void *sbh, uint32 bits);
-+extern void sb_core_tofixup(void *sbh);
-+extern void sb_core_disable(void *sbh, uint32 bits);
++extern void sb_core_reset(sb_t *sbh, uint32 bits);
++extern void sb_core_tofixup(sb_t *sbh);
++extern void sb_core_disable(sb_t *sbh, uint32 bits);
+extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
-+extern uint32 sb_clock(void *sbh);
-+extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
-+extern void sb_pcmcia_init(void *sbh);
-+extern void sb_watchdog(void *sbh, uint ticks);
-+extern void *sb_gpiosetcore(void *sbh);
-+extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpioin(void *sbh);
-+extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
-+extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
-+extern void sb_pwrctl_init(void *sbh);
-+extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
-+extern bool sb_pwrctl_clk(void *sbh, uint mode);
-+extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
-+extern int sb_pwrctl_slowclk(void *sbh, bool set, uint *div);
-+extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
-+
-+/* pwrctl xtal what flags */
++extern uint32 sb_clock(sb_t *sbh);
++extern void sb_pci_setup(sb_t *sbh, uint coremask);
++extern void sb_pcmcia_init(sb_t *sbh);
++extern void sb_watchdog(sb_t *sbh, uint ticks);
++extern void *sb_gpiosetcore(sb_t *sbh);
++extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioin(sb_t *sbh);
++extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
++extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
++extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
++extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
++
++extern void sb_clkctl_init(sb_t *sbh);
++extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
++extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
++extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
++extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
++ void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
++extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
++extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
++ uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
++extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
++extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
++extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
++
++
++
++/*
++* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
++* The returned path is NULL terminated and has trailing '/'.
++* Return 0 on success, nonzero otherwise.
++*/
++extern int sb_devpath(sb_t *sbh, char *path, int size);
++
++/* clkctl xtal what flags */
+#define XTAL 0x1 /* primary crystal oscillator (2050) */
+#define PLL 0x2 /* main chip pll */
+
-+/* pwrctl clk mode */
++/* clkctl clk mode */
+#define CLK_FAST 0 /* force fast (pll) clock */
-+#define CLK_SLOW 1 /* force slow clock */
-+#define CLK_DYNAMIC 2 /* enable dynamic power control */
++#define CLK_DYNAMIC 2 /* enable dynamic clock control */
++
++
++/* GPIO usage priorities */
++#define GPIO_DRV_PRIORITY 0
++#define GPIO_APP_PRIORITY 1
++
++/* device path */
++#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
+
+#endif /* _sbutils_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
--- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-08-26 13:44:34.304392736 +0200
++++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-11-07 21:57:07.881588000 +0100
@@ -0,0 +1,36 @@
+/*
+ * Broadcom SiliconBackplane chipcommon serial flash interface
+#endif /* _sflash_h_ */
diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
--- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-08-26 13:44:34.304392736 +0200
++++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-11-07 21:57:07.881588000 +0100
@@ -0,0 +1,33 @@
+/*
+ * TRX image file header format.
+typedef struct trx_header TRXHDR, *PTRXHDR;
diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
--- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-08-26 13:44:34.305392584 +0200
-@@ -0,0 +1,322 @@
++++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-11-07 22:51:38.788726750 +0100
+@@ -0,0 +1,326 @@
+/*
+ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+typedef ULONG_PTR uintptr;
+#endif
+
++#ifdef _HNDRTE_
++typedef long unsigned int size_t;
++#endif
++
+#ifdef _MSC_VER /* Microsoft C */
+#define TYPEDEF_INT64
+#define TYPEDEF_UINT64
+#endif /* _TYPEDEFS_H_ */
diff -urN linux.old/arch/mips/bcm947xx/include/wlioctl.h linux.dev/arch/mips/bcm947xx/include/wlioctl.h
--- linux.old/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-08-26 13:44:34.307392280 +0200
-@@ -0,0 +1,825 @@
++++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-11-07 22:51:38.792727000 +0100
+@@ -0,0 +1,1030 @@
+/*
+ * Custom OID/ioctl definitions for
+ * Broadcom 802.11abg Networking Device Driver
+
+#include <typedefs.h>
+#include <proto/ethernet.h>
++#include <proto/bcmeth.h>
++#include <proto/bcmevent.h>
+#include <proto/802.11.h>
+
+/* require default structure packing */
+ WLC_SUP_AUTHENTICATING,
+ WLC_SUP_AUTHENTICATED,
+ WLC_SUP_KEYXCHANGE,
-+ WLC_SUP_KEYED
++ WLC_SUP_KEYED,
++ WLC_SUP_TIMEOUT
+} sup_auth_status_t;
+#endif /* BCMCCX | BCMSUP_PSK */
+
+} wsec_pmk_t;
+
+/* wireless security bitvec */
-+#define WEP_ENABLED 1
-+#define TKIP_ENABLED 2
-+#define AES_ENABLED 4
-+#define WSEC_SWFLAG 8
++#define WEP_ENABLED 0x0001
++#define TKIP_ENABLED 0x0002
++#define AES_ENABLED 0x0004
++#define WSEC_SWFLAG 0x0008
++#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
+
+/* WPA authentication mode bitvec */
+#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
+#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
+#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
+/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
++
+#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
+#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
+
-+typedef struct wl_led_info {
-+ uint32 index; /* led index */
-+ uint32 behavior;
-+ bool activehi;
-+} wl_led_info_t;
-+
-+/*
-+ * definitions for driver messages passed from WL to NAS.
-+ */
-+/* Use this to recognize wpa and 802.1x driver messages. */
-+static const uint8 wl_wpa_snap_template[] =
-+ { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
+
-+#define WL_WPA_MSG_IFNAME_MAX 16
+
-+/* WPA driver message */
-+typedef struct wl_wpa_header {
-+ struct ether_header eth;
-+ struct dot11_llc_snap_header snap;
-+ uint8 version;
-+ uint8 type;
-+ /* version 2 additions */
-+ char ifname[WL_WPA_MSG_IFNAME_MAX];
-+ /* version specific data */
-+ /* uint8 data[1]; */
-+} wl_wpa_header_t;
-+
-+#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
-+
-+/* WPA driver message ethertype - private between wlc and nas */
-+#define WL_WPA_ETHER_TYPE 0x9999
-+
-+/* WPA driver message current version */
-+#define WL_WPA_MSG_VERSION 2
-+
-+/* Type field values for the 802.2 driver messages for WPA. */
-+#define WLC_ASSOC_MSG 1
-+#define WLC_DISASSOC_MSG 2
-+#define WLC_PTK_MIC_MSG 3
-+#define WLC_GTK_MIC_MSG 4
-+
-+/* 802.1x driver message */
-+typedef struct wl_eapol_header {
-+ struct ether_header eth;
-+ struct dot11_llc_snap_header snap;
-+ uint8 version;
-+ uint8 reserved;
-+ char ifname[WL_WPA_MSG_IFNAME_MAX];
-+ /* version specific data */
-+ /* uint8 802_1x_msg[1]; */
-+} wl_eapol_header_t;
++/* pmkid */
++#define MAXPMKID 16
+
-+#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
++typedef struct _pmkid
++{
++ struct ether_addr BSSID;
++ uint8 PMKID[WPA2_PMKID_LEN];
++} pmkid_t;
+
-+/* 802.1x driver message ethertype - private between wlc and nas */
-+#define WL_EAPOL_ETHER_TYPE 0x999A
++typedef struct _pmkid_list
++{
++ uint32 npmkid;
++ pmkid_t pmkid[1];
++} pmkid_list_t;
+
-+/* 802.1x driver message current version */
-+#define WL_EAPOL_MSG_VERSION 1
++typedef struct _pmkid_cand {
++ struct ether_addr BSSID;
++ uint8 preauth;
++} pmkid_cand_t;
+
-+#define WL_SECPVT_DATA_LEN (ETHER_HDR_LEN + 4 + WL_WPA_MSG_IFNAME_MAX)
++typedef struct _pmkid_cand_list {
++ uint32 npmkid_cand;
++ pmkid_cand_t pmkid_cand[1];
++} pmkid_cand_list_t;
+
-+/* message header for the private data exchange between nas and wl*/
-+typedef struct wl_secpvt_data {
-+ struct ether_header eth; /* use the Type field in the eth header with the private type*/
-+ uint8 version;
-+ uint8 sub_type;
-+ uint16 data_len;
-+ char ifname[WL_WPA_MSG_IFNAME_MAX];
-+ /* version specific data */
-+ /* uint8 802_1x_msg[1]; */
-+}wl_secpvt_data_t;
+
++typedef struct wl_led_info {
++ uint32 index; /* led index */
++ uint32 behavior;
++ bool activehi;
++} wl_led_info_t;
+
++typedef struct wlc_assoc_info {
++ uint32 req_len;
++ uint32 resp_len;
++ uint32 flags;
++ struct dot11_assoc_req req;
++ struct ether_addr reassoc_bssid; /* used in reassoc's */
++ struct dot11_assoc_resp resp;
++} wl_assoc_info_t;
++/* flags */
++#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
+/* srom read/write struct passed through ioctl */
+typedef struct {
+ uint byteoff; /* byte offset */
+ uint32 byteoff; /* byte offset of the field in d11regs_t */
+ uint32 val; /* read/write value of the field */
+ uint32 size; /* sizeof the field */
++ uint band; /* band (optional) */
+} rw_reg_t;
+
+/* Structure used by GET/SET_ATTEN ioctls */
+ struct ether_addr ea;
+} scb_val_t;
+
++
+/* Event data type */
-+typedef struct {
-+ uint msg; /* Message (see below) */
-+ struct ether_addr *addr; /* Station address (if applicable) */
-+ uint status; /* Status code (see below) */
-+ uint reason; /* Reason code (if applicable) */
-+ uint auth_type; /* WLC_E_AUTH */
-+ bool link; /* WLC_E_LINK */
-+ bool group; /* WLC_E_MIC_ERROR */
-+ bool flush_txq; /* WLC_E_MIC_ERROR */
++typedef struct wlc_event {
++ wl_event_msg_t event; /* encapsulated event */
++ struct ether_addr *addr; /* used to keep a trace of the potential present of
++ an address in wlc_event_msg_t */
++ void *data; /* used to hang additional data on an event */
++ struct wlc_event *next; /* enables ordered list of pending events */
+} wlc_event_t;
+
++#define BCM_MAC_STATUS_INDICATION (0x40010200L)
++
+typedef struct {
+ uint16 ver; /* version of this struct */
+ uint16 len; /* length in bytes of this structure */
+#define WL_STA_WDS 0x40
+#define WL_WDS_LINKUP 0x80
+
-+/* Event messages */
-+#define WLC_E_SET_SSID 1
-+#define WLC_E_JOIN 2
-+#define WLC_E_START 3
-+#define WLC_E_AUTH 4
-+#define WLC_E_AUTH_IND 5
-+#define WLC_E_DEAUTH 6
-+#define WLC_E_DEAUTH_IND 7
-+#define WLC_E_ASSOC 8
-+#define WLC_E_ASSOC_IND 9
-+#define WLC_E_REASSOC 10
-+#define WLC_E_REASSOC_IND 11
-+#define WLC_E_DISASSOC 12
-+#define WLC_E_DISASSOC_IND 13
-+#define WLC_E_QUIET_START 14 /* 802.11h Quiet period started */
-+#define WLC_E_QUIET_END 15 /* 802.11h Quiet period ended */
-+#define WLC_E_GOT_BEACONS 16
-+#define WLC_E_LINK 17 /* Link indication */
-+#define WLC_E_MIC_ERROR 18 /* TKIP MIC error occurred */
-+#define WLC_E_NDIS_LINK 19 /* NDIS style link indication */
-+#define WLC_E_ROAM 20
-+#define WLC_E_TXFAIL 21 /* dot11FailedCount (txfail) */
-+#define WLC_E_LAST 22
-+
-+/* Event status codes */
-+#define WLC_E_STATUS_SUCCESS 0
-+#define WLC_E_STATUS_FAIL 1
-+#define WLC_E_STATUS_TIMEOUT 2
-+#define WLC_E_STATUS_NO_NETWORKS 3
-+#define WLC_E_STATUS_ABORT 4
-+
-+typedef struct wlc_event_cb {
-+ uint msg; /* Event message or 0 for all */
-+ void (*fn)(void *, wlc_event_t *); /* Callback function */
-+ void *context; /* Passed to callback function */
-+ struct wlc_event_cb *next; /* Next in the chain */
-+} wlc_event_cb_t;
+
+/*
+ * Country locale determines which channels are available to us.
+ uint chipnum; /* chip number */
+} wlc_rev_info_t;
+
++#define WL_BRAND_MAX 10
++typedef struct wl_instance_info {
++ uint instance;
++ char brand[WL_BRAND_MAX];
++} wl_instance_info_t;
++
+/* check this magic number */
+#define WLC_IOCTL_MAGIC 0x14e46c77
+
+/* common ioctl definitions */
+#define WLC_GET_MAGIC 0
+#define WLC_GET_VERSION 1
-+#define WLC_UP 2
-+#define WLC_DOWN 3
-+#define WLC_DUMP 6
++#define WLC_UP 2
++#define WLC_DOWN 3
++#define WLC_DUMP 6
+#define WLC_GET_MSGLEVEL 7
+#define WLC_SET_MSGLEVEL 8
+#define WLC_GET_PROMISC 9
+#define WLC_SET_PROMISC 10
+#define WLC_GET_RATE 12
-+#define WLC_SET_RATE 13
++/* #define WLC_SET_RATE 13 */ /* no longer supported */
+#define WLC_GET_INSTANCE 14
-+#define WLC_GET_FRAG 15
-+#define WLC_SET_FRAG 16
-+#define WLC_GET_RTS 17
-+#define WLC_SET_RTS 18
++/* #define WLC_GET_FRAG 15 */ /* no longer supported */
++/* #define WLC_SET_FRAG 16 */ /* no longer supported */
++/* #define WLC_GET_RTS 17 */ /* no longer supported */
++/* #define WLC_SET_RTS 18 */ /* no longer supported */
+#define WLC_GET_INFRA 19
+#define WLC_SET_INFRA 20
+#define WLC_GET_AUTH 21
+#define WLC_GET_RADIO 37
+#define WLC_SET_RADIO 38
+#define WLC_GET_PHYTYPE 39
-+#define WLC_GET_WEP 42
-+#define WLC_SET_WEP 43
-+#define WLC_GET_KEY 44
-+#define WLC_SET_KEY 45
-+#define WLC_SCAN 50
++/* #define WLC_GET_WEP 42 */ /* no longer supported */
++/* #define WLC_SET_WEP 43 */ /* no longer supported */
++#define WLC_GET_KEY 44
++#define WLC_SET_KEY 45
++#define WLC_GET_REGULATORY 46
++#define WLC_SET_REGULATORY 47
++#define WLC_SCAN 50
+#define WLC_SCAN_RESULTS 51
+#define WLC_DISASSOC 52
-+#define WLC_REASSOC 53
-+#define WLC_GET_ROAM_TRIGGER 54
++#define WLC_REASSOC 53
++#define WLC_GET_ROAM_TRIGGER 54
+#define WLC_SET_ROAM_TRIGGER 55
+#define WLC_GET_TXANT 61
+#define WLC_SET_TXANT 62
+#define WLC_GET_ANTDIV 63
+#define WLC_SET_ANTDIV 64
-+#define WLC_GET_TXPWR 65
-+#define WLC_SET_TXPWR 66
++/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
++/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
+#define WLC_GET_CLOSED 67
+#define WLC_SET_CLOSED 68
+#define WLC_GET_MACLIST 69
+#define WLC_GET_RATESET 71
+#define WLC_SET_RATESET 72
+#define WLC_GET_LOCALE 73
-+#define WLC_SET_LOCALE 74
++#define WLC_LONGTRAIN 74
+#define WLC_GET_BCNPRD 75
+#define WLC_SET_BCNPRD 76
+#define WLC_GET_DTIMPRD 77
+#define WLC_GET_GMODE_PROTECTION 149
+#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
+#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
-+#define WLC_UPGRADE 152
-+#define WLC_GET_MRATE 153
-+#define WLC_SET_MRATE 154
-+#define WLC_GET_ASSOCLIST 159
-+#define WLC_GET_CLK 160
-+#define WLC_SET_CLK 161
-+#define WLC_GET_UP 162
-+#define WLC_OUT 163
-+#define WLC_GET_WPA_AUTH 164
++#define WLC_UPGRADE 152
++/* #define WLC_GET_MRATE 153 */ /* no longer supported */
++/* #define WLC_SET_MRATE 154 */ /* no longer supported */
++#define WLC_GET_ASSOCLIST 159
++#define WLC_GET_CLK 160
++#define WLC_SET_CLK 161
++#define WLC_GET_UP 162
++#define WLC_OUT 163
++#define WLC_GET_WPA_AUTH 164
+#define WLC_SET_WPA_AUTH 165
+#define WLC_GET_GMODE_PROTECTION_CONTROL 178
+#define WLC_SET_GMODE_PROTECTION_CONTROL 179
+#define WLC_SET_WET 231
+#define WLC_GET_KEY_PRIMARY 235
+#define WLC_SET_KEY_PRIMARY 236
++#define WLC_GET_RADAR 242
++#define WLC_SET_RADAR 243
++#define WLC_SET_SPECT_MANAGMENT 244
++#define WLC_GET_SPECT_MANAGMENT 245
+#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
+#define WLC_SET_CS_SCAN_TIMER 248
+#define WLC_GET_CS_SCAN_TIMER 249
++#define WLC_SEND_PWR_CONSTRAINT 254
+#define WLC_CURRENT_PWR 256
+#define WLC_GET_CHANNELS_IN_COUNTRY 260
+#define WLC_GET_COUNTRY_LIST 261
+#define WLC_SET_WSEC_PMK 268
+#define WLC_GET_AUTH_MODE 269
+#define WLC_SET_AUTH_MODE 270
-+#define WLC_LAST 273 /* do not change - use get_var/set_var */
++#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
++#define WLC_NVOTPW 274
++/* #define WLC_OTPW 275 */ /* no longer supported */
++#define WLC_SET_LOCALE 278
++#define WLC_LAST 279 /* do not change - use get_var/set_var */
+
+/*
+ * Minor kludge alert:
+
+/* NDIS overrides */
+#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
++#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
+
+#define WL_DECRYPT_STATUS_SUCCESS 1
+#define WL_DECRYPT_STATUS_FAILURE 2
+#define WLC_UPGRADE_SUCCESS 0
+#define WLC_UPGRADE_PENDING 1
+
++#ifdef CONFIG_USBRNDIS_RETAIL
++/* struct passed in for WLC_NDCONFIG_ITEM */
++typedef struct {
++ char *name;
++ void *param;
++} ndconfig_item_t;
++#endif
++
+/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
+#define WL_RADIO_SW_DISABLE (1<<0)
+#define WL_RADIO_HW_DISABLE (1<<1)
-+#define WL_RADIO_UNASSOC_DISABLE (1<<2)
++#define WL_RADIO_MPC_DISABLE (1<<2)
++#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
+
+/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
+#define WL_TXPWR_OVERRIDE (1<<31)
+
++/* "diag" iovar argument and error code */
++#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
++#define WL_DIAG_MEMORY 3 /* d11 memory test */
++#define WL_DIAG_LED 4 /* LED test */
++#define WL_DIAG_REG 5 /* d11/phy register test */
++#define WL_DIAG_SROM 6 /* srom read/crc test */
++#define WL_DIAG_DMA 7 /* DMA test */
++
++#define WL_DIAGERR_SUCCESS 0
++#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
++#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
++#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
++#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
++#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
++#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
++#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
++#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
++#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
++#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
+
+/* Bus types */
+#define WL_SB_BUS 0 /* Silicon Backplane */
+#define WLC_BAND_AUTO 0 /* auto-select */
+#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
+#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
++#define WLC_BAND_ALL 3 /* all bands */
++
++/* phy types (returned by WLC_GET_PHYTPE) */
++#define WLC_PHY_TYPE_A 0
++#define WLC_PHY_TYPE_B 1
++#define WLC_PHY_TYPE_G 2
++#define WLC_PHY_TYPE_NULL 0xf
+
+/* MAC list modes */
+#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
+
+
+
++typedef struct {
++ int npulses; /* required number of pulses at n * t_int */
++ int ncontig; /* required number of pulses at t_int */
++ int min_pw; /* minimum pulse width (20 MHz clocks) */
++ int max_pw; /* maximum pulse width (20 MHz clocks) */
++ uint16 thresh0; /* Radar detection, thresh 0 */
++ uint16 thresh1; /* Radar detection, thresh 1 */
++} wl_radar_args_t;
++
++/* radar iovar SET defines */
++#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
++#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
++#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
++
++/* dfs_status iovar-related defines */
++
++/* cac - channel availability check,
++ * ism - in-service monitoring
++ * csa - channel switching anouncement
++ */
++
++/* cac state values */
++#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
++#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
++#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
++#define WL_DFS_CACSTATE_CSA 3 /* csa */
++#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
++#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
++#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
++#define WL_DFS_CACSTATES 7 /* this many states exist */
++
++/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
++typedef struct {
++ uint state; /* noted by WL_DFS_CACSTATE_XX. */
++ uint duration; /* time spent in ms in state. */
++ /* as dfs enters ISM state, it removes the operational channel from quiet channel list
++ * and notes the channel in channel_cleared. set to 0 if no channel is cleared
++ */
++ uint channel_cleared;
++} wl_dfs_status_t;
++
++#define NUM_PWRCTRL_RATES 12
+
+
+/* 802.11h enforcement levels */
+#define SPECT_MNGMT_OFF 0 /* 11h disabled */
-+#define SPECT_MNGMT_LOOSE 1 /* qllow scan lists to contain non-11h AP */
++#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
+#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
-+
++#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
+
+#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
+#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
+#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
+#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
+
++#define WL_MPC_VAL 0x00400000
++#define WL_APSTA_VAL 0x00800000
++#define WL_DFS_VAL 0x01000000
+
+/* max # of leds supported by GPIO (gpio pin# == led index#) */
+#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
+#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
+#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
+
++/* number of bytes needed to define a 128-bit mask for MAC event reporting */
++#define WL_EVENTING_MASK_LEN 16
++
+/* Structures and constants used for "vndr_ie" IOVar interface */
+#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
+
+#define VNDR_IE_ASSOCRSP_FLAG 0x4
+#define VNDR_IE_AUTHRSP_FLAG 0x8
+
-+typedef struct vndr_ie_info {
++typedef struct {
+ uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
+ vndr_ie_t vndr_ie_data; /* vendor IE data */
+} vndr_ie_info_t;
+
-+typedef struct vndr_ie_buf {
++typedef struct {
+ int iecount; /* number of entries in the vndr_ie_list[] array */
+ vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
+} vndr_ie_buf_t;
+
-+typedef struct vndr_ie_setbuf {
++typedef struct {
+ char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
+ vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
+} vndr_ie_setbuf_t;
+
++/* join target preference types */
++#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
++#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
++#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
++
++/* band preference */
++#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
++ /* others use WLC_BAND_XXXX as values */
++
++/* any multicast cipher suite */
++#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
++
+#if !defined(__GNUC__)
+#pragma pack(pop)
+#endif
+
++#define NFIFO 6 /* # tx/rx fifopairs */
++
++#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
++
++typedef struct {
++ uint16 version; /* see definition of WL_CNT_T_VERSION */
++ uint16 length; /* length of entire structure */
++
++ /* transmit stat counters */
++ uint32 txframe; /* tx data frames */
++ uint32 txbyte; /* tx data bytes */
++ uint32 txretrans; /* tx mac retransmits */
++ uint32 txerror; /* tx data errors */
++ uint32 txctl; /* tx management frames */
++ uint32 txprshort; /* tx short preamble frames */
++ uint32 txserr; /* tx status errors */
++ uint32 txnobuf; /* tx out of buffers errors */
++ uint32 txnoassoc; /* tx discard because we're not associated */
++ uint32 txrunt; /* tx runt frames */
++ uint32 txchit; /* tx header cache hit (fastpath) */
++ uint32 txcmiss; /* tx header cache miss (slowpath) */
++
++ /* transmit chip error counters */
++ uint32 txuflo; /* tx fifo underflows */
++ uint32 txphyerr; /* tx phy errors (indicated in tx status) */
++ uint32 txphycrs;
++
++ /* receive stat counters */
++ uint32 rxframe; /* rx data frames */
++ uint32 rxbyte; /* rx data bytes */
++ uint32 rxerror; /* rx data errors */
++ uint32 rxctl; /* rx management frames */
++ uint32 rxnobuf; /* rx out of buffers errors */
++ uint32 rxnondata; /* rx non data frames in the data channel errors */
++ uint32 rxbadds; /* rx bad DS errors */
++ uint32 rxbadcm; /* rx bad control or management frames */
++ uint32 rxfragerr; /* rx fragmentation errors */
++ uint32 rxrunt; /* rx runt frames */
++ uint32 rxgiant; /* rx giant frames */
++ uint32 rxnoscb; /* rx no scb error */
++ uint32 rxbadproto; /* rx invalid frames */
++ uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
++ uint32 rxbadda; /* rx frames tossed for invalid da */
++ uint32 rxfilter; /* rx frames filtered out */
++
++ /* receive chip error counters */
++ uint32 rxoflo; /* rx fifo overflow errors */
++ uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
++
++ uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
++ uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
++ uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
++
++ /* misc counters */
++ uint32 dmade; /* tx/rx dma descriptor errors */
++ uint32 dmada; /* tx/rx dma data errors */
++ uint32 dmape; /* tx/rx dma descriptor protocol errors */
++ uint32 reset; /* reset count */
++ uint32 tbtt; /* cnts the TBTT int's */
++ uint32 txdmawar;
++
++ /* MAC counters: 32-bit version of d11.h's macstat_t */
++ uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
++ Control Management (includes retransmissions) */
++ uint32 txrtsfrm; /* number of RTS sent out by the MAC */
++ uint32 txctsfrm; /* number of CTS sent out by the MAC */
++ uint32 txackfrm; /* number of ACK frames sent out */
++ uint32 txdnlfrm; /* Not used */
++ uint32 txbcnfrm; /* beacons transmitted */
++ uint32 txfunfl[8]; /* per-fifo tx underflows */
++ uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
++ uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
++ driver enqueued frames*/
++ uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
++ uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
++ uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
++ data/control/management*/
++ uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
++ uint32 rxbadplcp; /* parity check of the PLCP header failed */
++ uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
++ uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
++ uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
++ uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
++ uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
++ uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
++ uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
++ uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
++ uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
++ uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
++ uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
++ uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
++ uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
++ uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
++ uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
++ uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
++ to see these) */
++ uint32 rxbeaconmbss; /* beacons received from member of BSS */
++ uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
++ uint32 rxbeaconobss; /* beacons received from other BSS */
++ uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
++ response */
++ uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
++ uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
++ uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
++ uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
++ uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
++ uint32 pmqovfl; /* Number of PMQ overflows */
++ uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
++ uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
++ uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
++ uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
++ uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
++ a probe response could not be sent out within the time limit defined
++ in M_PRS_MAXTIME */
++ uint32 rxnack; /* Number of NACKS received (Afterburner) */
++ uint32 frmscons; /* Number of frames completed without transmission because of an
++ Afterburner re-queue */
++ uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
++ uint32 txglitch_nack; /* obsolete */
++ uint32 txburst; /* obsolete */
++ uint32 rxburst; /* obsolete */
++
++ /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
++ uint32 txfrag; /* dot11TransmittedFragmentCount */
++ uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
++ uint32 txfail; /* dot11FailedCount */
++ uint32 txretry; /* dot11RetryCount */
++ uint32 txretrie; /* dot11MultipleRetryCount */
++ uint32 rxdup; /* dot11FrameduplicateCount */
++ uint32 txrts; /* dot11RTSSuccessCount */
++ uint32 txnocts; /* dot11RTSFailureCount */
++ uint32 txnoack; /* dot11ACKFailureCount */
++ uint32 rxfrag; /* dot11ReceivedFragmentCount */
++ uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
++ uint32 rxcrc; /* dot11FCSErrorCount */
++ uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
++ uint32 rxundec; /* dot11WEPUndecryptableCount */
++
++ /* WPA2 counters (see rxundec for DecryptFailureCount) */
++ uint32 tkipmicfaill; /* TKIPLocalMICFailures */
++ uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
++ uint32 tkipreplay; /* TKIPReplays */
++ uint32 ccmpfmterr; /* CCMPFormatErrors */
++ uint32 ccmpreplay; /* CCMPReplays */
++ uint32 ccmpundec; /* CCMPDecryptErrors */
++ uint32 fourwayfail; /* FourWayHandshakeFailures */
++ uint32 wepundec; /* dot11WEPUndecryptableCount */
++ uint32 wepicverr; /* dot11WEPICVErrorCount */
++ uint32 decsuccess; /* DecryptSuccessCount */
++ uint32 tkipicverr; /* TKIPICVErrorCount */
++ uint32 wepexcluded; /* dot11WEPExcludedCount */
++} wl_cnt_t;
++
+#endif /* _wlioctl_h_ */
diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
--- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-08-26 13:44:34.307392280 +0200
++++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-11-07 21:57:07.881588000 +0100
@@ -0,0 +1,321 @@
+/*
+ * NVRAM variable manipulation (common)
+}
diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
--- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-08-26 13:44:34.308392128 +0200
-@@ -0,0 +1,617 @@
++++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-11-08 00:54:56.755597250 +0100
+@@ -0,0 +1,633 @@
+/*
+ * NVRAM variable manipulation (Linux kernel half)
+ *
-+ * Copyright 2004, Broadcom Corporation
++ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+#include <sbchipc.h>
+#include <sbutils.h>
+#include <sbmips.h>
++#include <sflash.h>
+
+/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
+static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
+{
+ struct nvram_header *header;
+ chipcregs_t *cc;
++ struct sflash *info = NULL;
+ int i;
+ uint32 base, off, lim;
++ u32 *src, *dst;
+
+ if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
+ base = KSEG1ADDR(SB_FLASH2);
+
+ case SFLASH_ST:
+ case SFLASH_AT:
++ if ((info = sflash_init(cc)) == NULL)
++ return;
++ lim = info->size;
++ break;
++
+ case FLASH_NONE:
+ default:
+ return;
+ while (off <= lim) {
+ /* Windowed flash access */
+ header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
-+ if (header->magic == NVRAM_MAGIC) {
-+ u32 *src = (u32 *) header;
-+ u32 *dst = (u32 *) nvram_buf;
-+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
-+ *dst++ = *src++;
-+ for (; i < header->len && i < NVRAM_SPACE; i += 4)
-+ *dst++ = ltoh32(*src++);
-+ return;
-+ }
-+
-+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
-+ if (off == 1 KB)
-+ break;
-+ else if (off == 4 KB)
-+ off = 1 KB;
-+ else if (off == lim)
-+ off = 4 KB;
-+ else
-+ off <<= 1;
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++ off <<= 1;
+ }
++
++ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
++ header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++
++ header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
++ if (header->magic == NVRAM_MAGIC)
++ goto found;
++
++ printk("early_nvram_init: NVRAM not found\n");
++ return;
++
++found:
++ src = (u32 *) header;
++ dst = (u32 *) nvram_buf;
++ for (i = 0; i < sizeof(struct nvram_header); i += 4)
++ *dst++ = *src++;
++ for (; i < header->len && i < NVRAM_SPACE; i += 4)
++ *dst++ = ltoh32(*src++);
+}
+
+/* Early (before mm or mtd) read-only access to NVRAM */
+ if (!name)
+ return NULL;
+
++ /* Too early? */
++ if (sbh == NULL)
++ return NULL;
++
+ if (!nvram_buf[0])
+ early_nvram_init();
+
+module_exit(dev_nvram_exit);
diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
--- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-08-26 13:44:34.309391976 +0200
++++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-11-07 23:59:38.908750500 +0100
@@ -0,0 +1,355 @@
+/*
+ * Low-Level PCI and SB support for BCM47xx (Linux support code)
+ *
-+ * Copyright 2004, Broadcom Corporation
++ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+#include <typedefs.h>
+#include <bcmutils.h>
+#include <sbconfig.h>
++#include <sbutils.h>
+#include <sbpci.h>
+#include <pcicfg.h>
-+#include <sbutils.h>
+#include <bcmdevs.h>
+#include <bcmnvram.h>
+
+/* Global SB handle */
-+extern void *bcm947xx_sbh;
++extern sb_t *bcm947xx_sbh;
+extern spinlock_t bcm947xx_sbh_lock;
+
+/* Convenience */
+
diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
--- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/prom.c 2005-08-26 13:44:34.310391824 +0200
++++ linux.dev/arch/mips/bcm947xx/prom.c 2005-11-07 21:57:07.885588250 +0100
@@ -0,0 +1,41 @@
+/*
+ * Early initialization code for BCM94710 boards
+}
diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
--- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-09-01 01:30:26.074176728 +0200
-@@ -0,0 +1,1033 @@
++++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-11-07 23:55:45.682174750 +0100
+@@ -0,0 +1,1038 @@
+/*
+ * BCM47XX Sonics SiliconBackplane MIPS core routines
+ *
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
-+ * $Id: sbmips.c,v 1.3 2005/03/07 08:35:32 kanki Exp $
++ * $Id$
+ */
+
+#include <typedefs.h>
+#include <sbchipc.h>
+#include <sbmemc.h>
+#include <mipsinc.h>
++#include <sbutils.h>
+
-+/*
++/*
+ * Returns TRUE if an external UART exists at the given base
+ * register.
+ */
-+static bool
++static bool
+BCMINITFN(serial_exists)(uint8 *regs)
+{
+ uint8 save_mcr, status1;
+ return (status1 == 0x90);
+}
+
-+/*
++/*
+ * Initializes UART access. The callback function will be called once
+ * per found UART.
+ */
-+void
-+BCMINITFN(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
++void
++BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
+{
+ void *regs;
+ ulong base;
+ /* Internal backplane clock */
+ baud_base = sb_clock(sbh);
+ div = 2; /* Minimum divisor */
-+ W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
++ W_REG(&cc->clkdiv,
++ ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
+ } else {
+ /* Fixed internal backplane clock */
+ baud_base = 88000000;
+ * jtag_rwreg. Returns NULL on failure.
+ */
+void *
-+sb_jtagm_init(void *sbh, uint clkd, bool exttap)
++sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
+{
+ void *regs;
+
+
+/* Returns the SB interrupt flag of the current core. */
+uint32
-+sb_flag(void *sbh)
++sb_flag(sb_t *sbh)
+{
+ void *regs;
+ sbconfig_t *sb;
+ SBIPS_INT4_SHIFT
+};
+
-+/*
++/*
+ * Returns the MIPS IRQ assignment of the current core. If unassigned,
+ * 0 is returned.
+ */
+uint
-+sb_irq(void *sbh)
++sb_irq(sb_t *sbh)
+{
+ uint idx;
+ void *regs;
+}
+
+/* Clears the specified MIPS IRQ. */
-+static void
-+BCMINITFN(sb_clearirq)(void *sbh, uint irq)
++static void
++BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
+{
+ void *regs;
+ sbconfig_t *sb;
+ OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
+}
+
-+/*
++/*
+ * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
+ * IRQ 0 may be assigned more than once.
+ */
-+static void
-+BCMINITFN(sb_setirq)(void *sbh, uint irq, uint coreid, uint coreunit)
++static void
++BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
+{
+ void *regs;
+ sbconfig_t *sb;
+ flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
+ W_REG(&sb->sbipsflag, flag);
+ }
-+}
++}
+
-+/*
++/*
+ * Initializes clocks and interrupts. SB and NVRAM access must be
+ * initialized prior to calling.
+ */
-+void
-+BCMINITFN(sb_mips_init)(void *sbh)
++void
++BCMINITFN(sb_mips_init)(sb_t *sbh)
+{
+ ulong hz, ns, tmp;
+ extifregs_t *eir;
+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
+ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
+ } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
-+//==================================tallest===============================================
-+ /* set register for external IO to control LED. */
-+ W_REG(&cc->prog_config, 0x11);
-+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-+ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
-+ tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
-+ W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
-+//========================================================================================
+ /* Set timing for the flash */
+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
+ tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
+ tmp |= CEIL(120, ns); /* W0 = 120nS */
-+
++
+ // Added by Chen-I for 5365
+ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
+ {
+ }
+ else
+ {
-+ if (sb_corerev(sbh) < 9)
++ if (sb_corerev(sbh) < 9)
+ W_REG(&cc->flash_waitcount, tmp);
-+
-+ if ( (sb_corerev(sbh) < 9) ||
-+ ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0) ) {
++
++ if ((sb_corerev(sbh) < 9) ||
++ ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
+ W_REG(&cc->pcmcia_memwait, tmp);
+ }
+ }
-+
-+ // Added by Chen-I & Yen for enabling 5350 EXTIF
-+ if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
-+ {
-+ /* Set programmable interface timing for external uart */
-+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-+ tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
-+ tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
-+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
-+ W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
-+ //printf("===========config_REG=%d\n", R_REG(&cc->prog_config));
-+ //printf("-----------config_REG_addr=%x\n", &cc->prog_config);
-+ //printf("===========waitcount_REG=%d\n", R_REG(&cc->prog_waitcount));
-+ //printf("-----------waitcount_REG=%x\n", &cc->prog_waitcount);
-+ }
+ }
+
+ /* Chip specific initialization */
+ BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
+ }
+ break;
-+ case BCM4310_DEVICE_ID:
-+ MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
-+ break;
-+ case BCM5350_DEVICE_ID:
-+ /* Clear interrupt map */
-+ for (irq = 0; irq <= 4; irq++)
-+ BCMINIT(sb_clearirq)(sbh, irq);
-+ BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
-+ BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
-+ BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
-+ BCMINIT(sb_setirq)(sbh, 3, SB_IPSEC, 0);
-+ BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
++ case BCM5350_DEVICE_ID:
++ /* Clear interrupt map */
++ for (irq = 0; irq <= 4; irq++)
++ BCMINIT(sb_clearirq)(sbh, irq);
++ BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
++ BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
++ BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
++ BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
++ BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
+ break;
+ }
+}
+
+uint32
-+BCMINITFN(sb_mips_clock)(void *sbh)
++BCMINITFN(sb_mips_clock)(sb_t *sbh)
+{
+ extifregs_t *eir;
+ chipcregs_t *cc;
+
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
+
-+static void
++static void
+BCMINITFN(handler)(void)
+{
+ /* Step 11 */
+}
+
+/* The following MUST come right after handler() */
-+static void
++static void
+BCMINITFN(afterhandler)(void)
+{
+}
+/*
+ * Set the MIPS, backplane and PCI clocks as closely as possible.
+ */
-+bool
-+BCMINITFN(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
++bool
++BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
+{
+ extifregs_t *eir = NULL;
+ chipcregs_t *cc = NULL;
+ uint32 m2; /* that is the clockcontrol_m2 */
+ } type3_table_t;
+ static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
-+ { 150000000, 0x311, 0x4020005 },
-+ { 200000000, 0x311, 0x4020003 },
++ { 150000000, 0x311, 0x4020005 },
++ { 200000000, 0x311, 0x4020003 },
+ };
+ typedef struct {
+ uint32 mipsclock;
+
+ ulong start, end, dst;
+ bool ret = FALSE;
-+
++
+ /* get index of the current core */
+ idx = sb_coreidx(sbh);
+ clockcontrol_m2 = NULL;
+ clockcontrol_n = &cc->clockcontrol_n;
+ clockcontrol_sb = &cc->clockcontrol_sb;
+ clockcontrol_pci = &cc->clockcontrol_pci;
-+ clockcontrol_m2 = &cc->clockcontrol_m2;
++ clockcontrol_m2 = &cc->clockcontrol_m2;
+ }
+ } else
+ goto done;
+ /* No PLL change */
+ orig_m2 = R_REG(&cc->clockcontrol_m2);
+ if ((orig_n == type3_table[i].n) &&
-+ (orig_m2 == type3_table[i].m2)) {
++ (orig_m2 == type3_table[i].m2)) {
+ goto done;
+ }
-+
++
+ /* Set the PLL controls */
+ W_REG(clockcontrol_n, type3_table[i].n);
+ W_REG(clockcontrol_m2, type3_table[i].m2);
+ table = BCMINIT(type7_table);
+ tabsz = ARRAYSIZE(BCMINIT(type7_table));
+ } else
-+ ASSERT((char *)"No table for plltype" == NULL);
++ ASSERT("No table for plltype" == NULL);
+
+ /* Store the current clock register values */
+ orig_m2 = R_REG(&cc->clockcontrol_m2);
+ start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
+ end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
+ while (start < end) {
-+ cache_unroll(start, Fill_I);
++ cache_op(start, Fill_I);
+ start += ic_lsize;
+ }
+
+ dst = KSEG1ADDR(0x180);
+ for (i = 0; i < (end - start); i += 4)
+ *((ulong *)(dst + i)) = *((ulong *)(start + i));
-+
++
+ /* Preload handler into the cache one line at a time */
+ for (i = 0; i < (end - start); i += 4)
-+ cache_unroll(dst + i, Fill_I);
++ cache_op(dst + i, Fill_I);
+
+ /* Clear BEV bit */
+ MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
+ MTC0(C0_BROADCOM, 2, 0x9);
+
+
-+ /* steps 5 & 6 */
++ /* steps 5 & 6 */
+ __asm__ __volatile__ (
+ ".set\tmips3\n\t"
+ "wait\n\t"
+
+ /* step 7, clear cfg_active */
+ MTC0(C0_BROADCOM, 2, 0);
-+
++
+ /* Additional Step: set back to orig sync mode */
+ MTC0(C0_BROADCOM, 4, sync_mode);
+
+ return ret;
+}
+
++/*
++ * This also must be run from the cache on 47xx
++ * so there are no mips core BIU ops in progress
++ * when the PFC is enabled.
++ */
++
++static void
++BCMINITFN(_enable_pfc)(uint32 mode)
++{
++ /* write range */
++ *(volatile uint32 *)PFC_CR1 = 0xffff0000;
++
++ /* enable */
++ *(volatile uint32 *)PFC_CR0 = mode;
++}
++
++void
++BCMINITFN(enable_pfc)(uint32 mode)
++{
++ ulong start, end;
++ int i;
++
++ /* If auto then choose the correct mode for this
++ platform, currently we only ever select one mode */
++ if (mode == PFC_AUTO)
++ mode = PFC_INST;
++
++ /* enable prefetch cache if available */
++ if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
++ start = (ulong) &BCMINIT(_enable_pfc);
++ end = (ulong) &BCMINIT(enable_pfc);
++
++ /* Preload handler into the cache one line at a time */
++ for (i = 0; i < (end - start); i += 4)
++ cache_op(start + i, Fill_I);
++
++ BCMINIT(_enable_pfc)(mode);
++ }
++}
+
+/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
+uint32
-+BCMINITFN(sb_memc_get_ncdl)(void *sbh)
++BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
+{
+ sbmemcregs_t *memc;
+ uint32 ret = 0;
+ dqsg = R_REG(&memc->dqsgatencdl);
+
+ rd &= MEMC_RDNCDLCOR_RD_MASK;
-+ wr &= MEMC_WRNCDLCOR_WR_MASK;
++ wr &= MEMC_WRNCDLCOR_WR_MASK;
+ dqsg &= MEMC_DQSGATENCDL_G_MASK;
+
+ if (config & MEMC_CONFIG_DDR) {
+ ret = (wr << 16) | (rd << 8) | dqsg;
+ } else {
-+ if ((rev > 0) || (sb_chip(sbh) == BCM5365_DEVICE_ID))
++ if (rev > 0)
+ cd = rd;
+ else
+ cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
+ return ret;
+}
+
-+/* returns the PFC values to be used based on the chip ID*/
-+
-+uint32
-+BCMINITFN(sb_mips_get_pfc)(void *sbh)
-+{
-+ if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
-+ return 0x11;
-+ else
-+ return 0x15;
-+}
diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
--- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-08-26 13:44:34.313391368 +0200
++++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-11-07 23:53:20.981131500 +0100
@@ -0,0 +1,588 @@
+/*
+ * Low-Level PCI and SB support for BCM47xx
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
-+ * $Id: sbpci.c,v 1.7 2005/03/07 08:35:32 kanki Exp $
++ * $Id$
+ */
+
+#include <typedefs.h>
+#include <pcicfg.h>
+#include <bcmdevs.h>
+#include <sbconfig.h>
-+#include <sbpci.h>
+#include <osl.h>
++#include <sbutils.h>
++#include <sbpci.h>
+#include <bcmendian.h>
+#include <bcmutils.h>
-+#include <sbutils.h>
+#include <bcmnvram.h>
+#include <hndmips.h>
+
+#define PCI_SLOT_MAX 16
+
+static uint32
-+config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
++config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
+{
+ uint coreidx;
+ sbpciregs_t *regs;
+}
+
+static int
-+extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ uint32 addr, *reg = NULL, val;
+ int ret = 0;
+}
+
+static int
-+extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ uint32 addr, *reg = NULL, val;
+ int ret = 0;
+ */
+
+static int
-+sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ pci_config_regs *cfg;
+
+}
+
+static int
-+sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ uint coreidx, n;
+ void *regs;
+}
+
+int
-+sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ if (bus == 0)
+ return sb_read_config(sbh, bus, dev, func, off, buf, len);
+}
+
+int
-+sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
++sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
+{
+ if (bus == 0)
+ return sb_write_config(sbh, bus, dev, func, off, buf, len);
+}
+
+static int
-+sbpci_init_pci(void *sbh)
++sbpci_init_pci(sb_t *sbh)
+{
+ uint chip, chiprev, chippkg, host;
+ uint32 boardflags;
+ sbpciregs_t *pci;
+ sbconfig_t *sb;
-+ int CT4712_WR;
+ uint32 val;
+
+ chip = sb_chip(sbh);
+ if (cardbus) {
+ printf("PCI: Enabling CardBus\n");
+ /* GPIO 1 resets the CardBus device on bcm94710ap */
-+ sb_gpioout(sbh, 1, 1);
-+ sb_gpioouten(sbh, 1, 1);
++ sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
++ sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
+ W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
+ }
+
+}
+
+static int
-+sbpci_init_cores(void *sbh)
++sbpci_init_cores(sb_t *sbh)
+{
+ uint chip, chiprev, chippkg, coreidx, i;
+ sbconfig_t *sb;
+}
+
+int __init
-+sbpci_init(void *sbh)
++sbpci_init(sb_t *sbh)
+{
+ sbpci_init_pci(sbh);
+ sbpci_init_cores(sbh);
+}
+
+void
-+sbpci_check(void *sbh)
++sbpci_check(sb_t *sbh)
+{
+ uint coreidx;
+ sbpciregs_t *pci;
+
+ sb_setcoreidx(sbh, coreidx);
+}
++
diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
--- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/setup.c 2005-08-26 13:44:34.313391368 +0200
-@@ -0,0 +1,261 @@
++++ linux.dev/arch/mips/bcm947xx/setup.c 2005-11-08 00:11:55.346775000 +0100
+@@ -0,0 +1,272 @@
+/*
+ * Generic setup routines for Broadcom MIPS boards
+ *
-+ * Copyright 2004, Broadcom Corporation
++ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
-+ * $Id: setup.c,v 1.2 2005/04/02 12:12:57 wbx Exp $
++ * $Id$
+ */
+
+#include <linux/config.h>
+#include <linux/serialP.h>
+#include <linux/ide.h>
+#include <asm/bootinfo.h>
++#include <asm/cpu.h>
+#include <asm/time.h>
+#include <asm/reboot.h>
+
+#endif
+
+#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
+#include <bcmutils.h>
+#include <bcmnvram.h>
+#include <sbmips.h>
-+#include <sbutils.h>
+#include <trxhdr.h>
+
+extern void bcm947xx_time_init(void);
+extern void bcm947xx_timer_setup(struct irqaction *irq);
-+extern void check_enable_mips_pfc(int val);
+
+#ifdef CONFIG_REMOTE_DEBUG
+extern void set_debug_traps(void);
+#endif
+
+/* Global SB handle */
-+void *bcm947xx_sbh = NULL;
++sb_t *bcm947xx_sbh = NULL;
+spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
+EXPORT_SYMBOL(bcm947xx_sbh);
+EXPORT_SYMBOL(bcm947xx_sbh_lock);
+}
+
+static void __init
-+serial_setup(void *sbh)
++serial_setup(sb_t *sbh)
+{
+ sb_serial_init(sbh, serial_add);
+
+brcm_setup(void)
+{
+ char *value;
-+ uint pfc_val;
+
+ /* Get global SB handle */
+ sbh = sb_kattach();
+ /* Initialize clocks and interrupts */
+ sb_mips_init(sbh);
+
-+ /*
-+ * Now that the sbh is inited set the proper PFC value
-+ */
-+ pfc_val = sb_mips_get_pfc(sbh);
-+ printk("Setting the PFC value as 0x%x\n", pfc_val);
-+ check_enable_mips_pfc(pfc_val);
++ if (BCM330X(current_cpu_data.processor_id) &&
++ (read_c0_diag() & BRCM_PFC_AVAIL)) {
++ /*
++ * Now that the sbh is inited set the proper PFC value
++ */
++ printk("Setting the PFC to its default value\n");
++ enable_pfc(PFC_AUTO);
++ }
++
+
+#ifdef CONFIG_SERIAL
+ /* Initialize UARTs */
+const char *
+get_system_type(void)
+{
-+ return "Broadcom BCM947XX";
++ static char s[32];
++
++ if (bcm947xx_sbh) {
++ sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
++ sb_chiprev(bcm947xx_sbh));
++ return s;
++ }
++ else
++ return "Broadcom BCM947XX";
+}
+
+void __init
+EXPORT_SYMBOL(init_mtd_partitions);
+
+#endif
-diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
---- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/time.c 2005-08-26 13:44:34.314391216 +0200
-@@ -0,0 +1,117 @@
+diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
+--- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/sflash.c 2005-11-08 00:54:43.022739000 +0100
+@@ -0,0 +1,418 @@
+/*
-+ * Copyright 2004, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * Broadcom SiliconBackplane chipcommon serial flash interface
+ *
-+ * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/serial_reg.h>
-+#include <linux/interrupt.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
-+#include <asm/time.h>
+
++#include <osl.h>
+#include <typedefs.h>
-+#include <bcmnvram.h>
+#include <sbconfig.h>
-+#include <sbextif.h>
-+#include <sbutils.h>
-+#include <sbmips.h>
++#include <sbchipc.h>
++#include <mipsinc.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <sflash.h>
+
-+/* Global SB handle */
-+extern void *bcm947xx_sbh;
-+extern spinlock_t bcm947xx_sbh_lock;
++/* Private global state */
++static struct sflash sflash;
+
-+/* Convenience */
-+#define sbh bcm947xx_sbh
-+#define sbh_lock bcm947xx_sbh_lock
++/* Issue a serial flash command */
++static INLINE void
++sflash_cmd(chipcregs_t *cc, uint opcode)
++{
++ W_REG(&cc->flashcontrol, SFLASH_START | opcode);
++ while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
++}
+
-+extern int panic_timeout;
-+static int watchdog = 0;
-+static u8 *mcr = NULL;
++/* Initialize serial flash access */
++struct sflash *
++sflash_init(chipcregs_t *cc)
++{
++ uint32 id, id2;
+
-+void __init
-+bcm947xx_time_init(void)
++ bzero(&sflash, sizeof(sflash));
++
++ sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
++
++ switch (sflash.type) {
++ case SFLASH_ST:
++ /* Probe for ST chips */
++ sflash_cmd(cc, SFLASH_ST_DP);
++ sflash_cmd(cc, SFLASH_ST_RES);
++ id = R_REG(&cc->flashdata);
++ switch (id) {
++ case 0x11:
++ /* ST M25P20 2 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 4;
++ break;
++ case 0x12:
++ /* ST M25P40 4 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 8;
++ break;
++ case 0x13:
++ /* ST M25P80 8 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 16;
++ break;
++ case 0x14:
++ /* ST M25P16 16 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 32;
++ break;
++ case 0x15:
++ /* ST M25P32 32 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 64;
++ break;
++ case 0xbf:
++ W_REG(&cc->flashaddress, 1);
++ sflash_cmd(cc, SFLASH_ST_RES);
++ id2 = R_REG(&cc->flashdata);
++ if (id2 == 0x44) {
++ /* SST M25VF80 4 Mbit Serial Flash */
++ sflash.blocksize = 64 * 1024;
++ sflash.numblocks = 8;
++ }
++ break;
++ }
++ break;
++
++ case SFLASH_AT:
++ /* Probe for Atmel chips */
++ sflash_cmd(cc, SFLASH_AT_STATUS);
++ id = R_REG(&cc->flashdata) & 0x3c;
++ switch (id) {
++ case 0xc:
++ /* Atmel AT45DB011 1Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 512;
++ break;
++ case 0x14:
++ /* Atmel AT45DB021 2Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 1024;
++ break;
++ case 0x1c:
++ /* Atmel AT45DB041 4Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 2048;
++ break;
++ case 0x24:
++ /* Atmel AT45DB081 8Mbit Serial Flash */
++ sflash.blocksize = 256;
++ sflash.numblocks = 4096;
++ break;
++ case 0x2c:
++ /* Atmel AT45DB161 16Mbit Serial Flash */
++ sflash.blocksize = 512;
++ sflash.numblocks = 4096;
++ break;
++ case 0x34:
++ /* Atmel AT45DB321 32Mbit Serial Flash */
++ sflash.blocksize = 512;
++ sflash.numblocks = 8192;
++ break;
++ case 0x3c:
++ /* Atmel AT45DB642 64Mbit Serial Flash */
++ sflash.blocksize = 1024;
++ sflash.numblocks = 8192;
++ break;
++ }
++ break;
++ }
++
++ sflash.size = sflash.blocksize * sflash.numblocks;
++ return sflash.size ? &sflash : NULL;
++}
++
++/* Read len bytes starting at offset into buf. Returns number of bytes read. */
++int
++sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
+{
-+ unsigned int hz;
-+ extifregs_t *eir;
++ int cnt;
++ uint32 *from, *to;
+
-+ /*
-+ * Use deterministic values for initial counter interrupt
-+ * so that calibrate delay avoids encountering a counter wrap.
-+ */
-+ write_c0_count(0);
-+ write_c0_compare(0xffff);
++ if (!len)
++ return 0;
+
-+ if (!(hz = sb_mips_clock(sbh)))
-+ hz = 100000000;
++ if ((offset + len) > sflash.size)
++ return -22;
+
-+ printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
-+ (hz + 500000) / 1000000);
++ if ((len >= 4) && (offset & 3))
++ cnt = 4 - (offset & 3);
++ else if ((len >= 4) && ((uint32)buf & 3))
++ cnt = 4 - ((uint32)buf & 3);
++ else
++ cnt = len;
+
-+ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
-+ mips_hpt_frequency = hz / 2;
++ from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
++ to = (uint32 *)buf;
+
-+ /* Set watchdog interval in ms */
-+ watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
-+
-+ /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
-+ if (watchdog > 0) {
-+ if (watchdog < 3000)
-+ watchdog = 3000;
++ if (cnt < 4) {
++ bcopy(from, to, cnt);
++ return cnt;
+ }
+
++ while (cnt >= 4) {
++ *to++ = *from++;
++ cnt -= 4;
++ }
+
-+ /* Set panic timeout in seconds */
-+ panic_timeout = watchdog / 1000;
++ return (len - cnt);
++}
+
-+ /* Setup blink */
-+ if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
-+ sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
-+ unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
-+ mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
++/* Poll for command completion. Returns zero when complete. */
++int
++sflash_poll(chipcregs_t *cc, uint offset)
++{
++ if (offset >= sflash.size)
++ return -22;
++
++ switch (sflash.type) {
++ case SFLASH_ST:
++ /* Check for ST Write In Progress bit */
++ sflash_cmd(cc, SFLASH_ST_RDSR);
++ return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
++ case SFLASH_AT:
++ /* Check for Atmel Ready bit */
++ sflash_cmd(cc, SFLASH_AT_STATUS);
++ return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
+ }
++
++ return 0;
+}
+
-+static void
-+bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++/* Write len bytes starting at offset into buf. Returns number of bytes
++ * written. Caller should poll for completion.
++ */
++int
++sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
++{
++ struct sflash *sfl;
++ int ret = 0;
++ bool is4712b0;
++ uint32 page, byte, mask;
++
++ if (!len)
++ return 0;
++
++ if ((offset + len) > sflash.size)
++ return -22;
++
++ sfl = &sflash;
++ switch (sfl->type) {
++ case SFLASH_ST:
++ mask = R_REG(&cc->chipid);
++ is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
++ ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
++ /* Enable writes */
++ sflash_cmd(cc, SFLASH_ST_WREN);
++ if (is4712b0) {
++ mask = 1 << 14;
++ W_REG(&cc->flashaddress, offset);
++ W_REG(&cc->flashdata, *buf++);
++ /* Set chip select */
++ OR_REG(&cc->gpioout, mask);
++ /* Issue a page program with the first byte */
++ sflash_cmd(cc, SFLASH_ST_PP);
++ ret = 1;
++ offset++;
++ len--;
++ while (len > 0) {
++ if ((offset & 255) == 0) {
++ /* Page boundary, drop cs and return */
++ AND_REG(&cc->gpioout, ~mask);
++ if (!sflash_poll(cc, offset)) {
++ /* Flash rejected command */
++ return -11;
++ }
++ return ret;
++ } else {
++ /* Write single byte */
++ sflash_cmd(cc, *buf++);
++ }
++ ret++;
++ offset++;
++ len--;
++ }
++ /* All done, drop cs if needed */
++ if ((offset & 255) != 1) {
++ /* Drop cs */
++ AND_REG(&cc->gpioout, ~mask);
++ if (!sflash_poll(cc, offset)) {
++ /* Flash rejected command */
++ return -12;
++ }
++ }
++ } else {
++ ret = 1;
++ W_REG(&cc->flashaddress, offset);
++ W_REG(&cc->flashdata, *buf);
++ /* Page program */
++ sflash_cmd(cc, SFLASH_ST_PP);
++ }
++ break;
++ case SFLASH_AT:
++ mask = sfl->blocksize - 1;
++ page = (offset & ~mask) << 1;
++ byte = offset & mask;
++ /* Read main memory page into buffer 1 */
++ if (byte || len < sfl->blocksize) {
++ W_REG(&cc->flashaddress, page);
++ sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
++ /* 250 us for AT45DB321B */
++ SPINWAIT(sflash_poll(cc, offset), 1000);
++ ASSERT(!sflash_poll(cc, offset));
++ }
++ /* Write into buffer 1 */
++ for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
++ W_REG(&cc->flashaddress, byte++);
++ W_REG(&cc->flashdata, *buf++);
++ sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
++ }
++ /* Write buffer 1 into main memory page */
++ W_REG(&cc->flashaddress, page);
++ sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
++ break;
++ }
++
++ return ret;
++}
++
++/* Erase a region. Returns number of bytes scheduled for erasure.
++ * Caller should poll for completion.
++ */
++int
++sflash_erase(chipcregs_t *cc, uint offset)
++{
++ struct sflash *sfl;
++
++ if (offset >= sflash.size)
++ return -22;
++
++ sfl = &sflash;
++ switch (sfl->type) {
++ case SFLASH_ST:
++ sflash_cmd(cc, SFLASH_ST_WREN);
++ W_REG(&cc->flashaddress, offset);
++ sflash_cmd(cc, SFLASH_ST_SE);
++ return sfl->blocksize;
++ case SFLASH_AT:
++ W_REG(&cc->flashaddress, offset << 1);
++ sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
++ return sfl->blocksize;
++ }
++
++ return 0;
++}
++
++/*
++ * writes the appropriate range of flash, a NULL buf simply erases
++ * the region of flash
++ */
++int
++sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
++{
++ struct sflash *sfl;
++ uchar *block = NULL, *cur_ptr, *blk_ptr;
++ uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
++ uint blk_offset, blk_len, copied;
++ int bytes, ret = 0;
++
++ /* Check address range */
++ if (len <= 0)
++ return 0;
++
++ sfl = &sflash;
++ if ((offset + len) > sfl->size)
++ return -1;
++
++ blocksize = sfl->blocksize;
++ mask = blocksize - 1;
++
++ /* Allocate a block of mem */
++ if (!(block = MALLOC(NULL, blocksize)))
++ return -1;
++
++ while (len) {
++ /* Align offset */
++ cur_offset = offset & ~mask;
++ cur_length = blocksize;
++ cur_ptr = block;
++
++ remainder = blocksize - (offset & mask);
++ if (len < remainder)
++ cur_retlen = len;
++ else
++ cur_retlen = remainder;
++
++ /* buf == NULL means erase only */
++ if (buf) {
++ /* Copy existing data into holding block if necessary */
++ if ((offset & mask) || (len < blocksize)) {
++ blk_offset = cur_offset;
++ blk_len = cur_length;
++ blk_ptr = cur_ptr;
++
++ /* Copy entire block */
++ while(blk_len) {
++ copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
++ blk_offset += copied;
++ blk_len -= copied;
++ blk_ptr += copied;
++ }
++ }
++
++ /* Copy input data into holding block */
++ memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
++ }
++
++ /* Erase block */
++ if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
++ goto done;
++ while (sflash_poll(cc, (uint) cur_offset));
++
++ /* buf == NULL means erase only */
++ if (!buf) {
++ offset += cur_retlen;
++ len -= cur_retlen;
++ continue;
++ }
++
++ /* Write holding block */
++ while (cur_length > 0) {
++ if ((bytes = sflash_write(cc,
++ (uint) cur_offset,
++ (uint) cur_length,
++ (uchar *) cur_ptr)) < 0) {
++ ret = bytes;
++ goto done;
++ }
++ while (sflash_poll(cc, (uint) cur_offset));
++ cur_offset += bytes;
++ cur_length -= bytes;
++ cur_ptr += bytes;
++ }
++
++ offset += cur_retlen;
++ len -= cur_retlen;
++ buf += cur_retlen;
++ }
++
++ ret = len;
++done:
++ if (block)
++ MFREE(NULL, block, blocksize);
++ return ret;
++}
++
+diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
+--- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/bcm947xx/time.c 2005-11-07 23:47:27.528101500 +0100
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2004, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/serial_reg.h>
++#include <linux/interrupt.h>
++#include <asm/addrspace.h>
++#include <asm/io.h>
++#include <asm/time.h>
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmnvram.h>
++#include <sbconfig.h>
++#include <sbextif.h>
++#include <sbmips.h>
++
++/* Global SB handle */
++extern void *bcm947xx_sbh;
++extern spinlock_t bcm947xx_sbh_lock;
++
++/* Convenience */
++#define sbh bcm947xx_sbh
++#define sbh_lock bcm947xx_sbh_lock
++
++extern int panic_timeout;
++static int watchdog = 0;
++static u8 *mcr = NULL;
++
++void __init
++bcm947xx_time_init(void)
++{
++ unsigned int hz;
++ extifregs_t *eir;
++
++ /*
++ * Use deterministic values for initial counter interrupt
++ * so that calibrate delay avoids encountering a counter wrap.
++ */
++ write_c0_count(0);
++ write_c0_compare(0xffff);
++
++ if (!(hz = sb_mips_clock(sbh)))
++ hz = 100000000;
++
++ printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
++ (hz + 500000) / 1000000);
++
++ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
++ mips_hpt_frequency = hz / 2;
++
++ /* Set watchdog interval in ms */
++ watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
++
++ /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
++ if (watchdog > 0) {
++ if (watchdog < 3000)
++ watchdog = 3000;
++ }
++
++
++ /* Set panic timeout in seconds */
++ panic_timeout = watchdog / 1000;
++
++ /* Setup blink */
++ if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
++ sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
++ unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
++ mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
++ }
++}
++
++static void
++bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ /* Generic MIPS timer code */
+ timer_interrupt(irq, dev_id, regs);
+ setup_irq(7, &bcm947xx_timer_irqaction);
+}
diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
---- linux.old/arch/mips/config-shared.in 2005-08-26 13:41:43.371378504 +0200
-+++ linux.dev/arch/mips/config-shared.in 2005-08-26 13:44:34.315391064 +0200
+--- linux.old/arch/mips/config-shared.in 2005-11-07 23:12:50.850903750 +0100
++++ linux.dev/arch/mips/config-shared.in 2005-11-07 21:57:07.889588500 +0100
@@ -208,6 +208,14 @@
fi
define_bool CONFIG_MIPS_RTC y
if [ "$CONFIG_KGDB" = "y" ]; then
define_bool CONFIG_DEBUG_INFO y
diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
---- linux.old/arch/mips/kernel/cpu-probe.c 2005-08-26 13:41:41.803616840 +0200
-+++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-08-26 13:44:34.316390912 +0200
+--- linux.old/arch/mips/kernel/cpu-probe.c 2005-11-07 23:12:50.890906250 +0100
++++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-11-07 21:57:07.893588750 +0100
@@ -163,7 +163,7 @@
static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
cpu_probe_sibyte(c);
break;
diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
---- linux.old/arch/mips/kernel/head.S 2005-08-26 13:41:41.804616688 +0200
-+++ linux.dev/arch/mips/kernel/head.S 2005-08-26 13:44:34.317390760 +0200
+--- linux.old/arch/mips/kernel/head.S 2005-11-07 23:12:50.898906750 +0100
++++ linux.dev/arch/mips/kernel/head.S 2005-11-07 21:57:07.893588750 +0100
@@ -28,12 +28,20 @@
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
/* The following two symbols are used for kernel profiling. */
EXPORT(stext)
diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
---- linux.old/arch/mips/kernel/proc.c 2005-01-19 15:09:29.000000000 +0100
-+++ linux.dev/arch/mips/kernel/proc.c 2005-08-26 13:44:34.318390608 +0200
+--- linux.old/arch/mips/kernel/proc.c 2005-11-07 23:12:50.906907250 +0100
++++ linux.dev/arch/mips/kernel/proc.c 2005-11-07 21:57:07.893588750 +0100
@@ -78,9 +78,10 @@
[CPU_AU1550] "Au1550",
[CPU_24K] "MIPS 24K",
{
unsigned int version = current_cpu_data.processor_id;
diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
---- linux.old/arch/mips/kernel/setup.c 2005-08-26 13:41:41.805616536 +0200
-+++ linux.dev/arch/mips/kernel/setup.c 2005-08-26 13:44:34.318390608 +0200
+--- linux.old/arch/mips/kernel/setup.c 2005-11-07 23:12:50.906907250 +0100
++++ linux.dev/arch/mips/kernel/setup.c 2005-11-07 21:57:07.893588750 +0100
@@ -493,6 +493,7 @@
void swarm_setup(void);
void hp_setup(void);
panic("Unsupported architecture");
}
diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
---- linux.old/arch/mips/kernel/traps.c 2005-08-26 13:41:41.806616384 +0200
-+++ linux.dev/arch/mips/kernel/traps.c 2005-08-26 13:44:34.321390152 +0200
+--- linux.old/arch/mips/kernel/traps.c 2005-11-07 23:12:50.922908250 +0100
++++ linux.dev/arch/mips/kernel/traps.c 2005-11-07 21:57:07.893588750 +0100
@@ -920,6 +920,7 @@
void __init trap_init(void)
{
set_except_vector(15, handle_fpe);
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
---- linux.old/arch/mips/mm/c-r4k.c 2005-08-26 13:41:41.825613496 +0200
-+++ linux.dev/arch/mips/mm/c-r4k.c 2005-08-26 13:44:34.322390000 +0200
-@@ -1118,3 +1118,47 @@
+--- linux.old/arch/mips/mm/c-r4k.c 2005-11-07 23:12:50.954910250 +0100
++++ linux.dev/arch/mips/mm/c-r4k.c 2005-11-07 21:57:08.157605250 +0100
+@@ -1166,3 +1166,47 @@
build_clear_page();
build_copy_page();
}
+
+
diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
---- linux.old/arch/mips/pci/Makefile 2005-01-19 15:09:29.000000000 +0100
-+++ linux.dev/arch/mips/pci/Makefile 2005-08-26 13:44:34.323389848 +0200
+--- linux.old/arch/mips/pci/Makefile 2005-11-07 23:12:50.978911750 +0100
++++ linux.dev/arch/mips/pci/Makefile 2005-11-07 21:57:07.897589000 +0100
@@ -13,7 +13,9 @@
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
include $(TOPDIR)/Rules.make
diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
---- linux.old/drivers/char/serial.c 2005-08-26 13:41:41.952594192 +0200
-+++ linux.dev/drivers/char/serial.c 2005-09-01 02:33:38.312794792 +0200
+--- linux.old/drivers/char/serial.c 2005-11-07 23:12:51.038915500 +0100
++++ linux.dev/drivers/char/serial.c 2005-11-07 21:57:07.901589250 +0100
@@ -444,6 +444,10 @@
return inb(info->port+1);
#endif
/*
* Work around a bug in the Oxford Semiconductor 952 rev B
* chip which causes it to seriously miscalculate baud rates
-@@ -5996,6 +6003,13 @@
+@@ -5984,6 +5991,13 @@
* Divisor, bytesize and parity
*/
state = rs_table + co->index;
if (doflow)
state->flags |= ASYNC_CONS_FLOW;
info = &async_sercons;
-@@ -6009,7 +6023,7 @@
+@@ -5997,7 +6011,7 @@
info->io_type = state->io_type;
info->iomem_base = state->iomem_base;
info->iomem_reg_shift = state->iomem_reg_shift;
#if defined(__powerpc__) || defined(__alpha__)
cval >>= 8;
diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
---- linux.old/drivers/mtd/maps/Config.in 2005-08-26 13:41:41.963592520 +0200
-+++ linux.dev/drivers/mtd/maps/Config.in 2005-08-26 13:44:34.345386504 +0200
+--- linux.old/drivers/mtd/maps/Config.in 2005-11-07 23:12:51.086918500 +0100
++++ linux.dev/drivers/mtd/maps/Config.in 2005-11-07 21:57:07.901589250 +0100
@@ -48,6 +48,7 @@
fi
dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
---- linux.old/drivers/mtd/maps/Makefile 2005-08-26 13:41:41.963592520 +0200
-+++ linux.dev/drivers/mtd/maps/Makefile 2005-08-26 13:44:34.346386352 +0200
+--- linux.old/drivers/mtd/maps/Makefile 2005-11-07 23:12:51.086918500 +0100
++++ linux.dev/drivers/mtd/maps/Makefile 2005-11-07 21:57:07.905589500 +0100
@@ -3,6 +3,8 @@
#
# $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
diff -urN linux.old/drivers/mtd/maps/bcm947xx-flash.c linux.dev/drivers/mtd/maps/bcm947xx-flash.c
--- linux.old/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-08-26 13:44:34.346386352 +0200
-@@ -0,0 +1,236 @@
++++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-11-07 23:33:20.715765500 +0100
+@@ -0,0 +1,237 @@
+/*
+ * Flash mapping for BCM947XX boards
+ *
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+
++#include <osl.h>
+#include <typedefs.h>
+#include <bcmnvram.h>
+#include <bcmutils.h>
+module_init(init_bcm947xx_map);
+module_exit(cleanup_bcm947xx_map);
diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
---- linux.old/drivers/net/Config.in 2005-08-26 13:41:43.481361784 +0200
-+++ linux.dev/drivers/net/Config.in 2005-08-26 13:44:34.358384528 +0200
+--- linux.old/drivers/net/Config.in 2005-11-07 23:12:51.110920000 +0100
++++ linux.dev/drivers/net/Config.in 2005-11-07 21:57:07.905589500 +0100
@@ -2,6 +2,8 @@
# Network device configuration
#
dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
---- linux.old/drivers/net/Makefile 2005-08-26 13:41:43.082422432 +0200
-+++ linux.dev/drivers/net/Makefile 2005-08-26 13:44:34.370382704 +0200
+--- linux.old/drivers/net/Makefile 2005-11-07 23:12:51.110920000 +0100
++++ linux.dev/drivers/net/Makefile 2005-11-07 21:57:07.905589500 +0100
@@ -3,6 +3,8 @@
# Makefile for the Linux network (ethercard) device drivers.
#
clean:
diff -urN linux.old/drivers/net/et/Makefile linux.dev/drivers/net/et/Makefile
--- linux.old/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/net/et/Makefile 2005-08-26 13:44:34.371382552 +0200
++++ linux.dev/drivers/net/et/Makefile 2005-11-07 21:57:07.905589500 +0100
@@ -0,0 +1,21 @@
+#
+# Makefile for the Broadcom et driver
+include $(TOPDIR)/Rules.make
diff -urN linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
--- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/net/hnd/Makefile 2005-08-26 13:44:34.371382552 +0200
++++ linux.dev/drivers/net/hnd/Makefile 2005-11-07 21:57:07.905589500 +0100
@@ -0,0 +1,19 @@
+#
+# Makefile for the BCM47xx specific kernel interface routines
+ sh -e $< $(HND_OBJS) > $@
diff -urN linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
--- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-08-26 13:44:34.372382400 +0200
-@@ -0,0 +1,714 @@
++++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-11-07 22:28:05.077337250 +0100
+@@ -0,0 +1,936 @@
+/*
+ * Misc useful routines to access NIC SROM/OTP .
+ *
-+ * Copyright 2004, Broadcom Corporation
++ * Copyright 2005, Broadcom Corporation
+ * All Rights Reserved.
+ *
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+#include <sbpcmcia.h>
+#include <pcicfg.h>
+#include <sbutils.h>
++#include <bcmnvram.h>
+
+#include <proto/ethernet.h> /* for sprom content groking */
+
+#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
+#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
+
-+static int initvars_srom_pci(void *osh, void *curmap, char **vars, int *count);
-+static int initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count);
-+static int srom_parsecis(void *osh, uint8 *cis, char **vars, int *count);
-+static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
-+static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
-+static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
++static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
++static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
++static int initvars_flash_sb(void *sbh, char **vars, int *count);
++static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
++static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
++static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
++static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
+static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
+
++static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
++static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
++
+/*
+ * Initialize local vars from the right source for this platform.
+ * Return 0 on success, nonzero on error.
+ */
+int
-+srom_var_init(void *sbh, uint bustype, void *curmap, void *osh, char **vars, int *count)
++srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
+{
+ ASSERT(bustype == BUSTYPE(bustype));
-+ if (vars == NULL)
++ if (vars == NULL || count == NULL)
+ return (0);
+
+ switch (BUSTYPE(bustype)) {
+ case SB_BUS:
-+ /* These two could be asserts ... */
-+ *vars = NULL;
-+ *count = 0;
-+ return(0);
++ case JTAG_BUS:
++ return initvars_flash_sb(sbh, vars, count);
+
+ case PCI_BUS:
+ ASSERT(curmap); /* can not be NULL */
-+ return(initvars_srom_pci(osh, curmap, vars, count));
++ return initvars_srom_pci(sbh, curmap, vars, count);
+
+ case PCMCIA_BUS:
-+ return(initvars_cis_pcmcia(sbh, curmap, osh, vars, count));
++ return initvars_cis_pcmcia(sbh, osh, vars, count);
+
+
+ default:
+
+/* support only 16-bit word read from srom */
+int
-+srom_read(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
++srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
+{
+ void *srom;
+ uint i, off, nw;
+
+/* support only 16-bit word write into srom */
+int
-+srom_write(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
++srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
+{
+ uint16 *srom;
+ uint i, off, nw, crc_range;
+
+
+static int
-+srom_parsecis(void *osh, uint8 *cis, char **vars, int *count)
++srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
+{
+ char eabuf[32];
+ char *vp, *base;
+ int i, j;
+ uint varsize;
+ bool ag_init = FALSE;
-+ uint16 w;
++ uint32 w32;
+
+ ASSERT(vars);
+ ASSERT(count);
+
+ base = vp = MALLOC(osh, VARS_MAX);
+ ASSERT(vp);
++ if (!vp)
++ return -2;
+
+ i = 0;
+ do {
+
+ case CISTPL_BRCM_HNBU:
+ switch (cis[i]) {
++ case HNBU_SROMREV:
++ sromrev = cis[i + 1];
++ break;
++
+ case HNBU_CHIPID:
+ vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
+ vp++;
+ break;
+
+ case HNBU_CC:
++ ASSERT(sromrev > 1);
+ vp += sprintf(vp, "cc=%d", cis[i + 1]);
+ vp++;
+ break;
+
+ case HNBU_PAPARMS:
-+ vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
-+ vp++;
-+ if (tlen == 9) {
-+ /* New version */
++ if (tlen == 2) {
++ ASSERT(sromrev == 1);
++ vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
++ vp++;
++ } else if (tlen >= 9) {
++ if (tlen == 10) {
++ ASSERT(sromrev == 2);
++ vp += sprintf(vp, "opo=%d", cis[i + 9]);
++ vp++;
++ } else
++ ASSERT(tlen == 9);
++
+ for (j = 0; j < 3; j++) {
+ vp += sprintf(vp, "pa0b%d=%d", j,
+ (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
+ }
+ vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
+ vp++;
-+ }
++ vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
++ vp++;
++ } else
++ ASSERT(tlen >= 9);
+ break;
+
+ case HNBU_OEM:
++ ASSERT(sromrev == 1);
+ vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
+ cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
+ cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
+ vp++;
+ break;
++
+ case HNBU_BOARDFLAGS:
-+ w = (cis[i + 2] << 8) + cis[i + 1];
-+ if (w == 0xffff) w = 0;
-+ vp += sprintf(vp, "boardflags=%d", w);
++ w32 = (cis[i + 2] << 8) + cis[i + 1];
++ if (tlen == 5)
++ w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
++ vp += sprintf(vp, "boardflags=0x%x", w32);
+ vp++;
+ break;
-+ case HNBU_LED:
++
++ case HNBU_LEDS:
+ if (cis[i + 1] != 0xff) {
+ vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
+ vp++;
+ vp++;
+ }
+ break;
++
++ case HNBU_CCODE:
++ ASSERT(sromrev > 1);
++ vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
++ vp++;
++ vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
++ vp++;
++ break;
++
++ case HNBU_CCKPO:
++ ASSERT(sromrev > 2);
++ vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
++ vp++;
++ break;
++
++ case HNBU_OFDMPO:
++ ASSERT(sromrev > 2);
++ vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
++ (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
++ vp++;
++ break;
+ }
+ break;
+
+ vp += sprintf(vp, "sromrev=%d", sromrev);
+ vp++;
+
-+ /* For now just set boardflags2 to zero */
-+ vp += sprintf(vp, "boardflags2=0");
-+ vp++;
-+
+ /* if there is no antenna gain field, set default */
+ if (ag_init == FALSE) {
++ ASSERT(sromrev == 1);
+ vp += sprintf(vp, "ag0=%d", 0xff);
+ vp++;
+ }
+ } else {
+ vp = MALLOC(osh, varsize);
+ ASSERT(vp);
-+ bcopy(base, vp, varsize);
++ if (vp)
++ bcopy(base, vp, varsize);
+ MFREE(osh, base, VARS_MAX);
+ *vars = vp;
++ if (!vp) {
++ *count = 0;
++ return -2;
++ }
+ }
+ *count = varsize;
+
+
+/* set PCMCIA sprom command register */
+static int
-+sprom_cmd_pcmcia(void *osh, uint8 cmd)
++sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
+{
+ uint8 status = 0;
+ uint wait_cnt = 1000;
+
+/* read a word from the PCMCIA srom */
+static int
-+sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
++sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
+{
+ uint8 addr_l, addr_h, data_l, data_h;
+
+
+/* write a word to the PCMCIA srom */
+static int
-+sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
++sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
+{
+ uint8 addr_l, addr_h, data_l, data_h;
+
+static int
+sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
+{
-+ uint8 chk8;
++ int err = 0;
+ uint i;
+
+ /* read the sprom */
+ if (check_crc) {
+ /* fixup the endianness so crc8 will pass */
+ htol16_buf(buf, nwords * 2);
-+ if ((chk8 = hndcrc8((uchar*)buf, nwords * 2, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
-+ return (1);
++ if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
++ err = 1;
+ /* now correct the endianness of the byte array */
+ ltoh16_buf(buf, nwords * 2);
+ }
++
++ return err;
++}
+
-+ return (0);
++/*
++* Create variable table from memory.
++* Return 0 on success, nonzero on error.
++*/
++static int
++initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
++{
++ int c = (int)(end - start);
++
++ /* do it only when there is more than just the null string */
++ if (c > 1) {
++ char *vp = MALLOC(osh, c);
++ ASSERT(vp);
++ if (!vp)
++ return BCME_NOMEM;
++ bcopy(start, vp, c);
++ *vars = vp;
++ *count = c;
++ }
++ else {
++ *vars = NULL;
++ *count = 0;
++ }
++
++ return 0;
+}
+
+/*
-+ * Initialize nonvolatile variable table from sprom.
++* Find variables with <devpath> from flash. 'base' points to the beginning
++* of the table upon enter and to the end of the table upon exit when success.
++* Return 0 on success, nonzero on error.
++*/
++static int
++initvars_flash(osl_t *osh, char **base, int size, char *devpath)
++{
++ char *vp = *base;
++ char *flash;
++ int err;
++ char *s;
++ uint l, dl, copy_len;
++
++ /* allocate memory and read in flash */
++ if (!(flash = MALLOC(osh, NVRAM_SPACE)))
++ return BCME_NOMEM;
++ if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
++ goto exit;
++
++ /* grab vars with the <devpath> prefix in name */
++ dl = strlen(devpath);
++ for (s = flash; s && *s; s += l + 1) {
++ l = strlen(s);
++
++ /* skip non-matching variable */
++ if (strncmp(s, devpath, dl))
++ continue;
++
++ /* is there enough room to copy? */
++ copy_len = l - dl + 1;
++ if (size < (int)copy_len) {
++ err = BCME_BUFTOOSHORT;
++ goto exit;
++ }
++
++ /* no prefix, just the name=value */
++ strcpy(vp, &s[dl]);
++ vp += copy_len;
++ size -= copy_len;
++ }
++
++ /* add null string as terminator */
++ if (size < 1) {
++ err = BCME_BUFTOOSHORT;
++ goto exit;
++ }
++ *vp++ = '\0';
++
++ *base = vp;
++
++exit: MFREE(osh, flash, NVRAM_SPACE);
++ return err;
++}
++
++/*
++ * Initialize nonvolatile variable table from flash.
+ * Return 0 on success, nonzero on error.
+ */
++static int
++initvars_flash_sb(void *sbh, char **vars, int *count)
++{
++ osl_t *osh = sb_osh(sbh);
++ char devpath[SB_DEVPATH_BUFSZ];
++ char *vp, *base;
++ int err;
++
++ ASSERT(vars);
++ ASSERT(count);
++
++ if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
++ return err;
++
++ base = vp = MALLOC(osh, VARS_MAX);
++ ASSERT(vp);
++ if (!vp)
++ return BCME_NOMEM;
++
++ if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
++ goto err;
++
++ err = initvars_table(osh, base, vp, vars, count);
++
++err: MFREE(osh, base, VARS_MAX);
++ return err;
++}
+
++/*
++ * Initialize nonvolatile variable table from sprom.
++ * Return 0 on success, nonzero on error.
++ */
+static int
-+initvars_srom_pci(void *osh, void *curmap, char **vars, int *count)
++initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
+{
+ uint16 w, b[64];
+ uint8 sromrev;
+ struct ether_addr ea;
+ char eabuf[32];
-+ uint32 bfl;
-+ int c, woff, i;
++ uint32 w32;
++ int woff, i;
+ char *vp, *base;
++ osl_t *osh = sb_osh(sbh);
++ bool flash = FALSE;
++ char name[SB_DEVPATH_BUFSZ+16], *value;
++ char devpath[SB_DEVPATH_BUFSZ];
++ int err;
+
-+ if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE))
-+ return (-1);
-+
-+ /* top word of sprom contains version and crc8 */
-+ sromrev = b[63] & 0xff;
-+ /* bcm4401 sroms misprogrammed */
-+ if (sromrev == 0x10)
-+ sromrev = 1;
-+ if ((sromrev != 1) && (sromrev != 2))
++ /*
++ * Apply CRC over SROM content regardless SROM is present or not,
++ * and use variable <devpath>sromrev's existance in flash to decide
++ * if we should return an error when CRC fails or read SROM variables
++ * from flash.
++ */
++ if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
++ if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
++ return err;
++ sprintf(name, "%ssromrev", devpath);
++ if (!(value = getvar(NULL, name)))
++ return (-1);
++ sromrev = (uint8)bcm_strtoul(value, NULL, 0);
++ flash = TRUE;
++ }
++ /* srom is good */
++ else {
++ /* top word of sprom contains version and crc8 */
++ sromrev = b[63] & 0xff;
++ /* bcm4401 sroms misprogrammed */
++ if (sromrev == 0x10)
++ sromrev = 1;
++ }
++
++ /* srom version check */
++ if (sromrev > 3)
+ return (-2);
+
+ ASSERT(vars);
+
+ base = vp = MALLOC(osh, VARS_MAX);
+ ASSERT(vp);
++ if (!vp)
++ return -2;
+
++ /* read variables from flash */
++ if (flash) {
++ if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
++ goto err;
++ goto done;
++ }
++
+ vp += sprintf(vp, "sromrev=%d", sromrev);
+ vp++;
+
-+ if (sromrev >= 2) {
-+ /* New section takes over the 4th hardware function space */
++ if (sromrev >= 3) {
++ /* New section takes over the 3th hardware function space */
+
-+ /* Word 29 is max power 11a high/low */
-+ w = b[29];
-+ vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
++ /* Words 22+23 are 11a (mid) ofdm power offsets */
++ &nbs
projects / openwrt / svn-archive / archive.git / commitdiff