ar71xx: set MII interface speed from the set_speed callbacks
authorGabor Juhos <juhosg@openwrt.org>
Sun, 13 Nov 2011 11:26:59 +0000 (11:26 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Sun, 13 Nov 2011 11:26:59 +0000 (11:26 +0000)
SVN-Revision: 29013

target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

index b131818454306e84ea5d591661aabace2dc62ea4..be1e603d806bd797519fe0c5fef59995abc984f3 100644 (file)
@@ -206,6 +206,36 @@ static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
        iounmap(base);
 }
 
        iounmap(base);
 }
 
+static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
+{
+       void __iomem *base;
+       unsigned int mii_speed;
+       u32 t;
+
+       switch (speed) {
+       case SPEED_10:
+               mii_speed =  MII_CTRL_SPEED_10;
+               break;
+       case SPEED_100:
+               mii_speed =  MII_CTRL_SPEED_100;
+               break;
+       case SPEED_1000:
+               mii_speed =  MII_CTRL_SPEED_1000;
+               break;
+       default:
+               BUG();
+       }
+
+       base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+       t = __raw_readl(base + reg);
+       t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+       t |= mii_speed  << MII_CTRL_SPEED_SHIFT;
+       __raw_writel(t, base + reg);
+
+       iounmap(base);
+}
+
 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 {
        struct platform_device *mdio_dev;
 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 {
        struct platform_device *mdio_dev;
@@ -321,6 +351,7 @@ static void ar71xx_set_speed_ge0(int speed)
 
        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
                        val, AR71XX_ETH0_PLL_SHIFT);
 
        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
                        val, AR71XX_ETH0_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 }
 
 static void ar71xx_set_speed_ge1(int speed)
 }
 
 static void ar71xx_set_speed_ge1(int speed)
@@ -329,6 +360,7 @@ static void ar71xx_set_speed_ge1(int speed)
 
        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
                         val, AR71XX_ETH1_PLL_SHIFT);
 
        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
                         val, AR71XX_ETH1_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 }
 
 static void ar724x_set_speed_ge0(int speed)
 }
 
 static void ar724x_set_speed_ge0(int speed)
@@ -357,6 +389,7 @@ static void ar91xx_set_speed_ge0(int speed)
 
        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
                         val, AR91XX_ETH0_PLL_SHIFT);
 
        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
                         val, AR91XX_ETH0_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 }
 
 static void ar91xx_set_speed_ge1(int speed)
 }
 
 static void ar91xx_set_speed_ge1(int speed)
@@ -365,6 +398,7 @@ static void ar91xx_set_speed_ge1(int speed)
 
        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
                         val, AR91XX_ETH1_PLL_SHIFT);
 
        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
                         val, AR91XX_ETH1_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 }
 
 static void ar933x_set_speed_ge0(int speed)
 }
 
 static void ar933x_set_speed_ge0(int speed)
index c447e3e8f2188486d75e4deda10c1a330c8a35a1..db5bac7a0189c7526e3dc6dbb7a3c59ca53b5966 100644 (file)
@@ -817,6 +817,11 @@ void ar71xx_flash_release(void);
 #define MII_REG_MII1_CTRL      0x04
 
 #define MII_CTRL_IF_MASK       3
 #define MII_REG_MII1_CTRL      0x04
 
 #define MII_CTRL_IF_MASK       3
+#define MII_CTRL_SPEED_SHIFT   4
+#define MII_CTRL_SPEED_MASK    3
+#define MII_CTRL_SPEED_10      0
+#define MII_CTRL_SPEED_100     1
+#define MII_CTRL_SPEED_1000    2
 
 #define MII0_CTRL_IF_GMII      0
 #define MII0_CTRL_IF_MII       1
 
 #define MII0_CTRL_IF_GMII      0
 #define MII0_CTRL_IF_MII       1
index 9684b623b3b55d5bb1fbf2bd32d384a9259bbacf..5740549c2b316419020ca98d440617495a3e7730 100644 (file)
@@ -533,7 +533,6 @@ void ag71xx_link_adjust(struct ag71xx *ag)
        u32 cfg2;
        u32 ifctl;
        u32 fifo5;
        u32 cfg2;
        u32 ifctl;
        u32 fifo5;
-       u32 mii_speed;
 
        if (!ag->link) {
                ag71xx_hw_stop(ag);
 
        if (!ag->link) {
                ag71xx_hw_stop(ag);
@@ -558,17 +557,14 @@ void ag71xx_link_adjust(struct ag71xx *ag)
 
        switch (ag->speed) {
        case SPEED_1000:
 
        switch (ag->speed) {
        case SPEED_1000:
-               mii_speed =  MII_CTRL_SPEED_1000;
                cfg2 |= MAC_CFG2_IF_1000;
                fifo5 |= FIFO_CFG5_BM;
                break;
        case SPEED_100:
                cfg2 |= MAC_CFG2_IF_1000;
                fifo5 |= FIFO_CFG5_BM;
                break;
        case SPEED_100:
-               mii_speed = MII_CTRL_SPEED_100;
                cfg2 |= MAC_CFG2_IF_10_100;
                ifctl |= MAC_IFCTL_SPEED;
                break;
        case SPEED_10:
                cfg2 |= MAC_CFG2_IF_10_100;
                ifctl |= MAC_IFCTL_SPEED;
                break;
        case SPEED_10:
-               mii_speed = MII_CTRL_SPEED_10;
                cfg2 |= MAC_CFG2_IF_10_100;
                break;
        default:
                cfg2 |= MAC_CFG2_IF_10_100;
                break;
        default:
@@ -586,8 +582,6 @@ void ag71xx_link_adjust(struct ag71xx *ag)
        if (pdata->set_speed)
                pdata->set_speed(ag->speed);
 
        if (pdata->set_speed)
                pdata->set_speed(ag->speed);
 
-       ag71xx_mii_ctrl_set_speed(ag, mii_speed);
-
        ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
        ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
        ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
        ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);