ar71xx: reorganize 4.1 patch directory layout
authorFelix Fietkau <nbd@openwrt.org>
Sun, 19 Jul 2015 17:59:08 +0000 (17:59 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Sun, 19 Jul 2015 17:59:08 +0000 (17:59 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 46430

50 files changed:
target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/102-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch [deleted file]
target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/213-MIPS-ath79-fix-ar933x-wmac-reset.patch [deleted file]
target/linux/ar71xx/patches-4.1/480-ar913x_wmac_external_reset.patch [deleted file]
target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch
target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch
target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch
target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch
target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch
target/linux/ar71xx/patches-4.1/610-MIPS-ath79-openwrt-machines.patch [deleted file]
target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch
target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch
target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch [deleted file]
target/linux/ar71xx/patches-4.1/718-MIPS-ath79-add-EPG5000-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/727-MIPS-ath79-ar934x-wmac-revision.patch [deleted file]
target/linux/ar71xx/patches-4.1/728-MIPS-ath79-fix-restart.patch [deleted file]
target/linux/ar71xx/patches-4.1/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch [deleted file]
target/linux/ar71xx/patches-4.1/736-MIPS-ath79-add-MC-MAC1200R-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/736-MIPS-ath79-fix-chained-irq-disable.patch [deleted file]
target/linux/ar71xx/patches-4.1/737-MIPS-ath79-add-om5p-an-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/738-MIPS-ath79-add-meraki-mr12-mr16-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-irq-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/800-MIPS-ath79-add-RB922GS-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/810-MIPS-ath79-wmac-enable-set-led-pin.patch [deleted file]
target/linux/ar71xx/patches-4.1/811-MIPS-ath79-gpio-enable-set-direction.patch [deleted file]
target/linux/ar71xx/patches-4.1/812-MIPS-ath79-add-ap143-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/901-mdio_bitbang_ignore_ta_value.patch [deleted file]
target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch [new file with mode: 0644]
target/linux/ar71xx/patches-4.1/902-unaligned_access_hacks.patch [deleted file]
target/linux/ar71xx/patches-4.1/903-MIPS-ath79-ubnt-rocket-m-xw-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/904-MIPS-ath79-bitmain-antminer-s1-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/904-MIPS-ath79-ubnt-rocket-m-ti-supprt.patch [deleted file]
target/linux/ar71xx/patches-4.1/904-phy-mdio-bitbang-prevent-rescheduling-during-command.patch [deleted file]
target/linux/ar71xx/patches-4.1/905-MIPS-ath79-bitmain-antminer-s3-support.patch [deleted file]
target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch [new file with mode: 0644]

diff --git a/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch b/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch
new file mode 100644 (file)
index 0000000..79c7ab0
--- /dev/null
@@ -0,0 +1,42 @@
+From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001
+From: Markos Chandras <markos.chandras@imgtec.com>
+Date: Wed, 21 Aug 2013 11:47:22 +0100
+Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable
+
+Fixes the following build error:
+arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
+uninitialized in this function [-Werror=maybe-uninitialized]
+arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
+In file included from arch/mips/ath79/common.c:20:0:
+arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
+arch/mips/include/asm/mach-ath79/ath79.h:139:20:
+error: 'reg' may be used uninitialized in this function
+[-Werror=maybe-uninitialized]
+arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
+
+Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/common.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -75,7 +75,7 @@ void ath79_device_reset_set(u32 mask)
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
+       else
+-              BUG();
++              panic("Reset register not defined for this SOC");
+       spin_lock_irqsave(&ath79_device_reset_lock, flags);
+       t = ath79_reset_rr(reg);
+@@ -103,7 +103,7 @@ void ath79_device_reset_clear(u32 mask)
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
+       else
+-              BUG();
++              panic("Reset register not defined for this SOC");
+       spin_lock_irqsave(&ath79_device_reset_lock, flags);
+       t = ath79_reset_rr(reg);
diff --git a/target/linux/ar71xx/patches-4.1/102-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch b/target/linux/ar71xx/patches-4.1/102-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch
deleted file mode 100644 (file)
index 79c7ab0..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001
-From: Markos Chandras <markos.chandras@imgtec.com>
-Date: Wed, 21 Aug 2013 11:47:22 +0100
-Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable
-
-Fixes the following build error:
-arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
-uninitialized in this function [-Werror=maybe-uninitialized]
-arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
-In file included from arch/mips/ath79/common.c:20:0:
-arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
-arch/mips/include/asm/mach-ath79/ath79.h:139:20:
-error: 'reg' may be used uninitialized in this function
-[-Werror=maybe-uninitialized]
-arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
-
-Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-Acked-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/common.c |    4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -75,7 +75,7 @@ void ath79_device_reset_set(u32 mask)
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-       else
--              BUG();
-+              panic("Reset register not defined for this SOC");
-       spin_lock_irqsave(&ath79_device_reset_lock, flags);
-       t = ath79_reset_rr(reg);
-@@ -103,7 +103,7 @@ void ath79_device_reset_clear(u32 mask)
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-       else
--              BUG();
-+              panic("Reset register not defined for this SOC");
-       spin_lock_irqsave(&ath79_device_reset_lock, flags);
-       t = ath79_reset_rr(reg);
diff --git a/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch
new file mode 100644 (file)
index 0000000..e0821a7
--- /dev/null
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi
+ static int ar933x_wmac_reset(void)
+ {
++      int retries = 20;
++
+       ath79_device_reset_set(AR933X_RESET_WMAC);
+       ath79_device_reset_clear(AR933X_RESET_WMAC);
+-      return 0;
++      while (1) {
++              u32 bootstrap;
++
++              bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++              if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
++                      return 0;
++
++              if (retries-- == 0)
++                      break;
++
++              udelay(10000);
++              retries++;
++      }
++
++      pr_err("ar933x: WMAC reset timed out");
++      return -ETIMEDOUT;
+ }
+ static int ar933x_r1_get_wmac_revision(void)
diff --git a/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch b/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch
new file mode 100644 (file)
index 0000000..9b704a3
--- /dev/null
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac
+       },
+ };
+-static void __init ar913x_wmac_setup(void)
++static int ar913x_wmac_reset(void)
+ {
+       /* reset the WMAC */
+       ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi
+       ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+       mdelay(10);
++      return 0;
++}
++
++static void __init ar913x_wmac_setup(void)
++{
++      ar913x_wmac_reset();
++
+       ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+       ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+       ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
+       ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
++
++      ath79_wmac_data.external_reset = ar913x_wmac_reset;
+ }
diff --git a/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch b/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch
new file mode 100644 (file)
index 0000000..c91ecdf
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -140,6 +140,8 @@ static void ar934x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = false;
+       else
+               ath79_wmac_data.is_clk_25mhz = true;
++
++      ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+ }
+ static void qca955x_wmac_setup(void)
diff --git a/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch b/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch
new file mode 100644 (file)
index 0000000..713a191
--- /dev/null
@@ -0,0 +1,20 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
+ static void ath79_restart(char *command)
+ {
++      local_irq_disable();
+       ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
+       for (;;)
+               if (cpu_wait)
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -132,6 +132,7 @@ static inline u32 ath79_pll_rr(unsigned
+ static inline void ath79_reset_wr(unsigned reg, u32 val)
+ {
+       __raw_writel(val, ath79_reset_base + reg);
++      (void) __raw_readl(ath79_reset_base + reg); /* flush */
+ }
+ static inline u32 ath79_reset_rr(unsigned reg)
diff --git a/target/linux/ar71xx/patches-4.1/213-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-4.1/213-MIPS-ath79-fix-ar933x-wmac-reset.patch
deleted file mode 100644 (file)
index e0821a7..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi
- static int ar933x_wmac_reset(void)
- {
-+      int retries = 20;
-+
-       ath79_device_reset_set(AR933X_RESET_WMAC);
-       ath79_device_reset_clear(AR933X_RESET_WMAC);
--      return 0;
-+      while (1) {
-+              u32 bootstrap;
-+
-+              bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
-+              if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
-+                      return 0;
-+
-+              if (retries-- == 0)
-+                      break;
-+
-+              udelay(10000);
-+              retries++;
-+      }
-+
-+      pr_err("ar933x: WMAC reset timed out");
-+      return -ETIMEDOUT;
- }
- static int ar933x_r1_get_wmac_revision(void)
diff --git a/target/linux/ar71xx/patches-4.1/480-ar913x_wmac_external_reset.patch b/target/linux/ar71xx/patches-4.1/480-ar913x_wmac_external_reset.patch
deleted file mode 100644 (file)
index 9b704a3..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac
-       },
- };
--static void __init ar913x_wmac_setup(void)
-+static int ar913x_wmac_reset(void)
- {
-       /* reset the WMAC */
-       ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi
-       ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-       mdelay(10);
-+      return 0;
-+}
-+
-+static void __init ar913x_wmac_setup(void)
-+{
-+      ar913x_wmac_reset();
-+
-       ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
-       ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-       ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-       ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
-+
-+      ath79_wmac_data.external_reset = ar913x_wmac_reset;
- }
index b41c733..fdf353c 100644 (file)
@@ -16,7 +16,7 @@
  static struct ath9k_platform_data ath79_wmac_data;
  
  static struct resource ath79_wmac_resources[] = {
-@@ -160,7 +162,7 @@ static void qca955x_wmac_setup(void)
+@@ -162,7 +164,7 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = true;
  }
  
@@ -25,7 +25,7 @@
  {
        if (soc_is_ar913x())
                ar913x_wmac_setup();
-@@ -177,5 +179,10 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -179,5 +181,10 @@ void __init ath79_register_wmac(u8 *cal_
                memcpy(ath79_wmac_data.eeprom_data, cal_data,
                       sizeof(ath79_wmac_data.eeprom_data));
  
index 06f7902..108f659 100644 (file)
@@ -27,7 +27,7 @@
 +
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -143,4 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -144,4 +144,7 @@ static inline u32 ath79_reset_rr(unsigne
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
  
index 024a85d..8748aa3 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -142,6 +142,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -143,6 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
  
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
index ca7a890..98ef1e1 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -234,6 +234,8 @@ void __init plat_time_init(void)
+@@ -235,6 +235,8 @@ void __init plat_time_init(void)
        mips_hpt_frequency = cpu_clk_rate / 2;
  }
  
index 74928e6..a29c7be 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -189,3 +189,9 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -191,3 +191,9 @@ void __init ath79_register_wmac(u8 *cal_
  
        platform_device_register(&ath79_wmac_device);
  }
index 5ff1cb8..e030d7c 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -165,6 +165,137 @@ static void qca955x_wmac_setup(void)
+@@ -167,6 +167,137 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = true;
  }
  
index 7b4b6ef..31f885f 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -296,6 +296,16 @@ bool __init ar93xx_wmac_read_mac_address
+@@ -298,6 +298,16 @@ bool __init ar93xx_wmac_read_mac_address
        return ret;
  }
  
index 7803513..24b0f27 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/mach-ubnt-xm.c
 +++ b/arch/mips/ath79/mach-ubnt-xm.c
-@@ -12,16 +12,24 @@
+@@ -12,16 +12,26 @@
  
  #include <linux/init.h>
  #include <linux/pci.h>
@@ -13,6 +13,8 @@
  #include <asm/mach-ath79/irq.h>
 +#include <asm/mach-ath79/ar71xx_regs.h>
  
++#include <linux/platform_data/phy-at803x.h>
++
 +#include "common.h"
  #include "dev-ap9x-pci.h"
 +#include "dev-eth.h"
@@ -26,7 +28,7 @@
  
  #define UBNT_XM_GPIO_LED_L1           0
  #define UBNT_XM_GPIO_LED_L2           1
-@@ -37,19 +45,19 @@
+@@ -37,19 +47,19 @@
  
  static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
        {
@@ -50,7 +52,7 @@
                .gpio           = UBNT_XM_GPIO_LED_L4,
                .active_low     = 0,
        },
-@@ -66,9 +74,13 @@ static struct gpio_keys_button ubnt_xm_g
+@@ -66,9 +76,13 @@ static struct gpio_keys_button ubnt_xm_g
        }
  };
  
@@ -64,7 +66,7 @@
  
        ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
                                 ubnt_xm_leds_gpio);
-@@ -79,9 +91,428 @@ static void __init ubnt_xm_init(void)
+@@ -79,9 +93,552 @@ static void __init ubnt_xm_init(void)
  
        ath79_register_m25p80(NULL);
        ap91_pci_init(eeprom, NULL);
 +      },
 +};
 +
++#define UBNT_ROCKET_TI_GPIO_LED_L1    16
++#define UBNT_ROCKET_TI_GPIO_LED_L2    17
++#define UBNT_ROCKET_TI_GPIO_LED_L3    18
++#define UBNT_ROCKET_TI_GPIO_LED_L4    19
++#define UBNT_ROCKET_TI_GPIO_LED_L5    20
++#define UBNT_ROCKET_TI_GPIO_LED_L6    21
++static struct gpio_led ubnt_rocket_ti_leds_gpio[] __initdata = {
++      {
++              .name           = "ubnt:green:link1",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L1,
++              .active_low     = 1,
++      }, {
++              .name           = "ubnt:green:link2",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L2,
++              .active_low     = 1,
++      }, {
++              .name           = "ubnt:green:link3",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L3,
++              .active_low     = 1,
++      }, {
++              .name           = "ubnt:green:link4",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L4,
++              .active_low     = 0,
++      }, {
++              .name           = "ubnt:green:link5",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L5,
++              .active_low     = 0,
++      }, {
++              .name           = "ubnt:green:link6",
++              .gpio           = UBNT_ROCKET_TI_GPIO_LED_L6,
++              .active_low     = 0,
++      },
++};
++
 +static void __init ubnt_xw_init(void)
 +{
 +      u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
 +      ath79_register_eth(0);
 +}
 +
++static void __init ubnt_rocket_m_xw_setup(void)
++{
++      u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
++
++      ath79_register_m25p80(NULL);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio),
++                               ubnt_xw_leds_gpio);
++      ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++
++      ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
++      ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
++
++      ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
++      ath79_init_mac(ath79_eth0_data.mac_addr,
++                     eeprom + UAP_PRO_MAC0_OFFSET, 0);
++
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++
++      ath79_register_mdio(0, ~BIT(4));
++      ath79_eth0_data.phy_mask = BIT(4);
++      ath79_eth0_pll_data.pll_1000 = 0x06000000;
++      ath79_register_eth(0);
++}
++
++static struct at803x_platform_data ubnt_rocket_m_ti_at803_data = {
++      .disable_smarteee = 1,
++      .enable_rgmii_rx_delay = 1,
++      .enable_rgmii_tx_delay = 1,
++};
++static struct mdio_board_info ubnt_rocket_m_ti_mdio_info[] = {
++        {
++                .bus_id = "ag71xx-mdio.0",
++                .phy_addr = 4,
++                .platform_data = &ubnt_rocket_m_ti_at803_data,
++        },
++};
++
++static void __init ubnt_rocket_m_ti_setup(void)
++{
++      u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
++
++      ath79_register_m25p80(NULL);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rocket_ti_leds_gpio),
++                               ubnt_rocket_ti_leds_gpio);
++      ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++
++      ap91_pci_init(eeprom + 0x1000, NULL);
++
++      ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
++      ath79_setup_ar934x_eth_rx_delay(3, 3);
++      ath79_init_mac(ath79_eth0_data.mac_addr,
++                     eeprom + UAP_PRO_MAC0_OFFSET, 0);
++      ath79_init_mac(ath79_eth1_data.mac_addr,
++                     eeprom + UAP_PRO_MAC1_OFFSET, 0);
++
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++      ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
++
++      mdiobus_register_board_info(ubnt_rocket_m_ti_mdio_info,
++                      ARRAY_SIZE(ubnt_rocket_m_ti_mdio_info));
++      ath79_register_mdio(0, 0x0);
++
++
++      ath79_eth0_data.phy_mask = BIT(4);
++      /* read out from vendor */
++      ath79_eth0_pll_data.pll_1000 = 0x2000000;
++      ath79_eth0_pll_data.pll_10 = 0x1313;
++      ath79_register_eth(0);
++
++      ath79_register_mdio(1, 0x0);
++      ath79_eth1_data.phy_mask = BIT(3);
++      ath79_register_eth(1);
++}
++
++
 +MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M_XW, "UBNT-NM-XW", "Ubiquiti Nanostation M XW",
 +           ubnt_nano_m_xw_setup);
 +
 +MIPS_MACHINE(ATH79_MACH_UBNT_LOCO_M_XW, "UBNT-LOCO-XW", "Ubiquiti Loco M XW",
 +           ubnt_loco_m_xw_setup);
 +
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_XW, "UBNT-RM-XW", "Ubiquiti Rocket M XW",
++           ubnt_rocket_m_xw_setup);
++
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_TI, "UBNT-RM-TI", "Ubiquiti Rocket M TI",
++           ubnt_rocket_m_ti_setup);
++
 +static struct gpio_led ubnt_airgateway_gpio_leds[] __initdata = {
 +      {
 +              .name      = "ubnt:blue:wlan",
          Ubiquiti Networks XM (rev 1.0) board.
 --- a/arch/mips/ath79/machtypes.h
 +++ b/arch/mips/ath79/machtypes.h
-@@ -22,6 +22,13 @@ enum ath79_mach_type {
+@@ -22,6 +22,15 @@ enum ath79_mach_type {
        ATH79_MACH_AP81,                /* Atheros AP81 reference board */
        ATH79_MACH_DB120,               /* Atheros DB120 reference board */
        ATH79_MACH_PB44,                /* Atheros PB44 reference board */
 +      ATH79_MACH_UBNT_BULLET_M,       /* Ubiquiti Bullet M */
 +      ATH79_MACH_UBNT_NANO_M,         /* Ubiquiti NanoStation M */
 +      ATH79_MACH_UBNT_ROCKET_M,       /* Ubiquiti Rocket M */
++      ATH79_MACH_UBNT_ROCKET_M_XW,    /* Ubiquiti Rocket M XW*/
++      ATH79_MACH_UBNT_ROCKET_M_TI,    /* Ubiquiti Rocket M TI*/
 +      ATH79_MACH_UBNT_UAP_PRO,        /* Ubiquiti UniFi AP Pro */
 +      ATH79_MACH_UBNT_UNIFI,          /* Ubiquiti Unifi */
 +      ATH79_MACH_UBNT_UNIFI_OUTDOOR,  /* Ubiquiti UnifiAP Outdoor */
diff --git a/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-openwrt-machines.patch
deleted file mode 100644 (file)
index 8e0d194..0000000
+++ /dev/null
@@ -1,1595 +0,0 @@
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -16,22 +16,195 @@
- enum ath79_mach_type {
-       ATH79_MACH_GENERIC = 0,
-+      ATH79_MACH_ALFA_AP96,           /* ALFA Network AP96 board */
-+      ATH79_MACH_ALFA_NX,             /* ALFA Network N2/N5 board */
-+      ATH79_MACH_ALL0258N,            /* Allnet ALL0258N */
-+      ATH79_MACH_ALL0305,             /* Allnet ALL0305 */
-+      ATH79_MACH_ALL0315N,            /* Allnet ALL0315N */
-+      ATH79_MACH_AP113,               /* Atheros AP113 reference board */
-       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
-       ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
-+      ATH79_MACH_AP132,               /* Atheros AP132 reference board */
-       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
-       ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
-       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
-       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
-+      ATH79_MACH_AP83,                /* Atheros AP83 */
-+      ATH79_MACH_AP96,                /* Atheros AP96 */
-+      ATH79_MACH_ARCHER_C5,           /* TP-LINK Archer C5 board */
-+      ATH79_MACH_ARCHER_C7,           /* TP-LINK Archer C7 board */
-+      ATH79_MACH_AW_NR580,            /* AzureWave AW-NR580 */
-+      ATH79_MACH_BHU_BXU2000N2_A1,    /* BHU BXU2000n-2 A1 */
-+      ATH79_MACH_CAP4200AG,           /* Senao CAP4200AG */
-+      ATH79_MACH_CARAMBOLA2,          /* 8devices Carambola2 */
-+      ATH79_MACH_CPE510,              /* TP-LINK CPE510 */
-       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
-       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
-+      ATH79_MACH_DGL_5500_A1,         /* D-link DGL-5500 rev. A1 */
-+      ATH79_MACH_DHP_1565_A1,         /* D-Link DHP-1565 rev. A1 */
-+      ATH79_MACH_DIR_505_A1,          /* D-Link DIR-505 rev. A1 */
-+      ATH79_MACH_DIR_600_A1,          /* D-Link DIR-600 rev. A1 */
-+      ATH79_MACH_DIR_615_C1,          /* D-Link DIR-615 rev. C1 */
-+      ATH79_MACH_DIR_615_E1,          /* D-Link DIR-615 rev. E1 */
-+      ATH79_MACH_DIR_615_E4,          /* D-Link DIR-615 rev. E4 */
-+      ATH79_MACH_DIR_615_I1,          /* D-Link DIR-615 rev. I1 */
-+      ATH79_MACH_DIR_825_B1,          /* D-Link DIR-825 rev. B1 */
-+      ATH79_MACH_DIR_825_C1,          /* D-Link DIR-825 rev. C1 */
-+      ATH79_MACH_DIR_835_A1,          /* D-Link DIR-835 rev. A1 */
-+      ATH79_MACH_DLAN_PRO_500_WP,     /* devolo dLAN pro 500 Wireless+ */
-+      ATH79_MACH_DLAN_PRO_1200_AC,    /* devolo dLAN pro 1200+ WiFi ac*/
-+      ATH79_MACH_DRAGINO2,            /* Dragino Version 2 */
-+      ATH79_MACH_ESR900,              /* EnGenius ESR900 */
-+      ATH79_MACH_EW_DORIN,            /* embedded wireless Dorin Platform */
-+      ATH79_MACH_EW_DORIN_ROUTER,     /* embedded wireless Dorin Router Platform */
-+      ATH79_MACH_EAP300V2,            /* EnGenius EAP300 v2 */
-+      ATH79_MACH_EAP7660D,            /* Senao EAP7660D */
-+      ATH79_MACH_EL_M150,             /* EasyLink EL-M150 */
-+      ATH79_MACH_EL_MINI,             /* EasyLink EL-MINI */
-+      ATH79_MACH_ESR1750,             /* EnGenius ESR1750 */
-+      ATH79_MACH_F9K1115V2,           /* Belkin AC1750DB */
-+      ATH79_MACH_GL_INET,             /* GL-CONNECT GL-INET */
-+      ATH79_MACH_GS_OOLITE,           /* GS OOLITE V1.0 */
-+      ATH79_MACH_HIWIFI_HC6361,       /* HiWiFi HC6361 */
-+      ATH79_MACH_JA76PF,              /* jjPlus JA76PF */
-+      ATH79_MACH_JA76PF2,             /* jjPlus JA76PF2 */
-+      ATH79_MACH_JWAP003,             /* jjPlus JWAP003 */
-+      ATH79_MACH_HORNET_UB,           /* ALFA Networks Hornet-UB */
-+      ATH79_MACH_MR600V2,             /* OpenMesh MR600v2 */
-+      ATH79_MACH_MR600,               /* OpenMesh MR600 */
-+      ATH79_MACH_MR900,               /* OpenMesh MR900 */
-+      ATH79_MACH_MR900v2,             /* OpenMesh MR900v2 */
-+      ATH79_MACH_MYNET_N600,          /* WD My Net N600 */
-+      ATH79_MACH_MYNET_N750,          /* WD My Net N750 */
-+      ATH79_MACH_MYNET_REXT,          /* WD My Net Wi-Fi Range Extender */
-+      ATH79_MACH_MZK_W04NU,           /* Planex MZK-W04NU */
-+      ATH79_MACH_MZK_W300NH,          /* Planex MZK-W300NH */
-+      ATH79_MACH_NBG460N,             /* Zyxel NBG460N/550N/550NH */
-+      ATH79_MACH_NBG6716,             /* Zyxel NBG6716 */
-+      ATH79_MACH_OM2P_HSv2,           /* OpenMesh OM2P-HSv2 */
-+      ATH79_MACH_OM2P_HS,             /* OpenMesh OM2P-HS */
-+      ATH79_MACH_OM2P_LC,             /* OpenMesh OM2P-LC */
-+      ATH79_MACH_OM2Pv2,              /* OpenMesh OM2Pv2 */
-+      ATH79_MACH_OM2P,                /* OpenMesh OM2P */
-+      ATH79_MACH_OM5P,                /* OpenMesh OM5P */
-+      ATH79_MACH_PB42,                /* Atheros PB42 */
-+      ATH79_MACH_PB92,                /* Atheros PB92 */
-+      ATH79_MACH_QIHOO_C301,          /* Qihoo 360 C301 */
-+      ATH79_MACH_R6100,               /* NETGEAR R6100 */
-+      ATH79_MACH_RB_411,              /* MikroTik RouterBOARD 411/411A/411AH */
-+      ATH79_MACH_RB_411U,             /* MikroTik RouterBOARD 411U */
-+      ATH79_MACH_RB_433,              /* MikroTik RouterBOARD 433/433AH */
-+      ATH79_MACH_RB_433U,             /* MikroTik RouterBOARD 433UAH */
-+      ATH79_MACH_RB_435G,             /* MikroTik RouterBOARD 435G */
-+      ATH79_MACH_RB_450G,             /* MikroTik RouterBOARD 450G */
-+      ATH79_MACH_RB_450,              /* MikroTik RouterBOARD 450 */
-+      ATH79_MACH_RB_493,              /* Mikrotik RouterBOARD 493/493AH */
-+      ATH79_MACH_RB_493G,             /* Mikrotik RouterBOARD 493G */
-+      ATH79_MACH_RB_711GR100,         /* Mikrotik RouterBOARD 911/912 boards */
-+      ATH79_MACH_RB_750,              /* MikroTik RouterBOARD 750 */
-+      ATH79_MACH_RB_750G_R3,          /* MikroTik RouterBOARD 750GL */
-+      ATH79_MACH_RB_751,              /* MikroTik RouterBOARD 751 */
-+      ATH79_MACH_RB_751G,             /* Mikrotik RouterBOARD 751G */
-+      ATH79_MACH_RB_951G,             /* Mikrotik RouterBOARD 951G */
-+      ATH79_MACH_RB_951U,             /* Mikrotik RouterBOARD 951Ui-2HnD */
-+      ATH79_MACH_RB_2011G,            /* Mikrotik RouterBOARD 2011UAS-2HnD */
-+      ATH79_MACH_RB_2011L,            /* Mikrotik RouterBOARD 2011L */
-+      ATH79_MACH_RB_2011US,           /* Mikrotik RouterBOARD 2011UAS */
-+      ATH79_MACH_RB_2011R5,           /* Mikrotik RouterBOARD 2011UiAS(-2Hnd) */
-+      ATH79_MACH_RB_SXTLITE2ND,       /* Mikrotik RouterBOARD SXT Lite 2nD */
-+      ATH79_MACH_RB_SXTLITE5ND,       /* Mikrotik RouterBOARD SXT Lite 5nD */
-+      ATH79_MACH_RW2458N,             /* Redwave RW2458N */
-+      ATH79_MACH_SMART_300,           /* NC-LINK SMART-300 */
-+      ATH79_MACH_TEW_632BRP,          /* TRENDnet TEW-632BRP */
-+      ATH79_MACH_TEW_673GRU,          /* TRENDnet TEW-673GRU */
-+      ATH79_MACH_TEW_712BR,           /* TRENDnet TEW-712BR */
-+      ATH79_MACH_TEW_732BR,           /* TRENDnet TEW-732BR */
-+      ATH79_MACH_TL_MR10U,            /* TP-LINK TL-MR10U */
-+      ATH79_MACH_TL_MR11U,            /* TP-LINK TL-MR11U */
-+      ATH79_MACH_TL_MR13U,            /* TP-LINK TL-MR13U */
-+      ATH79_MACH_TL_MR3020,           /* TP-LINK TL-MR3020 */
-+      ATH79_MACH_TL_MR3040,           /* TP-LINK TL-MR3040 */
-+      ATH79_MACH_TL_MR3040_V2,        /* TP-LINK TL-MR3040 v2 */
-+      ATH79_MACH_TL_MR3220,           /* TP-LINK TL-MR3220 */
-+      ATH79_MACH_TL_MR3220_V2,        /* TP-LINK TL-MR3220 v2 */
-+      ATH79_MACH_TL_MR3420,           /* TP-LINK TL-MR3420 */
-+      ATH79_MACH_TL_MR3420_V2,        /* TP-LINK TL-MR3420 v2 */
-+      ATH79_MACH_TL_WA701ND_V2,       /* TP-LINK TL-WA701ND v2 */
-+      ATH79_MACH_TL_WA750RE,          /* TP-LINK TL-WA750RE */
-+       ATH79_MACH_TL_WA7210N_V2,       /* TP-LINK TL-WA7210N v2 */
-+      ATH79_MACH_TL_WA7510N_V1,       /* TP-LINK TL-WA7510N v1*/
-+      ATH79_MACH_TL_WA850RE,          /* TP-LINK TL-WA850RE */
-+      ATH79_MACH_TL_WA860RE,          /* TP-LINK TL-WA860RE */
-+      ATH79_MACH_TL_WA801ND_V2,       /* TP-LINK TL-WA801ND v2 */
-+      ATH79_MACH_TL_WA830RE_V2,       /* TP-LINK TL-WA830RE v2 */
-+      ATH79_MACH_TL_WA901ND,          /* TP-LINK TL-WA901ND */
-+      ATH79_MACH_TL_WA901ND_V2,       /* TP-LINK TL-WA901ND v2 */
-+      ATH79_MACH_TL_WA901ND_V3,       /* TP-LINK TL-WA901ND v3 */
-+      ATH79_MACH_TL_WDR3500,          /* TP-LINK TL-WDR3500 */
-+      ATH79_MACH_TL_WDR4300,          /* TP-LINK TL-WDR4300 */
-+      ATH79_MACH_TL_WDR4900_V2,       /* TP-LINK TL-WDR4900 v2 */
-+      ATH79_MACH_TL_WR1041N_V2,       /* TP-LINK TL-WR1041N v2 */
-+      ATH79_MACH_TL_WR1043ND,         /* TP-LINK TL-WR1043ND */
-+      ATH79_MACH_TL_WR1043ND_V2,      /* TP-LINK TL-WR1043ND v2 */
-+      ATH79_MACH_TL_WR2543N,          /* TP-LINK TL-WR2543N/ND */
-+      ATH79_MACH_TL_WR703N,           /* TP-LINK TL-WR703N */
-+      ATH79_MACH_TL_WR710N,           /* TP-LINK TL-WR710N */
-+      ATH79_MACH_TL_WR720N_V3,        /* TP-LINK TL-WR720N v3/v4 */
-+      ATH79_MACH_TL_WR741ND,          /* TP-LINK TL-WR741ND */
-+      ATH79_MACH_TL_WR741ND_V4,       /* TP-LINK TL-WR741ND  v4*/
-+      ATH79_MACH_TL_WR841N_V1,        /* TP-LINK TL-WR841N v1 */
-+      ATH79_MACH_TL_WR841N_V7,        /* TP-LINK TL-WR841N/ND v7 */
-+      ATH79_MACH_TL_WR841N_V8,        /* TP-LINK TL-WR841N/ND v8 */
-+      ATH79_MACH_TL_WR841N_V9,        /* TP-LINK TL-WR841N/ND v9 */
-+      ATH79_MACH_TL_WR842N_V2,        /* TP-LINK TL-WR842N/ND v2 */
-+      ATH79_MACH_TL_WR941ND,          /* TP-LINK TL-WR941ND */
-+      ATH79_MACH_TL_WR941ND_V5,       /* TP-LINK TL-WR941ND v5 */
-+      ATH79_MACH_TUBE2H,              /* Alfa Network Tube2H */
-+      ATH79_MACH_UBNT_AIRGW,          /* Ubiquiti AirGateway */
-       ATH79_MACH_UBNT_AIRROUTER,      /* Ubiquiti AirRouter */
-       ATH79_MACH_UBNT_BULLET_M,       /* Ubiquiti Bullet M */
-+      ATH79_MACH_UBNT_LOCO_M_XW,      /* Ubiquiti Loco M XW */
-+      ATH79_MACH_UBNT_LSSR71,         /* Ubiquiti LS-SR71 */
-+      ATH79_MACH_UBNT_LSX,            /* Ubiquiti LSX */
-       ATH79_MACH_UBNT_NANO_M,         /* Ubiquiti NanoStation M */
-+      ATH79_MACH_UBNT_NANO_M_XW,      /* Ubiquiti NanoStation M XW */
-       ATH79_MACH_UBNT_ROCKET_M,       /* Ubiquiti Rocket M */
-+      ATH79_MACH_UBNT_RSPRO,          /* Ubiquiti RouterStation Pro */
-+      ATH79_MACH_UBNT_RS,             /* Ubiquiti RouterStation */
-       ATH79_MACH_UBNT_UAP_PRO,        /* Ubiquiti UniFi AP Pro */
-       ATH79_MACH_UBNT_UNIFI,          /* Ubiquiti Unifi */
-       ATH79_MACH_UBNT_UNIFI_OUTDOOR,  /* Ubiquiti UnifiAP Outdoor */
-+      ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */
-       ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
-+      ATH79_MACH_WHR_G301N,           /* Buffalo WHR-G301N */
-+      ATH79_MACH_WHR_HP_G300N,        /* Buffalo WHR-HP-G300N */
-+      ATH79_MACH_WHR_HP_GN,           /* Buffalo WHR-HP-GN */
-+      ATH79_MACH_WLAE_AG300N,         /* Buffalo WLAE-AG300N */
-+      ATH79_MACH_WLR8100,             /* SITECOM WLR-8100 */
-+      ATH79_MACH_WNDAP360,            /* NETGEAR WNDAP360 */
-+      ATH79_MACH_WNDR3700,            /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
-+      ATH79_MACH_WNDR3700_V4,         /* NETGEAR WNDR3700v4 */
-+      ATH79_MACH_WNDR4300,            /* NETGEAR WNDR4300 */
-+      ATH79_MACH_WNR2000,             /* NETGEAR WNR2000 */
-+      ATH79_MACH_WNR2000_V3,          /* NETGEAR WNR2000 v3 */
-+      ATH79_MACH_WNR2000_V4,          /* NETGEAR WNR2000 v4 */
-+      ATH79_MACH_WNR2200,             /* NETGEAR WNR2200 */
-+      ATH79_MACH_WNR612_V2,           /* NETGEAR WNR612 v2 */
-+      ATH79_MACH_WNR1000_V2,          /* NETGEAR WNR1000 v2 */
-+      ATH79_MACH_WP543,               /* Compex WP543 */
-+      ATH79_MACH_WPE72,               /* Compex WPE72 */
-+      ATH79_MACH_WPJ344,              /* Compex WPJ344 */
-+      ATH79_MACH_WPJ531,              /* Compex WPJ531 */
-+      ATH79_MACH_WPJ558,              /* Compex WPJ558 */
-+      ATH79_MACH_WRT160NL,            /* Linksys WRT160NL */
-+      ATH79_MACH_WRT400N,             /* Linksys WRT400N */
-+      ATH79_MACH_WZR_HP_AG300H,       /* Buffalo WZR-HP-AG300H */
-+      ATH79_MACH_WZR_HP_G300NH,       /* Buffalo WZR-HP-G300NH */
-+      ATH79_MACH_WZR_HP_G300NH2,      /* Buffalo WZR-HP-G300NH2 */
-+      ATH79_MACH_WZR_HP_G450H,        /* Buffalo WZR-HP-G450H */
-+      ATH79_MACH_WZR_450HP2,          /* Buffalo WZR-450HP2 */
-+      ATH79_MACH_ZCN_1523H_2,         /* Zcomax ZCN-1523H-2-xx */
-+      ATH79_MACH_ZCN_1523H_5,         /* Zcomax ZCN-1523H-5-xx */
- };
- #endif /* _ATH79_MACHTYPE_H */
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -2,6 +2,70 @@ if ATH79
- menu "Atheros AR71XX/AR724X/AR913X machine selection"
-+config ATH79_MACH_ALFA_AP96
-+      bool "ALFA Network AP96 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_HORNET_UB
-+      bool "ALFA Network Hornet-UB board support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_ALFA_NX
-+      bool "ALFA Network N2/N5 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TUBE2H
-+      bool "ALFA Network Tube2H board support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_ALL0258N
-+      bool "Allnet ALL0258N support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_ALL0315N
-+      bool "Allnet ALL0315N support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_AP113
-+      bool "Atheros AP113 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_PB9X_PCI if PCI
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_ETH
-+
- config ATH79_MACH_AP121
-       bool "Atheros AP121 reference board"
-       select SOC_AR933X
-@@ -11,62 +75,1031 @@ config ATH79_MACH_AP121
-       select ATH79_DEV_M25P80
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
--      help
--        Say 'Y' here if you want your kernel to support the
--        Atheros AP121 reference board.
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros AP121 reference board.
-+
-+config ATH79_MACH_AP132
-+      bool "Atheros AP132 reference board"
-+      select SOC_QCA955X
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros AP132 reference boards.
-+
-+config ATH79_MACH_AP136
-+      bool "Atheros AP136/AP135 reference board"
-+      select SOC_QCA955X
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros AP136 or AP135 reference boards.
-+
-+config ATH79_MACH_AP81
-+      bool "Atheros AP81 reference board"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros AP81 reference board.
-+
-+config ATH79_MACH_AP83
-+      bool "Atheros AP83 board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_AP96
-+      bool "Atheros AP96 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_DB120
-+      bool "Atheros DB120 reference board"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros DB120 reference board.
-+
-+config ATH79_MACH_PB42
-+      bool "Atheros PB42 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_PB44
-+      bool "Atheros PB44 reference board"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_SPI
-+      select ATH79_DEV_USB
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros PB44 reference board.
-+
-+config ATH79_MACH_PB92
-+      bool "Atheros PB92 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_PB9X_PCI if PCI
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_AW_NR580
-+      bool "AzureWave AW-NR580 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_F9K1115V2
-+      bool "Belkin AC1750DB board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_ESR1750
-+      bool "EnGenius ESR1750 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WHR_HP_G300N
-+      bool "Buffalo WHR-HP-G300N board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_WLAE_AG300N
-+      bool "Buffalo WLAE-AG300N board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_WLR8100
-+      bool "Sitecom WLR-8100 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WZR_HP_AG300H
-+      bool "Buffalo WZR-HP-AG300H board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WZR_HP_G300NH
-+      bool "Buffalo WZR-HP-G300NH board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      select RTL8366_SMI
-+
-+config ATH79_MACH_WZR_HP_G300NH2
-+      bool "Buffalo WZR-HP-G300NH2 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WZR_HP_G450H
-+      bool "Buffalo WZR-HP-G450H board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WZR_450HP2
-+      bool "Buffalo WZR-450HP2 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WP543
-+      bool "Compex WP543/WPJ543 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select MYLOADER
-+
-+config ATH79_MACH_WPE72
-+      bool "Compex WPE72/WPE72NX board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select MYLOADER
-+
-+config ATH79_MACH_WPJ344
-+      bool "Compex WPJ344 board support"
-+      select SOC_AS934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WPJ531
-+       bool "Compex WPJ531 board support"
-+       select SOC_QCA953X
-+       select ATH79_DEV_ETH
-+       select ATH79_DEV_GPIO_BUTTONS
-+       select ATH79_DEV_LEDS_GPIO
-+       select ATH79_DEV_M25P80
-+       select ATH79_DEV_USB
-+       select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WPJ558
-+      bool "Compex WPJ558 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_DGL_5500_A1
-+      bool "D-Link DGL-5500 A1 support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_DHP_1565_A1
-+      bool "D-Link DHP-1565 rev. A1 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_DIR_505_A1
-+      bool "D-Link DIR-505-A1 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_600_A1
-+      bool "D-Link DIR-600 A1/DIR-615 E1/DIR-615 E4 support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_615_C1
-+      bool "D-Link DIR-615 rev. C1 support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_615_I1
-+      bool "D-Link DIR-615 rev. I1 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_DIR_825_B1
-+      bool "D-Link DIR-825 rev. B1 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_DIR_825_C1
-+      bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_DLAN_PRO_500_WP
-+      bool "devolo dLAN pro 500 Wireless+ support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_SPI
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_DLAN_PRO_1200_AC
-+      bool "devolo dLAN pro 1200+ WiFi ac support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_SPI
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_DRAGINO2
-+      bool "DRAGINO V2 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_ESR900
-+      bool "EnGenius ESR900 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_EW_DORIN
-+      bool "embedded wireless Dorin Platform support"
-+      select SOC_AR933X
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_ETH
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Dorin Platform from www.80211.de .
-+
-+config ATH79_MACH_EL_M150
-+      bool "EasyLink EL-M150 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_EL_MINI
-+      bool "EasyLink EL-MINI support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_GL_INET
-+      bool "GL-INET support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_EAP300V2
-+      bool "EnGenius EAP300 v2 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_GS_OOLITE
-+       bool "GS Oolite V1 support"
-+       select SOC_AR933X
-+       select ARH79_DEV_ETH
-+       select ARH79_DEV_GPIO_BUTTONS
-+       select ATH79_DEV_LEDS_GPIO
-+       select ATH79_DEV_M25P80
-+       select ATH79_DEV_USB
-+       select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_HIWIFI_HC6361
-+      bool "HiWiFi HC6361 board support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_JA76PF
-+      bool "jjPlus JA76PF board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_JWAP003
-+      bool "jjPlus JWAP003 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WRT160NL
-+      bool "Linksys WRT160NL board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_WRT400N
-+      bool "Linksys WRT400N board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_R6100
-+      bool "NETGEAR R6100 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_RB4XX
-+      bool "MikroTik RouterBOARD 4xx series support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_RB750
-+      bool "MikroTik RouterBOARD 750 support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_USB
-+      select ATH79_ROUTERBOOT
-+
-+config ATH79_MACH_RB91X
-+      bool "MikroTik RouterBOARD 91X support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_SPI
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_USB
-+      select ATH79_ROUTERBOOT
-+
-+config ATH79_MACH_RB95X
-+       bool "MikroTik RouterBOARD 95X support"
-+       select SOC_AR934X
-+       select ATH79_DEV_ETH
-+       select ATH79_DEV_NFC
-+       select ATH79_DEV_WMAC
-+       select ATH79_DEV_USB
-+       select ATH79_ROUTERBOOT
-+
-+config ATH79_MACH_RB2011
-+      bool "MikroTik RouterBOARD 2011 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      select ATH79_ROUTERBOOT
-+
-+config ATH79_MACH_RBSXTLITE
-+      bool "MikroTik RouterBOARD SXT Lite"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_WMAC
-+      select ATH79_ROUTERBOOT
-+
-+config ATH79_MACH_SMART_300
-+      bool "NC-LINK SMART-300 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WNDAP360
-+      bool "NETGEAR WNDAP360 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_WNDR3700
-+      bool "NETGEAR WNDR3700 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WNDR4300
-+      bool "NETGEAR WNDR3700v4/WNDR4300 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WNR2000
-+      bool "NETGEAR WNR2000 board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_WNR2000_V3
-+      bool "NETGEAR WNR2000 V3/WNR612 v2/WNR1000 v2 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+      config ATH79_MACH_WNR2200
-+      bool "NETGEAR WNR2200 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_WNR2000_V4
-+      bool "NETGEAR WNR2000 V4"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_OM2P
-+      bool "OpenMesh OM2P board support"
-+      select SOC_AR724X
-+      select SOC_AR933X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_OM5P
-+      bool "OpenMesh OM5P board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MR600
-+      bool "OpenMesh MR600 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MZK_W04NU
-+      bool "Planex MZK-W04NU board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MZK_W300NH
-+      bool "Planex MZK-W300NH board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_RW2458N
-+      bool "Redwave RW2458N board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_CAP4200AG
-+      bool "Senao CAP4200AG support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MR900
-+      bool "OpenMesh MR900 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_EAP7660D
-+      bool "Senao EAP7660D support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_ARCHER_C7
-+      bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_CPE510
-+      bool "TP-LINK CPE510 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR11U
-+      bool "TP-LINK TL-MR11U/TL-MR3040 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR13U
-+      bool "TP-LINK TL-MR13U support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR3020
-+      bool "TP-LINK TL-MR3020 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_MR3X20
-+      bool "TP-LINK TL-MR3220/3420 support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_TL_WAX50RE
-+      bool "TP-LINK TL-WA750/850RE support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WA701ND_V2
-+      bool "TP-LINK TL-WA701ND v2 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
--config ATH79_MACH_AP136
--      bool "Atheros AP136/AP135 reference board"
--      select SOC_QCA955X
-+config ATH79_MACH_TL_WA7210N_V2
-+       bool "TP-LINK TL-WA7210N v2 support"
-+       select SOC_AR724X
-+       select ATH79_DEV_AP9X_PCI if PCI
-+       select ATH79_DEV_ETH
-+       select ATH79_DEV_LEDS_GPIO
-+       select ATH79_DEV_GPIO_BUTTONS
-+       select ATH79_DEV_M25P80
-+       select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WA830RE_V2
-+      bool "TP-LINK TL-WA830RE v2 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-       select ATH79_DEV_GPIO_BUTTONS
-       select ATH79_DEV_LEDS_GPIO
--      select ATH79_DEV_NFC
--      select ATH79_DEV_SPI
-+      select ATH79_DEV_M25P80
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
--      help
--        Say 'Y' here if you want your kernel to support the
--        Atheros AP136 or AP135 reference boards.
--config ATH79_MACH_AP81
--      bool "Atheros AP81 reference board"
-+config ATH79_MACH_TL_WA901ND
-+      bool "TP-LINK TL-WA901ND/TL-WA7510N support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WA901ND_V2
-+      bool "TP-LINK TL-WA901ND v2 support"
-       select SOC_AR913X
-       select ATH79_DEV_ETH
-       select ATH79_DEV_GPIO_BUTTONS
-       select ATH79_DEV_LEDS_GPIO
-       select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WDR3500
-+      bool "TP-LINK TL-WDR3500 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
--      help
--        Say 'Y' here if you want your kernel to support the
--        Atheros AP81 reference board.
--config ATH79_MACH_DB120
--      bool "Atheros DB120 reference board"
-+config ATH79_MACH_TL_WDR4300
-+      bool "TP-LINK TL-WDR3600/4300/4310 board support"
-       select SOC_AR934X
-       select ATH79_DEV_AP9X_PCI if PCI
-       select ATH79_DEV_ETH
-       select ATH79_DEV_GPIO_BUTTONS
-       select ATH79_DEV_LEDS_GPIO
-       select ATH79_DEV_M25P80
--      select ATH79_DEV_NFC
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
--      help
--        Say 'Y' here if you want your kernel to support the
--        Atheros DB120 reference board.
--config ATH79_MACH_PB44
--      bool "Atheros PB44 reference board"
-+config ATH79_MACH_TL_WR703N
-+      bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR720N_V3
-+      bool "TP-LINK TL-WR720N v3/v4 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR741ND
-+      bool "TP-LINK TL-WR741ND support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WR741ND_V4
-+      bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR841N_V1
-+      bool "TP-LINK TL-WR841N v1 support"
-       select SOC_AR71XX
-+      select ATH79_DEV_DSA
-       select ATH79_DEV_ETH
-       select ATH79_DEV_GPIO_BUTTONS
-       select ATH79_DEV_LEDS_GPIO
--      select ATH79_DEV_SPI
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_TL_WR841N_V8
-+      bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR841N_V9
-+       bool "TP-LINK TL-WR841N/ND v9 support"
-+       select SOC_QCA953X
-+       select ATH79_DEV_ETH
-+       select ATH79_DEV_GPIO_BUTTONS
-+       select ATH79_DEV_LEDS_GPIO
-+       select ATH79_DEV_M25P80
-+       select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR941ND
-+      bool "TP-LINK TL-WR941ND support"
-+      select SOC_AR913X
-+      select ATH79_DEV_DSA
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR1041N_V2
-+      bool "TP-LINK TL-WR1041N v2 support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR1043ND
-+      bool "TP-LINK TL-WR1043ND support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR1043ND_V2
-+      bool "TP-LINK TL-WR1043ND v2 support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_TL_WR2543N
-+      bool "TP-LINK TL-WR2543N/ND support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+
-+config ATH79_MACH_TEW_632BRP
-+      bool "TRENDnet TEW-632BRP support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_TEW_673GRU
-+      bool "TRENDnet TEW-673GRU support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_TEW_712BR
-+      bool "TRENDnet TEW-712BR support"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_TEW_732BR
-+      bool "TRENDnet TEW-732BR support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_UBNT
-+      bool "Ubiquiti AR71xx based boards support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-       select ATH79_DEV_USB
--      help
--        Say 'Y' here if you want your kernel to support the
--        Atheros PB44 reference board.
- config ATH79_MACH_UBNT_XM
-       bool "Ubiquiti Networks XM/UniFi boards"
-@@ -83,6 +1116,97 @@ config ATH79_MACH_UBNT_XM
-         Say 'Y' here if you want your kernel to support the
-         Ubiquiti Networks XM (rev 1.0) board.
-+config ATH79_MACH_MYNET_N600
-+      bool "WD My Net N600 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_MYNET_N750
-+      bool "WD My Net N750 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_MYNET_REXT
-+      bool "WD My Net Wi-Fi Range Extender board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
-+config ATH79_MACH_ZCN_1523H
-+      bool "Zcomax ZCN-1523H support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+
-+config ATH79_MACH_NBG460N
-+      bool "Zyxel NBG460N/550N/550NH board support"
-+      select SOC_AR913X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_NBG6716
-+      bool "Zyxel NBG6716 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_CARAMBOLA2
-+      bool "8devices Carambola2 board"
-+      select SOC_AR933X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_BHU_BXU2000N2_A
-+      bool "BHU BXU2000n-2 rev. A support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_QIHOO_C301
-+      bool "Qihoo 360 C301 board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_USB
-+      select ATH79_NVRAM
-+
- endmenu
- config SOC_AR71XX
-@@ -124,7 +1248,10 @@ config ATH79_DEV_DSA
- config ATH79_DEV_ETH
-       def_bool n
--config PCI_AR724X
-+config ATH79_DEV_DSA
-+      def_bool n
-+
-+config ATH79_DEV_ETH
-       def_bool n
- config ATH79_DEV_GPIO_BUTTONS
-@@ -154,6 +1281,11 @@ config ATH79_PCI_ATH9K_FIXUP
-       def_bool n
- config ATH79_ROUTERBOOT
-+      select RLE_DECOMPRESS
-+      select LZO_DECOMPRESS
-+      def_bool n
-+
-+config PCI_AR724X
-       def_bool n
- endif
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -38,9 +38,124 @@ obj-$(CONFIG_ATH79_ROUTERBOOT)             += route
- #
- # Machines
- #
-+obj-$(CONFIG_ATH79_MACH_ALFA_AP96)    += mach-alfa-ap96.o
-+obj-$(CONFIG_ATH79_MACH_ALFA_NX)      += mach-alfa-nx.o
-+obj-$(CONFIG_ATH79_MACH_ALL0258N)     += mach-all0258n.o
-+obj-$(CONFIG_ATH79_MACH_ALL0315N)     += mach-all0315n.o
-+obj-$(CONFIG_ATH79_MACH_AP113)                += mach-ap113.o
- obj-$(CONFIG_ATH79_MACH_AP121)                += mach-ap121.o
-+obj-$(CONFIG_ATH79_MACH_AP132)                += mach-ap132.o
- obj-$(CONFIG_ATH79_MACH_AP136)                += mach-ap136.o
- obj-$(CONFIG_ATH79_MACH_AP81)         += mach-ap81.o
-+obj-$(CONFIG_ATH79_MACH_AP83)         += mach-ap83.o
-+obj-$(CONFIG_ATH79_MACH_AP96)         += mach-ap96.o
-+obj-$(CONFIG_ATH79_MACH_ARCHER_C7)    += mach-archer-c7.o
-+obj-$(CONFIG_ATH79_MACH_AW_NR580)     += mach-aw-nr580.o
-+obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o
-+obj-$(CONFIG_ATH79_MACH_CAP4200AG)    += mach-cap4200ag.o
-+obj-$(CONFIG_ATH79_MACH_CPE510)               += mach-cpe510.o
- obj-$(CONFIG_ATH79_MACH_DB120)                += mach-db120.o
-+obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP)      += mach-dlan-pro-500-wp.o
-+obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC)     += mach-dlan-pro-1200-ac.o
-+obj-$(CONFIG_ATH79_MACH_DGL_5500_A1)  += mach-dgl-5500-a1.o
-+obj-$(CONFIG_ATH79_MACH_DHP_1565_A1)  += mach-dhp-1565-a1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_505_A1)   += mach-dir-505-a1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_600_A1)   += mach-dir-600-a1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_615_C1)   += mach-dir-615-c1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_615_I1)   += mach-dir-615-i1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_825_B1)   += mach-dir-825-b1.o
-+obj-$(CONFIG_ATH79_MACH_DIR_825_C1)   += mach-dir-825-c1.o
-+obj-$(CONFIG_ATH79_MACH_DRAGINO2)     += mach-dragino2.o
-+obj-$(CONFIG_ATH79_MACH_ESR900)       += mach-esr900.o
-+obj-$(CONFIG_ATH79_MACH_EW_DORIN)     += mach-ew-dorin.o
-+obj-$(CONFIG_ATH79_MACH_EAP300V2)     += mach-eap300v2.o
-+obj-$(CONFIG_ATH79_MACH_EAP7660D)     += mach-eap7660d.o
-+obj-$(CONFIG_ATH79_MACH_EL_M150)      += mach-el-m150.o
-+obj-$(CONFIG_ATH79_MACH_EL_MINI)      += mach-el-mini.o
-+obj-$(CONFIG_ATH79_MACH_ESR1750)      += mach-esr1750.o
-+obj-$(CONFIG_ATH79_MACH_F9K1115V2)    += mach-f9k1115v2.o
-+obj-$(CONFIG_ATH79_MACH_GL_INET)      += mach-gl-inet.o
-+obj-$(CONFIG_ATH79_MACH_GS_OOLITE)    += mach-gs-oolite.o
-+obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361)        += mach-hiwifi-hc6361.o
-+obj-$(CONFIG_ATH79_MACH_JA76PF)               += mach-ja76pf.o
-+obj-$(CONFIG_ATH79_MACH_JWAP003)      += mach-jwap003.o
-+obj-$(CONFIG_ATH79_MACH_HORNET_UB)    += mach-hornet-ub.o
-+obj-$(CONFIG_ATH79_MACH_MR600)                += mach-mr600.o
-+obj-$(CONFIG_ATH79_MACH_MR900)                += mach-mr900.o
-+obj-$(CONFIG_ATH79_MACH_MYNET_N600)   += mach-mynet-n600.o
-+obj-$(CONFIG_ATH79_MACH_MYNET_N750)   += mach-mynet-n750.o
-+obj-$(CONFIG_ATH79_MACH_MYNET_REXT)   += mach-mynet-rext.o
-+obj-$(CONFIG_ATH79_MACH_MZK_W04NU)    += mach-mzk-w04nu.o
-+obj-$(CONFIG_ATH79_MACH_MZK_W300NH)   += mach-mzk-w300nh.o
-+obj-$(CONFIG_ATH79_MACH_NBG460N)      += mach-nbg460n.o
-+obj-$(CONFIG_ATH79_MACH_OM2P)         += mach-om2p.o
-+obj-$(CONFIG_ATH79_MACH_OM5P)         += mach-om5p.o
-+obj-$(CONFIG_ATH79_MACH_PB42)         += mach-pb42.o
- obj-$(CONFIG_ATH79_MACH_PB44)         += mach-pb44.o
-+obj-$(CONFIG_ATH79_MACH_PB92)         += mach-pb92.o
-+obj-$(CONFIG_ATH79_MACH_QIHOO_C301)   += mach-qihoo-c301.o
-+obj-$(CONFIG_ATH79_MACH_R6100)                += mach-r6100.o
-+obj-$(CONFIG_ATH79_MACH_RB4XX)                += mach-rb4xx.o
-+obj-$(CONFIG_ATH79_MACH_RB750)                += mach-rb750.o
-+obj-$(CONFIG_ATH79_MACH_RB91X)                += mach-rb91x.o
-+obj-$(CONFIG_ATH79_MACH_RB95X)                += mach-rb95x.o
-+obj-$(CONFIG_ATH79_MACH_RB2011)               += mach-rb2011.o
-+obj-$(CONFIG_ATH79_MACH_RBSXTLITE)    += mach-rbsxtlite.o
-+obj-$(CONFIG_ATH79_MACH_RW2458N)      += mach-rw2458n.o
-+obj-$(CONFIG_ATH79_MACH_SMART_300)    += mach-smart-300.o
-+obj-$(CONFIG_ATH79_MACH_TEW_632BRP)   += mach-tew-632brp.o
-+obj-$(CONFIG_ATH79_MACH_TEW_673GRU)   += mach-tew-673gru.o
-+obj-$(CONFIG_ATH79_MACH_TEW_712BR)    += mach-tew-712br.o
-+obj-$(CONFIG_ATH79_MACH_TEW_732BR)    += mach-tew-732br.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR11U)     += mach-tl-mr11u.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR13U)     += mach-tl-mr13u.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR3020)    += mach-tl-mr3020.o
-+obj-$(CONFIG_ATH79_MACH_TL_MR3X20)    += mach-tl-mr3x20.o
-+obj-$(CONFIG_ATH79_MACH_TL_WAX50RE)     += mach-tl-wax50re.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2)        += mach-tl-wa701nd-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2)        += mach-tl-wa7210n-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2)        += mach-tl-wa830re-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA901ND)   += mach-tl-wa901nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)        += mach-tl-wa901nd-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WDR3500)     += mach-tl-wdr3500.o
-+obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR741ND)   += mach-tl-wr741nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)        += mach-tl-wr741nd-v4.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR941ND)   += mach-tl-wr941nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2)        += mach-tl-wr1041n-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR1043ND)  += mach-tl-wr1043nd.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2)       += mach-tl-wr1043nd-v2.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR2543N)   += mach-tl-wr2543n.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR703N)    += mach-tl-wr703n.o
-+obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o
-+obj-$(CONFIG_ATH79_MACH_TUBE2H)               += mach-tube2h.o
-+obj-$(CONFIG_ATH79_MACH_UBNT)         += mach-ubnt.o
- obj-$(CONFIG_ATH79_MACH_UBNT_XM)      += mach-ubnt-xm.o
-+obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
-+obj-$(CONFIG_ATH79_MACH_WLAE_AG300N)  += mach-wlae-ag300n.o
-+obj-$(CONFIG_ATH79_MACH_WLR8100)      += mach-wlr8100.o
-+obj-$(CONFIG_ATH79_MACH_WNDAP360)     += mach-wndap360.o
-+obj-$(CONFIG_ATH79_MACH_WNDR3700)     += mach-wndr3700.o
-+obj-$(CONFIG_ATH79_MACH_WNDR4300)     += mach-wndr4300.o
-+obj-$(CONFIG_ATH79_MACH_WNR2000)      += mach-wnr2000.o
-+obj-$(CONFIG_ATH79_MACH_WNR2000_V3)   += mach-wnr2000-v3.o
-+obj-$(CONFIG_ATH79_MACH_WNR2000_V4)   += mach-wnr2000-v4.o
-+obj-$(CONFIG_ATH79_MACH_WNR2200)      += mach-wnr2200.o
-+obj-$(CONFIG_ATH79_MACH_WP543)                += mach-wp543.o
-+obj-$(CONFIG_ATH79_MACH_WPE72)                += mach-wpe72.o
-+obj-$(CONFIG_ATH79_MACH_WPJ344)       += mach-wpj344.o
-+obj-$(CONFIG_ATH79_MACH_WPJ531)       += mach-wpj531.o
-+obj-$(CONFIG_ATH79_MACH_WPJ558)       += mach-wpj558.o
-+obj-$(CONFIG_ATH79_MACH_WRT160NL)     += mach-wrt160nl.o
-+obj-$(CONFIG_ATH79_MACH_WRT400N)      += mach-wrt400n.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH)        += mach-wzr-hp-g300nh.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2)       += mach-wzr-hp-g300nh2.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H)        += mach-wzr-hp-ag300h.o
-+obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
-+obj-$(CONFIG_ATH79_MACH_WZR_450HP2)   += mach-wzr-450hp2.o
-+obj-$(CONFIG_ATH79_MACH_ZCN_1523H)    += mach-zcn-1523h.o
-+obj-$(CONFIG_ATH79_MACH_CARAMBOLA2)   += mach-carambola2.o
-+obj-$(CONFIG_ATH79_MACH_NBG6716)      += mach-nbg6716.o
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -130,6 +130,12 @@ void __init prom_init(void)
-               initrd_end = initrd_start + fw_getenvl("initrd_size");
-       }
- #endif
-+
-+      if (strstr(arcs_cmdline, "board=750Gr3") ||
-+          strstr(arcs_cmdline, "board=951G") ||
-+          strstr(arcs_cmdline, "board=2011L") ||
-+          strstr(arcs_cmdline, "board=711Gr100"))
-+              ath79_prom_append_cmdline("console", "ttyS0,115200");
- }
- void __init prom_free_prom_memory(void)
index fdef854..4e3ac70 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -306,6 +306,11 @@ void __init ath79_wmac_disable_5ghz(void
+@@ -308,6 +308,11 @@ void __init ath79_wmac_disable_5ghz(void
        ath79_wmac_data.disable_5ghz = true;
  }
  
index 83de7b1..a832bf8 100644 (file)
@@ -12,7 +12,7 @@
  #include "dev-wmac.h"
  
  static u8 ath79_wmac_mac[ETH_ALEN];
-@@ -311,6 +313,51 @@ void __init ath79_wmac_set_tx_gain_buffa
+@@ -313,6 +315,51 @@ void __init ath79_wmac_set_tx_gain_buffa
        ath79_wmac_data.tx_gain_buffalo = true;
  }
  
diff --git a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
new file mode 100644 (file)
index 0000000..58ca1d5
--- /dev/null
@@ -0,0 +1,721 @@
+From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
+Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
+From: Matthias Schiffer <mschiffer@universe-factory.net>
+Date: Sat, 29 Mar 2014 20:26:08 +0100
+Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
+
+Note that the clock calculation looks very similar to the QCA955x, but the
+meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+---
+ arch/mips/ath79/Kconfig                        |  6 +-
+ arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
+ arch/mips/ath79/common.c                       |  4 ++
+ arch/mips/ath79/dev-common.c                   |  1 +
+ arch/mips/ath79/dev-wmac.c                     | 20 +++++++
+ arch/mips/ath79/early_printk.c                 |  1 +
+ arch/mips/ath79/gpio.c                         |  4 +-
+ arch/mips/ath79/irq.c                          |  4 ++
+ arch/mips/ath79/setup.c                        |  8 ++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
+ 11 files changed, 182 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -105,6 +105,10 @@ config SOC_AR934X
+       select PCI_AR724X if PCI
+       def_bool n
++config SOC_QCA953X
++      select USB_ARCH_HAS_EHCI
++      def_bool n
++
+ config SOC_QCA955X
+       select HW_HAS_PCI
+       select PCI_AR724X if PCI
+@@ -144,7 +148,7 @@ config ATH79_DEV_USB
+       def_bool n
+ config ATH79_DEV_WMAC
+-      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
++      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
+       def_bool n
+ config ATH79_NVRAM
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
+       iounmap(dpll_base);
+ }
++static void __init qca953x_clocks_init(void)
++{
++      unsigned long ref_rate;
++      unsigned long cpu_rate;
++      unsigned long ddr_rate;
++      unsigned long ahb_rate;
++      u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++      u32 cpu_pll, ddr_pll;
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++      if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
++              ref_rate = 40 * 1000 * 1000;
++      else
++              ref_rate = 25 * 1000 * 1000;
++
++      pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
++      out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++                QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++                QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
++             QCA953X_PLL_CPU_CONFIG_NINT_MASK;
++      frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++             QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++      cpu_pll = nint * ref_rate / ref_div;
++      cpu_pll += frac * (ref_rate >> 6) / ref_div;
++      cpu_pll /= (1 << out_div);
++
++      pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
++      out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++                QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++                QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
++             QCA953X_PLL_DDR_CONFIG_NINT_MASK;
++      frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++             QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++      ddr_pll = nint * ref_rate / ref_div;
++      ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
++      ddr_pll /= (1 << out_div);
++
++      clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
++
++      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++                QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++              cpu_rate = ref_rate;
++      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++              cpu_rate = cpu_pll / (postdiv + 1);
++      else
++              cpu_rate = ddr_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++                QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++              ddr_rate = ref_rate;
++      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++              ddr_rate = ddr_pll / (postdiv + 1);
++      else
++              ddr_rate = cpu_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++                QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++              ahb_rate = ref_rate;
++      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++              ahb_rate = ddr_pll / (postdiv + 1);
++      else
++              ahb_rate = cpu_pll / (postdiv + 1);
++
++      ath79_add_sys_clkdev("ref", ref_rate);
++      ath79_add_sys_clkdev("cpu", cpu_rate);
++      ath79_add_sys_clkdev("ddr", ddr_rate);
++      ath79_add_sys_clkdev("ahb", ahb_rate);
++
++      clk_add_alias("wdt", NULL, "ref", NULL);
++      clk_add_alias("uart", NULL, "ref", NULL);
++}
++
+ static void __init qca955x_clocks_init(void)
+ {
+       unsigned long ref_rate;
+@@ -447,6 +532,8 @@ void __init ath79_clocks_init(void)
+               ar933x_clocks_init();
+       else if (soc_is_ar934x())
+               ar934x_clocks_init();
++      else if (soc_is_qca953x())
++              qca953x_clocks_init();
+       else if (soc_is_qca955x())
+               qca955x_clocks_init();
+       else
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
+               reg = AR933X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar934x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
++      else if (soc_is_qca953x())
++              reg = QCA953X_RESET_REG_RESET_MODULE;
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
+       else
+@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
+               reg = AR933X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar934x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
++      else if (soc_is_qca953x())
++              reg = QCA953X_RESET_REG_RESET_MODULE;
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
+       else
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -93,6 +93,7 @@ void __init ath79_register_uart(void)
+           soc_is_ar724x() ||
+           soc_is_ar913x() ||
+           soc_is_ar934x() ||
++          soc_is_qca953x() ||
+           soc_is_qca955x()) {
+               ath79_uart_data[0].uartclk = uart_clk_rate;
+               platform_device_register(&ath79_uart_device);
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
+                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
++static void __init qca953x_usb_setup(void)
++{
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++
++      ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
++      udelay(1000);
++
++      ath79_usb_register("ehci-platform", -1,
++                         QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
++                         ATH79_CPU_IRQ(3),
++                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ static void qca955x_usb_reset_notifier(struct platform_device *pdev)
+ {
+       u32 base;
+@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
+               ar933x_usb_setup();
+       else if (soc_is_ar934x())
+               ar934x_usb_setup();
++      else if (soc_is_qca953x())
++              qca953x_usb_setup();
+       else if (soc_is_qca955x())
+               qca955x_usb_setup();
+       else
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
+       return -ETIMEDOUT;
+ }
+-static int ar933x_r1_get_wmac_revision(void)
++static int ar93xx_get_soc_revision(void)
+ {
+       return ath79_soc_rev;
+ }
+@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
+               ath79_wmac_data.is_clk_25mhz = true;
+       if (ath79_soc_rev == 1)
+-              ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
++              ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+       ath79_wmac_data.external_reset = ar933x_wmac_reset;
+ }
+@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
+       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+ }
++static void qca953x_wmac_setup(void)
++{
++      u32 t;
++
++      ath79_wmac_device.name = "qca953x_wmac";
++
++      ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
++      ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++      ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
++
++      t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++      if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
++              ath79_wmac_data.is_clk_25mhz = false;
++      else
++              ath79_wmac_data.is_clk_25mhz = true;
++
++      ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
++}
++
+ static void qca955x_wmac_setup(void)
+ {
+       u32 t;
+@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_
+               ar933x_wmac_setup();
+       else if (soc_is_ar934x())
+               ar934x_wmac_setup();
++      else if (soc_is_qca953x())
++              qca953x_wmac_setup();
+       else if (soc_is_qca955x())
+               qca955x_wmac_setup();
+       else
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -114,6 +114,8 @@ static void prom_putchar_init(void)
+       case REV_ID_MAJOR_AR9341:
+       case REV_ID_MAJOR_AR9342:
+       case REV_ID_MAJOR_AR9344:
++      case REV_ID_MAJOR_QCA9533:
++      case REV_ID_MAJOR_QCA9533_V2:
+       case REV_ID_MAJOR_QCA9556:
+       case REV_ID_MAJOR_QCA9558:
+               _prom_putchar = prom_putchar_ar71xx;
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
+           soc_is_ar913x() ||
+           soc_is_ar933x())
+               reg = AR71XX_GPIO_REG_FUNC;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() || soc_is_qca953x())
+               reg = AR934X_GPIO_REG_FUNC;
+       else
+               BUG();
+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
+       unsigned int reg;
+       u32 t, s;
+-      BUG_ON(!soc_is_ar934x());
++      BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
+       if (gpio >= AR934X_GPIO_COUNT)
+               return;
+@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
+               ath79_gpio_count = AR933X_GPIO_COUNT;
+       else if (soc_is_ar934x())
+               ath79_gpio_count = AR934X_GPIO_COUNT;
++      else if (soc_is_qca953x())
++              ath79_gpio_count = QCA953X_GPIO_COUNT;
+       else if (soc_is_qca955x())
+               ath79_gpio_count = QCA955X_GPIO_COUNT;
+       else
+@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
+       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+       ath79_gpio_chip.ngpio = ath79_gpio_count;
+-      if (soc_is_ar934x() || soc_is_qca955x()) {
++      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
+               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+       }
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
+       else if (soc_is_ar724x() ||
+                soc_is_ar933x() ||
+                soc_is_ar934x() ||
++               soc_is_qca953x() ||
+                soc_is_qca955x())
+               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+       else
+@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
++
++      if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
++              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
++              generic_handle_irq(ATH79_IP2_IRQ(0));
++      } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
++              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
++              generic_handle_irq(ATH79_IP2_IRQ(1));
++      } else {
++              spurious_interrupt();
++      }
++
++      enable_irq(irq);
++}
++
++static void qca953x_irq_init(void)
++{
++      int i;
++
++      for (i = ATH79_IP2_IRQ_BASE;
++           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
++}
++
+ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+ {
+       u32 status;
+@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
+       do_IRQ(ATH79_CPU_IRQ(3));
+ }
++static void qca953x_ip3_handler(void)
++{
++      ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
++      do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ void __init arch_init_irq(void)
+ {
+       if (soc_is_ar71xx()) {
+@@ -352,6 +391,9 @@ void __init arch_init_irq(void)
+       } else if (soc_is_ar934x()) {
+               ath79_ip2_handler = ath79_default_ip2_handler;
+               ath79_ip3_handler = ar934x_ip3_handler;
++      } else if (soc_is_qca953x()) {
++              ath79_ip2_handler = ath79_default_ip2_handler;
++              ath79_ip3_handler = qca953x_ip3_handler;
+       } else if (soc_is_qca955x()) {
+               ath79_ip2_handler = ath79_default_ip2_handler;
+               ath79_ip3_handler = ath79_default_ip3_handler;
+@@ -364,6 +406,8 @@ void __init arch_init_irq(void)
+       if (soc_is_ar934x())
+               ar934x_ip2_irq_init();
++      else if (soc_is_qca953x())
++              qca953x_irq_init();
+       else if (soc_is_qca955x())
+               qca955x_irq_init();
+ }
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
+       u32 major;
+       u32 minor;
+       u32 rev = 0;
++      u32 ver = 1;
+       id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
+       major = id & REV_ID_MAJOR_MASK;
+@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type
+               rev = id & AR934X_REV_ID_REVISION_MASK;
+               break;
++      case REV_ID_MAJOR_QCA9533_V2:
++              ver = 2;
++              /* drop through */
++
++      case REV_ID_MAJOR_QCA9533:
++              ath79_soc = ATH79_SOC_QCA9533;
++              chip = "9533";
++              rev = id & QCA953X_REV_ID_REVISION_MASK;
++              break;
++
+       case REV_ID_MAJOR_QCA9556:
+               ath79_soc = ATH79_SOC_QCA9556;
+               chip = "9556";
+@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type
+       ath79_soc_rev = rev;
+-      if (soc_is_qca955x())
++      if (soc_is_qca953x() || soc_is_qca955x())
+               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+                       chip, rev);
+       else
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -105,6 +105,21 @@
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
++#define QCA953X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
++#define QCA953X_GMAC_SIZE     0x14
++#define QCA953X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
++#define QCA953X_WMAC_SIZE     0x20000
++#define QCA953X_EHCI_BASE     0x1b000000
++#define QCA953X_EHCI_SIZE     0x200
++#define QCA953X_SRIF_BASE     (AR71XX_APB_BASE + 0x00116000)
++#define QCA953X_SRIF_SIZE     0x1000
++
++#define QCA953X_PCI_CFG_BASE0 0x14000000
++#define QCA953X_PCI_CTRL_BASE0        (AR71XX_APB_BASE + 0x000f0000)
++#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA953X_PCI_MEM_BASE0 0x10000000
++#define QCA953X_PCI_MEM_SIZE  0x02000000
++
+ #define QCA955X_PCI_MEM_BASE0 0x10000000
+ #define QCA955X_PCI_MEM_BASE1 0x12000000
+ #define QCA955X_PCI_MEM_SIZE  0x02000000
+@@ -173,6 +188,12 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC     0xac
++#define QCA953X_DDR_REG_FLUSH_GE0     0x9c
++#define QCA953X_DDR_REG_FLUSH_GE1     0xa0
++#define QCA953X_DDR_REG_FLUSH_USB     0xa4
++#define QCA953X_DDR_REG_FLUSH_PCIE    0xa8
++#define QCA953X_DDR_REG_FLUSH_WMAC    0xac
++
+ /*
+  * PLL block
+  */
+@@ -279,6 +300,44 @@
+ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
++#define QCA953X_PLL_CPU_CONFIG_REG            0x00
++#define QCA953X_PLL_DDR_CONFIG_REG            0x04
++#define QCA953X_PLL_CLK_CTRL_REG              0x08
++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG  0x24
++#define QCA953X_PLL_ETH_XMII_CONTROL_REG      0x2c
++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG     0x48
++
++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT     6
++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK      0x3f
++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK    0x7
++
++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff
++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT     10
++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK      0x3f
++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT   16
++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK    0x1f
++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT   23
++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK    0x7
++
++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL               BIT(20)
++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG            0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG            0x04
+ #define QCA955X_PLL_CLK_CTRL_REG              0x08
+@@ -355,6 +414,10 @@
+ #define AR934X_RESET_REG_BOOTSTRAP            0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
++#define QCA953X_RESET_REG_RESET_MODULE                0x1c
++#define QCA953X_RESET_REG_BOOTSTRAP           0xb0
++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS        0xac
++
+ #define QCA955X_RESET_REG_RESET_MODULE                0x1c
+ #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
+ #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
+@@ -450,6 +513,27 @@
+ #define AR934X_RESET_MBOX             BIT(1)
+ #define AR934X_RESET_I2S              BIT(0)
++#define QCA953X_RESET_USB_EXT_PWR     BIT(29)
++#define QCA953X_RESET_EXTERNAL                BIT(28)
++#define QCA953X_RESET_RTC             BIT(27)
++#define QCA953X_RESET_FULL_CHIP               BIT(24)
++#define QCA953X_RESET_GE1_MDIO                BIT(23)
++#define QCA953X_RESET_GE0_MDIO                BIT(22)
++#define QCA953X_RESET_CPU_NMI         BIT(21)
++#define QCA953X_RESET_CPU_COLD                BIT(20)
++#define QCA953X_RESET_DDR             BIT(16)
++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA953X_RESET_GE1_MAC         BIT(13)
++#define QCA953X_RESET_ETH_SWITCH_ANALOG       BIT(12)
++#define QCA953X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA953X_RESET_GE0_MAC         BIT(9)
++#define QCA953X_RESET_ETH_SWITCH      BIT(8)
++#define QCA953X_RESET_PCIE_PHY                BIT(7)
++#define QCA953X_RESET_PCIE            BIT(6)
++#define QCA953X_RESET_USB_HOST                BIT(5)
++#define QCA953X_RESET_USB_PHY         BIT(4)
++#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
++
+ #define QCA955X_RESET_HOST            BIT(31)
+ #define QCA955X_RESET_SLIC            BIT(30)
+ #define QCA955X_RESET_HDMA            BIT(29)
+@@ -503,6 +587,13 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1         BIT(0)
++#define QCA953X_BOOTSTRAP_SW_OPTION2  BIT(12)
++#define QCA953X_BOOTSTRAP_SW_OPTION1  BIT(11)
++#define QCA953X_BOOTSTRAP_EJTAG_MODE  BIT(5)
++#define QCA953X_BOOTSTRAP_REF_CLK_40  BIT(4)
++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++#define QCA953X_BOOTSTRAP_DDR1                BIT(0)
++
+ #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
+@@ -523,6 +614,24 @@
+        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC3)
++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC               BIT(0)
++#define QCA953X_PCIE_WMAC_INT_WMAC_TX         BIT(1)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP               BIT(2)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP               BIT(3)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC         BIT(4)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0                BIT(5)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1                BIT(6)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2                BIT(7)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3                BIT(8)
++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
++      (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
++       QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
++
++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
++      (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
++       QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
++       QCA953X_PCIE_WMAC_INT_PCIE_RC3)
++
+ #define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
+ #define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
+ #define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
+@@ -565,6 +674,8 @@
+ #define REV_ID_MAJOR_AR9341           0x0120
+ #define REV_ID_MAJOR_AR9342           0x1120
+ #define REV_ID_MAJOR_AR9344           0x2120
++#define REV_ID_MAJOR_QCA9533          0x0140
++#define REV_ID_MAJOR_QCA9533_V2               0x0160
+ #define REV_ID_MAJOR_QCA9556          0x0130
+ #define REV_ID_MAJOR_QCA9558          0x1130
+@@ -587,6 +698,8 @@
+ #define AR934X_REV_ID_REVISION_MASK   0xf
++#define QCA953X_REV_ID_REVISION_MASK  0xf
++
+ #define QCA955X_REV_ID_REVISION_MASK  0xf
+ /*
+@@ -634,12 +747,32 @@
+ #define AR934X_GPIO_REG_OUT_FUNC5     0x40
+ #define AR934X_GPIO_REG_FUNC          0x6c
++#define QCA953X_GPIO_REG_OUT_FUNC0    0x2c
++#define QCA953X_GPIO_REG_OUT_FUNC1    0x30
++#define QCA953X_GPIO_REG_OUT_FUNC2    0x34
++#define QCA953X_GPIO_REG_OUT_FUNC3    0x38
++#define QCA953X_GPIO_REG_OUT_FUNC4    0x3c
++#define QCA953X_GPIO_REG_IN_ENABLE0   0x44
++#define QCA953X_GPIO_REG_FUNC         0x6c
++
++#define QCA953X_GPIO_OUT_MUX_SPI_CS1          10
++#define QCA953X_GPIO_OUT_MUX_SPI_CS2          11
++#define QCA953X_GPIO_OUT_MUX_SPI_CS0          9
++#define QCA953X_GPIO_OUT_MUX_SPI_CLK          8
++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI         12
++#define QCA953X_GPIO_OUT_MUX_LED_LINK1                41
++#define QCA953X_GPIO_OUT_MUX_LED_LINK2                42
++#define QCA953X_GPIO_OUT_MUX_LED_LINK3                43
++#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
++#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
++
+ #define AR71XX_GPIO_COUNT             16
+ #define AR7240_GPIO_COUNT             18
+ #define AR7241_GPIO_COUNT             20
+ #define AR913X_GPIO_COUNT             22
+ #define AR933X_GPIO_COUNT             30
+ #define AR934X_GPIO_COUNT             23
++#define QCA953X_GPIO_COUNT            18
+ #define QCA955X_GPIO_COUNT            24
+ /*
+@@ -663,6 +796,24 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
++#define QCA953X_SRIF_CPU_DPLL1_REG    0x1c0
++#define QCA953X_SRIF_CPU_DPLL2_REG    0x1c4
++#define QCA953X_SRIF_CPU_DPLL3_REG    0x1c8
++
++#define QCA953X_SRIF_DDR_DPLL1_REG    0x240
++#define QCA953X_SRIF_DDR_DPLL2_REG    0x244
++#define QCA953X_SRIF_DDR_DPLL3_REG    0x248
++
++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT       27
++#define QCA953X_SRIF_DPLL1_REFDIV_MASK        0x1f
++#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
++#define QCA953X_SRIF_DPLL1_NINT_MASK  0x1ff
++#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
++
++#define QCA953X_SRIF_DPLL2_LOCAL_PLL  BIT(30)
++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT       13
++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK        0x7
++
+ #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
+ #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
+ #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
+@@ -804,6 +955,16 @@
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+ /*
++ * QCA953X GMAC Interface
++ */
++#define QCA953X_GMAC_REG_ETH_CFG              0x00
++
++#define QCA953X_ETH_CFG_SW_ONLY_MODE          BIT(6)
++#define QCA953X_ETH_CFG_SW_PHY_SWAP           BIT(7)
++#define QCA953X_ETH_CFG_SW_APB_ACCESS         BIT(9)
++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
++
++/*
+  * QCA955X GMAC Interface
+  */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+       ATH79_SOC_AR9341,
+       ATH79_SOC_AR9342,
+       ATH79_SOC_AR9344,
++      ATH79_SOC_QCA9533,
+       ATH79_SOC_QCA9556,
+       ATH79_SOC_QCA9558,
+ };
+@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
+       return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
++static inline int soc_is_qca9533(void)
++{
++      return ath79_soc == ATH79_SOC_QCA9533;
++}
++
++static inline int soc_is_qca953x(void)
++{
++      return soc_is_qca9533();
++}
++
+ static inline int soc_is_qca9556(void)
+ {
+       return ath79_soc == ATH79_SOC_QCA9556;
diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
new file mode 100644 (file)
index 0000000..b23c18e
--- /dev/null
@@ -0,0 +1,700 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -114,6 +114,12 @@ config SOC_QCA955X
+       select PCI_AR724X if PCI
+       def_bool n
++config SOC_QCA956X
++      select USB_ARCH_HAS_EHCI
++      select HW_HAS_PCI
++      select PCI_AR724X if PCI
++      def_bool n
++
+ config ATH79_DEV_M25P80
+       select ATH79_DEV_SPI
+       def_bool n
+@@ -148,7 +154,7 @@ config ATH79_DEV_USB
+       def_bool n
+ config ATH79_DEV_WMAC
+-      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
++      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
+       def_bool n
+ config ATH79_NVRAM
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
+       clk_add_alias("uart", NULL, "ref", NULL);
+ }
++static void __init qca956x_clocks_init(void)
++{
++      unsigned long ref_rate;
++      unsigned long cpu_rate;
++      unsigned long ddr_rate;
++      unsigned long ahb_rate;
++      u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
++      u32 cpu_pll, ddr_pll;
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
++      if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
++              ref_rate = 40 * 1000 * 1000;
++      else
++              ref_rate = 25 * 1000 * 1000;
++
++      pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
++      out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++                QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++                QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
++
++      pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
++      nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
++             QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
++      hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
++             QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
++      lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
++             QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
++
++      cpu_pll = nint * ref_rate / ref_div;
++      cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
++      cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
++      cpu_pll /= (1 << out_div);
++
++      pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
++      out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++                QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++                QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
++      pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
++      nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
++             QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
++      hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
++             QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
++      lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
++             QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
++
++      ddr_pll = nint * ref_rate / ref_div;
++      ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
++      ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
++      ddr_pll /= (1 << out_div);
++
++      clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
++
++      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++                QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++              cpu_rate = ref_rate;
++      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
++              cpu_rate = ddr_pll / (postdiv + 1);
++      else
++              cpu_rate = cpu_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++                QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++              ddr_rate = ref_rate;
++      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
++              ddr_rate = cpu_pll / (postdiv + 1);
++      else
++              ddr_rate = ddr_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++                QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++              ahb_rate = ref_rate;
++      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++              ahb_rate = ddr_pll / (postdiv + 1);
++      else
++              ahb_rate = cpu_pll / (postdiv + 1);
++
++      ath79_add_sys_clkdev("ref", ref_rate);
++      ath79_add_sys_clkdev("cpu", cpu_rate);
++      ath79_add_sys_clkdev("ddr", ddr_rate);
++      ath79_add_sys_clkdev("ahb", ahb_rate);
++
++      clk_add_alias("wdt", NULL, "ref", NULL);
++      clk_add_alias("uart", NULL, "ref", NULL);
++}
++
+ void __init ath79_clocks_init(void)
+ {
+       if (soc_is_ar71xx())
+@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
+               qca953x_clocks_init();
+       else if (soc_is_qca955x())
+               qca955x_clocks_init();
++      else if (soc_is_qca956x())
++              qca956x_clocks_init();
+       else
+               BUG();
+ }
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
+               reg = QCA953X_RESET_REG_RESET_MODULE;
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
++      else if (soc_is_qca956x())
++              reg = QCA956X_RESET_REG_RESET_MODULE;
+       else
+               panic("Reset register not defined for this SOC");
+@@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
+               reg = QCA953X_RESET_REG_RESET_MODULE;
+       else if (soc_is_qca955x())
+               reg = QCA955X_RESET_REG_RESET_MODULE;
++      else if (soc_is_qca956x())
++              reg = QCA956X_RESET_REG_RESET_MODULE;
+       else
+               panic("Reset register not defined for this SOC");
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
+           soc_is_ar913x() ||
+           soc_is_ar934x() ||
+           soc_is_qca953x() ||
+-          soc_is_qca955x()) {
++          soc_is_qca955x() ||
++          soc_is_qca956x()) {
+               ath79_uart_data[0].uartclk = uart_clk_rate;
+               platform_device_register(&ath79_uart_device);
+       } else if (soc_is_ar933x()) {
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
+                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
++static void __init qca956x_usb_setup(void)
++{
++      ath79_usb_register("ehci-platform", 0,
++                         QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
++                         ATH79_IP3_IRQ(0),
++                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++
++      ath79_usb_register("ehci-platform", 1,
++                         QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
++                         ATH79_IP3_IRQ(1),
++                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ void __init ath79_register_usb(void)
+ {
+       if (soc_is_ar71xx())
+@@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
+               qca953x_usb_setup();
+       else if (soc_is_qca955x())
+               qca955x_usb_setup();
++      else if (soc_is_qca9561())
++              qca956x_usb_setup();
+       else
+               BUG();
+ }
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
+ }
++static void qca956x_wmac_setup(void)
++{
++      u32 t;
++
++      ath79_wmac_device.name = "qca956x_wmac";
++
++      ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
++      ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++      ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
++
++      t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
++      if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
++              ath79_wmac_data.is_clk_25mhz = false;
++      else
++              ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ static bool __init
+ ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
+ {
+@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
+               qca953x_wmac_setup();
+       else if (soc_is_qca955x())
+               qca955x_wmac_setup();
++      else if (soc_is_qca956x())
++              qca956x_wmac_setup();
+       else
+               BUG();
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -118,6 +118,8 @@ static void prom_putchar_init(void)
+       case REV_ID_MAJOR_QCA9533_V2:
+       case REV_ID_MAJOR_QCA9556:
+       case REV_ID_MAJOR_QCA9558:
++      case REV_ID_MAJOR_TP9343:
++      case REV_ID_MAJOR_QCA9561:
+               _prom_putchar = prom_putchar_ar71xx;
+               break;
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
+           soc_is_ar913x() ||
+           soc_is_ar933x())
+               reg = AR71XX_GPIO_REG_FUNC;
+-      else if (soc_is_ar934x() || soc_is_qca953x())
++      else if (soc_is_ar934x() ||
++               soc_is_qca953x() || soc_is_qca956x())
+               reg = AR934X_GPIO_REG_FUNC;
+       else
+               BUG();
+@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
+               ath79_gpio_count = QCA953X_GPIO_COUNT;
+       else if (soc_is_qca955x())
+               ath79_gpio_count = QCA955X_GPIO_COUNT;
++      else if (soc_is_qca956x())
++              ath79_gpio_count = QCA956X_GPIO_COUNT;
+       else
+               BUG();
+       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+       ath79_gpio_chip.ngpio = ath79_gpio_count;
+-      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
++      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
++          soc_is_qca956x()) {
+               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+       }
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
+                soc_is_ar933x() ||
+                soc_is_ar934x() ||
+                soc_is_qca953x() ||
+-               soc_is_qca955x())
++               soc_is_qca955x() ||
++               soc_is_qca956x())
+               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+       else
+               BUG();
+@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
+       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
+ }
++static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(0));
++      }
++
++      if (status & QCA956X_EXT_INT_WMAC_ALL) {
++              /* TODO: flsuh DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(1));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
++                QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA956X_EXT_INT_USB1) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(0));
++      }
++
++      if (status & QCA956X_EXT_INT_USB2) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(1));
++      }
++
++      if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(2));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca956x_enable_timer_cb(void) {
++      u32 misc;
++
++      misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
++      misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
++      ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
++}
++
++static void qca956x_irq_init(void)
++{
++      int i;
++
++      for (i = ATH79_IP2_IRQ_BASE;
++           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
++
++      for (i = ATH79_IP3_IRQ_BASE;
++           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
++
++      /* QCA956x timer init workaround has to be applied right before setting
++       * up the clock. Else, there will be no jiffies */
++      late_time_init = &qca956x_enable_timer_cb;
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+       unsigned long pending;
+@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
+       } else if (soc_is_qca955x()) {
+               ath79_ip2_handler = ath79_default_ip2_handler;
+               ath79_ip3_handler = ath79_default_ip3_handler;
++      } else if (soc_is_qca956x()) {
++              ath79_ip2_handler = ath79_default_ip2_handler;
++              ath79_ip3_handler = ath79_default_ip3_handler;
+       } else {
+               BUG();
+       }
+@@ -410,4 +505,6 @@ void __init arch_init_irq(void)
+               qca953x_irq_init();
+       else if (soc_is_qca955x())
+               qca955x_irq_init();
++      else if (soc_is_qca956x())
++              qca956x_irq_init();
+ }
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
+       },
+ };
++static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
++      {
++              .bus    = 0,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(0),
++      },
++      {
++              .bus    = 1,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(1),
++      },
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+       int irq = -1;
+@@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
+               } else if (soc_is_qca955x()) {
+                       ath79_pci_irq_map = qca955x_pci_irq_map;
+                       ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
++              } else if (soc_is_qca9561()) {
++                      ath79_pci_irq_map = qca956x_pci_irq_map;
++                      ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
+               } else {
+                       pr_crit("pci %s: invalid irq map\n",
+                               pci_name((struct pci_dev *) dev));
+@@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
+                                                QCA955X_PCI_MEM_SIZE,
+                                                1,
+                                                ATH79_IP3_IRQ(2));
++      } else if (soc_is_qca9561()) {
++              pdev = ath79_register_pci_ar724x(0,
++                                               QCA956X_PCI_CFG_BASE1,
++                                               QCA956X_PCI_CTRL_BASE1,
++                                               QCA956X_PCI_CRP_BASE1,
++                                               QCA956X_PCI_MEM_BASE1,
++                                               QCA956X_PCI_MEM_SIZE,
++                                               1,
++                                               ATH79_IP3_IRQ(2));
+       } else {
+               /* No PCI support */
+               return -ENODEV;
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type
+               rev = id & QCA955X_REV_ID_REVISION_MASK;
+               break;
++      case REV_ID_MAJOR_TP9343:
++              ath79_soc = ATH79_SOC_TP9343;
++              chip = "9343";
++              rev = id & QCA956X_REV_ID_REVISION_MASK;
++              break;
++
++      case REV_ID_MAJOR_QCA9561:
++              ath79_soc = ATH79_SOC_QCA9561;
++              chip = "9561";
++              rev = id & QCA956X_REV_ID_REVISION_MASK;
++              break;
++
+       default:
+               panic("ath79: unknown SoC, id:0x%08x", id);
+       }
+       ath79_soc_rev = rev;
+-      if (soc_is_qca953x() || soc_is_qca955x())
+-              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++      if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++                      chip, ver, rev);
++      else if (soc_is_tp9343())
++              sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
+                       chip, rev);
+       else
+               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -143,6 +143,23 @@
+ #define QCA955X_NFC_BASE      0x1b800200
+ #define QCA955X_NFC_SIZE      0xb8
++#define QCA956X_PCI_MEM_BASE1 0x12000000
++#define QCA956X_PCI_MEM_SIZE  0x02000000
++#define QCA956X_PCI_CFG_BASE1 0x16000000
++#define QCA956X_PCI_CFG_SIZE  0x1000
++#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
++#define QCA956X_PCI_CRP_SIZE  0x1000
++#define QCA956X_PCI_CTRL_BASE1        (AR71XX_APB_BASE + 0x00280000)
++#define QCA956X_PCI_CTRL_SIZE 0x100
++
++#define QCA956X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
++#define QCA956X_WMAC_SIZE     0x20000
++#define QCA956X_EHCI0_BASE    0x1b000000
++#define QCA956X_EHCI1_BASE    0x1b400000
++#define QCA956X_EHCI_SIZE     0x200
++#define QCA956X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
++#define QCA956X_GMAC_SIZE     0x64
++
+ #define AR9300_OTP_BASE               0x14000
+ #define AR9300_OTP_STATUS     0x15f18
+ #define AR9300_OTP_STATUS_TYPE                0x7
+@@ -375,6 +392,49 @@
+ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
+ #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++#define QCA956X_PLL_CPU_CONFIG_REG                    0x00
++#define QCA956X_PLL_CPU_CONFIG1_REG                   0x04
++#define QCA956X_PLL_DDR_CONFIG_REG                    0x08
++#define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
++#define QCA956X_PLL_CLK_CTRL_REG                      0x10
++
++#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
++#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT           19
++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK            0x7
++
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT         0
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK          0x1f
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT         5
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT            18
++#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK             0x1ff
++
++#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT           16
++#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK            0x1f
++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT           23
++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK            0x7
++
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT         0
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK          0x1f
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT         5
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT            18
++#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK             0x1ff
++
++#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
++#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
++#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL   BIT(20)
++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL   BIT(21)
++#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -422,6 +482,11 @@
+ #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
+ #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
++#define QCA956X_RESET_REG_RESET_MODULE                0x1c
++#define QCA956X_RESET_REG_BOOTSTRAP           0xb0
++#define QCA956X_RESET_REG_EXT_INT_STATUS      0xac
++
++#define MISC_INT_MIPS_SI_TIMERINT_MASK        BIT(28)
+ #define MISC_INT_ETHSW                        BIT(12)
+ #define MISC_INT_TIMER4                       BIT(10)
+ #define MISC_INT_TIMER3                       BIT(9)
+@@ -596,6 +661,8 @@
+ #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
++#define QCA956X_BOOTSTRAP_REF_CLK_40  BIT(2)
++
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
+ #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
+ #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
+@@ -663,6 +730,37 @@
+        QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+        QCA955X_EXT_INT_PCIE_RC2_INT3)
++#define QCA956X_EXT_INT_WMAC_MISC             BIT(0)
++#define QCA956X_EXT_INT_WMAC_TX                       BIT(1)
++#define QCA956X_EXT_INT_WMAC_RXLP             BIT(2)
++#define QCA956X_EXT_INT_WMAC_RXHP             BIT(3)
++#define QCA956X_EXT_INT_PCIE_RC1              BIT(4)
++#define QCA956X_EXT_INT_PCIE_RC1_INT0         BIT(5)
++#define QCA956X_EXT_INT_PCIE_RC1_INT1         BIT(6)
++#define QCA956X_EXT_INT_PCIE_RC1_INT2         BIT(7)
++#define QCA956X_EXT_INT_PCIE_RC1_INT3         BIT(8)
++#define QCA956X_EXT_INT_PCIE_RC2              BIT(12)
++#define QCA956X_EXT_INT_PCIE_RC2_INT0         BIT(13)
++#define QCA956X_EXT_INT_PCIE_RC2_INT1         BIT(14)
++#define QCA956X_EXT_INT_PCIE_RC2_INT2         BIT(15)
++#define QCA956X_EXT_INT_PCIE_RC2_INT3         BIT(16)
++#define QCA956X_EXT_INT_USB1                  BIT(24)
++#define QCA956X_EXT_INT_USB2                  BIT(28)
++
++#define QCA956X_EXT_INT_WMAC_ALL \
++      (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
++       QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
++
++#define QCA956X_EXT_INT_PCIE_RC1_ALL \
++      (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
++       QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
++       QCA956X_EXT_INT_PCIE_RC1_INT3)
++
++#define QCA956X_EXT_INT_PCIE_RC2_ALL \
++      (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
++       QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
++       QCA956X_EXT_INT_PCIE_RC2_INT3)
++
+ #define REV_ID_MAJOR_MASK             0xfff0
+ #define REV_ID_MAJOR_AR71XX           0x00a0
+ #define REV_ID_MAJOR_AR913X           0x00b0
+@@ -678,6 +776,8 @@
+ #define REV_ID_MAJOR_QCA9533_V2               0x0160
+ #define REV_ID_MAJOR_QCA9556          0x0130
+ #define REV_ID_MAJOR_QCA9558          0x1130
++#define REV_ID_MAJOR_TP9343           0x0150
++#define REV_ID_MAJOR_QCA9561          0x1150
+ #define AR71XX_REV_ID_MINOR_MASK      0x3
+ #define AR71XX_REV_ID_MINOR_AR7130    0x0
+@@ -702,6 +802,8 @@
+ #define QCA955X_REV_ID_REVISION_MASK  0xf
++#define QCA956X_REV_ID_REVISION_MASK  0xf
++
+ /*
+  * SPI block
+  */
+@@ -766,6 +868,19 @@
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
++#define QCA956X_GPIO_REG_OUT_FUNC0    0x2c
++#define QCA956X_GPIO_REG_OUT_FUNC1    0x30
++#define QCA956X_GPIO_REG_OUT_FUNC2    0x34
++#define QCA956X_GPIO_REG_OUT_FUNC3    0x38
++#define QCA956X_GPIO_REG_OUT_FUNC4    0x3c
++#define QCA956X_GPIO_REG_OUT_FUNC5    0x40
++#define QCA956X_GPIO_REG_IN_ENABLE0   0x44
++#define QCA956X_GPIO_REG_IN_ENABLE3   0x50
++#define QCA956X_GPIO_REG_FUNC         0x6c
++
++#define QCA956X_GPIO_OUT_MUX_GE0_MDO  32
++#define QCA956X_GPIO_OUT_MUX_GE0_MDC  33
++
+ #define AR71XX_GPIO_COUNT             16
+ #define AR7240_GPIO_COUNT             18
+ #define AR7241_GPIO_COUNT             20
+@@ -774,6 +889,7 @@
+ #define AR934X_GPIO_COUNT             23
+ #define QCA953X_GPIO_COUNT            18
+ #define QCA955X_GPIO_COUNT            24
++#define QCA956X_GPIO_COUNT            23
+ /*
+  * SRIF block
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -35,6 +35,8 @@ enum ath79_soc_type {
+       ATH79_SOC_QCA9533,
+       ATH79_SOC_QCA9556,
+       ATH79_SOC_QCA9558,
++      ATH79_SOC_TP9343,
++      ATH79_SOC_QCA9561,
+ };
+ extern enum ath79_soc_type ath79_soc;
+@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
+       return soc_is_qca9556() || soc_is_qca9558();
+ }
++static inline int soc_is_tp9343(void)
++{
++      return ath79_soc == ATH79_SOC_TP9343;
++}
++ 
++static inline int soc_is_qca9561(void)
++{
++      return ath79_soc == ATH79_SOC_QCA9561;
++}
++
++static inline int soc_is_qca956x(void)
++{
++      return soc_is_tp9343() || soc_is_qca9561();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
diff --git a/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch
new file mode 100644 (file)
index 0000000..8c0cc95
--- /dev/null
@@ -0,0 +1,100 @@
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -26,6 +26,8 @@
+ static void (*ath79_ip2_handler)(void);
+ static void (*ath79_ip3_handler)(void);
++static struct irq_chip ip2_chip;
++static struct irq_chip ip3_chip;
+ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
+       for (i = ATH79_IP2_IRQ_BASE;
+            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip,
+-                                       handle_level_irq);
++              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
+       for (i = ATH79_IP2_IRQ_BASE;
+            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
+ }
+@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
+       for (i = ATH79_IP2_IRQ_BASE;
+            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip,
+-                                       handle_level_irq);
++              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
+       for (i = ATH79_IP3_IRQ_BASE;
+            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip,
+-                                       handle_level_irq);
++              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
+ }
+@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
+       for (i = ATH79_IP2_IRQ_BASE;
+            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
+       for (i = ATH79_IP3_IRQ_BASE;
+            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
+       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
+@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
+       do_IRQ(ATH79_CPU_IRQ(3));
+ }
++static void ath79_ip2_disable(struct irq_data *data)
++{
++      disable_irq(ATH79_CPU_IRQ(2));
++}
++
++static void ath79_ip2_enable(struct irq_data *data)
++{
++      enable_irq(ATH79_CPU_IRQ(2));
++}
++
++static void ath79_ip3_disable(struct irq_data *data)
++{
++      disable_irq(ATH79_CPU_IRQ(3));
++}
++
++static void ath79_ip3_enable(struct irq_data *data)
++{
++      enable_irq(ATH79_CPU_IRQ(3));
++}
++
+ void __init arch_init_irq(void)
+ {
++      ip2_chip = dummy_irq_chip;
++      ip3_chip = dummy_irq_chip;
++      ip2_chip.irq_disable = ath79_ip2_disable;
++      ip2_chip.irq_enable = ath79_ip2_enable;
++      ip3_chip.irq_disable = ath79_ip3_disable;
++      ip3_chip.irq_enable = ath79_ip3_enable;
++
+       if (soc_is_ar71xx()) {
+               ath79_ip2_handler = ar71xx_ip2_handler;
+               ath79_ip3_handler = ar71xx_ip3_handler;
diff --git a/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch
new file mode 100644 (file)
index 0000000..03b32b1
--- /dev/null
@@ -0,0 +1,24 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -398,6 +398,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
+               ar934x_set_ext_lna_gpio(chain, gpio);
+ }
++void __init ath79_wmac_set_led_pin(int gpio)
++{
++      ath79_wmac_data.led_pin = gpio;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+       if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void);
+ void ath79_wmac_disable_5ghz(void);
+ void ath79_wmac_set_tx_gain_buffalo(void);
+ void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio);
++void ath79_wmac_set_led_pin(int gpio);
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
diff --git a/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch
new file mode 100644 (file)
index 0000000..c628f1d
--- /dev/null
@@ -0,0 +1,43 @@
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
+ void ath79_gpio_output_select(unsigned gpio, u8 val);
++int ath79_gpio_direction_select(unsigned gpio, bool oe);
+ void ath79_gpio_init(void);
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output(
+       return 0;
+ }
++int ath79_gpio_direction_select(unsigned gpio, bool oe)
++{
++      void __iomem *base = ath79_gpio_base;
++      unsigned long flags;
++      bool ieq_1 = (soc_is_ar934x() ||
++                      soc_is_qca953x());
++
++      if (gpio >= ath79_gpio_count)
++              return -1;
++
++      spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++      if ((ieq_1 && oe) || (!ieq_1 && !oe))
++              __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
++                              base + AR71XX_GPIO_REG_OE);
++      else
++              __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
++                              base + AR71XX_GPIO_REG_OE);
++
++      spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++
++      return 0;
++}
++
+ static struct gpio_chip ath79_gpio_chip = {
+       .label                  = "ath79",
+       .get                    = ath79_gpio_get_value,
diff --git a/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch b/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch
new file mode 100644 (file)
index 0000000..e8183e7
--- /dev/null
@@ -0,0 +1,224 @@
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -20,9 +20,14 @@
+ #include <linux/io.h>
+ #include <linux/ioport.h>
+ #include <linux/gpio.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++
++#include <linux/of.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/irq.h>
+ #include "common.h"
+ void __iomem *ath79_gpio_base;
+@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base);
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
++/*
++ * gpio_both_edge is a bitmask of which gpio pins need to have
++ * the detect priority flipped from the interrupt handler to
++ * emulate IRQ_TYPE_EDGE_BOTH.
++ */
++static unsigned long gpio_both_edge = 0;
++
+ static void __ath79_gpio_set_value(unsigned gpio, int value)
+ {
+       void __iomem *base = ath79_gpio_base;
+@@ -233,6 +245,132 @@ void __init ath79_gpio_output_select(uns
+       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
++static int ath79_gpio_irq_type(struct irq_data *d, unsigned type)
++{
++      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++      void __iomem *base = ath79_gpio_base;
++      unsigned long flags;
++      unsigned long int_type;
++      unsigned long int_polarity;
++      unsigned long bit = (1 << offset);
++
++      spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++      int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE);
++      int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY);
++
++      gpio_both_edge &= ~bit;
++
++      switch (type) {
++      case IRQ_TYPE_EDGE_RISING:
++              int_type &= ~bit;
++              int_polarity |= bit;
++              break;
++
++      case IRQ_TYPE_EDGE_FALLING:
++              int_type &= ~bit;
++              int_polarity &= ~bit;
++              break;
++
++      case IRQ_TYPE_LEVEL_HIGH:
++              int_type |= bit;
++              int_polarity |= bit;
++              break;
++
++      case IRQ_TYPE_LEVEL_LOW:
++              int_type |= bit;
++              int_polarity &= ~bit;
++              break;
++
++      case IRQ_TYPE_EDGE_BOTH:
++              int_type |= bit;
++              /* set polarity based on current value */
++              if (gpio_get_value(offset)) {
++                      int_polarity &= ~bit;
++              } else {
++                      int_polarity |= bit;
++              }
++              /* flip this gpio in the interrupt handler */
++              gpio_both_edge |= bit;
++              break;
++
++      default:
++              spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++              return -EINVAL;
++      }
++
++      __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE);
++      __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY);
++
++      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset),
++                   base + AR71XX_GPIO_REG_INT_MODE);
++
++      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
++                   base + AR71XX_GPIO_REG_INT_ENABLE);
++
++      spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++      return 0;
++}
++
++static void ath79_gpio_irq_enable(struct irq_data *d)
++{
++      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++      void __iomem *base = ath79_gpio_base;
++
++      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset),
++                   base + AR71XX_GPIO_REG_INT_ENABLE);
++}
++
++static void ath79_gpio_irq_disable(struct irq_data *d)
++{
++      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
++      void __iomem *base = ath79_gpio_base;
++
++      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
++                   base + AR71XX_GPIO_REG_INT_ENABLE);
++}
++
++static struct irq_chip ath79_gpio_irqchip = {
++      .name = "GPIO",
++      .irq_enable = ath79_gpio_irq_enable,
++      .irq_disable = ath79_gpio_irq_disable,
++      .irq_set_type = ath79_gpio_irq_type,
++};
++
++static irqreturn_t ath79_gpio_irq(int irq, void *dev)
++{
++      void __iomem *base = ath79_gpio_base;
++      unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING);
++      int bit_num;
++
++      for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) {
++              unsigned long bit = BIT(bit_num);
++
++              if (bit & gpio_both_edge) {
++                      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit,
++                              base + AR71XX_GPIO_REG_INT_POLARITY);
++              }
++
++              generic_handle_irq(ATH79_GPIO_IRQ(bit_num));
++      }
++
++      return IRQ_HANDLED;
++}
++
++static int __init ath79_gpio_irq_init(struct gpio_chip *chip)
++{
++      int irq;
++      int irq_base = ATH79_GPIO_IRQ_BASE;
++
++      for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) {
++              irq_set_chip_data(irq, chip);
++              irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq);
++              irq_set_noprobe(irq);
++      }
++
++      return 0;
++}
++
+ void __init ath79_gpio_init(void)
+ {
+       int err;
+@@ -269,6 +407,10 @@ void __init ath79_gpio_init(void)
+       err = gpiochip_add(&ath79_gpio_chip);
+       if (err)
+               panic("cannot add AR71xx GPIO chip, error=%d", err);
++
++      ath79_gpio_irq_init(&ath79_gpio_chip);
++
++      request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL);
+ }
+ int gpio_get_value(unsigned gpio)
+@@ -291,14 +433,22 @@ EXPORT_SYMBOL(gpio_set_value);
+ int gpio_to_irq(unsigned gpio)
+ {
+-      /* FIXME */
+-      return -EINVAL;
++      if (gpio > ath79_gpio_count) {
++              return -EINVAL;
++      }
++
++      return ATH79_GPIO_IRQ_BASE + gpio;
+ }
+ EXPORT_SYMBOL(gpio_to_irq);
+ int irq_to_gpio(unsigned irq)
+ {
+-      /* FIXME */
+-      return -EINVAL;
++      unsigned gpio = irq - ATH79_GPIO_IRQ_BASE;
++
++      if (gpio > ath79_gpio_count) {
++              return -EINVAL;
++      }
++
++      return gpio;
+ }
+ EXPORT_SYMBOL(irq_to_gpio);
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+ #define MIPS_CPU_IRQ_BASE     0
+-#define NR_IRQS                       51
++#define NR_IRQS                       83
+ #define ATH79_CPU_IRQ(_x)     (MIPS_CPU_IRQ_BASE + (_x))
+@@ -30,6 +30,10 @@
+ #define ATH79_IP3_IRQ_COUNT     3
+ #define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
++#define ATH79_GPIO_IRQ_BASE   (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT)
++#define ATH79_GPIO_IRQ_COUNT  32
++#define ATH79_GPIO_IRQ(_x)    (ATH79_GPIO_IRQ_BASE + (_x))
++
+ #include_next <irq.h>
+ #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch
new file mode 100644 (file)
index 0000000..02d9966
--- /dev/null
@@ -0,0 +1,1701 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,24 +16,206 @@
+ enum ath79_mach_type {
+       ATH79_MACH_GENERIC = 0,
++      ATH79_MACH_ALFA_AP96,           /* ALFA Network AP96 board */
++      ATH79_MACH_ALFA_NX,             /* ALFA Network N2/N5 board */
++      ATH79_MACH_ALL0258N,            /* Allnet ALL0258N */
++      ATH79_MACH_ALL0305,             /* Allnet ALL0305 */
++      ATH79_MACH_ALL0315N,            /* Allnet ALL0315N */
++      ATH79_MACH_ANTMINER_S1, /* Bitmain Antminer S1 */
++      ATH79_MACH_ANTMINER_S3, /* Bitmain Antminer S3 */
++      ATH79_MACH_AP113,               /* Atheros AP113 reference board */
+       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
+       ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
++      ATH79_MACH_AP132,               /* Atheros AP132 reference board */
+       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
+       ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
+       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
++      ATH79_MACH_AP143,               /* Atheros AP143 reference board */
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
++      ATH79_MACH_AP83,                /* Atheros AP83 */
++      ATH79_MACH_AP96,                /* Atheros AP96 */
++      ATH79_MACH_ARCHER_C5,           /* TP-LINK Archer C5 board */
++      ATH79_MACH_ARCHER_C7,           /* TP-LINK Archer C7 board */
++      ATH79_MACH_AW_NR580,            /* AzureWave AW-NR580 */
++      ATH79_MACH_BHU_BXU2000N2_A1,    /* BHU BXU2000n-2 A1 */
++      ATH79_MACH_CAP4200AG,           /* Senao CAP4200AG */
++      ATH79_MACH_CARAMBOLA2,          /* 8devices Carambola2 */
++      ATH79_MACH_CPE510,              /* TP-LINK CPE510 */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
+       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
++      ATH79_MACH_DGL_5500_A1,         /* D-link DGL-5500 rev. A1 */
++      ATH79_MACH_DHP_1565_A1,         /* D-Link DHP-1565 rev. A1 */
++      ATH79_MACH_DIR_505_A1,          /* D-Link DIR-505 rev. A1 */
++      ATH79_MACH_DIR_600_A1,          /* D-Link DIR-600 rev. A1 */
++      ATH79_MACH_DIR_615_C1,          /* D-Link DIR-615 rev. C1 */
++      ATH79_MACH_DIR_615_E1,          /* D-Link DIR-615 rev. E1 */
++      ATH79_MACH_DIR_615_E4,          /* D-Link DIR-615 rev. E4 */
++      ATH79_MACH_DIR_615_I1,          /* D-Link DIR-615 rev. I1 */
++      ATH79_MACH_DIR_825_B1,          /* D-Link DIR-825 rev. B1 */
++      ATH79_MACH_DIR_825_C1,          /* D-Link DIR-825 rev. C1 */
++      ATH79_MACH_DIR_835_A1,          /* D-Link DIR-835 rev. A1 */
++      ATH79_MACH_DLAN_PRO_500_WP,     /* devolo dLAN pro 500 Wireless+ */
++      ATH79_MACH_DLAN_PRO_1200_AC,    /* devolo dLAN pro 1200+ WiFi ac*/
++      ATH79_MACH_DRAGINO2,            /* Dragino Version 2 */
++      ATH79_MACH_ESR900,              /* EnGenius ESR900 */
++      ATH79_MACH_EW_DORIN,            /* embedded wireless Dorin Platform */
++      ATH79_MACH_EW_DORIN_ROUTER,     /* embedded wireless Dorin Router Platform */
++      ATH79_MACH_EAP300V2,            /* EnGenius EAP300 v2 */
++      ATH79_MACH_EAP7660D,            /* Senao EAP7660D */
++      ATH79_MACH_EL_M150,             /* EasyLink EL-M150 */
++      ATH79_MACH_EL_MINI,             /* EasyLink EL-MINI */
++      ATH79_MACH_ESR1750,             /* EnGenius ESR1750 */
++      ATH79_MACH_EPG5000,             /* EnGenius EPG5000 */
++      ATH79_MACH_F9K1115V2,           /* Belkin AC1750DB */
++      ATH79_MACH_GL_INET,             /* GL-CONNECT GL-INET */
++      ATH79_MACH_GS_OOLITE,           /* GS OOLITE V1.0 */
++      ATH79_MACH_HIWIFI_HC6361,       /* HiWiFi HC6361 */
++      ATH79_MACH_JA76PF,              /* jjPlus JA76PF */
++      ATH79_MACH_JA76PF2,             /* jjPlus JA76PF2 */
++      ATH79_MACH_JWAP003,             /* jjPlus JWAP003 */
++      ATH79_MACH_HORNET_UB,           /* ALFA Networks Hornet-UB */
++      ATH79_MACH_MR12,                /* Cisco Meraki MR12 */
++      ATH79_MACH_MR16,                /* Cisco Meraki MR16 */
++      ATH79_MACH_MR600V2,             /* OpenMesh MR600v2 */
++      ATH79_MACH_MR600,               /* OpenMesh MR600 */
++      ATH79_MACH_MR900,               /* OpenMesh MR900 */
++      ATH79_MACH_MR900v2,             /* OpenMesh MR900v2 */
++      ATH79_MACH_MYNET_N600,          /* WD My Net N600 */
++      ATH79_MACH_MYNET_N750,          /* WD My Net N750 */
++      ATH79_MACH_MYNET_REXT,          /* WD My Net Wi-Fi Range Extender */
++      ATH79_MACH_MZK_W04NU,           /* Planex MZK-W04NU */
++      ATH79_MACH_MZK_W300NH,          /* Planex MZK-W300NH */
++      ATH79_MACH_NBG460N,             /* Zyxel NBG460N/550N/550NH */
++      ATH79_MACH_NBG6716,             /* Zyxel NBG6716 */
++      ATH79_MACH_OM2P_HSv2,           /* OpenMesh OM2P-HSv2 */
++      ATH79_MACH_OM2P_HS,             /* OpenMesh OM2P-HS */
++      ATH79_MACH_OM2P_LC,             /* OpenMesh OM2P-LC */
++      ATH79_MACH_OM2Pv2,              /* OpenMesh OM2Pv2 */
++      ATH79_MACH_OM2P,                /* OpenMesh OM2P */
++      ATH79_MACH_OM5P_AN,             /* OpenMesh OM5P-AN */
++      ATH79_MACH_OM5P,                /* OpenMesh OM5P */
++      ATH79_MACH_PB42,                /* Atheros PB42 */
++      ATH79_MACH_PB92,                /* Atheros PB92 */
++      ATH79_MACH_QIHOO_C301,          /* Qihoo 360 C301 */
++      ATH79_MACH_R6100,               /* NETGEAR R6100 */
++      ATH79_MACH_RB_411,              /* MikroTik RouterBOARD 411/411A/411AH */
++      ATH79_MACH_RB_411U,             /* MikroTik RouterBOARD 411U */
++      ATH79_MACH_RB_433,              /* MikroTik RouterBOARD 433/433AH */
++      ATH79_MACH_RB_433U,             /* MikroTik RouterBOARD 433UAH */
++      ATH79_MACH_RB_435G,             /* MikroTik RouterBOARD 435G */
++      ATH79_MACH_RB_450G,             /* MikroTik RouterBOARD 450G */
++      ATH79_MACH_RB_450,              /* MikroTik RouterBOARD 450 */
++      ATH79_MACH_RB_493,              /* Mikrotik RouterBOARD 493/493AH */
++      ATH79_MACH_RB_493G,             /* Mikrotik RouterBOARD 493G */
++      ATH79_MACH_RB_711GR100,         /* Mikrotik RouterBOARD 911/912 boards */
++      ATH79_MACH_RB_750,              /* MikroTik RouterBOARD 750 */
++      ATH79_MACH_RB_750G_R3,          /* MikroTik RouterBOARD 750GL */
++      ATH79_MACH_RB_751,              /* MikroTik RouterBOARD 751 */
++      ATH79_MACH_RB_751G,             /* Mikrotik RouterBOARD 751G */
++      ATH79_MACH_RB_922GS,            /* Mikrotik RouterBOARD 911/922GS boards */
++      ATH79_MACH_RB_951G,             /* Mikrotik RouterBOARD 951G */
++      ATH79_MACH_RB_951U,             /* Mikrotik RouterBOARD 951Ui-2HnD */
++      ATH79_MACH_RB_2011G,            /* Mikrotik RouterBOARD 2011UAS-2HnD */
++      ATH79_MACH_RB_2011L,            /* Mikrotik RouterBOARD 2011L */
++      ATH79_MACH_RB_2011US,           /* Mikrotik RouterBOARD 2011UAS */
++      ATH79_MACH_RB_2011R5,           /* Mikrotik RouterBOARD 2011UiAS(-2Hnd) */
++      ATH79_MACH_RB_SXTLITE2ND,       /* Mikrotik RouterBOARD SXT Lite 2nD */
++      ATH79_MACH_RB_SXTLITE5ND,       /* Mikrotik RouterBOARD SXT Lite 5nD */
++      ATH79_MACH_RW2458N,             /* Redwave RW2458N */
++      ATH79_MACH_SMART_300,           /* NC-LINK SMART-300 */
++      ATH79_MACH_TEW_632BRP,          /* TRENDnet TEW-632BRP */
++      ATH79_MACH_TEW_673GRU,          /* TRENDnet TEW-673GRU */
++      ATH79_MACH_TEW_712BR,           /* TRENDnet TEW-712BR */
++      ATH79_MACH_TEW_732BR,           /* TRENDnet TEW-732BR */
++      ATH79_MACH_MC_MAC1200R,         /* MERCURY MAC1200R*/
++      ATH79_MACH_TL_MR10U,            /* TP-LINK TL-MR10U */
++      ATH79_MACH_TL_MR11U,            /* TP-LINK TL-MR11U */
++      ATH79_MACH_TL_MR13U,            /* TP-LINK TL-MR13U */
++      ATH79_MACH_TL_MR3020,           /* TP-LINK TL-MR3020 */
++      ATH79_MACH_TL_MR3040,           /* TP-LINK TL-MR3040 */
++      ATH79_MACH_TL_MR3040_V2,        /* TP-LINK TL-MR3040 v2 */
++      ATH79_MACH_TL_MR3220,           /* TP-LINK TL-MR3220 */
++      ATH79_MACH_TL_MR3220_V2,        /* TP-LINK TL-MR3220 v2 */
++      ATH79_MACH_TL_MR3420,           /* TP-LINK TL-MR3420 */
++      ATH79_MACH_TL_MR3420_V2,        /* TP-LINK TL-MR3420 v2 */
++      ATH79_MACH_TL_WA701ND_V2,       /* TP-LINK TL-WA701ND v2 */
++      ATH79_MACH_TL_WA750RE,          /* TP-LINK TL-WA750RE */
++       ATH79_MACH_TL_WA7210N_V2,       /* TP-LINK TL-WA7210N v2 */
++      ATH79_MACH_TL_WA7510N_V1,       /* TP-LINK TL-WA7510N v1*/
++      ATH79_MACH_TL_WA850RE,          /* TP-LINK TL-WA850RE */
++      ATH79_MACH_TL_WA860RE,          /* TP-LINK TL-WA860RE */
++      ATH79_MACH_TL_WA801ND_V2,       /* TP-LINK TL-WA801ND v2 */
++      ATH79_MACH_TL_WA830RE_V2,       /* TP-LINK TL-WA830RE v2 */
++      ATH79_MACH_TL_WA901ND,          /* TP-LINK TL-WA901ND */
++      ATH79_MACH_TL_WA901ND_V2,       /* TP-LINK TL-WA901ND v2 */
++      ATH79_MACH_TL_WA901ND_V3,       /* TP-LINK TL-WA901ND v3 */
++      ATH79_MACH_TL_WDR3500,          /* TP-LINK TL-WDR3500 */
++      ATH79_MACH_TL_WDR4300,          /* TP-LINK TL-WDR4300 */
++      ATH79_MACH_TL_WDR4900_V2,       /* TP-LINK TL-WDR4900 v2 */
++      ATH79_MACH_TL_WR1041N_V2,       /* TP-LINK TL-WR1041N v2 */
++      ATH79_MACH_TL_WR1043ND,         /* TP-LINK TL-WR1043ND */
++      ATH79_MACH_TL_WR1043ND_V2,      /* TP-LINK TL-WR1043ND v2 */
++      ATH79_MACH_TL_WR2543N,          /* TP-LINK TL-WR2543N/ND */
++      ATH79_MACH_TL_WR703N,           /* TP-LINK TL-WR703N */
++      ATH79_MACH_TL_WR710N,           /* TP-LINK TL-WR710N */
++      ATH79_MACH_TL_WR720N_V3,        /* TP-LINK TL-WR720N v3/v4 */
++      ATH79_MACH_TL_WR741ND,          /* TP-LINK TL-WR741ND */
++      ATH79_MACH_TL_WR741ND_V4,       /* TP-LINK TL-WR741ND  v4*/
++      ATH79_MACH_TL_WR841N_V1,        /* TP-LINK TL-WR841N v1 */
++      ATH79_MACH_TL_WR841N_V7,        /* TP-LINK TL-WR841N/ND v7 */
++      ATH79_MACH_TL_WR841N_V8,        /* TP-LINK TL-WR841N/ND v8 */
++      ATH79_MACH_TL_WR841N_V9,        /* TP-LINK TL-WR841N/ND v9 */
++      ATH79_MACH_TL_WR842N_V2,        /* TP-LINK TL-WR842N/ND v2 */
++      ATH79_MACH_TL_WR941ND,          /* TP-LINK TL-WR941ND */
++      ATH79_MACH_TL_WR941ND_V5,       /* TP-LINK TL-WR941ND v5 */
++      ATH79_MACH_TUBE2H,              /* Alfa Network Tube2H */
++      ATH79_MACH_UBNT_AIRGW,          /* Ubiquiti AirGateway */
+       ATH79_MACH_UBNT_AIRROUTER,      /* Ubiquiti AirRouter */
+       ATH79_MACH_UBNT_BULLET_M,       /* Ubiquiti Bullet M */
++      ATH79_MACH_UBNT_LOCO_M_XW,      /* Ubiquiti Loco M XW */
++      ATH79_MACH_UBNT_LSSR71,         /* Ubiquiti LS-SR71 */
++      ATH79_MACH_UBNT_LSX,            /* Ubiquiti LSX */
+       ATH79_MACH_UBNT_NANO_M,         /* Ubiquiti NanoStation M */
++      ATH79_MACH_UBNT_NANO_M_XW,      /* Ubiquiti NanoStation M XW */
+       ATH79_MACH_UBNT_ROCKET_M,       /* Ubiquiti Rocket M */
+       ATH79_MACH_UBNT_ROCKET_M_XW,    /* Ubiquiti Rocket M XW*/
+       ATH79_MACH_UBNT_ROCKET_M_TI,    /* Ubiquiti Rocket M TI*/
++      ATH79_MACH_UBNT_RSPRO,          /* Ubiquiti RouterStation Pro */
++      ATH79_MACH_UBNT_RS,             /* Ubiquiti RouterStation */
+       ATH79_MACH_UBNT_UAP_PRO,        /* Ubiquiti UniFi AP Pro */
+       ATH79_MACH_UBNT_UNIFI,          /* Ubiquiti Unifi */
+       ATH79_MACH_UBNT_UNIFI_OUTDOOR,  /* Ubiquiti UnifiAP Outdoor */
++      ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */
+       ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
++      ATH79_MACH_WHR_G301N,           /* Buffalo WHR-G301N */
++      ATH79_MACH_WHR_HP_G300N,        /* Buffalo WHR-HP-G300N */
++      ATH79_MACH_WHR_HP_GN,           /* Buffalo WHR-HP-GN */
++      ATH79_MACH_WLAE_AG300N,         /* Buffalo WLAE-AG300N */
++      ATH79_MACH_WLR8100,             /* SITECOM WLR-8100 */
++      ATH79_MACH_WNDAP360,            /* NETGEAR WNDAP360 */
++      ATH79_MACH_WNDR3700,            /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
++      ATH79_MACH_WNDR3700_V4,         /* NETGEAR WNDR3700v4 */
++      ATH79_MACH_WNDR4300,            /* NETGEAR WNDR4300 */
++      ATH79_MACH_WNR2000,             /* NETGEAR WNR2000 */
++      ATH79_MACH_WNR2000_V3,          /* NETGEAR WNR2000 v3 */
++      ATH79_MACH_WNR2000_V4,          /* NETGEAR WNR2000 v4 */
++      ATH79_MACH_WNR2200,             /* NETGEAR WNR2200 */
++      ATH79_MACH_WNR612_V2,           /* NETGEAR WNR612 v2 */
++      ATH79_MACH_WNR1000_V2,          /* NETGEAR WNR1000 v2 */
++      ATH79_MACH_WP543,               /* Compex WP543 */
++      ATH79_MACH_WPE72,               /* Compex WPE72 */
++      ATH79_MACH_WPJ344,              /* Compex WPJ344 */
++      ATH79_MACH_WPJ531,              /* Compex WPJ531 */
++      ATH79_MACH_WPJ558,              /* Compex WPJ558 */
++      ATH79_MACH_WRT160NL,            /* Linksys WRT160NL */
++      ATH79_MACH_WRT400N,             /* Linksys WRT400N */
++      ATH79_MACH_WZR_HP_AG300H,       /* Buffalo WZR-HP-AG300H */
++      ATH79_MACH_WZR_HP_G300NH,       /* Buffalo WZR-HP-G300NH */
++      ATH79_MACH_WZR_HP_G300NH2,      /* Buffalo WZR-HP-G300NH2 */
++      ATH79_MACH_WZR_HP_G450H,        /* Buffalo WZR-HP-G450H */
++      ATH79_MACH_WZR_450HP2,          /* Buffalo WZR-450HP2 */
++      ATH79_MACH_ZCN_1523H_2,         /* Zcomax ZCN-1523H-2-xx */
++      ATH79_MACH_ZCN_1523H_5,         /* Zcomax ZCN-1523H-5-xx */
+ };
+ #endif /* _ATH79_MACHTYPE_H */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -2,6 +2,90 @@ if ATH79
+ menu "Atheros AR71XX/AR724X/AR913X machine selection"
++config ATH79_MACH_ALFA_AP96
++      bool "ALFA Network AP96 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_HORNET_UB
++      bool "ALFA Network Hornet-UB board support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_ALFA_NX
++      bool "ALFA Network N2/N5 board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_TUBE2H
++      bool "ALFA Network Tube2H board support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_ALL0258N
++      bool "Allnet ALL0258N support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0315N
++      bool "Allnet ALL0315N support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_ANTMINER_S1
++      bool "Bitmain Antminer S1 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_ANTMINER_S3
++      bool "Bitmain Antminer S3 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_AP113
++      bool "Atheros AP113 board support"
++      select SOC_AR724X
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_PB9X_PCI if PCI
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_USB
++      select ATH79_DEV_ETH
++
+ config ATH79_MACH_AP121
+       bool "Atheros AP121 reference board"
+       select SOC_AR933X
+@@ -11,62 +95,1097 @@ config ATH79_MACH_AP121
+       select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+-      help
+-        Say 'Y' here if you want your kernel to support the
+-        Atheros AP121 reference board.
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP121 reference board.
++
++config ATH79_MACH_AP132
++      bool "Atheros AP132 reference board"
++      select SOC_QCA955X
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP132 reference boards.
++
++config ATH79_MACH_AP136
++      bool "Atheros AP136/AP135 reference board"
++      select SOC_QCA955X
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_NFC
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP136 or AP135 reference boards.
++
++config ATH79_MACH_AP143
++      bool "Atheros AP143 reference board"
++      select SOC_QCA953X
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_SPI
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_ETH
++      select ATH79_DEV_M25P80
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP143 reference board.
++
++config ATH79_MACH_AP81
++      bool "Atheros AP81 reference board"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP81 reference board.
++
++config ATH79_MACH_AP83
++      bool "Atheros AP83 board support"
++      select SOC_AR913X
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_AP96
++      bool "Atheros AP96 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_DB120
++      bool "Atheros DB120 reference board"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros DB120 reference board.
++
++config ATH79_MACH_PB42
++      bool "Atheros PB42 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_PB44
++      bool "Atheros PB44 reference board"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_SPI
++      select ATH79_DEV_USB
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros PB44 reference board.
++
++config ATH79_MACH_PB92
++      bool "Atheros PB92 board support"
++      select SOC_AR724X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_PB9X_PCI if PCI
++      select ATH79_DEV_USB
++
++config ATH79_MACH_AW_NR580
++      bool "AzureWave AW-NR580 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_F9K1115V2
++      bool "Belkin AC1750DB board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_EPG5000
++      bool "EnGenius EPG5000 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_ESR1750
++      bool "EnGenius ESR1750 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WHR_HP_G300N
++      bool "Buffalo WHR-HP-G300N board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_WLAE_AG300N
++      bool "Buffalo WLAE-AG300N board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_WLR8100
++      bool "Sitecom WLR-8100 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WZR_HP_AG300H
++      bool "Buffalo WZR-HP-AG300H board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G300NH
++      bool "Buffalo WZR-HP-G300NH board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      select RTL8366_SMI
++
++config ATH79_MACH_WZR_HP_G300NH2
++      bool "Buffalo WZR-HP-G300NH2 board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G450H
++      bool "Buffalo WZR-HP-G450H board support"
++      select SOC_AR724X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_450HP2
++      bool "Buffalo WZR-450HP2 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WP543
++      bool "Compex WP543/WPJ543 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select MYLOADER
++
++config ATH79_MACH_WPE72
++      bool "Compex WPE72/WPE72NX board support"
++      select SOC_AR724X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select MYLOADER
++
++config ATH79_MACH_WPJ344
++      bool "Compex WPJ344 board support"
++      select SOC_AS934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WPJ531
++       bool "Compex WPJ531 board support"
++       select SOC_QCA953X
++       select ATH79_DEV_ETH
++       select ATH79_DEV_GPIO_BUTTONS
++       select ATH79_DEV_LEDS_GPIO
++       select ATH79_DEV_M25P80
++       select ATH79_DEV_USB
++       select ATH79_DEV_WMAC
++
++config ATH79_MACH_WPJ558
++      bool "Compex WPJ558 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_DGL_5500_A1
++      bool "D-Link DGL-5500 A1 support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_USB
++
++config ATH79_MACH_DHP_1565_A1
++      bool "D-Link DHP-1565 rev. A1 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_DIR_505_A1
++      bool "D-Link DIR-505-A1 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_DIR_600_A1
++      bool "D-Link DIR-600 A1/DIR-615 E1/DIR-615 E4 support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_NVRAM
++
++config ATH79_MACH_DIR_615_C1
++      bool "D-Link DIR-615 rev. C1 support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_DIR_615_I1
++      bool "D-Link DIR-615 rev. I1 support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_DIR_825_B1
++      bool "D-Link DIR-825 rev. B1 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_DIR_825_C1
++      bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_DLAN_PRO_500_WP
++      bool "devolo dLAN pro 500 Wireless+ support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_USB
++
++config ATH79_MACH_DLAN_PRO_1200_AC
++      bool "devolo dLAN pro 1200+ WiFi ac support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++
++config ATH79_MACH_DRAGINO2
++      bool "DRAGINO V2 support"
++      select SOC_AR933X
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_ETH
++      select ATH79_DEV_USB
++
++config ATH79_MACH_ESR900
++      bool "EnGenius ESR900 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_EW_DORIN
++      bool "embedded wireless Dorin Platform support"
++      select SOC_AR933X
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_ETH
++      help
++        Say 'Y' here if you want your kernel to support the
++        Dorin Platform from www.80211.de .
++
++config ATH79_MACH_EL_M150
++      bool "EasyLink EL-M150 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_EL_MINI
++      bool "EasyLink EL-MINI support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_GL_INET
++      bool "GL-INET support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_EAP300V2
++      bool "EnGenius EAP300 v2 support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_GS_OOLITE
++       bool "GS Oolite V1 support"
++       select SOC_AR933X
++       select ARH79_DEV_ETH
++       select ARH79_DEV_GPIO_BUTTONS
++       select ATH79_DEV_LEDS_GPIO
++       select ATH79_DEV_M25P80
++       select ATH79_DEV_USB
++       select ATH79_DEV_WMAC
++
++config ATH79_MACH_HIWIFI_HC6361
++      bool "HiWiFi HC6361 board support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_JA76PF
++      bool "jjPlus JA76PF board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_JWAP003
++      bool "jjPlus JWAP003 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WRT160NL
++      bool "Linksys WRT160NL board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_WRT400N
++      bool "Linksys WRT400N board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_R6100
++      bool "NETGEAR R6100 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MC_MAC1200R
++      bool "MERCURY MAC1200R board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_RB4XX
++      bool "MikroTik RouterBOARD 4xx series support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_USB
++
++config ATH79_MACH_RB750
++      bool "MikroTik RouterBOARD 750 support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_USB
++      select ATH79_ROUTERBOOT
++
++config ATH79_MACH_RB91X
++      bool "MikroTik RouterBOARD 91X support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_SPI
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_USB
++      select ATH79_ROUTERBOOT
++
++config ATH79_MACH_RB922
++      bool "MikroTik RouterBOARD 922 support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_ROUTERBOOT
++      select RLE_DECOMPRESS
++
++config ATH79_MACH_RB95X
++       bool "MikroTik RouterBOARD 95X support"
++       select SOC_AR934X
++       select ATH79_DEV_ETH
++       select ATH79_DEV_NFC
++       select ATH79_DEV_WMAC
++       select ATH79_DEV_USB
++       select ATH79_ROUTERBOOT
++
++config ATH79_MACH_RB2011
++      bool "MikroTik RouterBOARD 2011 support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      select ATH79_ROUTERBOOT
++
++config ATH79_MACH_RBSXTLITE
++      bool "MikroTik RouterBOARD SXT Lite"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_NFC
++      select ATH79_DEV_WMAC
++      select ATH79_ROUTERBOOT
++
++config ATH79_MACH_SMART_300
++      bool "NC-LINK SMART-300 board support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WNDAP360
++      bool "NETGEAR WNDAP360 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_WNDR3700
++      bool "NETGEAR WNDR3700 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WNDR4300
++      bool "NETGEAR WNDR3700v4/WNDR4300 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WNR2000
++      bool "NETGEAR WNR2000 board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_WNR2000_V3
++      bool "NETGEAR WNR2000 V3/WNR612 v2/WNR1000 v2 board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++      config ATH79_MACH_WNR2200
++      bool "NETGEAR WNR2200 board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_WNR2000_V4
++      bool "NETGEAR WNR2000 V4"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_OM2P
++      bool "OpenMesh OM2P board support"
++      select SOC_AR724X
++      select SOC_AR933X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_OM5P
++      bool "OpenMesh OM5P board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR12
++      bool "Meraki MR12 board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR16
++      bool "Meraki MR16 board support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR600
++      bool "OpenMesh MR600 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W04NU
++      bool "Planex MZK-W04NU board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W300NH
++      bool "Planex MZK-W300NH board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_RW2458N
++      bool "Redwave RW2458N board support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_CAP4200AG
++      bool "Senao CAP4200AG support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_MR900
++      bool "OpenMesh MR900 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_EAP7660D
++      bool "Senao EAP7660D support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_ARCHER_C7
++      bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_CPE510
++      bool "TP-LINK CPE510 support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR11U
++      bool "TP-LINK TL-MR11U/TL-MR3040 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR13U
++      bool "TP-LINK TL-MR13U support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3020
++      bool "TP-LINK TL-MR3020 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3X20
++      bool "TP-LINK TL-MR3220/3420 support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_TL_WAX50RE
++      bool "TP-LINK TL-WA750/850RE support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WA701ND_V2
++      bool "TP-LINK TL-WA701ND v2 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
+-config ATH79_MACH_AP136
+-      bool "Atheros AP136/AP135 reference board"
+-      select SOC_QCA955X
++config ATH79_MACH_TL_WA7210N_V2
++       bool "TP-LINK TL-WA7210N v2 support"
++       select SOC_AR724X
++       select ATH79_DEV_AP9X_PCI if PCI
++       select ATH79_DEV_ETH
++       select ATH79_DEV_LEDS_GPIO
++       select ATH79_DEV_GPIO_BUTTONS
++       select ATH79_DEV_M25P80
++       select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WA830RE_V2
++      bool "TP-LINK TL-WA830RE v2 support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_NFC
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+-      help
+-        Say 'Y' here if you want your kernel to support the
+-        Atheros AP136 or AP135 reference boards.
+-config ATH79_MACH_AP81
+-      bool "Atheros AP81 reference board"
++config ATH79_MACH_TL_WA901ND
++      bool "TP-LINK TL-WA901ND/TL-WA7510N support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WA901ND_V2
++      bool "TP-LINK TL-WA901ND v2 support"
+       select SOC_AR913X
+       select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+       select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WDR3500
++      bool "TP-LINK TL-WDR3500 board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+-      help
+-        Say 'Y' here if you want your kernel to support the
+-        Atheros AP81 reference board.
+-config ATH79_MACH_DB120
+-      bool "Atheros DB120 reference board"
++config ATH79_MACH_TL_WDR4300
++      bool "TP-LINK TL-WDR3600/4300/4310 board support"
+       select SOC_AR934X
+       select ATH79_DEV_AP9X_PCI if PCI
+       select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+       select ATH79_DEV_M25P80
+-      select ATH79_DEV_NFC
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+-      help
+-        Say 'Y' here if you want your kernel to support the
+-        Atheros DB120 reference board.
+-config ATH79_MACH_PB44
+-      bool "Atheros PB44 reference board"
++config ATH79_MACH_TL_WR703N
++      bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR720N_V3
++      bool "TP-LINK TL-WR720N v3/v4 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR741ND
++      bool "TP-LINK TL-WR741ND support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR741ND_V4
++      bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR841N_V1
++      bool "TP-LINK TL-WR841N v1 support"
+       select SOC_AR71XX
++      select ATH79_DEV_DSA
+       select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR841N_V8
++      bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR841N_V9
++       bool "TP-LINK TL-WR841N/ND v9 support"
++       select SOC_QCA953X
++       select ATH79_DEV_ETH
++       select ATH79_DEV_GPIO_BUTTONS
++       select ATH79_DEV_LEDS_GPIO
++       select ATH79_DEV_M25P80
++       select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR941ND
++      bool "TP-LINK TL-WR941ND support"
++      select SOC_AR913X
++      select ATH79_DEV_DSA
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1041N_V2
++      bool "TP-LINK TL-WR1041N v2 support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1043ND
++      bool "TP-LINK TL-WR1043ND support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1043ND_V2
++      bool "TP-LINK TL-WR1043ND v2 support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR2543N
++      bool "TP-LINK TL-WR2543N/ND support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++
++config ATH79_MACH_TEW_632BRP
++      bool "TRENDnet TEW-632BRP support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_TEW_673GRU
++      bool "TRENDnet TEW-673GRU support"
++      select SOC_AR71XX
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_NVRAM
++
++config ATH79_MACH_TEW_712BR
++      bool "TRENDnet TEW-712BR support"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_TEW_732BR
++      bool "TRENDnet TEW-732BR support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_UBNT
++      bool "Ubiquiti AR71xx based boards support"
++      select SOC_AR71XX
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+-      help
+-        Say 'Y' here if you want your kernel to support the
+-        Atheros PB44 reference board.
+ config ATH79_MACH_UBNT_XM
+       bool "Ubiquiti Networks XM/UniFi boards"
+@@ -83,6 +1202,97 @@ config ATH79_MACH_UBNT_XM
+         Say 'Y' here if you want your kernel to support the
+         Ubiquiti Networks XM (rev 1.0) board.
++config ATH79_MACH_MYNET_N600
++      bool "WD My Net N600 board support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_MYNET_N750
++      bool "WD My Net N750 board support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_MYNET_REXT
++      bool "WD My Net Wi-Fi Range Extender board support"
++      select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_NVRAM
++
++config ATH79_MACH_ZCN_1523H
++      bool "Zcomax ZCN-1523H support"
++      select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++
++config ATH79_MACH_NBG460N
++      bool "Zyxel NBG460N/550N/550NH board support"
++      select SOC_AR913X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_NBG6716
++      bool "Zyxel NBG6716 board support"
++      select SOC_QCA955X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_NFC
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_CARAMBOLA2
++      bool "8devices Carambola2 board"
++      select SOC_AR933X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_BHU_BXU2000N2_A
++      bool "BHU BXU2000n-2 rev. A support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++
++config ATH79_MACH_QIHOO_C301
++      bool "Qihoo 360 C301 board support"
++      select SOC_AR934X
++      select ATH79_DEV_ETH
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_WMAC
++      select ATH79_DEV_USB
++      select ATH79_NVRAM
++
+ endmenu
+ config SOC_AR71XX
+@@ -134,7 +1344,10 @@ config ATH79_DEV_DSA
+ config ATH79_DEV_ETH
+       def_bool n
+-config PCI_AR724X
++config ATH79_DEV_DSA
++      def_bool n
++
++config ATH79_DEV_ETH
+       def_bool n
+ config ATH79_DEV_GPIO_BUTTONS
+@@ -164,6 +1377,11 @@ config ATH79_PCI_ATH9K_FIXUP
+       def_bool n
+ config ATH79_ROUTERBOOT
++      select RLE_DECOMPRESS
++      select LZO_DECOMPRESS
++      def_bool n
++
++config PCI_AR724X
+       def_bool n
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -38,9 +38,132 @@ obj-$(CONFIG_ATH79_ROUTERBOOT)             += route
+ #
+ # Machines
+ #
++obj-$(CONFIG_ATH79_MACH_ALFA_AP96)    += mach-alfa-ap96.o
++obj-$(CONFIG_ATH79_MACH_ALFA_NX)      += mach-alfa-nx.o
++obj-$(CONFIG_ATH79_MACH_ALL0258N)     += mach-all0258n.o
++obj-$(CONFIG_ATH79_MACH_ALL0315N)     += mach-all0315n.o
++obj-$(CONFIG_ATH79_MACH_ANTMINER_S1)+= mach-antminer-s1.o
++obj-$(CONFIG_ATH79_MACH_ANTMINER_S3)+= mach-antminer-s3.o
++obj-$(CONFIG_ATH79_MACH_AP113)                += mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121)                += mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP132)                += mach-ap132.o
+ obj-$(CONFIG_ATH79_MACH_AP136)                += mach-ap136.o
++obj-$(CONFIG_ATH79_MACH_AP143)                += mach-ap143.o
+ obj-$(CONFIG_ATH79_MACH_AP81)         += mach-ap81.o
++obj-$(CONFIG_ATH79_MACH_AP83)         += mach-ap83.o
++obj-$(CONFIG_ATH79_MACH_AP96)         += mach-ap96.o
++obj-$(CONFIG_ATH79_MACH_ARCHER_C7)    += mach-archer-c7.o
++obj-$(CONFIG_ATH79_MACH_AW_NR580)     += mach-aw-nr580.o
++obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o
++obj-$(CONFIG_ATH79_MACH_CAP4200AG)    += mach-cap4200ag.o
++obj-$(CONFIG_ATH79_MACH_CPE510)               += mach-cpe510.o
+ obj-$(CONFIG_ATH79_MACH_DB120)                += mach-db120.o
++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP)      += mach-dlan-pro-500-wp.o
++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC)     += mach-dlan-pro-1200-ac.o
++obj-$(CONFIG_ATH79_MACH_DGL_5500_A1)  += mach-dgl-5500-a1.o
++obj-$(CONFIG_ATH79_MACH_DHP_1565_A1)  += mach-dhp-1565-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_505_A1)   += mach-dir-505-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_600_A1)   += mach-dir-600-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_615_C1)   += mach-dir-615-c1.o
++obj-$(CONFIG_ATH79_MACH_DIR_615_I1)   += mach-dir-615-i1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_B1)   += mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_C1)   += mach-dir-825-c1.o
++obj-$(CONFIG_ATH79_MACH_DRAGINO2)     += mach-dragino2.o
++obj-$(CONFIG_ATH79_MACH_ESR900)       += mach-esr900.o
++obj-$(CONFIG_ATH79_MACH_EW_DORIN)     += mach-ew-dorin.o
++obj-$(CONFIG_ATH79_MACH_EAP300V2)     += mach-eap300v2.o
++obj-$(CONFIG_ATH79_MACH_EAP7660D)     += mach-eap7660d.o
++obj-$(CONFIG_ATH79_MACH_EL_M150)      += mach-el-m150.o
++obj-$(CONFIG_ATH79_MACH_EL_MINI)      += mach-el-mini.o
++obj-$(CONFIG_ATH79_MACH_EPG5000)      += mach-epg5000.o
++obj-$(CONFIG_ATH79_MACH_ESR1750)      += mach-esr1750.o
++obj-$(CONFIG_ATH79_MACH_F9K1115V2)    += mach-f9k1115v2.o
++obj-$(CONFIG_ATH79_MACH_GL_INET)      += mach-gl-inet.o
++obj-$(CONFIG_ATH79_MACH_GS_OOLITE)    += mach-gs-oolite.o
++obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361)        += mach-hiwifi-hc6361.o
++obj-$(CONFIG_ATH79_MACH_JA76PF)               += mach-ja76pf.o
++obj-$(CONFIG_ATH79_MACH_JWAP003)      += mach-jwap003.o
++obj-$(CONFIG_ATH79_MACH_HORNET_UB)    += mach-hornet-ub.o
++obj-$(CONFIG_ATH79_MACH_MC_MAC1200R)     += mach-mc-mac1200r.o
++obj-$(CONFIG_ATH79_MACH_MR12)         += mach-mr12.o
++obj-$(CONFIG_ATH79_MACH_MR16)         += mach-mr16.o
++obj-$(CONFIG_ATH79_MACH_MR600)                += mach-mr600.o
++obj-$(CONFIG_ATH79_MACH_MR900)                += mach-mr900.o
++obj-$(CONFIG_ATH79_MACH_MYNET_N600)   += mach-mynet-n600.o
++obj-$(CONFIG_ATH79_MACH_MYNET_N750)   += mach-mynet-n750.o
++obj-$(CONFIG_ATH79_MACH_MYNET_REXT)   += mach-mynet-rext.o
++obj-$(CONFIG_ATH79_MACH_MZK_W04NU)    += mach-mzk-w04nu.o
++obj-$(CONFIG_ATH79_MACH_MZK_W300NH)   += mach-mzk-w300nh.o
++obj-$(CONFIG_ATH79_MACH_NBG460N)      += mach-nbg460n.o
++obj-$(CONFIG_ATH79_MACH_OM2P)         += mach-om2p.o
++obj-$(CONFIG_ATH79_MACH_OM5P)         += mach-om5p.o
++obj-$(CONFIG_ATH79_MACH_PB42)         += mach-pb42.o
+ obj-$(CONFIG_ATH79_MACH_PB44)         += mach-pb44.o
++obj-$(CONFIG_ATH79_MACH_PB92)         += mach-pb92.o
++obj-$(CONFIG_ATH79_MACH_QIHOO_C301)   += mach-qihoo-c301.o
++obj-$(CONFIG_ATH79_MACH_R6100)                += mach-r6100.o
++obj-$(CONFIG_ATH79_MACH_RB4XX)                += mach-rb4xx.o
++obj-$(CONFIG_ATH79_MACH_RB750)                += mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RB91X)                += mach-rb91x.o
++obj-$(CONFIG_ATH79_MACH_RB922)                += mach-rb922.o
++obj-$(CONFIG_ATH79_MACH_RB95X)                += mach-rb95x.o
++obj-$(CONFIG_ATH79_MACH_RB2011)               += mach-rb2011.o
++obj-$(CONFIG_ATH79_MACH_RBSXTLITE)    += mach-rbsxtlite.o
++obj-$(CONFIG_ATH79_MACH_RW2458N)      += mach-rw2458n.o
++obj-$(CONFIG_ATH79_MACH_SMART_300)    += mach-smart-300.o
++obj-$(CONFIG_ATH79_MACH_TEW_632BRP)   += mach-tew-632brp.o
++obj-$(CONFIG_ATH79_MACH_TEW_673GRU)   += mach-tew-673gru.o
++obj-$(CONFIG_ATH79_MACH_TEW_712BR)    += mach-tew-712br.o
++obj-$(CONFIG_ATH79_MACH_TEW_732BR)    += mach-tew-732br.o
++obj-$(CONFIG_ATH79_MACH_TL_MR11U)     += mach-tl-mr11u.o
++obj-$(CONFIG_ATH79_MACH_TL_MR13U)     += mach-tl-mr13u.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3020)    += mach-tl-mr3020.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3X20)    += mach-tl-mr3x20.o
++obj-$(CONFIG_ATH79_MACH_TL_WAX50RE)     += mach-tl-wax50re.o
++obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2)        += mach-tl-wa701nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2)        += mach-tl-wa7210n-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2)        += mach-tl-wa830re-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND)   += mach-tl-wa901nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2)        += mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR3500)     += mach-tl-wdr3500.o
++obj-$(CONFIG_ATH79_MACH_TL_WDR4300)     += mach-tl-wdr4300.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND)   += mach-tl-wr741nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4)        += mach-tl-wr741nd-v4.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o
++obj-$(CONFIG_ATH79_MACH_TL_WR941ND)   += mach-tl-wr941nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2)        += mach-tl-wr1041n-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND)  += mach-tl-wr1043nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2)       += mach-tl-wr1043nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WR2543N)   += mach-tl-wr2543n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR703N)    += mach-tl-wr703n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o
++obj-$(CONFIG_ATH79_MACH_TUBE2H)               += mach-tube2h.o
++obj-$(CONFIG_ATH79_MACH_UBNT)         += mach-ubnt.o
+ obj-$(CONFIG_ATH79_MACH_UBNT_XM)      += mach-ubnt-xm.o
++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N)  += mach-wlae-ag300n.o
++obj-$(CONFIG_ATH79_MACH_WLR8100)      += mach-wlr8100.o
++obj-$(CONFIG_ATH79_MACH_WNDAP360)     += mach-wndap360.o
++obj-$(CONFIG_ATH79_MACH_WNDR3700)     += mach-wndr3700.o
++obj-$(CONFIG_ATH79_MACH_WNDR4300)     += mach-wndr4300.o
++obj-$(CONFIG_ATH79_MACH_WNR2000)      += mach-wnr2000.o
++obj-$(CONFIG_ATH79_MACH_WNR2000_V3)   += mach-wnr2000-v3.o
++obj-$(CONFIG_ATH79_MACH_WNR2000_V4)   += mach-wnr2000-v4.o
++obj-$(CONFIG_ATH79_MACH_WNR2200)      += mach-wnr2200.o
++obj-$(CONFIG_ATH79_MACH_WP543)                += mach-wp543.o
++obj-$(CONFIG_ATH79_MACH_WPE72)                += mach-wpe72.o
++obj-$(CONFIG_ATH79_MACH_WPJ344)       += mach-wpj344.o
++obj-$(CONFIG_ATH79_MACH_WPJ531)       += mach-wpj531.o
++obj-$(CONFIG_ATH79_MACH_WPJ558)       += mach-wpj558.o
++obj-$(CONFIG_ATH79_MACH_WRT160NL)     += mach-wrt160nl.o
++obj-$(CONFIG_ATH79_MACH_WRT400N)      += mach-wrt400n.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH)        += mach-wzr-hp-g300nh.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2)       += mach-wzr-hp-g300nh2.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H)        += mach-wzr-hp-ag300h.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
++obj-$(CONFIG_ATH79_MACH_WZR_450HP2)   += mach-wzr-450hp2.o
++obj-$(CONFIG_ATH79_MACH_ZCN_1523H)    += mach-zcn-1523h.o
++obj-$(CONFIG_ATH79_MACH_CARAMBOLA2)   += mach-carambola2.o
++obj-$(CONFIG_ATH79_MACH_NBG6716)      += mach-nbg6716.o
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -130,6 +130,13 @@ void __init prom_init(void)
+               initrd_end = initrd_start + fw_getenvl("initrd_size");
+       }
+ #endif
++
++      if (strstr(arcs_cmdline, "board=750Gr3") ||
++          strstr(arcs_cmdline, "board=951G") ||
++          strstr(arcs_cmdline, "board=2011L") ||
++          strstr(arcs_cmdline, "board=711Gr100") ||
++          strstr(arcs_cmdline, "board=922gs"))
++              ath79_prom_append_cmdline("console", "ttyS0,115200");
+ }
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
deleted file mode 100644 (file)
index 2c624b3..0000000
+++ /dev/null
@@ -1,721 +0,0 @@
-From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
-Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
-From: Matthias Schiffer <mschiffer@universe-factory.net>
-Date: Sat, 29 Mar 2014 20:26:08 +0100
-Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
-
-Note that the clock calculation looks very similar to the QCA955x, but the
-meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
----
- arch/mips/ath79/Kconfig                        |  6 +-
- arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
- arch/mips/ath79/common.c                       |  4 ++
- arch/mips/ath79/dev-common.c                   |  1 +
- arch/mips/ath79/dev-wmac.c                     | 20 +++++++
- arch/mips/ath79/early_printk.c                 |  1 +
- arch/mips/ath79/gpio.c                         |  4 +-
- arch/mips/ath79/irq.c                          |  4 ++
- arch/mips/ath79/setup.c                        |  8 ++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
- arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
- 11 files changed, 182 insertions(+), 3 deletions(-)
-
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1229,6 +1229,10 @@ config SOC_AR934X
-       select PCI_AR724X if PCI
-       def_bool n
-+config SOC_QCA953X
-+      select USB_ARCH_HAS_EHCI
-+      def_bool n
-+
- config SOC_QCA955X
-       select HW_HAS_PCI
-       select PCI_AR724X if PCI
-@@ -1271,7 +1275,7 @@ config ATH79_DEV_USB
-       def_bool n
- config ATH79_DEV_WMAC
--      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
-+      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
-       def_bool n
- config ATH79_NVRAM
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
-       iounmap(dpll_base);
- }
-+static void __init qca953x_clocks_init(void)
-+{
-+      unsigned long ref_rate;
-+      unsigned long cpu_rate;
-+      unsigned long ddr_rate;
-+      unsigned long ahb_rate;
-+      u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
-+      u32 cpu_pll, ddr_pll;
-+      u32 bootstrap;
-+
-+      bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
-+      if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
-+              ref_rate = 40 * 1000 * 1000;
-+      else
-+              ref_rate = 25 * 1000 * 1000;
-+
-+      pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
-+      out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+                QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+      ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+                QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
-+      nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
-+             QCA953X_PLL_CPU_CONFIG_NINT_MASK;
-+      frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-+             QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
-+
-+      cpu_pll = nint * ref_rate / ref_div;
-+      cpu_pll += frac * (ref_rate >> 6) / ref_div;
-+      cpu_pll /= (1 << out_div);
-+
-+      pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
-+      out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+                QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+      ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+                QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
-+      nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
-+             QCA953X_PLL_DDR_CONFIG_NINT_MASK;
-+      frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-+             QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
-+
-+      ddr_pll = nint * ref_rate / ref_div;
-+      ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
-+      ddr_pll /= (1 << out_div);
-+
-+      clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
-+
-+      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+                QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+              cpu_rate = ref_rate;
-+      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-+              cpu_rate = cpu_pll / (postdiv + 1);
-+      else
-+              cpu_rate = ddr_pll / (postdiv + 1);
-+
-+      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+                QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+              ddr_rate = ref_rate;
-+      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-+              ddr_rate = ddr_pll / (postdiv + 1);
-+      else
-+              ddr_rate = cpu_pll / (postdiv + 1);
-+
-+      postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+                QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+              ahb_rate = ref_rate;
-+      else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+              ahb_rate = ddr_pll / (postdiv + 1);
-+      else
-+              ahb_rate = cpu_pll / (postdiv + 1);
-+
-+      ath79_add_sys_clkdev("ref", ref_rate);
-+      ath79_add_sys_clkdev("cpu", cpu_rate);
-+      ath79_add_sys_clkdev("ddr", ddr_rate);
-+      ath79_add_sys_clkdev("ahb", ahb_rate);
-+
-+      clk_add_alias("wdt", NULL, "ref", NULL);
-+      clk_add_alias("uart", NULL, "ref", NULL);
-+}
-+
- static void __init qca955x_clocks_init(void)
- {
-       unsigned long ref_rate;
-@@ -447,6 +532,8 @@ void __init ath79_clocks_init(void)
-               ar933x_clocks_init();
-       else if (soc_is_ar934x())
-               ar934x_clocks_init();
-+      else if (soc_is_qca953x())
-+              qca953x_clocks_init();
-       else if (soc_is_qca955x())
-               qca955x_clocks_init();
-       else
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
-               reg = AR933X_RESET_REG_RESET_MODULE;
-       else if (soc_is_ar934x())
-               reg = AR934X_RESET_REG_RESET_MODULE;
-+      else if (soc_is_qca953x())
-+              reg = QCA953X_RESET_REG_RESET_MODULE;
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-       else
-@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
-               reg = AR933X_RESET_REG_RESET_MODULE;
-       else if (soc_is_ar934x())
-               reg = AR934X_RESET_REG_RESET_MODULE;
-+      else if (soc_is_qca953x())
-+              reg = QCA953X_RESET_REG_RESET_MODULE;
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-       else
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -93,6 +93,7 @@ void __init ath79_register_uart(void)
-           soc_is_ar724x() ||
-           soc_is_ar913x() ||
-           soc_is_ar934x() ||
-+          soc_is_qca953x() ||
-           soc_is_qca955x()) {
-               ath79_uart_data[0].uartclk = uart_clk_rate;
-               platform_device_register(&ath79_uart_device);
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
-                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
- }
-+static void __init qca953x_usb_setup(void)
-+{
-+      u32 bootstrap;
-+
-+      bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
-+
-+      ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
-+      udelay(1000);
-+
-+      ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
-+      udelay(1000);
-+
-+      ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
-+      udelay(1000);
-+
-+      ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
-+      udelay(1000);
-+
-+      ath79_usb_register("ehci-platform", -1,
-+                         QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
-+                         ATH79_CPU_IRQ(3),
-+                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-+}
-+
- static void qca955x_usb_reset_notifier(struct platform_device *pdev)
- {
-       u32 base;
-@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
-               ar933x_usb_setup();
-       else if (soc_is_ar934x())
-               ar934x_usb_setup();
-+      else if (soc_is_qca953x())
-+              qca953x_usb_setup();
-       else if (soc_is_qca955x())
-               qca955x_usb_setup();
-       else
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
-       return -ETIMEDOUT;
- }
--static int ar933x_r1_get_wmac_revision(void)
-+static int ar93xx_get_soc_revision(void)
- {
-       return ath79_soc_rev;
- }
-@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
-               ath79_wmac_data.is_clk_25mhz = true;
-       if (ath79_soc_rev == 1)
--              ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
-+              ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
-       ath79_wmac_data.external_reset = ar933x_wmac_reset;
- }
-@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
-               ath79_wmac_data.is_clk_25mhz = true;
- }
-+static void qca953x_wmac_setup(void)
-+{
-+      u32 t;
-+
-+      ath79_wmac_device.name = "qca953x_wmac";
-+
-+      ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
-+      ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
-+      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-+      ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
-+
-+      t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
-+      if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
-+              ath79_wmac_data.is_clk_25mhz = false;
-+      else
-+              ath79_wmac_data.is_clk_25mhz = true;
-+
-+      ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
-+}
-+
- static void qca955x_wmac_setup(void)
- {
-       u32 t;
-@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
-               ar933x_wmac_setup();
-       else if (soc_is_ar934x())
-               ar934x_wmac_setup();
-+      else if (soc_is_qca953x())
-+              qca953x_wmac_setup();
-       else if (soc_is_qca955x())
-               qca955x_wmac_setup();
-       else
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -114,6 +114,8 @@ static void prom_putchar_init(void)
-       case REV_ID_MAJOR_AR9341:
-       case REV_ID_MAJOR_AR9342:
-       case REV_ID_MAJOR_AR9344:
-+      case REV_ID_MAJOR_QCA9533:
-+      case REV_ID_MAJOR_QCA9533_V2:
-       case REV_ID_MAJOR_QCA9556:
-       case REV_ID_MAJOR_QCA9558:
-               _prom_putchar = prom_putchar_ar71xx;
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
-           soc_is_ar913x() ||
-           soc_is_ar933x())
-               reg = AR71XX_GPIO_REG_FUNC;
--      else if (soc_is_ar934x())
-+      else if (soc_is_ar934x() || soc_is_qca953x())
-               reg = AR934X_GPIO_REG_FUNC;
-       else
-               BUG();
-@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
-       unsigned int reg;
-       u32 t, s;
--      BUG_ON(!soc_is_ar934x());
-+      BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
-       if (gpio >= AR934X_GPIO_COUNT)
-               return;
-@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
-               ath79_gpio_count = AR933X_GPIO_COUNT;
-       else if (soc_is_ar934x())
-               ath79_gpio_count = AR934X_GPIO_COUNT;
-+      else if (soc_is_qca953x())
-+              ath79_gpio_count = QCA953X_GPIO_COUNT;
-       else if (soc_is_qca955x())
-               ath79_gpio_count = QCA955X_GPIO_COUNT;
-       else
-@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
-       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
-       ath79_gpio_chip.ngpio = ath79_gpio_count;
--      if (soc_is_ar934x() || soc_is_qca955x()) {
-+      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
-               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
-               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
-       }
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
-       else if (soc_is_ar724x() ||
-                soc_is_ar933x() ||
-                soc_is_ar934x() ||
-+               soc_is_qca953x() ||
-                soc_is_qca955x())
-               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
-       else
-@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
-       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
- }
-+static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
-+{
-+      u32 status;
-+
-+      disable_irq_nosync(irq);
-+
-+      status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
-+
-+      if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
-+              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
-+              generic_handle_irq(ATH79_IP2_IRQ(0));
-+      } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
-+              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
-+              generic_handle_irq(ATH79_IP2_IRQ(1));
-+      } else {
-+              spurious_interrupt();
-+      }
-+
-+      enable_irq(irq);
-+}
-+
-+static void qca953x_irq_init(void)
-+{
-+      int i;
-+
-+      for (i = ATH79_IP2_IRQ_BASE;
-+           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
-+}
-+
- static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
- {
-       u32 status;
-@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
-       do_IRQ(ATH79_CPU_IRQ(3));
- }
-+static void qca953x_ip3_handler(void)
-+{
-+      ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
-+      do_IRQ(ATH79_CPU_IRQ(3));
-+}
-+
- void __init arch_init_irq(void)
- {
-       if (soc_is_ar71xx()) {
-@@ -352,6 +391,9 @@ void __init arch_init_irq(void)
-       } else if (soc_is_ar934x()) {
-               ath79_ip2_handler = ath79_default_ip2_handler;
-               ath79_ip3_handler = ar934x_ip3_handler;
-+      } else if (soc_is_qca953x()) {
-+              ath79_ip2_handler = ath79_default_ip2_handler;
-+              ath79_ip3_handler = qca953x_ip3_handler;
-       } else if (soc_is_qca955x()) {
-               ath79_ip2_handler = ath79_default_ip2_handler;
-               ath79_ip3_handler = ath79_default_ip3_handler;
-@@ -364,6 +406,8 @@ void __init arch_init_irq(void)
-       if (soc_is_ar934x())
-               ar934x_ip2_irq_init();
-+      else if (soc_is_qca953x())
-+              qca953x_irq_init();
-       else if (soc_is_qca955x())
-               qca955x_irq_init();
- }
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
-       u32 major;
-       u32 minor;
-       u32 rev = 0;
-+      u32 ver = 1;
-       id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
-       major = id & REV_ID_MAJOR_MASK;
-@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
-               rev = id & AR934X_REV_ID_REVISION_MASK;
-               break;
-+      case REV_ID_MAJOR_QCA9533_V2:
-+              ver = 2;
-+              /* drop through */
-+
-+      case REV_ID_MAJOR_QCA9533:
-+              ath79_soc = ATH79_SOC_QCA9533;
-+              chip = "9533";
-+              rev = id & QCA953X_REV_ID_REVISION_MASK;
-+              break;
-+
-       case REV_ID_MAJOR_QCA9556:
-               ath79_soc = ATH79_SOC_QCA9556;
-               chip = "9556";
-@@ -169,7 +180,7 @@ static void __init ath79_detect_sys_type
-       ath79_soc_rev = rev;
--      if (soc_is_qca955x())
-+      if (soc_is_qca953x() || soc_is_qca955x())
-               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
-                       chip, rev);
-       else
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -105,6 +105,21 @@
- #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
- #define AR934X_SRIF_SIZE      0x1000
-+#define QCA953X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
-+#define QCA953X_GMAC_SIZE     0x14
-+#define QCA953X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
-+#define QCA953X_WMAC_SIZE     0x20000
-+#define QCA953X_EHCI_BASE     0x1b000000
-+#define QCA953X_EHCI_SIZE     0x200
-+#define QCA953X_SRIF_BASE     (AR71XX_APB_BASE + 0x00116000)
-+#define QCA953X_SRIF_SIZE     0x1000
-+
-+#define QCA953X_PCI_CFG_BASE0 0x14000000
-+#define QCA953X_PCI_CTRL_BASE0        (AR71XX_APB_BASE + 0x000f0000)
-+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
-+#define QCA953X_PCI_MEM_BASE0 0x10000000
-+#define QCA953X_PCI_MEM_SIZE  0x02000000
-+
- #define QCA955X_PCI_MEM_BASE0 0x10000000
- #define QCA955X_PCI_MEM_BASE1 0x12000000
- #define QCA955X_PCI_MEM_SIZE  0x02000000
-@@ -173,6 +188,12 @@
- #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
- #define AR934X_DDR_REG_FLUSH_WMAC     0xac
-+#define QCA953X_DDR_REG_FLUSH_GE0     0x9c
-+#define QCA953X_DDR_REG_FLUSH_GE1     0xa0
-+#define QCA953X_DDR_REG_FLUSH_USB     0xa4
-+#define QCA953X_DDR_REG_FLUSH_PCIE    0xa8
-+#define QCA953X_DDR_REG_FLUSH_WMAC    0xac
-+
- /*
-  * PLL block
-  */
-@@ -279,6 +300,44 @@
- #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
-+#define QCA953X_PLL_CPU_CONFIG_REG            0x00
-+#define QCA953X_PLL_DDR_CONFIG_REG            0x04
-+#define QCA953X_PLL_CLK_CTRL_REG              0x08
-+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG  0x24
-+#define QCA953X_PLL_ETH_XMII_CONTROL_REG      0x2c
-+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG     0x48
-+
-+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
-+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
-+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT     6
-+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK      0x3f
-+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
-+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK    0x7
-+
-+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
-+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff
-+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT     10
-+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK      0x3f
-+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT   16
-+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK    0x1f
-+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT   23
-+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK    0x7
-+
-+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
-+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
-+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
-+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
-+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
-+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
-+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
-+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
-+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
-+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL               BIT(20)
-+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
-+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
-+
- #define QCA955X_PLL_CPU_CONFIG_REG            0x00
- #define QCA955X_PLL_DDR_CONFIG_REG            0x04
- #define QCA955X_PLL_CLK_CTRL_REG              0x08
-@@ -355,6 +414,10 @@
- #define AR934X_RESET_REG_BOOTSTRAP            0xb0
- #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
-+#define QCA953X_RESET_REG_RESET_MODULE                0x1c
-+#define QCA953X_RESET_REG_BOOTSTRAP           0xb0
-+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS        0xac
-+
- #define QCA955X_RESET_REG_RESET_MODULE                0x1c
- #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
- #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
-@@ -450,6 +513,27 @@
- #define AR934X_RESET_MBOX             BIT(1)
- #define AR934X_RESET_I2S              BIT(0)
-+#define QCA953X_RESET_USB_EXT_PWR     BIT(29)
-+#define QCA953X_RESET_EXTERNAL                BIT(28)
-+#define QCA953X_RESET_RTC             BIT(27)
-+#define QCA953X_RESET_FULL_CHIP               BIT(24)
-+#define QCA953X_RESET_GE1_MDIO                BIT(23)
-+#define QCA953X_RESET_GE0_MDIO                BIT(22)
-+#define QCA953X_RESET_CPU_NMI         BIT(21)
-+#define QCA953X_RESET_CPU_COLD                BIT(20)
-+#define QCA953X_RESET_DDR             BIT(16)
-+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
-+#define QCA953X_RESET_GE1_MAC         BIT(13)
-+#define QCA953X_RESET_ETH_SWITCH_ANALOG       BIT(12)
-+#define QCA953X_RESET_USB_PHY_ANALOG  BIT(11)
-+#define QCA953X_RESET_GE0_MAC         BIT(9)
-+#define QCA953X_RESET_ETH_SWITCH      BIT(8)
-+#define QCA953X_RESET_PCIE_PHY                BIT(7)
-+#define QCA953X_RESET_PCIE            BIT(6)
-+#define QCA953X_RESET_USB_HOST                BIT(5)
-+#define QCA953X_RESET_USB_PHY         BIT(4)
-+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
-+
- #define QCA955X_RESET_HOST            BIT(31)
- #define QCA955X_RESET_SLIC            BIT(30)
- #define QCA955X_RESET_HDMA            BIT(29)
-@@ -503,6 +587,13 @@
- #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
- #define AR934X_BOOTSTRAP_DDR1         BIT(0)
-+#define QCA953X_BOOTSTRAP_SW_OPTION2  BIT(12)
-+#define QCA953X_BOOTSTRAP_SW_OPTION1  BIT(11)
-+#define QCA953X_BOOTSTRAP_EJTAG_MODE  BIT(5)
-+#define QCA953X_BOOTSTRAP_REF_CLK_40  BIT(4)
-+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
-+#define QCA953X_BOOTSTRAP_DDR1                BIT(0)
-+
- #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
- #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
-@@ -523,6 +614,24 @@
-        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
-        AR934X_PCIE_WMAC_INT_PCIE_RC3)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC               BIT(0)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_TX         BIT(1)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP               BIT(2)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP               BIT(3)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC         BIT(4)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0                BIT(5)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1                BIT(6)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2                BIT(7)
-+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3                BIT(8)
-+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
-+      (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
-+       QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
-+
-+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
-+      (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
-+       QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
-+       QCA953X_PCIE_WMAC_INT_PCIE_RC3)
-+
- #define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
- #define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
- #define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
-@@ -565,6 +674,8 @@
- #define REV_ID_MAJOR_AR9341           0x0120
- #define REV_ID_MAJOR_AR9342           0x1120
- #define REV_ID_MAJOR_AR9344           0x2120
-+#define REV_ID_MAJOR_QCA9533          0x0140
-+#define REV_ID_MAJOR_QCA9533_V2               0x0160
- #define REV_ID_MAJOR_QCA9556          0x0130
- #define REV_ID_MAJOR_QCA9558          0x1130
-@@ -587,6 +698,8 @@
- #define AR934X_REV_ID_REVISION_MASK   0xf
-+#define QCA953X_REV_ID_REVISION_MASK  0xf
-+
- #define QCA955X_REV_ID_REVISION_MASK  0xf
- /*
-@@ -634,12 +747,32 @@
- #define AR934X_GPIO_REG_OUT_FUNC5     0x40
- #define AR934X_GPIO_REG_FUNC          0x6c
-+#define QCA953X_GPIO_REG_OUT_FUNC0    0x2c
-+#define QCA953X_GPIO_REG_OUT_FUNC1    0x30
-+#define QCA953X_GPIO_REG_OUT_FUNC2    0x34
-+#define QCA953X_GPIO_REG_OUT_FUNC3    0x38
-+#define QCA953X_GPIO_REG_OUT_FUNC4    0x3c
-+#define QCA953X_GPIO_REG_IN_ENABLE0   0x44
-+#define QCA953X_GPIO_REG_FUNC         0x6c
-+
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS1          10
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS2          11
-+#define QCA953X_GPIO_OUT_MUX_SPI_CS0          9
-+#define QCA953X_GPIO_OUT_MUX_SPI_CLK          8
-+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI         12
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK1                41
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK2                42
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK3                43
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
-+#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
-+
- #define AR71XX_GPIO_COUNT             16
- #define AR7240_GPIO_COUNT             18
- #define AR7241_GPIO_COUNT             20
- #define AR913X_GPIO_COUNT             22
- #define AR933X_GPIO_COUNT             30
- #define AR934X_GPIO_COUNT             23
-+#define QCA953X_GPIO_COUNT            18
- #define QCA955X_GPIO_COUNT            24
- /*
-@@ -663,6 +796,24 @@
- #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
- #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
-+#define QCA953X_SRIF_CPU_DPLL1_REG    0x1c0
-+#define QCA953X_SRIF_CPU_DPLL2_REG    0x1c4
-+#define QCA953X_SRIF_CPU_DPLL3_REG    0x1c8
-+
-+#define QCA953X_SRIF_DDR_DPLL1_REG    0x240
-+#define QCA953X_SRIF_DDR_DPLL2_REG    0x244
-+#define QCA953X_SRIF_DDR_DPLL3_REG    0x248
-+
-+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT       27
-+#define QCA953X_SRIF_DPLL1_REFDIV_MASK        0x1f
-+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
-+#define QCA953X_SRIF_DPLL1_NINT_MASK  0x1ff
-+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
-+
-+#define QCA953X_SRIF_DPLL2_LOCAL_PLL  BIT(30)
-+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT       13
-+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK        0x7
-+
- #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
- #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
- #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
-@@ -804,6 +955,16 @@
- #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
- /*
-+ * QCA953X GMAC Interface
-+ */
-+#define QCA953X_GMAC_REG_ETH_CFG              0x00
-+
-+#define QCA953X_ETH_CFG_SW_ONLY_MODE          BIT(6)
-+#define QCA953X_ETH_CFG_SW_PHY_SWAP           BIT(7)
-+#define QCA953X_ETH_CFG_SW_APB_ACCESS         BIT(9)
-+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
-+
-+/*
-  * QCA955X GMAC Interface
-  */
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -32,6 +32,7 @@ enum ath79_soc_type {
-       ATH79_SOC_AR9341,
-       ATH79_SOC_AR9342,
-       ATH79_SOC_AR9344,
-+      ATH79_SOC_QCA9533,
-       ATH79_SOC_QCA9556,
-       ATH79_SOC_QCA9558,
- };
-@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
-       return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
- }
-+static inline int soc_is_qca9533(void)
-+{
-+      return ath79_soc == ATH79_SOC_QCA9533;
-+}
-+
-+static inline int soc_is_qca953x(void)
-+{
-+      return soc_is_qca9533();
-+}
-+
- static inline int soc_is_qca9556(void)
- {
-       return ath79_soc == ATH79_SOC_QCA9556;
diff --git a/target/linux/ar71xx/patches-4.1/718-MIPS-ath79-add-EPG5000-support.patch b/target/linux/ar71xx/patches-4.1/718-MIPS-ath79-add-EPG5000-support.patch
deleted file mode 100644 (file)
index a47e24d..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -196,6 +196,17 @@ config ATH79_MACH_F9K1115V2
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
-+config ATH79_MACH_EPG5000
-+      bool "EnGenius EPG5000 board support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      select ATH79_NVRAM
-+
- config ATH79_MACH_ESR1750
-       bool "EnGenius ESR1750 board support"
-       select SOC_QCA955X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -72,6 +72,7 @@ obj-$(CONFIG_ATH79_MACH_EAP300V2)    += mac
- obj-$(CONFIG_ATH79_MACH_EAP7660D)     += mach-eap7660d.o
- obj-$(CONFIG_ATH79_MACH_EL_M150)      += mach-el-m150.o
- obj-$(CONFIG_ATH79_MACH_EL_MINI)      += mach-el-mini.o
-+obj-$(CONFIG_ATH79_MACH_EPG5000)      += mach-epg5000.o
- obj-$(CONFIG_ATH79_MACH_ESR1750)      += mach-esr1750.o
- obj-$(CONFIG_ATH79_MACH_F9K1115V2)    += mach-f9k1115v2.o
- obj-$(CONFIG_ATH79_MACH_GL_INET)      += mach-gl-inet.o
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -62,6 +62,7 @@ enum ath79_mach_type {
-       ATH79_MACH_EL_M150,             /* EasyLink EL-M150 */
-       ATH79_MACH_EL_MINI,             /* EasyLink EL-MINI */
-       ATH79_MACH_ESR1750,             /* EnGenius ESR1750 */
-+      ATH79_MACH_EPG5000,             /* EnGenius EPG5000 */
-       ATH79_MACH_F9K1115V2,           /* Belkin AC1750DB */
-       ATH79_MACH_GL_INET,             /* GL-CONNECT GL-INET */
-       ATH79_MACH_GS_OOLITE,           /* GS OOLITE V1.0 */
diff --git a/target/linux/ar71xx/patches-4.1/727-MIPS-ath79-ar934x-wmac-revision.patch b/target/linux/ar71xx/patches-4.1/727-MIPS-ath79-ar934x-wmac-revision.patch
deleted file mode 100644 (file)
index b1b4946..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -147,6 +147,8 @@ static void ar934x_wmac_setup(void)
-               ath79_wmac_data.is_clk_25mhz = false;
-       else
-               ath79_wmac_data.is_clk_25mhz = true;
-+
-+      ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
- }
- static void qca953x_wmac_setup(void)
diff --git a/target/linux/ar71xx/patches-4.1/728-MIPS-ath79-fix-restart.patch b/target/linux/ar71xx/patches-4.1/728-MIPS-ath79-fix-restart.patch
deleted file mode 100644 (file)
index 612078c..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
- static void ath79_restart(char *command)
- {
-+      local_irq_disable();
-       ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
-       for (;;)
-               if (cpu_wait)
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -144,6 +144,7 @@ static inline u32 ath79_pll_rr(unsigned
- static inline void ath79_reset_wr(unsigned reg, u32 val)
- {
-       __raw_writel(val, ath79_reset_base + reg);
-+      (void) __raw_readl(ath79_reset_base + reg); /* flush */
- }
- static inline u32 ath79_reset_rr(unsigned reg)
diff --git a/target/linux/ar71xx/patches-4.1/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
deleted file mode 100644 (file)
index 47e8c79..0000000
+++ /dev/null
@@ -1,700 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1249,6 +1249,12 @@ config SOC_QCA955X
-       select PCI_AR724X if PCI
-       def_bool n
-+config SOC_QCA956X
-+      select USB_ARCH_HAS_EHCI
-+      select HW_HAS_PCI
-+      select PCI_AR724X if PCI
-+      def_bool n
-+
- config ATH79_DEV_M25P80
-       select ATH79_DEV_SPI
-       def_bool n
-@@ -1286,7 +1292,7 @@ config ATH79_DEV_USB
-       def_bool n
- config ATH79_DEV_WMAC
--      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
-+      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
-       def_bool n
- config ATH79_NVRAM
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
-       clk_add_alias("uart", NULL, "ref", NULL);
- }
-+static void __init qca956x_clocks_init(void)
-+{
-+      unsigned long ref_rate;
-+      unsigned long cpu_rate;
-+      unsigned long ddr_rate;
-+      unsigned long ahb_rate;
-+      u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
-+      u32 cpu_pll, ddr_pll;
-+      u32 bootstrap;
-+
-+      bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
-+      if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
-+              ref_rate = 40 * 1000 * 1000;
-+      else
-+              ref_rate = 25 * 1000 * 1000;
-+
-+      pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
-+      out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-+                QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
-+      ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-+                QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
-+
-+      pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
-+      nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
-+             QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
-+      hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
-+             QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
-+      lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
-+             QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
-+
-+      cpu_pll = nint * ref_rate / ref_div;
-+      cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
-+      cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
-+      cpu_pll /= (1 << out_div);
-+
-+      pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
-+      out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-+                QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
-+      ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-+                QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
-+      pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
-+      nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
-+             QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
-+      hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
-+             QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
-+      lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
-+             QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
-+
-+      ddr_pll = nint * ref_rate / ref_div;
-+      ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
-+      ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
-+      ddr_pll /= (1 << out_div);
-+
-+      clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
-+
-+      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-+                QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
-+              cpu_rate = ref_rate;
-+      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
-+              cpu_rate = ddr_pll / (postdiv + 1);
-+      else
-+              cpu_rate = cpu_pll / (postdiv + 1);
-+
-+      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-+                QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
-+              ddr_rate = ref_rate;
-+      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
-+              ddr_rate = cpu_pll / (postdiv + 1);
-+      else
-+              ddr_rate = ddr_pll / (postdiv + 1);
-+
-+      postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-+                QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
-+
-+      if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
-+              ahb_rate = ref_rate;
-+      else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-+              ahb_rate = ddr_pll / (postdiv + 1);
-+      else
-+              ahb_rate = cpu_pll / (postdiv + 1);
-+
-+      ath79_add_sys_clkdev("ref", ref_rate);
-+      ath79_add_sys_clkdev("cpu", cpu_rate);
-+      ath79_add_sys_clkdev("ddr", ddr_rate);
-+      ath79_add_sys_clkdev("ahb", ahb_rate);
-+
-+      clk_add_alias("wdt", NULL, "ref", NULL);
-+      clk_add_alias("uart", NULL, "ref", NULL);
-+}
-+
- void __init ath79_clocks_init(void)
- {
-       if (soc_is_ar71xx())
-@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
-               qca953x_clocks_init();
-       else if (soc_is_qca955x())
-               qca955x_clocks_init();
-+      else if (soc_is_qca956x())
-+              qca956x_clocks_init();
-       else
-               BUG();
- }
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
-               reg = QCA953X_RESET_REG_RESET_MODULE;
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-+      else if (soc_is_qca956x())
-+              reg = QCA956X_RESET_REG_RESET_MODULE;
-       else
-               panic("Reset register not defined for this SOC");
-@@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
-               reg = QCA953X_RESET_REG_RESET_MODULE;
-       else if (soc_is_qca955x())
-               reg = QCA955X_RESET_REG_RESET_MODULE;
-+      else if (soc_is_qca956x())
-+              reg = QCA956X_RESET_REG_RESET_MODULE;
-       else
-               panic("Reset register not defined for this SOC");
---- a/arch/mips/ath79/dev-common.c
-+++ b/arch/mips/ath79/dev-common.c
-@@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
-           soc_is_ar913x() ||
-           soc_is_ar934x() ||
-           soc_is_qca953x() ||
--          soc_is_qca955x()) {
-+          soc_is_qca955x() ||
-+          soc_is_qca956x()) {
-               ath79_uart_data[0].uartclk = uart_clk_rate;
-               platform_device_register(&ath79_uart_device);
-       } else if (soc_is_ar933x()) {
---- a/arch/mips/ath79/dev-usb.c
-+++ b/arch/mips/ath79/dev-usb.c
-@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
-                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
- }
-+static void __init qca956x_usb_setup(void)
-+{
-+      ath79_usb_register("ehci-platform", 0,
-+                         QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
-+                         ATH79_IP3_IRQ(0),
-+                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-+
-+      ath79_usb_register("ehci-platform", 1,
-+                         QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
-+                         ATH79_IP3_IRQ(1),
-+                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-+}
-+
- void __init ath79_register_usb(void)
- {
-       if (soc_is_ar71xx())
-@@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
-               qca953x_usb_setup();
-       else if (soc_is_qca955x())
-               qca955x_usb_setup();
-+      else if (soc_is_qca9561())
-+              qca956x_usb_setup();
-       else
-               BUG();
- }
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
-               ath79_wmac_data.is_clk_25mhz = true;
- }
-+static void qca956x_wmac_setup(void)
-+{
-+      u32 t;
-+
-+      ath79_wmac_device.name = "qca956x_wmac";
-+
-+      ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
-+      ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
-+      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-+      ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
-+
-+      t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
-+      if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
-+              ath79_wmac_data.is_clk_25mhz = false;
-+      else
-+              ath79_wmac_data.is_clk_25mhz = true;
-+}
-+
- static bool __init
- ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
- {
-@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
-               qca953x_wmac_setup();
-       else if (soc_is_qca955x())
-               qca955x_wmac_setup();
-+      else if (soc_is_qca956x())
-+              qca956x_wmac_setup();
-       else
-               BUG();
---- a/arch/mips/ath79/early_printk.c
-+++ b/arch/mips/ath79/early_printk.c
-@@ -118,6 +118,8 @@ static void prom_putchar_init(void)
-       case REV_ID_MAJOR_QCA9533_V2:
-       case REV_ID_MAJOR_QCA9556:
-       case REV_ID_MAJOR_QCA9558:
-+      case REV_ID_MAJOR_TP9343:
-+      case REV_ID_MAJOR_QCA9561:
-               _prom_putchar = prom_putchar_ar71xx;
-               break;
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
-           soc_is_ar913x() ||
-           soc_is_ar933x())
-               reg = AR71XX_GPIO_REG_FUNC;
--      else if (soc_is_ar934x() || soc_is_qca953x())
-+      else if (soc_is_ar934x() ||
-+               soc_is_qca953x() || soc_is_qca956x())
-               reg = AR934X_GPIO_REG_FUNC;
-       else
-               BUG();
-@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
-               ath79_gpio_count = QCA953X_GPIO_COUNT;
-       else if (soc_is_qca955x())
-               ath79_gpio_count = QCA955X_GPIO_COUNT;
-+      else if (soc_is_qca956x())
-+              ath79_gpio_count = QCA956X_GPIO_COUNT;
-       else
-               BUG();
-       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
-       ath79_gpio_chip.ngpio = ath79_gpio_count;
--      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
-+      if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
-+          soc_is_qca956x()) {
-               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
-               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
-       }
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
-                soc_is_ar933x() ||
-                soc_is_ar934x() ||
-                soc_is_qca953x() ||
--               soc_is_qca955x())
-+               soc_is_qca955x() ||
-+               soc_is_qca956x())
-               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
-       else
-               BUG();
-@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
-       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
- }
-+static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
-+{
-+      u32 status;
-+
-+      disable_irq_nosync(irq);
-+
-+      status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-+      status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
-+
-+      if (status == 0) {
-+              spurious_interrupt();
-+              goto enable;
-+      }
-+
-+      if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
-+              /* TODO: flush DDR? */
-+              generic_handle_irq(ATH79_IP2_IRQ(0));
-+      }
-+
-+      if (status & QCA956X_EXT_INT_WMAC_ALL) {
-+              /* TODO: flsuh DDR? */
-+              generic_handle_irq(ATH79_IP2_IRQ(1));
-+      }
-+
-+enable:
-+      enable_irq(irq);
-+}
-+
-+static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
-+{
-+      u32 status;
-+
-+      disable_irq_nosync(irq);
-+
-+      status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
-+      status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
-+                QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
-+
-+      if (status == 0) {
-+              spurious_interrupt();
-+              goto enable;
-+      }
-+
-+      if (status & QCA956X_EXT_INT_USB1) {
-+              /* TODO: flush DDR? */
-+              generic_handle_irq(ATH79_IP3_IRQ(0));
-+      }
-+
-+      if (status & QCA956X_EXT_INT_USB2) {
-+              /* TODO: flush DDR? */
-+              generic_handle_irq(ATH79_IP3_IRQ(1));
-+      }
-+
-+      if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
-+              /* TODO: flush DDR? */
-+              generic_handle_irq(ATH79_IP3_IRQ(2));
-+      }
-+
-+enable:
-+      enable_irq(irq);
-+}
-+
-+static void qca956x_enable_timer_cb(void) {
-+      u32 misc;
-+
-+      misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
-+      misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
-+      ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
-+}
-+
-+static void qca956x_irq_init(void)
-+{
-+      int i;
-+
-+      for (i = ATH79_IP2_IRQ_BASE;
-+           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
-+
-+      for (i = ATH79_IP3_IRQ_BASE;
-+           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-+              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+
-+      irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
-+
-+      /* QCA956x timer init workaround has to be applied right before setting
-+       * up the clock. Else, there will be no jiffies */
-+      late_time_init = &qca956x_enable_timer_cb;
-+}
-+
- asmlinkage void plat_irq_dispatch(void)
- {
-       unsigned long pending;
-@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
-       } else if (soc_is_qca955x()) {
-               ath79_ip2_handler = ath79_default_ip2_handler;
-               ath79_ip3_handler = ath79_default_ip3_handler;
-+      } else if (soc_is_qca956x()) {
-+              ath79_ip2_handler = ath79_default_ip2_handler;
-+              ath79_ip3_handler = ath79_default_ip3_handler;
-       } else {
-               BUG();
-       }
-@@ -410,4 +505,6 @@ void __init arch_init_irq(void)
-               qca953x_irq_init();
-       else if (soc_is_qca955x())
-               qca955x_irq_init();
-+      else if (soc_is_qca956x())
-+              qca956x_irq_init();
- }
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
-       },
- };
-+static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
-+      {
-+              .bus    = 0,
-+              .slot   = 0,
-+              .pin    = 1,
-+              .irq    = ATH79_PCI_IRQ(0),
-+      },
-+      {
-+              .bus    = 1,
-+              .slot   = 0,
-+              .pin    = 1,
-+              .irq    = ATH79_PCI_IRQ(1),
-+      },
-+};
-+
- int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
- {
-       int irq = -1;
-@@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
-               } else if (soc_is_qca955x()) {
-                       ath79_pci_irq_map = qca955x_pci_irq_map;
-                       ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
-+              } else if (soc_is_qca9561()) {
-+                      ath79_pci_irq_map = qca956x_pci_irq_map;
-+                      ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
-               } else {
-                       pr_crit("pci %s: invalid irq map\n",
-                               pci_name((struct pci_dev *) dev));
-@@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
-                                                QCA955X_PCI_MEM_SIZE,
-                                                1,
-                                                ATH79_IP3_IRQ(2));
-+      } else if (soc_is_qca9561()) {
-+              pdev = ath79_register_pci_ar724x(0,
-+                                               QCA956X_PCI_CFG_BASE1,
-+                                               QCA956X_PCI_CTRL_BASE1,
-+                                               QCA956X_PCI_CRP_BASE1,
-+                                               QCA956X_PCI_MEM_BASE1,
-+                                               QCA956X_PCI_MEM_SIZE,
-+                                               1,
-+                                               ATH79_IP3_IRQ(2));
-       } else {
-               /* No PCI support */
-               return -ENODEV;
---- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type
-               rev = id & QCA955X_REV_ID_REVISION_MASK;
-               break;
-+      case REV_ID_MAJOR_TP9343:
-+              ath79_soc = ATH79_SOC_TP9343;
-+              chip = "9343";
-+              rev = id & QCA956X_REV_ID_REVISION_MASK;
-+              break;
-+
-+      case REV_ID_MAJOR_QCA9561:
-+              ath79_soc = ATH79_SOC_QCA9561;
-+              chip = "9561";
-+              rev = id & QCA956X_REV_ID_REVISION_MASK;
-+              break;
-+
-       default:
-               panic("ath79: unknown SoC, id:0x%08x", id);
-       }
-       ath79_soc_rev = rev;
--      if (soc_is_qca953x() || soc_is_qca955x())
--              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
-+      if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
-+              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
-+                      chip, ver, rev);
-+      else if (soc_is_tp9343())
-+              sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
-                       chip, rev);
-       else
-               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -143,6 +143,23 @@
- #define QCA955X_NFC_BASE      0x1b800200
- #define QCA955X_NFC_SIZE      0xb8
-+#define QCA956X_PCI_MEM_BASE1 0x12000000
-+#define QCA956X_PCI_MEM_SIZE  0x02000000
-+#define QCA956X_PCI_CFG_BASE1 0x16000000
-+#define QCA956X_PCI_CFG_SIZE  0x1000
-+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
-+#define QCA956X_PCI_CRP_SIZE  0x1000
-+#define QCA956X_PCI_CTRL_BASE1        (AR71XX_APB_BASE + 0x00280000)
-+#define QCA956X_PCI_CTRL_SIZE 0x100
-+
-+#define QCA956X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
-+#define QCA956X_WMAC_SIZE     0x20000
-+#define QCA956X_EHCI0_BASE    0x1b000000
-+#define QCA956X_EHCI1_BASE    0x1b400000
-+#define QCA956X_EHCI_SIZE     0x200
-+#define QCA956X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
-+#define QCA956X_GMAC_SIZE     0x64
-+
- #define AR9300_OTP_BASE               0x14000
- #define AR9300_OTP_STATUS     0x15f18
- #define AR9300_OTP_STATUS_TYPE                0x7
-@@ -375,6 +392,49 @@
- #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
- #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
-+#define QCA956X_PLL_CPU_CONFIG_REG                    0x00
-+#define QCA956X_PLL_CPU_CONFIG1_REG                   0x04
-+#define QCA956X_PLL_DDR_CONFIG_REG                    0x08
-+#define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
-+#define QCA956X_PLL_CLK_CTRL_REG                      0x10
-+
-+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
-+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
-+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT           19
-+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK            0x7
-+
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT         0
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK          0x1f
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x3fff
-+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT            18
-+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK             0x1ff
-+
-+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT           16
-+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK            0x1f
-+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT           23
-+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK            0x7
-+
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT         0
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK          0x1f
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x3fff
-+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT            18
-+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK             0x1ff
-+
-+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
-+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
-+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
-+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
-+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
-+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
-+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
-+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
-+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
-+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL   BIT(20)
-+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL   BIT(21)
-+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
-+
- /*
-  * USB_CONFIG block
-  */
-@@ -422,6 +482,11 @@
- #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
- #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
-+#define QCA956X_RESET_REG_RESET_MODULE                0x1c
-+#define QCA956X_RESET_REG_BOOTSTRAP           0xb0
-+#define QCA956X_RESET_REG_EXT_INT_STATUS      0xac
-+
-+#define MISC_INT_MIPS_SI_TIMERINT_MASK        BIT(28)
- #define MISC_INT_ETHSW                        BIT(12)
- #define MISC_INT_TIMER4                       BIT(10)
- #define MISC_INT_TIMER3                       BIT(9)
-@@ -596,6 +661,8 @@
- #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
-+#define QCA956X_BOOTSTRAP_REF_CLK_40  BIT(2)
-+
- #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
- #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
- #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
-@@ -663,6 +730,37 @@
-        QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
-        QCA955X_EXT_INT_PCIE_RC2_INT3)
-+#define QCA956X_EXT_INT_WMAC_MISC             BIT(0)
-+#define QCA956X_EXT_INT_WMAC_TX                       BIT(1)
-+#define QCA956X_EXT_INT_WMAC_RXLP             BIT(2)
-+#define QCA956X_EXT_INT_WMAC_RXHP             BIT(3)
-+#define QCA956X_EXT_INT_PCIE_RC1              BIT(4)
-+#define QCA956X_EXT_INT_PCIE_RC1_INT0         BIT(5)
-+#define QCA956X_EXT_INT_PCIE_RC1_INT1         BIT(6)
-+#define QCA956X_EXT_INT_PCIE_RC1_INT2         BIT(7)
-+#define QCA956X_EXT_INT_PCIE_RC1_INT3         BIT(8)
-+#define QCA956X_EXT_INT_PCIE_RC2              BIT(12)
-+#define QCA956X_EXT_INT_PCIE_RC2_INT0         BIT(13)
-+#define QCA956X_EXT_INT_PCIE_RC2_INT1         BIT(14)
-+#define QCA956X_EXT_INT_PCIE_RC2_INT2         BIT(15)
-+#define QCA956X_EXT_INT_PCIE_RC2_INT3         BIT(16)
-+#define QCA956X_EXT_INT_USB1                  BIT(24)
-+#define QCA956X_EXT_INT_USB2                  BIT(28)
-+
-+#define QCA956X_EXT_INT_WMAC_ALL \
-+      (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
-+       QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
-+
-+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
-+      (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
-+       QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
-+       QCA956X_EXT_INT_PCIE_RC1_INT3)
-+
-+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
-+      (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
-+       QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
-+       QCA956X_EXT_INT_PCIE_RC2_INT3)
-+
- #define REV_ID_MAJOR_MASK             0xfff0
- #define REV_ID_MAJOR_AR71XX           0x00a0
- #define REV_ID_MAJOR_AR913X           0x00b0
-@@ -678,6 +776,8 @@
- #define REV_ID_MAJOR_QCA9533_V2               0x0160
- #define REV_ID_MAJOR_QCA9556          0x0130
- #define REV_ID_MAJOR_QCA9558          0x1130
-+#define REV_ID_MAJOR_TP9343           0x0150
-+#define REV_ID_MAJOR_QCA9561          0x1150
- #define AR71XX_REV_ID_MINOR_MASK      0x3
- #define AR71XX_REV_ID_MINOR_AR7130    0x0
-@@ -702,6 +802,8 @@
- #define QCA955X_REV_ID_REVISION_MASK  0xf
-+#define QCA956X_REV_ID_REVISION_MASK  0xf
-+
- /*
-  * SPI block
-  */
-@@ -766,6 +868,19 @@
- #define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
- #define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
-+#define QCA956X_GPIO_REG_OUT_FUNC0    0x2c
-+#define QCA956X_GPIO_REG_OUT_FUNC1    0x30
-+#define QCA956X_GPIO_REG_OUT_FUNC2    0x34
-+#define QCA956X_GPIO_REG_OUT_FUNC3    0x38
-+#define QCA956X_GPIO_REG_OUT_FUNC4    0x3c
-+#define QCA956X_GPIO_REG_OUT_FUNC5    0x40
-+#define QCA956X_GPIO_REG_IN_ENABLE0   0x44
-+#define QCA956X_GPIO_REG_IN_ENABLE3   0x50
-+#define QCA956X_GPIO_REG_FUNC         0x6c
-+
-+#define QCA956X_GPIO_OUT_MUX_GE0_MDO  32
-+#define QCA956X_GPIO_OUT_MUX_GE0_MDC  33
-+
- #define AR71XX_GPIO_COUNT             16
- #define AR7240_GPIO_COUNT             18
- #define AR7241_GPIO_COUNT             20
-@@ -774,6 +889,7 @@
- #define AR934X_GPIO_COUNT             23
- #define QCA953X_GPIO_COUNT            18
- #define QCA955X_GPIO_COUNT            24
-+#define QCA956X_GPIO_COUNT            23
- /*
-  * SRIF block
---- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -35,6 +35,8 @@ enum ath79_soc_type {
-       ATH79_SOC_QCA9533,
-       ATH79_SOC_QCA9556,
-       ATH79_SOC_QCA9558,
-+      ATH79_SOC_TP9343,
-+      ATH79_SOC_QCA9561,
- };
- extern enum ath79_soc_type ath79_soc;
-@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
-       return soc_is_qca9556() || soc_is_qca9558();
- }
-+static inline int soc_is_tp9343(void)
-+{
-+      return ath79_soc == ATH79_SOC_TP9343;
-+}
-+ 
-+static inline int soc_is_qca9561(void)
-+{
-+      return ath79_soc == ATH79_SOC_QCA9561;
-+}
-+
-+static inline int soc_is_qca956x(void)
-+{
-+      return soc_is_tp9343() || soc_is_qca9561();
-+}
-+
- extern void __iomem *ath79_ddr_base;
- extern void __iomem *ath79_gpio_base;
- extern void __iomem *ath79_pll_base;
diff --git a/target/linux/ar71xx/patches-4.1/736-MIPS-ath79-add-MC-MAC1200R-support.patch b/target/linux/ar71xx/patches-4.1/736-MIPS-ath79-add-MC-MAC1200R-support.patch
deleted file mode 100644 (file)
index 4c041d0..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -590,6 +590,16 @@ config ATH79_MACH_R6100
-       select ATH79_DEV_USB
-       select ATH79_DEV_WMAC
-+config ATH79_MACH_MC_MAC1200R
-+      bool "MERCURY MAC1200R board support"
-+      select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
- config ATH79_MACH_RB4XX
-       bool "MikroTik RouterBOARD 4xx series support"
-       select SOC_AR71XX
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -81,6 +81,7 @@ obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361)       +
- obj-$(CONFIG_ATH79_MACH_JA76PF)               += mach-ja76pf.o
- obj-$(CONFIG_ATH79_MACH_JWAP003)      += mach-jwap003.o
- obj-$(CONFIG_ATH79_MACH_HORNET_UB)    += mach-hornet-ub.o
-+obj-$(CONFIG_ATH79_MACH_MC_MAC1200R)     += mach-mc-mac1200r.o
- obj-$(CONFIG_ATH79_MACH_MR600)                += mach-mr600.o
- obj-$(CONFIG_ATH79_MACH_MR900)                += mach-mr900.o
- obj-$(CONFIG_ATH79_MACH_MYNET_N600)   += mach-mynet-n600.o
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -120,6 +120,7 @@ enum ath79_mach_type {
-       ATH79_MACH_TEW_673GRU,          /* TRENDnet TEW-673GRU */
-       ATH79_MACH_TEW_712BR,           /* TRENDnet TEW-712BR */
-       ATH79_MACH_TEW_732BR,           /* TRENDnet TEW-732BR */
-+      ATH79_MACH_MC_MAC1200R,         /* MERCURY MAC1200R*/
-       ATH79_MACH_TL_MR10U,            /* TP-LINK TL-MR10U */
-       ATH79_MACH_TL_MR11U,            /* TP-LINK TL-MR11U */
-       ATH79_MACH_TL_MR13U,            /* TP-LINK TL-MR13U */
diff --git a/target/linux/ar71xx/patches-4.1/736-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.1/736-MIPS-ath79-fix-chained-irq-disable.patch
deleted file mode 100644 (file)
index 8c0cc95..0000000
+++ /dev/null
@@ -1,100 +0,0 @@
---- a/arch/mips/ath79/irq.c
-+++ b/arch/mips/ath79/irq.c
-@@ -26,6 +26,8 @@
- static void (*ath79_ip2_handler)(void);
- static void (*ath79_ip3_handler)(void);
-+static struct irq_chip ip2_chip;
-+static struct irq_chip ip3_chip;
- static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
-@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
-       for (i = ATH79_IP2_IRQ_BASE;
-            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip,
--                                       handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
- }
-@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
-       for (i = ATH79_IP2_IRQ_BASE;
-            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
- }
-@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
-       for (i = ATH79_IP2_IRQ_BASE;
-            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip,
--                                       handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
-       for (i = ATH79_IP3_IRQ_BASE;
-            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip,
--                                       handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
- }
-@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
-       for (i = ATH79_IP2_IRQ_BASE;
-            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
-       for (i = ATH79_IP3_IRQ_BASE;
-            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
--              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
-+              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
-       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
-@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
-       do_IRQ(ATH79_CPU_IRQ(3));
- }
-+static void ath79_ip2_disable(struct irq_data *data)
-+{
-+      disable_irq(ATH79_CPU_IRQ(2));
-+}
-+
-+static void ath79_ip2_enable(struct irq_data *data)
-+{
-+      enable_irq(ATH79_CPU_IRQ(2));
-+}
-+
-+static void ath79_ip3_disable(struct irq_data *data)
-+{
-+      disable_irq(ATH79_CPU_IRQ(3));
-+}
-+
-+static void ath79_ip3_enable(struct irq_data *data)
-+{
-+      enable_irq(ATH79_CPU_IRQ(3));
-+}
-+
- void __init arch_init_irq(void)
- {
-+      ip2_chip = dummy_irq_chip;
-+      ip3_chip = dummy_irq_chip;
-+      ip2_chip.irq_disable = ath79_ip2_disable;
-+      ip2_chip.irq_enable = ath79_ip2_enable;
-+      ip3_chip.irq_disable = ath79_ip3_disable;
-+      ip3_chip.irq_enable = ath79_ip3_enable;
-+
-       if (soc_is_ar71xx()) {
-               ath79_ip2_handler = ar71xx_ip2_handler;
-               ath79_ip3_handler = ar71xx_ip3_handler;
diff --git a/target/linux/ar71xx/patches-4.1/737-MIPS-ath79-add-om5p-an-support.patch b/target/linux/ar71xx/patches-4.1/737-MIPS-ath79-add-om5p-an-support.patch
deleted file mode 100644 (file)
index 935a845..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -87,6 +87,7 @@ enum ath79_mach_type {
-       ATH79_MACH_OM2P_LC,             /* OpenMesh OM2P-LC */
-       ATH79_MACH_OM2Pv2,              /* OpenMesh OM2Pv2 */
-       ATH79_MACH_OM2P,                /* OpenMesh OM2P */
-+      ATH79_MACH_OM5P_AN,             /* OpenMesh OM5P-AN */
-       ATH79_MACH_OM5P,                /* OpenMesh OM5P */
-       ATH79_MACH_PB42,                /* Atheros PB42 */
-       ATH79_MACH_PB92,                /* Atheros PB92 */
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -743,6 +743,7 @@ config ATH79_MACH_OM2P
- config ATH79_MACH_OM5P
-       bool "OpenMesh OM5P board support"
-       select SOC_AR934X
-+      select ATH79_DEV_AP9X_PCI if PCI
-       select ATH79_DEV_ETH
-       select ATH79_DEV_GPIO_BUTTONS
-       select ATH79_DEV_LEDS_GPIO
diff --git a/target/linux/ar71xx/patches-4.1/738-MIPS-ath79-add-meraki-mr12-mr16-support.patch b/target/linux/ar71xx/patches-4.1/738-MIPS-ath79-add-meraki-mr12-mr16-support.patch
deleted file mode 100644 (file)
index 94d0aed..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -750,6 +750,26 @@ config ATH79_MACH_OM5P
-       select ATH79_DEV_M25P80
-       select ATH79_DEV_WMAC
-+config ATH79_MACH_MR12
-+      bool "Meraki MR12 board support"
-+      select SOC_AR724X
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
-+config ATH79_MACH_MR16
-+      bool "Meraki MR16 board support"
-+      select SOC_AR71XX
-+      select ATH79_DEV_AP9X_PCI if PCI
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_WMAC
-+
- config ATH79_MACH_MR600
-       bool "OpenMesh MR600 board support"
-       select SOC_AR934X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -82,6 +82,8 @@ obj-$(CONFIG_ATH79_MACH_JA76PF)              += mach
- obj-$(CONFIG_ATH79_MACH_JWAP003)      += mach-jwap003.o
- obj-$(CONFIG_ATH79_MACH_HORNET_UB)    += mach-hornet-ub.o
- obj-$(CONFIG_ATH79_MACH_MC_MAC1200R)     += mach-mc-mac1200r.o
-+obj-$(CONFIG_ATH79_MACH_MR12)         += mach-mr12.o
-+obj-$(CONFIG_ATH79_MACH_MR16)         += mach-mr16.o
- obj-$(CONFIG_ATH79_MACH_MR600)                += mach-mr600.o
- obj-$(CONFIG_ATH79_MACH_MR900)                += mach-mr900.o
- obj-$(CONFIG_ATH79_MACH_MYNET_N600)   += mach-mynet-n600.o
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -71,6 +71,8 @@ enum ath79_mach_type {
-       ATH79_MACH_JA76PF2,             /* jjPlus JA76PF2 */
-       ATH79_MACH_JWAP003,             /* jjPlus JWAP003 */
-       ATH79_MACH_HORNET_UB,           /* ALFA Networks Hornet-UB */
-+      ATH79_MACH_MR12,                /* Cisco Meraki MR12 */
-+      ATH79_MACH_MR16,                /* Cisco Meraki MR16 */
-       ATH79_MACH_MR600V2,             /* OpenMesh MR600v2 */
-       ATH79_MACH_MR600,               /* OpenMesh MR600 */
-       ATH79_MACH_MR900,               /* OpenMesh MR900 */
diff --git a/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-irq-support.patch b/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-irq-support.patch
deleted file mode 100644 (file)
index 90bc963..0000000
+++ /dev/null
@@ -1,224 +0,0 @@
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -20,9 +20,14 @@
- #include <linux/io.h>
- #include <linux/ioport.h>
- #include <linux/gpio.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+
-+#include <linux/of.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/irq.h>
- #include "common.h"
- void __iomem *ath79_gpio_base;
-@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base);
- static unsigned long ath79_gpio_count;
- static DEFINE_SPINLOCK(ath79_gpio_lock);
-+/*
-+ * gpio_both_edge is a bitmask of which gpio pins need to have
-+ * the detect priority flipped from the interrupt handler to
-+ * emulate IRQ_TYPE_EDGE_BOTH.
-+ */
-+static unsigned long gpio_both_edge = 0;
-+
- static void __ath79_gpio_set_value(unsigned gpio, int value)
- {
-       void __iomem *base = ath79_gpio_base;
-@@ -209,6 +221,132 @@ void __init ath79_gpio_output_select(uns
-       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
- }
-+static int ath79_gpio_irq_type(struct irq_data *d, unsigned type)
-+{
-+      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
-+      void __iomem *base = ath79_gpio_base;
-+      unsigned long flags;
-+      unsigned long int_type;
-+      unsigned long int_polarity;
-+      unsigned long bit = (1 << offset);
-+
-+      spin_lock_irqsave(&ath79_gpio_lock, flags);
-+
-+      int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE);
-+      int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY);
-+
-+      gpio_both_edge &= ~bit;
-+
-+      switch (type) {
-+      case IRQ_TYPE_EDGE_RISING:
-+              int_type &= ~bit;
-+              int_polarity |= bit;
-+              break;
-+
-+      case IRQ_TYPE_EDGE_FALLING:
-+              int_type &= ~bit;
-+              int_polarity &= ~bit;
-+              break;
-+
-+      case IRQ_TYPE_LEVEL_HIGH:
-+              int_type |= bit;
-+              int_polarity |= bit;
-+              break;
-+
-+      case IRQ_TYPE_LEVEL_LOW:
-+              int_type |= bit;
-+              int_polarity &= ~bit;
-+              break;
-+
-+      case IRQ_TYPE_EDGE_BOTH:
-+              int_type |= bit;
-+              /* set polarity based on current value */
-+              if (gpio_get_value(offset)) {
-+                      int_polarity &= ~bit;
-+              } else {
-+                      int_polarity |= bit;
-+              }
-+              /* flip this gpio in the interrupt handler */
-+              gpio_both_edge |= bit;
-+              break;
-+
-+      default:
-+              spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+              return -EINVAL;
-+      }
-+
-+      __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE);
-+      __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY);
-+
-+      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset),
-+                   base + AR71XX_GPIO_REG_INT_MODE);
-+
-+      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
-+                   base + AR71XX_GPIO_REG_INT_ENABLE);
-+
-+      spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+      return 0;
-+}
-+
-+static void ath79_gpio_irq_enable(struct irq_data *d)
-+{
-+      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
-+      void __iomem *base = ath79_gpio_base;
-+
-+      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset),
-+                   base + AR71XX_GPIO_REG_INT_ENABLE);
-+}
-+
-+static void ath79_gpio_irq_disable(struct irq_data *d)
-+{
-+      int offset = d->irq - ATH79_GPIO_IRQ_BASE;
-+      void __iomem *base = ath79_gpio_base;
-+
-+      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
-+                   base + AR71XX_GPIO_REG_INT_ENABLE);
-+}
-+
-+static struct irq_chip ath79_gpio_irqchip = {
-+      .name = "GPIO",
-+      .irq_enable = ath79_gpio_irq_enable,
-+      .irq_disable = ath79_gpio_irq_disable,
-+      .irq_set_type = ath79_gpio_irq_type,
-+};
-+
-+static irqreturn_t ath79_gpio_irq(int irq, void *dev)
-+{
-+      void __iomem *base = ath79_gpio_base;
-+      unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING);
-+      int bit_num;
-+
-+      for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) {
-+              unsigned long bit = BIT(bit_num);
-+
-+              if (bit & gpio_both_edge) {
-+                      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit,
-+                              base + AR71XX_GPIO_REG_INT_POLARITY);
-+              }
-+
-+              generic_handle_irq(ATH79_GPIO_IRQ(bit_num));
-+      }
-+
-+      return IRQ_HANDLED;
-+}
-+
-+static int __init ath79_gpio_irq_init(struct gpio_chip *chip)
-+{
-+      int irq;
-+      int irq_base = ATH79_GPIO_IRQ_BASE;
-+
-+      for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) {
-+              irq_set_chip_data(irq, chip);
-+              irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq);
-+              irq_set_noprobe(irq);
-+      }
-+
-+      return 0;
-+}
-+
- void __init ath79_gpio_init(void)
- {
-       int err;
-@@ -245,6 +383,10 @@ void __init ath79_gpio_init(void)
-       err = gpiochip_add(&ath79_gpio_chip);
-       if (err)
-               panic("cannot add AR71xx GPIO chip, error=%d", err);
-+
-+      ath79_gpio_irq_init(&ath79_gpio_chip);
-+
-+      request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL);
- }
- int gpio_get_value(unsigned gpio)
-@@ -267,14 +409,22 @@ EXPORT_SYMBOL(gpio_set_value);
- int gpio_to_irq(unsigned gpio)
- {
--      /* FIXME */
--      return -EINVAL;
-+      if (gpio > ath79_gpio_count) {
-+              return -EINVAL;
-+      }
-+
-+      return ATH79_GPIO_IRQ_BASE + gpio;
- }
- EXPORT_SYMBOL(gpio_to_irq);
- int irq_to_gpio(unsigned irq)
- {
--      /* FIXME */
--      return -EINVAL;
-+      unsigned gpio = irq - ATH79_GPIO_IRQ_BASE;
-+
-+      if (gpio > ath79_gpio_count) {
-+              return -EINVAL;
-+      }
-+
-+      return gpio;
- }
- EXPORT_SYMBOL(irq_to_gpio);
---- a/arch/mips/include/asm/mach-ath79/irq.h
-+++ b/arch/mips/include/asm/mach-ath79/irq.h
-@@ -10,7 +10,7 @@
- #define __ASM_MACH_ATH79_IRQ_H
- #define MIPS_CPU_IRQ_BASE     0
--#define NR_IRQS                       51
-+#define NR_IRQS                       83
- #define ATH79_CPU_IRQ(_x)     (MIPS_CPU_IRQ_BASE + (_x))
-@@ -30,6 +30,10 @@
- #define ATH79_IP3_IRQ_COUNT     3
- #define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
-+#define ATH79_GPIO_IRQ_BASE   (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT)
-+#define ATH79_GPIO_IRQ_COUNT  32
-+#define ATH79_GPIO_IRQ(_x)    (ATH79_GPIO_IRQ_BASE + (_x))
-+
- #include_next <irq.h>
- #endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/target/linux/ar71xx/patches-4.1/800-MIPS-ath79-add-RB922GS-support.patch b/target/linux/ar71xx/patches-4.1/800-MIPS-ath79-add-RB922GS-support.patch
deleted file mode 100644 (file)
index ca28652..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -625,6 +625,16 @@ config ATH79_MACH_RB91X
-       select ATH79_DEV_USB
-       select ATH79_ROUTERBOOT
-+config ATH79_MACH_RB922
-+      bool "MikroTik RouterBOARD 922 support"
-+      select SOC_QCA955X
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_M25P80
-+      select ATH79_DEV_NFC
-+      select ATH79_DEV_USB
-+      select ATH79_ROUTERBOOT
-+      select RLE_DECOMPRESS
-+
- config ATH79_MACH_RB95X
-        bool "MikroTik RouterBOARD 95X support"
-        select SOC_AR934X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -102,6 +102,7 @@ obj-$(CONFIG_ATH79_MACH_R6100)             += mach-
- obj-$(CONFIG_ATH79_MACH_RB4XX)                += mach-rb4xx.o
- obj-$(CONFIG_ATH79_MACH_RB750)                += mach-rb750.o
- obj-$(CONFIG_ATH79_MACH_RB91X)                += mach-rb91x.o
-+obj-$(CONFIG_ATH79_MACH_RB922)                += mach-rb922.o
- obj-$(CONFIG_ATH79_MACH_RB95X)                += mach-rb95x.o
- obj-$(CONFIG_ATH79_MACH_RB2011)               += mach-rb2011.o
- obj-$(CONFIG_ATH79_MACH_RBSXTLITE)    += mach-rbsxtlite.o
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -109,6 +109,7 @@ enum ath79_mach_type {
-       ATH79_MACH_RB_750G_R3,          /* MikroTik RouterBOARD 750GL */
-       ATH79_MACH_RB_751,              /* MikroTik RouterBOARD 751 */
-       ATH79_MACH_RB_751G,             /* Mikrotik RouterBOARD 751G */
-+      ATH79_MACH_RB_922GS,            /* Mikrotik RouterBOARD 911/922GS boards */
-       ATH79_MACH_RB_951G,             /* Mikrotik RouterBOARD 951G */
-       ATH79_MACH_RB_951U,             /* Mikrotik RouterBOARD 951Ui-2HnD */
-       ATH79_MACH_RB_2011G,            /* Mikrotik RouterBOARD 2011UAS-2HnD */
---- a/arch/mips/ath79/prom.c
-+++ b/arch/mips/ath79/prom.c
-@@ -134,7 +134,8 @@ void __init prom_init(void)
-       if (strstr(arcs_cmdline, "board=750Gr3") ||
-           strstr(arcs_cmdline, "board=951G") ||
-           strstr(arcs_cmdline, "board=2011L") ||
--          strstr(arcs_cmdline, "board=711Gr100"))
-+          strstr(arcs_cmdline, "board=711Gr100") ||
-+          strstr(arcs_cmdline, "board=922gs"))
-               ath79_prom_append_cmdline("console", "ttyS0,115200");
- }
diff --git a/target/linux/ar71xx/patches-4.1/810-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.1/810-MIPS-ath79-wmac-enable-set-led-pin.patch
deleted file mode 100644 (file)
index 03b32b1..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/arch/mips/ath79/dev-wmac.c
-+++ b/arch/mips/ath79/dev-wmac.c
-@@ -398,6 +398,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
-               ar934x_set_ext_lna_gpio(chain, gpio);
- }
-+void __init ath79_wmac_set_led_pin(int gpio)
-+{
-+      ath79_wmac_data.led_pin = gpio;
-+}
-+
- void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
- {
-       if (soc_is_ar913x())
---- a/arch/mips/ath79/dev-wmac.h
-+++ b/arch/mips/ath79/dev-wmac.h
-@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void);
- void ath79_wmac_disable_5ghz(void);
- void ath79_wmac_set_tx_gain_buffalo(void);
- void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio);
-+void ath79_wmac_set_led_pin(int gpio);
- bool ar93xx_wmac_read_mac_address(u8 *dest);
diff --git a/target/linux/ar71xx/patches-4.1/811-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.1/811-MIPS-ath79-gpio-enable-set-direction.patch
deleted file mode 100644 (file)
index b5dbb74..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
---- a/arch/mips/ath79/common.h
-+++ b/arch/mips/ath79/common.h
-@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask
- void ath79_gpio_function_disable(u32 mask);
- void ath79_gpio_function_setup(u32 set, u32 clear);
- void ath79_gpio_output_select(unsigned gpio, u8 val);
-+int ath79_gpio_direction_select(unsigned gpio, bool oe);
- void ath79_gpio_init(void);
- #endif /* __ATH79_COMMON_H */
---- a/arch/mips/ath79/gpio.c
-+++ b/arch/mips/ath79/gpio.c
-@@ -142,6 +142,30 @@ static int ar934x_gpio_direction_output(
-       return 0;
- }
-+int ath79_gpio_direction_select(unsigned gpio, bool oe)
-+{
-+      void __iomem *base = ath79_gpio_base;
-+      unsigned long flags;
-+      bool ieq_1 = (soc_is_ar934x() ||
-+                      soc_is_qca953x());
-+
-+      if (gpio >= ath79_gpio_count)
-+              return -1;
-+
-+      spin_lock_irqsave(&ath79_gpio_lock, flags);
-+
-+      if ((ieq_1 && oe) || (!ieq_1 && !oe))
-+              __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
-+                              base + AR71XX_GPIO_REG_OE);
-+      else
-+              __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
-+                              base + AR71XX_GPIO_REG_OE);
-+
-+      spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-+
-+      return 0;
-+}
-+
- static struct gpio_chip ath79_gpio_chip = {
-       .label                  = "ath79",
-       .get                    = ath79_gpio_get_value,
diff --git a/target/linux/ar71xx/patches-4.1/812-MIPS-ath79-add-ap143-support.patch b/target/linux/ar71xx/patches-4.1/812-MIPS-ath79-add-ap143-support.patch
deleted file mode 100644 (file)
index 29d91ef..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -104,6 +104,20 @@ config ATH79_MACH_AP136
-         Say 'Y' here if you want your kernel to support the
-         Atheros AP136 or AP135 reference boards.
-+config ATH79_MACH_AP143
-+      bool "Atheros AP143 reference board"
-+      select SOC_QCA953X
-+      select ATH79_DEV_GPIO_BUTTONS
-+      select ATH79_DEV_LEDS_GPIO
-+      select ATH79_DEV_SPI
-+      select ATH79_DEV_USB
-+      select ATH79_DEV_WMAC
-+      select ATH79_DEV_ETH
-+      select ATH79_DEV_M25P80
-+      help
-+        Say 'Y' here if you want your kernel to support the
-+        Atheros AP143 reference board.
-+
- config ATH79_MACH_AP81
-       bool "Atheros AP81 reference board"
-       select SOC_AR913X
---- a/arch/mips/ath79/Makefile
-+++ b/arch/mips/ath79/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_ATH79_MACH_AP113)               += mach-
- obj-$(CONFIG_ATH79_MACH_AP121)                += mach-ap121.o
- obj-$(CONFIG_ATH79_MACH_AP132)                += mach-ap132.o
- obj-$(CONFIG_ATH79_MACH_AP136)                += mach-ap136.o
-+obj-$(CONFIG_ATH79_MACH_AP143)                += mach-ap143.o
- obj-$(CONFIG_ATH79_MACH_AP81)         += mach-ap81.o
- obj-$(CONFIG_ATH79_MACH_AP83)         += mach-ap83.o
- obj-$(CONFIG_ATH79_MACH_AP96)         += mach-ap96.o
---- a/arch/mips/ath79/machtypes.h
-+++ b/arch/mips/ath79/machtypes.h
-@@ -28,6 +28,7 @@ enum ath79_mach_type {
-       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
-       ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
-       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
-+      ATH79_MACH_AP143,               /* Atheros AP143 reference board */
-       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
-       ATH79_MACH_AP83,                /* Atheros AP83 */
-       ATH79_MACH_AP96,                /* Atheros AP96 */
diff --git a/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch
new file mode 100644 (file)
index 0000000..39584aa
--- /dev/null
@@ -0,0 +1,20 @@
+--- a/drivers/net/phy/mdio-bitbang.c
++++ b/drivers/net/phy/mdio-bitbang.c
+@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
+       ctrl->ops->set_mdio_dir(ctrl, 0);
+-      /* check the turnaround bit: the PHY should be driving it to zero */
+-      if (mdiobb_get_bit(ctrl) != 0) {
+-              /* PHY didn't drive TA low -- flush any bits it
+-               * may be trying to send.
+-               */
+-              for (i = 0; i < 32; i++)
+-                      mdiobb_get_bit(ctrl);
+-
+-              return 0xffff;
+-      }
++      mdiobb_get_bit(ctrl);
+       ret = mdiobb_get_num(ctrl, 16);
+       mdiobb_get_bit(ctrl);
diff --git a/target/linux/ar71xx/patches-4.1/901-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-4.1/901-mdio_bitbang_ignore_ta_value.patch
deleted file mode 100644 (file)
index 39584aa..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/net/phy/mdio-bitbang.c
-+++ b/drivers/net/phy/mdio-bitbang.c
-@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
-       ctrl->ops->set_mdio_dir(ctrl, 0);
--      /* check the turnaround bit: the PHY should be driving it to zero */
--      if (mdiobb_get_bit(ctrl) != 0) {
--              /* PHY didn't drive TA low -- flush any bits it
--               * may be trying to send.
--               */
--              for (i = 0; i < 32; i++)
--                      mdiobb_get_bit(ctrl);
--
--              return 0xffff;
--      }
-+      mdiobb_get_bit(ctrl);
-       ret = mdiobb_get_num(ctrl, 16);
-       mdiobb_get_bit(ctrl);
diff --git a/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch
new file mode 100644 (file)
index 0000000..68f86e0
--- /dev/null
@@ -0,0 +1,61 @@
+From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 16 Jun 2015 13:15:08 +0200
+Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command
+
+It seems some phys have some maximum timings for accessing the MDIO line,
+resulting in bit errors under cpu stress. Prevent this from happening by
+disabling interrupts when sending commands.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/phy/mdio-bitbang.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/net/phy/mdio-bitbang.c
++++ b/drivers/net/phy/mdio-bitbang.c
+@@ -17,6 +17,7 @@
+  * kind, whether express or implied.
+  */
++#include <linux/irqflags.h>
+ #include <linux/module.h>
+ #include <linux/mdio-bitbang.h>
+ #include <linux/types.h>
+@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b
+ {
+       struct mdiobb_ctrl *ctrl = bus->priv;
+       int ret, i;
++      long flags;
++      local_irq_save(flags);
+       if (reg & MII_ADDR_C45) {
+               reg = mdiobb_cmd_addr(ctrl, phy, reg);
+               mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
+@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b
+       ret = mdiobb_get_num(ctrl, 16);
+       mdiobb_get_bit(ctrl);
++      local_irq_restore(flags);
++
+       return ret;
+ }
+ static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
+ {
+       struct mdiobb_ctrl *ctrl = bus->priv;
++      long flags;
++      local_irq_save(flags);
+       if (reg & MII_ADDR_C45) {
+               reg = mdiobb_cmd_addr(ctrl, phy, reg);
+               mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
+@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus *
+       ctrl->ops->set_mdio_dir(ctrl, 0);
+       mdiobb_get_bit(ctrl);
++      local_irq_restore(flags);
++
+       return 0;
+ }
diff --git a/target/linux/ar71xx/patches-4.1/902-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.1/902-unaligned_access_hacks.patch
deleted file mode 100644 (file)
index fbbe22e..0000000
+++ /dev/null
@@ -1,878 +0,0 @@
---- a/arch/mips/include/asm/checksum.h
-+++ b/arch/mips/include/asm/checksum.h
-@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const
-       const unsigned int *stop = word + ihl;
-       unsigned int csum;
-       int carry;
-+      unsigned int w;
--      csum = word[0];
--      csum += word[1];
--      carry = (csum < word[1]);
-+      csum = net_hdr_word(word++);
-+
-+      w = net_hdr_word(word++);
-+      csum += w;
-+      carry = (csum < w);
-       csum += carry;
--      csum += word[2];
--      carry = (csum < word[2]);
-+      w = net_hdr_word(word++);
-+      csum += w;
-+      carry = (csum < w);
-       csum += carry;
--      csum += word[3];
--      carry = (csum < word[3]);
-+      w = net_hdr_word(word++);
-+      csum += w;
-+      carry = (csum < w);
-       csum += carry;
--      word += 4;
-       do {
--              csum += *word;
--              carry = (csum < *word);
-+              w = net_hdr_word(word++);
-+              csum += w;
-+              carry = (csum < w);
-               csum += carry;
--              word++;
-       } while (word != stop);
-       return csum_fold(csum);
-@@ -212,73 +216,6 @@ static inline __sum16 ip_compute_csum(co
-       return csum_fold(csum_partial(buff, len, 0));
- }
--#define _HAVE_ARCH_IPV6_CSUM
--static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
--                                        const struct in6_addr *daddr,
--                                        __u32 len, unsigned short proto,
--                                        __wsum sum)
--{
--      __wsum tmp;
--
--      __asm__(
--      "       .set    push            # csum_ipv6_magic\n"
--      "       .set    noreorder       \n"
--      "       .set    noat            \n"
--      "       addu    %0, %5          # proto (long in network byte order)\n"
--      "       sltu    $1, %0, %5      \n"
--      "       addu    %0, $1          \n"
--
--      "       addu    %0, %6          # csum\n"
--      "       sltu    $1, %0, %6      \n"
--      "       lw      %1, 0(%2)       # four words source address\n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 4(%2)       \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 8(%2)       \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 12(%2)      \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 0(%3)       \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 4(%3)       \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 8(%3)       \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       lw      %1, 12(%3)      \n"
--      "       addu    %0, $1          \n"
--      "       addu    %0, %1          \n"
--      "       sltu    $1, %0, %1      \n"
--
--      "       addu    %0, $1          # Add final carry\n"
--      "       .set    pop"
--      : "=&r" (sum), "=&r" (tmp)
--      : "r" (saddr), "r" (daddr),
--        "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
--
--      return csum_fold(sum);
--}
--
- #include <asm-generic/checksum.h>
- #endif /* CONFIG_GENERIC_CSUM */
---- a/include/uapi/linux/ip.h
-+++ b/include/uapi/linux/ip.h
-@@ -102,7 +102,7 @@ struct iphdr {
-       __be32  saddr;
-       __be32  daddr;
-       /*The options start here. */
--};
-+} __attribute__((packed, aligned(2)));
- struct ip_auth_hdr {
---- a/include/uapi/linux/ipv6.h
-+++ b/include/uapi/linux/ipv6.h
-@@ -129,7 +129,7 @@ struct ipv6hdr {
-       struct  in6_addr        saddr;
-       struct  in6_addr        daddr;
--};
-+} __attribute__((packed, aligned(2)));
- /* index values for the variables in ipv6_devconf */
---- a/include/uapi/linux/tcp.h
-+++ b/include/uapi/linux/tcp.h
-@@ -54,7 +54,7 @@ struct tcphdr {
-       __be16  window;
-       __sum16 check;
-       __be16  urg_ptr;
--};
-+} __attribute__((packed, aligned(2)));
- /*
-  *    The union cast uses a gcc extension to avoid aliasing problems
-@@ -64,7 +64,7 @@ struct tcphdr {
- union tcp_word_hdr { 
-       struct tcphdr hdr;
-       __be32            words[5];
--}; 
-+} __attribute__((packed, aligned(2)));
- #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) 
---- a/include/uapi/linux/udp.h
-+++ b/include/uapi/linux/udp.h
-@@ -24,7 +24,7 @@ struct udphdr {
-       __be16  dest;
-       __be16  len;
-       __sum16 check;
--};
-+} __attribute__((packed, aligned(2)));
- /* UDP socket options */
- #define UDP_CORK      1       /* Never send partially complete segments */
---- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
-+++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
-@@ -41,8 +41,8 @@ static bool ipv4_pkt_to_tuple(const stru
-       if (ap == NULL)
-               return false;
--      tuple->src.u3.ip = ap[0];
--      tuple->dst.u3.ip = ap[1];
-+      tuple->src.u3.ip = net_hdr_word(ap++);
-+      tuple->dst.u3.ip = net_hdr_word(ap);
-       return true;
- }
---- a/include/uapi/linux/icmp.h
-+++ b/include/uapi/linux/icmp.h
-@@ -80,7 +80,7 @@ struct icmphdr {
-               __be16  mtu;
-       } frag;
-   } un;
--};
-+} __attribute__((packed, aligned(2)));
- /*
---- a/include/uapi/linux/in6.h
-+++ b/include/uapi/linux/in6.h
-@@ -42,7 +42,7 @@ struct in6_addr {
- #define s6_addr16             in6_u.u6_addr16
- #define s6_addr32             in6_u.u6_addr32
- #endif
--};
-+} __attribute__((packed, aligned(2)));
- #endif /* __UAPI_DEF_IN6_ADDR */
- #if __UAPI_DEF_SOCKADDR_IN6
---- a/net/ipv6/tcp_ipv6.c
-+++ b/net/ipv6/tcp_ipv6.c
-@@ -39,6 +39,7 @@
- #include <linux/ipsec.h>
- #include <linux/times.h>
- #include <linux/slab.h>
-+#include <asm/unaligned.h>
- #include <linux/uaccess.h>
- #include <linux/ipv6.h>
- #include <linux/icmpv6.h>
-@@ -772,10 +773,10 @@ static void tcp_v6_send_response(struct
-       topt = (__be32 *)(t1 + 1);
-       if (tsecr) {
--              *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
--                              (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
--              *topt++ = htonl(tsval);
--              *topt++ = htonl(tsecr);
-+              put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
-+                              (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
-+              put_unaligned_be32(tsval, topt++);
-+              put_unaligned_be32(tsecr, topt++);
-       }
- #ifdef CONFIG_TCP_MD5SIG
---- a/include/linux/ipv6.h
-+++ b/include/linux/ipv6.h
-@@ -5,6 +5,7 @@
- #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)
- #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
-+
- /*
-  * This structure contains configuration options per IPv6 link.
-  */
---- a/net/ipv6/datagram.c
-+++ b/net/ipv6/datagram.c
-@@ -414,7 +414,7 @@ int ipv6_recv_error(struct sock *sk, str
-                               ipv6_iface_scope_id(&sin->sin6_addr,
-                                                   IP6CB(skb)->iif);
-               } else {
--                      ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
-+                      ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
-                                              &sin->sin6_addr);
-                       sin->sin6_scope_id = 0;
-               }
-@@ -751,12 +751,12 @@ int ip6_datagram_send_ctl(struct net *ne
-                       }
-                       if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
--                              if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
-+                              if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
-                                       err = -EINVAL;
-                                       goto exit_f;
-                               }
-                       }
--                      fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
-+                      fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
-                       break;
-               case IPV6_2292HOPOPTS:
---- a/net/ipv6/ip6_gre.c
-+++ b/net/ipv6/ip6_gre.c
-@@ -393,7 +393,7 @@ static void ip6gre_err(struct sk_buff *s
-       t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
-                               flags & GRE_KEY ?
--                              *(((__be32 *)p) + (grehlen / 4) - 1) : 0,
-+                              net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0,
-                               p[1]);
-       if (!t)
-               return;
-@@ -475,11 +475,11 @@ static int ip6gre_rcv(struct sk_buff *sk
-                       offset += 4;
-               }
-               if (flags&GRE_KEY) {
--                      key = *(__be32 *)(h + offset);
-+                      key = net_hdr_word(h + offset);
-                       offset += 4;
-               }
-               if (flags&GRE_SEQ) {
--                      seqno = ntohl(*(__be32 *)(h + offset));
-+                      seqno = ntohl(net_hdr_word(h + offset));
-                       offset += 4;
-               }
-       }
-@@ -744,7 +744,7 @@ static netdev_tx_t ip6gre_xmit2(struct s
-               if (tunnel->parms.o_flags&GRE_SEQ) {
-                       ++tunnel->o_seqno;
--                      *ptr = htonl(tunnel->o_seqno);
-+                      net_hdr_word(ptr) = htonl(tunnel->o_seqno);
-                       ptr--;
-               }
-               if (tunnel->parms.o_flags&GRE_KEY) {
-@@ -840,7 +840,7 @@ static inline int ip6gre_xmit_ipv6(struc
-       dsfield = ipv6_get_dsfield(ipv6h);
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
--              fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
-+              fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
-               fl6.flowlabel |= ip6_flowlabel(ipv6h);
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
---- a/net/ipv6/ip6_tunnel.c
-+++ b/net/ipv6/ip6_tunnel.c
-@@ -1340,7 +1340,7 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str
-       dsfield = ipv6_get_dsfield(ipv6h);
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS)
--              fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK);
-+              fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK;
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL)
-               fl6.flowlabel |= ip6_flowlabel(ipv6h);
-       if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK)
---- a/net/ipv6/exthdrs.c
-+++ b/net/ipv6/exthdrs.c
-@@ -573,7 +573,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
-               goto drop;
-       }
--      pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
-+      pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
-       if (pkt_len <= IPV6_MAXPLEN) {
-               IP6_INC_STATS_BH(net, ipv6_skb_idev(skb),
-                                IPSTATS_MIB_INHDRERRORS);
---- a/include/linux/types.h
-+++ b/include/linux/types.h
-@@ -207,5 +207,11 @@ struct callback_head {
- /* clocksource cycle base type */
- typedef u64 cycle_t;
-+struct net_hdr_word {
-+       u32 words[1];
-+} __attribute__((packed, aligned(2)));
-+
-+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
-+
- #endif /*  __ASSEMBLY__ */
- #endif /* _LINUX_TYPES_H */
---- a/net/ipv4/af_inet.c
-+++ b/net/ipv4/af_inet.c
-@@ -1323,8 +1323,8 @@ static struct sk_buff **inet_gro_receive
-       if (unlikely(ip_fast_csum((u8 *)iph, 5)))
-               goto out_unlock;
--      id = ntohl(*(__be32 *)&iph->id);
--      flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
-+      id = ntohl(net_hdr_word(&iph->id));
-+      flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
-       id >>= 16;
-       for (p = *head; p; p = p->next) {
---- a/net/ipv4/route.c
-+++ b/net/ipv4/route.c
-@@ -453,7 +453,7 @@ static struct neighbour *ipv4_neigh_look
-       else if (skb)
-               pkey = &ip_hdr(skb)->daddr;
--      n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
-+      n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
-       if (n)
-               return n;
-       return neigh_create(&arp_tbl, pkey, dev);
---- a/net/ipv4/tcp_output.c
-+++ b/net/ipv4/tcp_output.c
-@@ -452,48 +452,53 @@ static void tcp_options_write(__be32 *pt
-       u16 options = opts->options;    /* mungable copy */
-       if (unlikely(OPTION_MD5 & options)) {
--              *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
--                             (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
-+              net_hdr_word(ptr++) =
-+                      htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
-+                            (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
-               /* overload cookie hash location */
-               opts->hash_location = (__u8 *)ptr;
-               ptr += 4;
-       }
-       if (unlikely(opts->mss)) {
--              *ptr++ = htonl((TCPOPT_MSS << 24) |
--                             (TCPOLEN_MSS << 16) |
--                             opts->mss);
-+              net_hdr_word(ptr++) =
-+                      htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
-+                            opts->mss);
-       }
-       if (likely(OPTION_TS & options)) {
-               if (unlikely(OPTION_SACK_ADVERTISE & options)) {
--                      *ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
--                                     (TCPOLEN_SACK_PERM << 16) |
--                                     (TCPOPT_TIMESTAMP << 8) |
--                                     TCPOLEN_TIMESTAMP);
-+                      net_hdr_word(ptr++) =
-+                              htonl((TCPOPT_SACK_PERM << 24) |
-+                                    (TCPOLEN_SACK_PERM << 16) |
-+                                    (TCPOPT_TIMESTAMP << 8) |
-+                                    TCPOLEN_TIMESTAMP);
-                       options &= ~OPTION_SACK_ADVERTISE;
-               } else {
--                      *ptr++ = htonl((TCPOPT_NOP << 24) |
--                                     (TCPOPT_NOP << 16) |
--                                     (TCPOPT_TIMESTAMP << 8) |
--                                     TCPOLEN_TIMESTAMP);
-+                      net_hdr_word(ptr++) =
-+                              htonl((TCPOPT_NOP << 24) |
-+                                    (TCPOPT_NOP << 16) |
-+                                    (TCPOPT_TIMESTAMP << 8) |
-+                                    TCPOLEN_TIMESTAMP);
-               }
--              *ptr++ = htonl(opts->tsval);
--              *ptr++ = htonl(opts->tsecr);
-+              net_hdr_word(ptr++) = htonl(opts->tsval);
-+              net_hdr_word(ptr++) = htonl(opts->tsecr);
-       }
-       if (unlikely(OPTION_SACK_ADVERTISE & options)) {
--              *ptr++ = htonl((TCPOPT_NOP << 24) |
--                             (TCPOPT_NOP << 16) |
--                             (TCPOPT_SACK_PERM << 8) |
--                             TCPOLEN_SACK_PERM);
-+              net_hdr_word(ptr++) =
-+                      htonl((TCPOPT_NOP << 24) |
-+                            (TCPOPT_NOP << 16) |
-+                            (TCPOPT_SACK_PERM << 8) |
-+                            TCPOLEN_SACK_PERM);
-       }
-       if (unlikely(OPTION_WSCALE & options)) {
--              *ptr++ = htonl((TCPOPT_NOP << 24) |
--                             (TCPOPT_WINDOW << 16) |
--                             (TCPOLEN_WINDOW << 8) |
--                             opts->ws);
-+              net_hdr_word(ptr++) =
-+                      htonl((TCPOPT_NOP << 24) |
-+                            (TCPOPT_WINDOW << 16) |
-+                            (TCPOLEN_WINDOW << 8) |
-+                            opts->ws);
-       }
-       if (unlikely(opts->num_sack_blocks)) {
-@@ -501,16 +506,17 @@ static void tcp_options_write(__be32 *pt
-                       tp->duplicate_sack : tp->selective_acks;
-               int this_sack;
--              *ptr++ = htonl((TCPOPT_NOP  << 24) |
--                             (TCPOPT_NOP  << 16) |
--                             (TCPOPT_SACK <<  8) |
--                             (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
-+              net_hdr_word(ptr++) =
-+                      htonl((TCPOPT_NOP << 24) |
-+                            (TCPOPT_NOP << 16) |
-+                            (TCPOPT_SACK << 8) |
-+                            (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
-                                                    TCPOLEN_SACK_PERBLOCK)));
-               for (this_sack = 0; this_sack < opts->num_sack_blocks;
-                    ++this_sack) {
--                      *ptr++ = htonl(sp[this_sack].start_seq);
--                      *ptr++ = htonl(sp[this_sack].end_seq);
-+                      net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
-+                      net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
-               }
-               tp->rx_opt.dsack = 0;
-@@ -523,13 +529,14 @@ static void tcp_options_write(__be32 *pt
-               if (foc->exp) {
-                       len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
--                      *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
-+                      net_hdr_word(ptr) =
-+                              htonl((TCPOPT_EXP << 24) | (len << 16) |
-                                    TCPOPT_FASTOPEN_MAGIC);
-                       p += TCPOLEN_EXP_FASTOPEN_BASE;
-               } else {
-                       len = TCPOLEN_FASTOPEN_BASE + foc->len;
--                      *p++ = TCPOPT_FASTOPEN;
--                      *p++ = len;
-+                      net_hdr_word(p++) = TCPOPT_FASTOPEN;
-+                      net_hdr_word(p++) = len;
-               }
-               memcpy(p, foc->val, foc->len);
---- a/net/ipv4/igmp.c
-+++ b/net/ipv4/igmp.c
-@@ -496,7 +496,7 @@ static struct sk_buff *add_grec(struct s
-               if (!skb)
-                       return NULL;
-               psrc = (__be32 *)skb_put(skb, sizeof(__be32));
--              *psrc = psf->sf_inaddr;
-+              net_hdr_word(psrc) = psf->sf_inaddr;
-               scount++; stotal++;
-               if ((type == IGMPV3_ALLOW_NEW_SOURCES ||
-                    type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) {
---- a/include/uapi/linux/igmp.h
-+++ b/include/uapi/linux/igmp.h
-@@ -32,7 +32,7 @@ struct igmphdr {
-       __u8 code;              /* For newer IGMP */
-       __sum16 csum;
-       __be32 group;
--};
-+} __attribute__((packed, aligned(2)));
- /* V3 group record types [grec_type] */
- #define IGMPV3_MODE_IS_INCLUDE                1
-@@ -48,7 +48,7 @@ struct igmpv3_grec {
-       __be16  grec_nsrcs;
-       __be32  grec_mca;
-       __be32  grec_src[0];
--};
-+} __attribute__((packed, aligned(2)));
- struct igmpv3_report {
-       __u8 type;
-@@ -57,7 +57,7 @@ struct igmpv3_report {
-       __be16 resv2;
-       __be16 ngrec;
-       struct igmpv3_grec grec[0];
--};
-+} __attribute__((packed, aligned(2)));
- struct igmpv3_query {
-       __u8 type;
-@@ -78,7 +78,7 @@ struct igmpv3_query {
-       __u8 qqic;
-       __be16 nsrcs;
-       __be32 srcs[0];
--};
-+} __attribute__((packed, aligned(2)));
- #define IGMP_HOST_MEMBERSHIP_QUERY    0x11    /* From RFC1112 */
- #define IGMP_HOST_MEMBERSHIP_REPORT   0x12    /* Ditto */
---- a/net/core/flow_dissector.c
-+++ b/net/core/flow_dissector.c
-@@ -53,7 +53,7 @@ __be32 __skb_flow_get_ports(const struct
-               ports = __skb_header_pointer(skb, thoff + poff,
-                                            sizeof(_ports), data, hlen, &_ports);
-               if (ports)
--                      return *ports;
-+                      return (__be32)net_hdr_word(ports);
-       }
-       return 0;
---- a/include/uapi/linux/icmpv6.h
-+++ b/include/uapi/linux/icmpv6.h
-@@ -76,7 +76,7 @@ struct icmp6hdr {
- #define icmp6_addrconf_other  icmp6_dataun.u_nd_ra.other
- #define icmp6_rt_lifetime     icmp6_dataun.u_nd_ra.rt_lifetime
- #define icmp6_router_pref     icmp6_dataun.u_nd_ra.router_pref
--};
-+} __attribute__((packed, aligned(2)));
- #define ICMPV6_ROUTER_PREF_LOW                0x3
---- a/include/net/ndisc.h
-+++ b/include/net/ndisc.h
-@@ -76,7 +76,7 @@ struct ra_msg {
-         struct icmp6hdr               icmph;
-       __be32                  reachable_time;
-       __be32                  retrans_timer;
--};
-+} __attribute__((packed, aligned(2)));
- struct rd_msg {
-       struct icmp6hdr icmph;
-@@ -148,10 +148,10 @@ static inline u32 ndisc_hashfn(const voi
- {
-       const u32 *p32 = pkey;
--      return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
--              (p32[1] * hash_rnd[1]) +
--              (p32[2] * hash_rnd[2]) +
--              (p32[3] * hash_rnd[3]));
-+      return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
-+              (net_hdr_word(&p32[1]) * hash_rnd[1]) +
-+              (net_hdr_word(&p32[2]) * hash_rnd[2]) +
-+              (net_hdr_word(&p32[3]) * hash_rnd[3]));
- }
- static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
---- a/net/sched/cls_u32.c
-+++ b/net/sched/cls_u32.c
-@@ -151,7 +151,7 @@ next_knode:
-                       data = skb_header_pointer(skb, toff, 4, &hdata);
-                       if (!data)
-                               goto out;
--                      if ((*data ^ key->val) & key->mask) {
-+                      if ((net_hdr_word(data) ^ key->val) & key->mask) {
-                               n = rcu_dereference_bh(n->next);
-                               goto next_knode;
-                       }
-@@ -204,8 +204,8 @@ check_terminal:
-                                                 &hdata);
-                       if (!data)
-                               goto out;
--                      sel = ht->divisor & u32_hash_fold(*data, &n->sel,
--                                                        n->fshift);
-+                      sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
-+                                                        &n->sel, n->fshift);
-               }
-               if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
-                       goto next_ht;
---- a/net/ipv6/ip6_offload.c
-+++ b/net/ipv6/ip6_offload.c
-@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive
-                       continue;
-               iph2 = (struct ipv6hdr *)(p->data + off);
--              first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
-+              first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
-               /* All fields must match except length and Traffic Class.
-                * XXX skbs on the gro_list have all been parsed and pulled
---- a/include/net/addrconf.h
-+++ b/include/net/addrconf.h
-@@ -43,7 +43,7 @@ struct prefix_info {
-       __be32                  reserved2;
-       struct in6_addr         prefix;
--};
-+} __attribute__((packed, aligned(2)));
- #include <linux/netdevice.h>
---- a/include/net/inet_ecn.h
-+++ b/include/net/inet_ecn.h
-@@ -115,13 +115,13 @@ static inline int IP6_ECN_set_ce(struct
- {
-       if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))
-               return 0;
--      *(__be32*)iph |= htonl(INET_ECN_CE << 20);
-+      net_hdr_word(iph) |= htonl(INET_ECN_CE << 20);
-       return 1;
- }
- static inline void IP6_ECN_clear(struct ipv6hdr *iph)
- {
--      *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20);
-+      net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20);
- }
- static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner)
---- a/include/net/ipv6.h
-+++ b/include/net/ipv6.h
-@@ -107,7 +107,7 @@ struct frag_hdr {
-       __u8    reserved;
-       __be16  frag_off;
-       __be32  identification;
--};
-+} __attribute__((packed, aligned(2)));
- #define       IP6_MF          0x0001
- #define       IP6_OFFSET      0xFFF8
-@@ -396,8 +396,8 @@ static inline void __ipv6_addr_set_half(
-       }
- #endif
- #endif
--      addr[0] = wh;
--      addr[1] = wl;
-+      net_hdr_word(&addr[0]) = wh;
-+      net_hdr_word(&addr[1]) = wl;
- }
- static inline void ipv6_addr_set(struct in6_addr *addr, 
-@@ -456,6 +456,8 @@ static inline bool ipv6_prefix_equal(con
-       const __be32 *a1 = addr1->s6_addr32;
-       const __be32 *a2 = addr2->s6_addr32;
-       unsigned int pdw, pbi;
-+      /* Used for last <32-bit fraction of prefix */
-+      u32 pbia1, pbia2;
-       /* check complete u32 in prefix */
-       pdw = prefixlen >> 5;
-@@ -464,7 +466,9 @