ar71xx: move arch specific files to files-2.6.39
authorGabor Juhos <juhosg@openwrt.org>
Sun, 22 Jan 2012 22:38:11 +0000 (22:38 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Sun, 22 Jan 2012 22:38:11 +0000 (22:38 +0000)
SVN-Revision: 29867

242 files changed:
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Kconfig [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Makefile [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/ar71xx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/early_printk.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/gpio.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/irq.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-ap96.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-nx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-all0258n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap121.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap81.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap83.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap96.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-db120.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-eap7660d.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-hornet-ub.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ja76pf.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-jwap003.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-nbg460n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-om2p.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-pb42.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-pb44.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-pb92.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-rb4xx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-rb750.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-rw2458n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tew-632brp.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-mr3020.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-mr3x20.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd-v2.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr1043nd.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr2543n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr703n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd-v4.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr841n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-tl-wr941nd.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ubnt.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-whr-hp-g300n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wndr3700.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wnr2000.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wp543.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wrt160nl.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wrt400n.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wzr-hp-ag300h.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh2.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g450h.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-zcn-1523h.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/machtype.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/nvram.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/nvram.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/pci.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/prom.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/setup.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/ar71xx.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/gpio.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/irq.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/mach-rb750.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/mangle-port.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/pci.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/platform.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/include/asm/mach-ar71xx/war.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/pci/pci-ar71xx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/arch/mips/pci/pci-ar724x.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/mtd/maps/ar91xx_flash.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/Kconfig [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/Makefile [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx.h [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_ar7240.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_ar8216.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_debugfs.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_ethtool.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_main.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_mdio.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/net/ag71xx/ag71xx_phy.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/spi/ar71xx_spi.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/spi/pb44_spi.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/tty/serial/ar933x_uart.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/usb/host/ehci-ar71xx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/usb/host/ohci-ar71xx.c [new file with mode: 0644]
target/linux/ar71xx/files-2.6.39/drivers/watchdog/ar71xx_wdt.c [new file with mode: 0644]
target/linux/ar71xx/files/arch/mips/ar71xx/Kconfig [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/Makefile [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap94-pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap94-pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-ar9xxx-wmac.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-db120-pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-db120-pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-dsa.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-dsa.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-gpio-buttons.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-gpio-buttons.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-leds-gpio.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-leds-gpio.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-m25p80.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-m25p80.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-pb42-pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-pb42-pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-pb9x-pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-pb9x-pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-usb.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/dev-usb.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/devices.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/devices.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/irq.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-alfa-ap96.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-alfa-nx.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-all0258n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap121.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap81.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap83.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ap96.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-aw-nr580.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-db120.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-600-a1.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-615-c1.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-825-b1.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-eap7660d.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-hornet-ub.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ja76pf.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-jwap003.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w04nu.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-mzk-w300nh.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-nbg460n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-om2p.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb44.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb92.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb4xx.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-rw2458n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tew-632brp.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-mr3020.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-mr3x20.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wa901nd-v2.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wa901nd.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr1043nd.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr2543n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr703n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr741nd-v4.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr741nd.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr841n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr941nd.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ubnt.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-whr-hp-g300n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wndr3700.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wnr2000.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wp543.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wrt160nl.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wrt400n.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wzr-hp-ag300h.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wzr-hp-g300nh.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wzr-hp-g300nh2.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-wzr-hp-g450h.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/mach-zcn-1523h.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/machtype.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/nvram.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/nvram.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.h [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/pci.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/prom.c [deleted file]
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/gpio.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/irq.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/mach-rb750.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/mangle-port.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/pci.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h [deleted file]
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/war.h [deleted file]
target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c [deleted file]
target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c [deleted file]
target/linux/ar71xx/files/drivers/mtd/maps/ar91xx_flash.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/Kconfig [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/Makefile [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar8216.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_debugfs.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ethtool.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mdio.c [deleted file]
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c [deleted file]
target/linux/ar71xx/files/drivers/spi/ar71xx_spi.c [deleted file]
target/linux/ar71xx/files/drivers/spi/pb44_spi.c [deleted file]
target/linux/ar71xx/files/drivers/tty/serial/ar933x_uart.c [deleted file]
target/linux/ar71xx/files/drivers/usb/host/ehci-ar71xx.c [deleted file]
target/linux/ar71xx/files/drivers/usb/host/ohci-ar71xx.c [deleted file]
target/linux/ar71xx/files/drivers/watchdog/ar71xx_wdt.c [deleted file]

diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Kconfig b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Kconfig
new file mode 100644 (file)
index 0000000..c22cd4a
--- /dev/null
@@ -0,0 +1,492 @@
+if ATHEROS_AR71XX
+
+menu "Atheros AR71xx machine selection"
+config AR71XX_MACH_ALFA_AP96
+       bool "ALFA Network AP96 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_HORNET_UB
+       bool "Alfa Networks Hornet-UB board support"
+       select SOC_AR933X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select AR71XX_DEV_AR9XXX_WMAC
+
+config AR71XX_MACH_ALFA_NX
+       bool "ALFA Network N2/N5 board support"
+       select SOC_AR724X
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_ALL0258N
+       bool "Allnet ALL0258N support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_AP81
+       bool "Atheros AP81 board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_AP83
+       bool "Atheros AP83 board support"
+       select SOC_AR913X
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_AP96
+       bool "Atheros AP96 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP94_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_AP121
+       bool "Atheros AP121 board support"
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select AR71XX_DEV_AR9XXX_WMAC
+       select SOC_AR933X
+
+config AR71XX_MACH_DB120
+       bool "Atheros DB120 board support"
+       select SOC_AR934X
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_DB120_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_DIR_600_A1
+       bool "D-Link DIR-600 rev. A1 support"
+       select SOC_AR724X
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_NVRAM
+
+config AR71XX_MACH_DIR_615_C1
+       bool "D-Link DIR-615 rev. C1 support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_NVRAM
+
+config AR71XX_MACH_DIR_825_B1
+       bool "D-Link DIR-825 rev. B1 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP94_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_JA76PF
+       bool "jjPlus JA76PF board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_JWAP003
+       bool "jjPlus JWAP003 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_PB42
+       bool "Atheros PB42 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+
+config AR71XX_MACH_PB44
+       bool "Atheros PB44 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_PB92
+       bool "Atheros PB92 board support"
+       select SOC_AR724X
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB9X_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_RW2458N
+       bool "Redwave RW2458N board support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_AW_NR580
+       bool "AzureWave AW-NR580 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_WZR_HP_AG300H
+       bool "Buffalo WZR-HP-AG300H board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_WZR_HP_G450H
+       bool "Buffalo WZR-HP-G450H board support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_WZR_HP_G300NH
+       bool "Buffalo WZR-HP-G300NH board support"
+       select SOC_AR913X
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select RTL8366_SMI
+
+config AR71XX_MACH_WZR_HP_G300NH2
+       bool "Buffalo WZR-HP-G300NH2 board support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_WHR_HP_G300N
+       bool "Buffalo WHR-HP-G300N board support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_WP543
+       bool "Compex WP543/WPJ543 board support"
+       select SOC_AR71XX
+       select MYLOADER
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_WRT160NL
+       bool "Linksys WRT160NL board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select AR71XX_NVRAM
+
+config AR71XX_MACH_WRT400N
+       bool "Linksys WRT400N board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_AP94_PCI if PCI
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_RB4XX
+       bool "MikroTik RouterBOARD 4xx series support"
+       select SOC_AR71XX
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_RB750
+       bool "MikroTik RouterBOARD 750 support"
+       select SOC_AR724X
+
+config AR71XX_MACH_WNDR3700
+       bool "NETGEAR WNDR3700 board support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP94_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_WNR2000
+       bool "NETGEAR WNR2000 board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_OM2P
+       bool "OpenMesh OM2P board support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_MZK_W04NU
+       bool "Planex MZK-W04NU board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_MZK_W300NH
+       bool "Planex MZK-W300NH board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_NBG460N
+       bool "Zyxel NBG460N/550N/550NH board support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_MR3020
+       bool "TP-LINK TL-MR3020 support"
+       select SOC_AR933X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select AR71XX_DEV_AR9XXX_WMAC
+
+config AR71XX_MACH_TL_MR3X20
+       bool "TP-LINK TL-MR3220/3420 support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_TL_WA901ND
+       bool "TP-LINK TL-WA901ND support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_WA901ND_V2
+       bool "TP-LINK TL-WA901ND v2 support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_WR703N
+       bool "TP-LINK TL-WR703N support"
+       select SOC_AR933X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+       select AR71XX_DEV_AR9XXX_WMAC
+
+config AR71XX_MACH_TL_WR741ND
+       bool "TP-LINK TL-WR741ND support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_WR741ND_V4
+       bool "TP-LINK TL-WR741ND v4 support"
+       select SOC_AR933X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_AR9XXX_WMAC
+
+config AR71XX_MACH_TL_WR841N_V1
+       bool "TP-LINK TL-WR841N v1 support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_DSA
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_WR941ND
+       bool "TP-LINK TL-WR941ND support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_DSA
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_TL_WR1043ND
+       bool "TP-LINK TL-WR1043ND support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_TL_WR2543N
+       bool "TP-LINK TL-WR2543N/ND support"
+       select SOC_AR724X
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_TEW_632BRP
+       bool "TRENDnet TEW-632BRP support"
+       select SOC_AR913X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AR9XXX_WMAC
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_NVRAM
+
+config AR71XX_MACH_UBNT
+       bool "Ubiquiti AR71xx based boards support"
+       select SOC_AR71XX
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+       select AR71XX_DEV_PB42_PCI if PCI
+       select AR71XX_DEV_USB
+
+config AR71XX_MACH_EAP7660D
+       bool "Senao EAP7660D support"
+       select SOC_AR71XX
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+config AR71XX_MACH_ZCN_1523H
+       bool "Zcomax ZCN-1523H support"
+       select SOC_AR724X
+       select AR71XX_DEV_M25P80
+       select AR71XX_DEV_AP91_PCI if PCI
+       select AR71XX_DEV_GPIO_BUTTONS
+       select AR71XX_DEV_LEDS_GPIO
+
+endmenu
+
+config SOC_AR71XX
+       bool
+       select USB_ARCH_HAS_EHCI
+       select USB_ARCH_HAS_OHCI
+
+config SOC_AR724X
+       bool
+       select USB_ARCH_HAS_EHCI
+       select USB_ARCH_HAS_OHCI
+
+config SOC_AR913X
+       bool
+       select USB_ARCH_HAS_EHCI
+
+config SOC_AR934X
+       bool
+       select USB_ARCH_HAS_EHCI
+
+config AR71XX_DEV_M25P80
+       def_bool n
+
+config AR71XX_DEV_AP91_PCI
+       select AR71XX_PCI_ATH9K_FIXUP
+       def_bool n
+
+config AR71XX_DEV_AP94_PCI
+       select AR71XX_PCI_ATH9K_FIXUP
+       def_bool n
+
+config AR71XX_DEV_AR9XXX_WMAC
+       def_bool n
+
+config AR71XX_DEV_DB120_PCI
+       select AR71XX_PCI_ATH9K_FIXUP
+       def_bool n
+
+config AR71XX_DEV_DSA
+       def_bool n
+
+config AR71XX_DEV_GPIO_BUTTONS
+       def_bool n
+
+config AR71XX_DEV_LEDS_GPIO
+       def_bool n
+
+config AR71XX_DEV_PB42_PCI
+       def_bool n
+
+config AR71XX_DEV_PB9X_PCI
+       def_bool n
+
+config AR71XX_DEV_USB
+       def_bool n
+
+config AR71XX_NVRAM
+       def_bool n
+
+config AR71XX_PCI_ATH9K_FIXUP
+       def_bool n
+
+config SOC_AR933X
+       bool
+       select USB_ARCH_HAS_EHCI
+
+endif
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Makefile b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/Makefile
new file mode 100644 (file)
index 0000000..ba12234
--- /dev/null
@@ -0,0 +1,80 @@
+#
+# Makefile for the Atheros AR71xx SoC specific parts of the kernel
+#
+# Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+# Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 as published
+# by the Free Software Foundation.
+
+obj-y  := prom.o irq.o setup.o devices.o gpio.o ar71xx.o
+
+obj-$(CONFIG_EARLY_PRINTK)             += early_printk.o
+obj-$(CONFIG_PCI)                      += pci.o
+
+obj-$(CONFIG_AR71XX_DEV_AP91_PCI)      += dev-ap91-pci.o
+obj-$(CONFIG_AR71XX_DEV_AP94_PCI)      += dev-ap94-pci.o
+obj-$(CONFIG_AR71XX_DEV_AR9XXX_WMAC)   += dev-ar9xxx-wmac.o
+obj-$(CONFIG_AR71XX_DEV_DB120_PCI)     += dev-db120-pci.o
+obj-$(CONFIG_AR71XX_DEV_DSA)           += dev-dsa.o
+obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS)  += dev-gpio-buttons.o
+obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO)     += dev-leds-gpio.o
+obj-$(CONFIG_AR71XX_DEV_M25P80)                += dev-m25p80.o
+obj-$(CONFIG_AR71XX_DEV_PB42_PCI)      += dev-pb42-pci.o
+obj-$(CONFIG_AR71XX_DEV_PB9X_PCI)      += dev-pb9x-pci.o
+obj-$(CONFIG_AR71XX_DEV_USB)           += dev-usb.o
+
+obj-$(CONFIG_AR71XX_NVRAM)             += nvram.o
+obj-$(CONFIG_AR71XX_PCI_ATH9K_FIXUP)   += pci-ath9k-fixup.o
+
+obj-$(CONFIG_AR71XX_MACH_ALFA_AP96)    += mach-alfa-ap96.o
+obj-$(CONFIG_AR71XX_MACH_ALFA_NX)      += mach-alfa-nx.o
+obj-$(CONFIG_AR71XX_MACH_ALL0258N)     += mach-all0258n.o
+obj-$(CONFIG_AR71XX_MACH_AP121)                += mach-ap121.o
+obj-$(CONFIG_AR71XX_MACH_AP81)         += mach-ap81.o
+obj-$(CONFIG_AR71XX_MACH_AP83)         += mach-ap83.o
+obj-$(CONFIG_AR71XX_MACH_AP96)         += mach-ap96.o
+obj-$(CONFIG_AR71XX_MACH_AW_NR580)     += mach-aw-nr580.o
+obj-$(CONFIG_AR71XX_MACH_DB120)                += mach-db120.o
+obj-$(CONFIG_AR71XX_MACH_DIR_600_A1)   += mach-dir-600-a1.o
+obj-$(CONFIG_AR71XX_MACH_DIR_615_C1)   += mach-dir-615-c1.o
+obj-$(CONFIG_AR71XX_MACH_DIR_825_B1)   += mach-dir-825-b1.o
+obj-$(CONFIG_AR71XX_MACH_EAP7660D)     += mach-eap7660d.o
+obj-$(CONFIG_AR71XX_MACH_JA76PF)       += mach-ja76pf.o
+obj-$(CONFIG_AR71XX_MACH_JWAP003)      += mach-jwap003.o
+obj-$(CONFIG_AR71XX_MACH_HORNET_UB)    += mach-hornet-ub.o
+obj-$(CONFIG_AR71XX_MACH_MZK_W04NU)    += mach-mzk-w04nu.o
+obj-$(CONFIG_AR71XX_MACH_MZK_W300NH)   += mach-mzk-w300nh.o
+obj-$(CONFIG_AR71XX_MACH_NBG460N)      += mach-nbg460n.o
+obj-$(CONFIG_AR71XX_MACH_OM2P)         += mach-om2p.o
+obj-$(CONFIG_AR71XX_MACH_PB42)         += mach-pb42.o
+obj-$(CONFIG_AR71XX_MACH_PB44)         += mach-pb44.o
+obj-$(CONFIG_AR71XX_MACH_PB92)         += mach-pb92.o
+obj-$(CONFIG_AR71XX_MACH_RB4XX)                += mach-rb4xx.o
+obj-$(CONFIG_AR71XX_MACH_RB750)                += mach-rb750.o
+obj-$(CONFIG_AR71XX_MACH_RW2458N)      += mach-rw2458n.o
+obj-$(CONFIG_AR71XX_MACH_TEW_632BRP)   += mach-tew-632brp.o
+obj-$(CONFIG_AR71XX_MACH_TL_MR3020)    += mach-tl-mr3020.o
+obj-$(CONFIG_AR71XX_MACH_TL_MR3X20)    += mach-tl-mr3x20.o
+obj-$(CONFIG_AR71XX_MACH_TL_WA901ND)   += mach-tl-wa901nd.o
+obj-$(CONFIG_AR71XX_MACH_TL_WA901ND_V2)        += mach-tl-wa901nd-v2.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND)   += mach-tl-wr741nd.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND_V4)        += mach-tl-wr741nd-v4.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR941ND)   += mach-tl-wr941nd.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND)  += mach-tl-wr1043nd.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR2543N)   += mach-tl-wr2543n.o
+obj-$(CONFIG_AR71XX_MACH_TL_WR703N)    += mach-tl-wr703n.o
+obj-$(CONFIG_AR71XX_MACH_UBNT)         += mach-ubnt.o
+obj-$(CONFIG_AR71XX_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
+obj-$(CONFIG_AR71XX_MACH_WNDR3700)     += mach-wndr3700.o
+obj-$(CONFIG_AR71XX_MACH_WNR2000)      += mach-wnr2000.o
+obj-$(CONFIG_AR71XX_MACH_WP543)                += mach-wp543.o
+obj-$(CONFIG_AR71XX_MACH_WRT160NL)     += mach-wrt160nl.o
+obj-$(CONFIG_AR71XX_MACH_WRT400N)      += mach-wrt400n.o
+obj-$(CONFIG_AR71XX_MACH_WZR_HP_G300NH)        += mach-wzr-hp-g300nh.o
+obj-$(CONFIG_AR71XX_MACH_WZR_HP_G300NH2)       += mach-wzr-hp-g300nh2.o
+obj-$(CONFIG_AR71XX_MACH_WZR_HP_AG300H)        += mach-wzr-hp-ag300h.o
+obj-$(CONFIG_AR71XX_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
+obj-$(CONFIG_AR71XX_MACH_ZCN_1523H)    += mach-zcn-1523h.o
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/ar71xx.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/ar71xx.c
new file mode 100644 (file)
index 0000000..93cbe53
--- /dev/null
@@ -0,0 +1,278 @@
+/*
+ *  AR71xx SoC routines
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+static DEFINE_MUTEX(ar71xx_flash_mutex);
+static DEFINE_SPINLOCK(ar71xx_device_lock);
+
+void __iomem *ar71xx_ddr_base;
+EXPORT_SYMBOL_GPL(ar71xx_ddr_base);
+
+void __iomem *ar71xx_pll_base;
+EXPORT_SYMBOL_GPL(ar71xx_pll_base);
+
+void __iomem *ar71xx_reset_base;
+EXPORT_SYMBOL_GPL(ar71xx_reset_base);
+
+void __iomem *ar71xx_gpio_base;
+EXPORT_SYMBOL_GPL(ar71xx_gpio_base);
+
+void __iomem *ar71xx_usb_ctrl_base;
+EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base);
+
+void ar71xx_device_stop(u32 mask)
+{
+       unsigned long flags;
+       u32 mask_inv;
+       u32 t;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240;
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+               t |= mask;
+               t &= ~mask_inv;
+               ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t | mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t | mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       default:
+               BUG();
+       }
+}
+EXPORT_SYMBOL_GPL(ar71xx_device_stop);
+
+void ar71xx_device_start(u32 mask)
+{
+       unsigned long flags;
+       u32 mask_inv;
+       u32 t;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240;
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+               t &= ~mask;
+               t |= mask_inv;
+               ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t & ~mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t & ~mask);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       default:
+               BUG();
+       }
+}
+EXPORT_SYMBOL_GPL(ar71xx_device_start);
+
+void ar71xx_device_reset_rmw(u32 clear, u32 set)
+{
+       unsigned long flags;
+       unsigned int reg;
+       u32 t;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               reg = AR71XX_RESET_REG_RESET_MODULE;
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               reg = AR724X_RESET_REG_RESET_MODULE;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               reg = AR91XX_RESET_REG_RESET_MODULE;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               reg = AR933X_RESET_REG_RESET_MODULE;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               reg = AR934X_RESET_REG_RESET_MODULE;
+               break;
+
+       default:
+               BUG();
+       }
+
+       spin_lock_irqsave(&ar71xx_device_lock, flags);
+       t = ar71xx_reset_rr(reg);
+       t &= ~clear;
+       t |= set;
+       ar71xx_reset_wr(reg, t);
+       spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+}
+EXPORT_SYMBOL_GPL(ar71xx_device_reset_rmw);
+
+int ar71xx_device_stopped(u32 mask)
+{
+       unsigned long flags;
+       u32 t;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               spin_lock_irqsave(&ar71xx_device_lock, flags);
+               t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE);
+               spin_unlock_irqrestore(&ar71xx_device_lock, flags);
+               break;
+
+       default:
+               BUG();
+       }
+
+       return ((t & mask) == mask);
+}
+EXPORT_SYMBOL_GPL(ar71xx_device_stopped);
+
+void ar71xx_ddr_flush(u32 reg)
+{
+       ar71xx_ddr_wr(reg, 1);
+       while ((ar71xx_ddr_rr(reg) & 0x1))
+               ;
+
+       ar71xx_ddr_wr(reg, 1);
+       while ((ar71xx_ddr_rr(reg) & 0x1))
+               ;
+}
+EXPORT_SYMBOL_GPL(ar71xx_ddr_flush);
+
+void ar71xx_flash_acquire(void)
+{
+       mutex_lock(&ar71xx_flash_mutex);
+}
+EXPORT_SYMBOL_GPL(ar71xx_flash_acquire);
+
+void ar71xx_flash_release(void)
+{
+       mutex_unlock(&ar71xx_flash_mutex);
+}
+EXPORT_SYMBOL_GPL(ar71xx_flash_release);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c
new file mode 100644 (file)
index 0000000..7cd8c65
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ *  Atheros AP91 reference board PCI initialization
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath9k_platform.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "dev-ap91-pci.h"
+#include "pci-ath9k-fixup.h"
+
+static struct ath9k_platform_data ap91_wmac_data = {
+       .led_pin = -1,
+};
+static char ap91_wmac_mac[6];
+
+static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }
+};
+
+static int ap91_pci_plat_dev_init(struct pci_dev *dev)
+{
+       switch (PCI_SLOT(dev->devfn)) {
+       case 0:
+               dev->dev.platform_data = &ap91_wmac_data;
+               break;
+       }
+
+       return 0;
+}
+
+__init void ap91_pci_setup_wmac_leds(struct gpio_led *leds, int num_leds)
+{
+       ap91_wmac_data.leds = leds;
+       ap91_wmac_data.num_leds = num_leds;
+}
+
+__init void ap91_pci_setup_wmac_led_pin(int pin)
+{
+       ap91_wmac_data.led_pin = pin;
+}
+
+__init void ap91_pci_setup_wmac_gpio(u32 mask, u32 val)
+{
+       ap91_wmac_data.gpio_mask = mask;
+       ap91_wmac_data.gpio_val = val;
+}
+
+void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr)
+{
+       if (cal_data)
+               memcpy(ap91_wmac_data.eeprom_data, cal_data,
+                      sizeof(ap91_wmac_data.eeprom_data));
+
+       if (mac_addr) {
+               memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac));
+               ap91_wmac_data.macaddr = ap91_wmac_mac;
+       }
+
+       ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init;
+       ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs);
+
+       pci_enable_ath9k_fixup(0, ap91_wmac_data.eeprom_data);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h
new file mode 100644 (file)
index 0000000..ebcbc47
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ *  Atheros AP91 reference board PCI initialization
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_AP91_PCI_H
+#define _AR71XX_DEV_AP91_PCI_H
+
+#include <linux/leds.h>
+
+#if defined(CONFIG_AR71XX_DEV_AP91_PCI)
+void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init;
+void ap91_pci_setup_wmac_led_pin(int pin) __init;
+void ap91_pci_setup_wmac_gpio(u32 mask, u32 val) __init;
+void ap91_pci_setup_wmac_leds(struct gpio_led *leds, int num_leds) __init;
+#else
+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { }
+static inline void ap91_pci_setup_wmac_led_pin(int pin) { }
+static inline void ap91_pci_setup_wmac_gpio(u32 mask, u32 gpio) { }
+static inline void ap91_pci_setup_wmac_leds(struct gpio_led *leds, int num_leds) { };
+#endif
+
+#endif /* _AR71XX_DEV_AP91_PCI_H */
+
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c
new file mode 100644 (file)
index 0000000..05b5be4
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ *  Atheros AP94 reference board PCI initialization
+ *
+ *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath9k_platform.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "dev-ap94-pci.h"
+#include "pci-ath9k-fixup.h"
+
+static struct ath9k_platform_data ap94_wmac0_data = {
+       .led_pin = -1,
+};
+static struct ath9k_platform_data ap94_wmac1_data = {
+       .led_pin = -1,
+};
+static char ap94_wmac0_mac[6];
+static char ap94_wmac1_mac[6];
+
+static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }, {
+               .slot   = 1,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV1,
+       }
+};
+
+static int ap94_pci_plat_dev_init(struct pci_dev *dev)
+{
+       switch (PCI_SLOT(dev->devfn)) {
+       case 17:
+               dev->dev.platform_data = &ap94_wmac0_data;
+               break;
+
+       case 18:
+               dev->dev.platform_data = &ap94_wmac1_data;
+               break;
+       }
+
+       return 0;
+}
+
+__init void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin)
+{
+       switch (wmac) {
+       case 0:
+               ap94_wmac0_data.led_pin = pin;
+               break;
+       case 1:
+               ap94_wmac1_data.led_pin = pin;
+               break;
+       }
+}
+
+__init void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val)
+{
+       switch (wmac) {
+       case 0:
+               ap94_wmac0_data.gpio_mask = mask;
+               ap94_wmac0_data.gpio_val = val;
+               break;
+       case 1:
+               ap94_wmac1_data.gpio_mask = mask;
+               ap94_wmac1_data.gpio_val = val;
+               break;
+       }
+}
+
+void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+                         u8 *cal_data1, u8 *mac_addr1)
+{
+       if (cal_data0)
+               memcpy(ap94_wmac0_data.eeprom_data, cal_data0,
+                      sizeof(ap94_wmac0_data.eeprom_data));
+
+       if (cal_data1)
+               memcpy(ap94_wmac1_data.eeprom_data, cal_data1,
+                      sizeof(ap94_wmac1_data.eeprom_data));
+
+       if (mac_addr0) {
+               memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac));
+               ap94_wmac0_data.macaddr = ap94_wmac0_mac;
+       }
+
+       if (mac_addr1) {
+               memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac));
+               ap94_wmac1_data.macaddr = ap94_wmac1_mac;
+       }
+
+       ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init;
+       ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs);
+
+       pci_enable_ath9k_fixup(17, ap94_wmac0_data.eeprom_data);
+       pci_enable_ath9k_fixup(18, ap94_wmac1_data.eeprom_data);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h
new file mode 100644 (file)
index 0000000..4584528
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ *  Atheros AP94 reference board PCI initialization
+ *
+ *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_AP94_PCI_H
+#define _AR71XX_DEV_AP94_PCI_H
+
+#if defined(CONFIG_AR71XX_DEV_AP94_PCI)
+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+                  u8 *cal_data1, u8 *mac_addr1) __init;
+
+void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) __init;
+void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) __init;
+
+#else
+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+                                u8 *cal_data1, u8 *mac_addr1) {}
+
+static inline void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) {}
+static inline void ap94_pci_setup_wmac_gpio(unsigned wmac,
+                                           u32 mask, u32 val) {}
+#endif
+
+#endif /* _AR71XX_DEV_AP94_PCI_H */
+
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c
new file mode 100644 (file)
index 0000000..90db388
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ *  Atheros AR9XXX SoCs built-in WMAC device support
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "dev-ar9xxx-wmac.h"
+
+#define MHZ_25 (25 * 1000 * 1000)
+
+static struct ath9k_platform_data ar9xxx_wmac_data = {
+       .led_pin = -1,
+};
+static char ar9xxx_wmac_mac[6];
+
+static struct resource ar9xxx_wmac_resources[] = {
+       {
+               /* .start and .end fields are filled dynamically */
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = AR71XX_CPU_IRQ_IP2,
+               .end    = AR71XX_CPU_IRQ_IP2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device ar9xxx_wmac_device = {
+       .name           = "ath9k",
+       .id             = -1,
+       .resource       = ar9xxx_wmac_resources,
+       .num_resources  = ARRAY_SIZE(ar9xxx_wmac_resources),
+       .dev = {
+               .platform_data = &ar9xxx_wmac_data,
+       },
+};
+
+static void ar913x_wmac_init(void)
+{
+       ar71xx_device_stop(RESET_MODULE_AMBA2WMAC);
+       mdelay(10);
+
+       ar71xx_device_start(RESET_MODULE_AMBA2WMAC);
+       mdelay(10);
+
+       ar9xxx_wmac_resources[0].start = AR91XX_WMAC_BASE;
+       ar9xxx_wmac_resources[0].end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1;
+}
+
+static int ar933x_r1_get_wmac_revision(void)
+{
+       return ar71xx_soc_rev;
+}
+
+static int ar933x_wmac_reset(void)
+{
+       unsigned retries = 0;
+
+       ar71xx_device_stop(AR933X_RESET_WMAC);
+       ar71xx_device_start(AR933X_RESET_WMAC);
+
+       while (1) {
+               u32 bootstrap;
+
+               bootstrap = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+               if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
+                       return 0;
+
+               if (retries > 20)
+                       break;
+
+               udelay(10000);
+               retries++;
+       }
+
+       pr_err("ar93xx: WMAC reset timed out");
+       return -ETIMEDOUT;
+}
+
+static void ar933x_wmac_init(void)
+{
+       ar9xxx_wmac_device.name = "ar933x_wmac";
+       ar9xxx_wmac_resources[0].start = AR933X_WMAC_BASE;
+       ar9xxx_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+       if (ar71xx_ref_freq == MHZ_25)
+               ar9xxx_wmac_data.is_clk_25mhz = true;
+
+       if (ar71xx_soc_rev == 1)
+               ar9xxx_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
+
+       ar9xxx_wmac_data.external_reset = ar933x_wmac_reset;
+
+       ar933x_wmac_reset();
+}
+
+static void ar934x_wmac_init(void)
+{
+       ar9xxx_wmac_device.name = "ar934x_wmac";
+       ar9xxx_wmac_resources[0].start = AR934X_WMAC_BASE;
+       ar9xxx_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
+       ar9xxx_wmac_resources[1].start = AR934X_IP2_IRQ_WMAC;
+       ar9xxx_wmac_resources[1].start = AR934X_IP2_IRQ_WMAC;
+       if (ar71xx_ref_freq == MHZ_25)
+               ar9xxx_wmac_data.is_clk_25mhz = true;
+}
+
+void __init ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr)
+{
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ar913x_wmac_init();
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ar933x_wmac_init();
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ar934x_wmac_init();
+               break;
+
+       default:
+               BUG();
+       }
+
+       if (cal_data)
+               memcpy(ar9xxx_wmac_data.eeprom_data, cal_data,
+                      sizeof(ar9xxx_wmac_data.eeprom_data));
+
+       if (mac_addr) {
+               memcpy(ar9xxx_wmac_mac, mac_addr, sizeof(ar9xxx_wmac_mac));
+               ar9xxx_wmac_data.macaddr = ar9xxx_wmac_mac;
+       }
+
+       platform_device_register(&ar9xxx_wmac_device);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h
new file mode 100644 (file)
index 0000000..4fa7ec2
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ *  Atheros AR9XXX SoCs built-in WMAC device support
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_AR9XXX_WMAC_H
+#define _AR71XX_DEV_AR9XXX_WMAC_H
+
+void ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init;
+
+#endif /* _AR71XX_DEV_AR9XXX_WMAC_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.c
new file mode 100644 (file)
index 0000000..6e6e583
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ *  Atheros db120 reference board PCI initialization
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros linux 2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath9k_platform.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "dev-db120-pci.h"
+
+static struct ath9k_platform_data db120_wmac_data = {
+       .led_pin = -1,
+};
+static char db120_wmac_mac[6];
+
+static struct ar71xx_pci_irq db120_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }
+};
+
+static int db120_pci_plat_dev_init(struct pci_dev *dev)
+{
+       switch (PCI_SLOT(dev->devfn)) {
+       case 0:
+               dev->dev.platform_data = &db120_wmac_data;
+               break;
+       }
+
+       return 0;
+}
+
+void __init db120_pci_init(u8 *cal_data, u8 *mac_addr)
+{
+       if (cal_data)
+               memcpy(db120_wmac_data.eeprom_data, cal_data,
+                      sizeof(db120_wmac_data.eeprom_data));
+
+       if (mac_addr) {
+               memcpy(db120_wmac_mac, mac_addr, sizeof(db120_wmac_mac));
+               db120_wmac_data.macaddr = db120_wmac_mac;
+       }
+
+       ar71xx_pci_plat_dev_init = db120_pci_plat_dev_init;
+       ar71xx_pci_init(ARRAY_SIZE(db120_pci_irqs), db120_pci_irqs);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-db120-pci.h
new file mode 100644 (file)
index 0000000..b96d989
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ *  Atheros DB120 reference board PCI initialization
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros linux 2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_DB120_PCI_H
+#define _AR71XX_DEV_DB120_PCI_H
+
+#if defined(CONFIG_AR71XX_DEV_DB120_PCI)
+void db120_pci_init(u8 *cal_data, u8 *mac_addr);
+#else
+static inline void db120_pci_init(u8 *cal_data, u8 *mac_addr) { }
+#endif
+
+#endif /* _AR71XX_DEV_DB120_PCI_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.c
new file mode 100644 (file)
index 0000000..8b8fcfa
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ *  Atheros AR71xx DSA switch device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "devices.h"
+#include "dev-dsa.h"
+
+static struct platform_device ar71xx_dsa_switch_device = {
+       .name           = "dsa",
+       .id             = 0,
+};
+
+void __init ar71xx_add_device_dsa(struct device *netdev,
+                                 struct device *miidev,
+                                 struct dsa_platform_data *d)
+{
+       int i;
+
+       d->netdev = netdev;
+       for (i = 0; i < d->nr_chips; i++)
+               d->chip[i].mii_bus = miidev;
+
+       ar71xx_dsa_switch_device.dev.platform_data = d;
+
+       platform_device_register(&ar71xx_dsa_switch_device);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-dsa.h
new file mode 100644 (file)
index 0000000..25b9881
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ *  Atheros AR71xx DSA switch device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_DSA_H
+#define _AR71XX_DEV_DSA_H
+
+#include <net/dsa.h>
+
+void ar71xx_add_device_dsa(struct device *netdev,
+                          struct device *miidev,
+                          struct dsa_platform_data *d) __init;
+
+#endif /* _AR71XX_DEV_DSA_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c
new file mode 100644 (file)
index 0000000..c22e652
--- /dev/null
@@ -0,0 +1,58 @@
+/*
+ *  Atheros AR71xx GPIO button support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "linux/init.h"
+#include "linux/slab.h"
+#include <linux/platform_device.h>
+
+#include "dev-gpio-buttons.h"
+
+void __init ar71xx_register_gpio_keys_polled(int id,
+                                            unsigned poll_interval,
+                                            unsigned nbuttons,
+                                            struct gpio_keys_button *buttons)
+{
+       struct platform_device *pdev;
+       struct gpio_keys_platform_data pdata;
+       struct gpio_keys_button *p;
+       int err;
+
+       p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
+       if (!p)
+               return;
+
+       memcpy(p, buttons, nbuttons * sizeof(*p));
+
+       pdev = platform_device_alloc("gpio-keys-polled", id);
+       if (!pdev)
+               goto err_free_buttons;
+
+       memset(&pdata, 0, sizeof(pdata));
+       pdata.poll_interval = poll_interval;
+       pdata.nbuttons = nbuttons;
+       pdata.buttons = p;
+
+       err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+       if (err)
+               goto err_put_pdev;
+
+       err = platform_device_add(pdev);
+       if (err)
+               goto err_put_pdev;
+
+       return;
+
+err_put_pdev:
+       platform_device_put(pdev);
+
+err_free_buttons:
+       kfree(p);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h
new file mode 100644 (file)
index 0000000..5ed8634
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ *  Atheros AR71xx GPIO button support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_GPIO_BUTTONS_H
+#define _AR71XX_DEV_GPIO_BUTTONS_H
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+void ar71xx_register_gpio_keys_polled(int id,
+                                     unsigned poll_interval,
+                                     unsigned nbuttons,
+                                     struct gpio_keys_button *buttons);
+
+#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c
new file mode 100644 (file)
index 0000000..0fb8c6d
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ *  Atheros AR71xx GPIO LED device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include "dev-leds-gpio.h"
+
+void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds,
+                                       struct gpio_led *leds)
+{
+       struct platform_device *pdev;
+       struct gpio_led_platform_data pdata;
+       struct gpio_led *p;
+       int err;
+
+       p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
+       if (!p)
+               return;
+
+       memcpy(p, leds, num_leds * sizeof(*p));
+
+       pdev = platform_device_alloc("leds-gpio", id);
+       if (!pdev)
+               goto err_free_leds;
+
+       memset(&pdata, 0, sizeof(pdata));
+       pdata.num_leds = num_leds;
+       pdata.leds = p;
+
+       err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+       if (err)
+               goto err_put_pdev;
+
+       err = platform_device_add(pdev);
+       if (err)
+               goto err_put_pdev;
+
+       return;
+
+err_put_pdev:
+       platform_device_put(pdev);
+
+err_free_leds:
+       kfree(p);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h
new file mode 100644 (file)
index 0000000..ab4a89d
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ *  Atheros AR71xx GPIO LED device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_LEDS_GPIO_H
+#define _AR71XX_DEV_LEDS_GPIO_H
+
+#include <linux/leds.h>
+
+void ar71xx_add_device_leds_gpio(int id,
+                                unsigned num_leds,
+                                struct gpio_led *leds) __init;
+
+#endif /* _AR71XX_DEV_LEDS_GPIO_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.c
new file mode 100644 (file)
index 0000000..cf6580e
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+
+#include "devices.h"
+#include "dev-m25p80.h"
+
+static struct spi_board_info ar71xx_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "m25p80",
+       },
+       {
+               .bus_num        = 0,
+               .chip_select    = 1,
+               .max_speed_hz   = 25000000,
+               .modalias   = "m25p80",
+       }
+};
+
+void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata)
+{
+       ar71xx_spi_info[0].platform_data = pdata;
+       ar71xx_add_device_spi(NULL, ar71xx_spi_info, 1);
+}
+
+static struct flash_platform_data *multi_pdata;
+
+static struct mtd_info *concat_devs[2] = { NULL, NULL };
+static struct work_struct mtd_concat_work;
+
+static void mtd_concat_add_work(struct work_struct *work)
+{
+       struct mtd_info *mtd;
+
+       mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash");
+
+#ifdef CONFIG_MTD_PARTITIONS
+       add_mtd_partitions(mtd, multi_pdata->parts, multi_pdata->nr_parts);
+#else
+       add_mtd_device(mtd);
+#endif
+}
+
+static void mtd_concat_add(struct mtd_info *mtd)
+{
+       static bool registered = false;
+
+       if (registered)
+               return;
+
+       if (!strcmp(mtd->name, "spi0.0"))
+               concat_devs[0] = mtd;
+       else if (!strcmp(mtd->name, "spi0.1"))
+               concat_devs[1] = mtd;
+       else
+               return;
+
+       if (!concat_devs[0] || !concat_devs[1])
+               return;
+
+       registered = true;
+       INIT_WORK(&mtd_concat_work, mtd_concat_add_work);
+       schedule_work(&mtd_concat_work);
+}
+
+static void mtd_concat_remove(struct mtd_info *mtd)
+{
+}
+
+static void add_mtd_concat_notifier(void)
+{
+       static struct mtd_notifier not = {
+               .add = mtd_concat_add,
+               .remove = mtd_concat_remove,
+       };
+
+       register_mtd_user(&not);
+}
+
+
+void __init ar71xx_add_device_m25p80_multi(struct flash_platform_data *pdata)
+{
+       multi_pdata = pdata;
+       add_mtd_concat_notifier();
+       ar71xx_add_device_spi(NULL, ar71xx_spi_info, ARRAY_SIZE(ar71xx_spi_info));
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-m25p80.h
new file mode 100644 (file)
index 0000000..f732a84
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_M25P80_H
+#define _AR71XX_DEV_M25P80_H
+
+#include <linux/spi/flash.h>
+
+void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init;
+void ar71xx_add_device_m25p80_multi(struct flash_platform_data *pdata) __init;
+
+#endif /* _AR71XX_DEV_M25P80_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c
new file mode 100644 (file)
index 0000000..0678567
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ *  Atheros PB42 reference board PCI initialization
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "dev-pb42-pci.h"
+
+static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }, {
+               .slot   = 1,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV1,
+       }, {
+               .slot   = 2,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV2,
+       }
+};
+
+void __init pb42_pci_init(void)
+{
+       ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h
new file mode 100644 (file)
index 0000000..f9ef951
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ *  Atheros PB42 reference board PCI initialization
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_PB42_PCI_H
+#define _AR71XX_DEV_PB42_PCI_H
+
+#if defined(CONFIG_AR71XX_DEV_PB42_PCI)
+void pb42_pci_init(void) __init;
+#else
+static inline void pb42_pci_init(void) { }
+#endif
+
+#endif /* _AR71XX_DEV_PB42_PCI_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c
new file mode 100644 (file)
index 0000000..762bd55
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ *  Atheros PB9x reference board PCI initialization
+ *
+ *  Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "dev-pb9x-pci.h"
+
+static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }
+};
+
+void __init pb9x_pci_init(void)
+{
+       ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h
new file mode 100644 (file)
index 0000000..be53f0a
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ *  Atheros PB9x reference board PCI initialization
+ *
+ *  Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_PB9X_PCI_H
+#define _AR71XX_DEV_PB9X_PCI_H
+
+#if defined(CONFIG_AR71XX_DEV_PB9X_PCI)
+void pb9x_pci_init(void) __init;
+#else
+static inline void pb9x_pci_init(void) { }
+#endif
+
+#endif /* _AR71XX_DEV_PB9X_PCI_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.c
new file mode 100644 (file)
index 0000000..57c7ef2
--- /dev/null
@@ -0,0 +1,246 @@
+/*
+ *  Atheros AR71xx USB host device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/platform.h>
+
+#include "dev-usb.h"
+
+/*
+ * OHCI (USB full speed host controller)
+ */
+static struct resource ar71xx_ohci_resources[] = {
+       [0] = {
+               .start  = AR71XX_OHCI_BASE,
+               .end    = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AR71XX_MISC_IRQ_OHCI,
+               .end    = AR71XX_MISC_IRQ_OHCI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct resource ar7240_ohci_resources[] = {
+       [0] = {
+               .start  = AR7240_OHCI_BASE,
+               .end    = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AR71XX_CPU_IRQ_USB,
+               .end    = AR71XX_CPU_IRQ_USB,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device ar71xx_ohci_device = {
+       .name           = "ar71xx-ohci",
+       .id             = -1,
+       .resource       = ar71xx_ohci_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_ohci_resources),
+       .dev = {
+               .dma_mask               = &ar71xx_ohci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+};
+
+/*
+ * EHCI (USB high/full speed host controller)
+ */
+static struct resource ar71xx_ehci_resources[] = {
+       [0] = {
+               .start  = AR71XX_EHCI_BASE,
+               .end    = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AR71XX_CPU_IRQ_USB,
+               .end    = AR71XX_CPU_IRQ_USB,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32);
+static struct ar71xx_ehci_platform_data ar71xx_ehci_data;
+
+static struct platform_device ar71xx_ehci_device = {
+       .name           = "ar71xx-ehci",
+       .id             = -1,
+       .resource       = ar71xx_ehci_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_ehci_resources),
+       .dev = {
+               .dma_mask               = &ar71xx_ehci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+               .platform_data          = &ar71xx_ehci_data,
+       },
+};
+
+#define AR71XX_USB_RESET_MASK \
+       (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
+       | RESET_MODULE_USB_OHCI_DLL)
+
+#define AR7240_USB_RESET_MASK \
+       (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240)
+
+static void __init ar71xx_usb_setup(void)
+{
+       ar71xx_device_stop(AR71XX_USB_RESET_MASK);
+       mdelay(1000);
+       ar71xx_device_start(AR71XX_USB_RESET_MASK);
+
+       /* Turning on the Buff and Desc swap bits */
+       ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000);
+
+       /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+       ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00);
+
+       mdelay(900);
+
+       platform_device_register(&ar71xx_ohci_device);
+       platform_device_register(&ar71xx_ehci_device);
+}
+
+static void __init ar7240_usb_setup(void)
+{
+       ar71xx_device_stop(AR7240_USB_RESET_MASK);
+       mdelay(1000);
+       ar71xx_device_start(AR7240_USB_RESET_MASK);
+
+       /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+       ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3);
+
+       ar71xx_ohci_device.resource = ar7240_ohci_resources;
+       ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources);
+       platform_device_register(&ar71xx_ohci_device);
+}
+
+static void __init ar7241_usb_setup(void)
+{
+       ar71xx_device_start(AR724X_RESET_USBSUS_OVERRIDE);
+       mdelay(10);
+
+       ar71xx_device_start(AR724X_RESET_USB_HOST);
+       mdelay(10);
+
+       ar71xx_device_start(AR724X_RESET_USB_PHY);
+       mdelay(10);
+
+       ar71xx_ehci_data.is_ar91xx = 1;
+       ar71xx_ehci_device.resource = ar7240_ohci_resources;
+       ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources);
+       platform_device_register(&ar71xx_ehci_device);
+}
+
+static void __init ar91xx_usb_setup(void)
+{
+       ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE);
+       mdelay(10);
+
+       ar71xx_device_start(RESET_MODULE_USB_HOST);
+       mdelay(10);
+
+       ar71xx_device_start(RESET_MODULE_USB_PHY);
+       mdelay(10);
+
+       ar71xx_ehci_data.is_ar91xx = 1;
+       platform_device_register(&ar71xx_ehci_device);
+}
+
+static void __init ar933x_usb_setup(void)
+{
+       ar71xx_device_reset_rmw(0, AR933X_RESET_USBSUS_OVERRIDE);
+       mdelay(10);
+
+       ar71xx_device_reset_rmw(AR933X_RESET_USB_HOST,
+                               AR933X_RESET_USBSUS_OVERRIDE);
+       mdelay(10);
+
+       ar71xx_device_reset_rmw(AR933X_RESET_USB_PHY,
+                               AR933X_RESET_USBSUS_OVERRIDE);
+       mdelay(10);
+
+       ar71xx_ehci_data.is_ar91xx = 1;
+       platform_device_register(&ar71xx_ehci_device);
+}
+
+static void __init ar934x_usb_setup(void)
+{
+       u32 bootstrap;
+
+       bootstrap = ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+       if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+               return;
+
+       ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE);
+       udelay(1000);
+
+       ar71xx_device_start(AR934X_RESET_USB_PHY);
+       udelay(1000);
+
+       ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG);
+       udelay(1000);
+
+       ar71xx_device_start(AR934X_RESET_USB_HOST);
+       udelay(1000);
+
+       ar71xx_ehci_data.is_ar91xx = 1;
+       platform_device_register(&ar71xx_ehci_device);
+}
+
+void __init ar71xx_add_device_usb(void)
+{
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7240:
+               ar7240_usb_setup();
+               break;
+
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               ar7241_usb_setup();
+               break;
+
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               ar71xx_usb_setup();
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ar91xx_usb_setup();
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ar933x_usb_setup();
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ar934x_usb_setup();
+               break;
+
+       default:
+               BUG();
+       }
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/dev-usb.h
new file mode 100644 (file)
index 0000000..aa49f53
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ *  Atheros AR71xx USB host device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR71XX_DEV_USB_H
+#define _AR71XX_DEV_USB_H
+
+void ar71xx_add_device_usb(void) __init;
+
+#endif /* _AR71XX_DEV_USB_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.c
new file mode 100644 (file)
index 0000000..75b24b0
--- /dev/null
@@ -0,0 +1,1076 @@
+/*
+ *  Atheros AR71xx SoC platform devices
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros 2.6.15 BSP
+ *  Parts of this file are based on Atheros 2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/ar933x_uart_platform.h>
+
+#include "devices.h"
+
+unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
+
+static struct resource ar71xx_uart_resources[] = {
+       {
+               .start  = AR71XX_UART_BASE,
+               .end    = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
+static struct plat_serial8250_port ar71xx_uart_data[] = {
+       {
+               .mapbase        = AR71XX_UART_BASE,
+               .irq            = AR71XX_MISC_IRQ_UART,
+               .flags          = AR71XX_UART_FLAGS,
+               .iotype         = UPIO_MEM32,
+               .regshift       = 2,
+       }, {
+               /* terminating entry */
+       }
+};
+
+static struct platform_device ar71xx_uart_device = {
+       .name           = "serial8250",
+       .id             = PLAT8250_DEV_PLATFORM,
+       .resource       = ar71xx_uart_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_uart_resources),
+       .dev = {
+               .platform_data  = ar71xx_uart_data
+       },
+};
+
+static struct resource ar933x_uart_resources[] = {
+       {
+               .start  = AR933X_UART_BASE,
+               .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = AR71XX_MISC_IRQ_UART,
+               .end    = AR71XX_MISC_IRQ_UART,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct ar933x_uart_platform_data ar933x_uart_data;
+static struct platform_device ar933x_uart_device = {
+       .name           = "ar933x-uart",
+       .id             = -1,
+       .resource       = ar933x_uart_resources,
+       .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
+       .dev = {
+               .platform_data  = &ar933x_uart_data,
+       },
+};
+
+void __init ar71xx_add_device_uart(void)
+{
+       struct platform_device *pdev;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               pdev = &ar71xx_uart_device;
+               ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               pdev = &ar933x_uart_device;
+               ar933x_uart_data.uartclk = ar71xx_ref_freq;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               pdev = &ar71xx_uart_device;
+               ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
+               break;
+
+       default:
+               BUG();
+       }
+
+       platform_device_register(pdev);
+}
+
+static struct resource ar71xx_mdio0_resources[] = {
+       {
+               .name   = "mdio_base",
+               .flags  = IORESOURCE_MEM,
+               .start  = AR71XX_GE0_BASE,
+               .end    = AR71XX_GE0_BASE + 0x200 - 1,
+       }
+};
+
+static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
+
+struct platform_device ar71xx_mdio0_device = {
+       .name           = "ag71xx-mdio",
+       .id             = 0,
+       .resource       = ar71xx_mdio0_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_mdio0_resources),
+       .dev = {
+               .platform_data = &ar71xx_mdio0_data,
+       },
+};
+
+static struct resource ar71xx_mdio1_resources[] = {
+       {
+               .name   = "mdio_base",
+               .flags  = IORESOURCE_MEM,
+               .start  = AR71XX_GE1_BASE,
+               .end    = AR71XX_GE1_BASE + 0x200 - 1,
+       }
+};
+
+static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
+
+struct platform_device ar71xx_mdio1_device = {
+       .name           = "ag71xx-mdio",
+       .id             = 1,
+       .resource       = ar71xx_mdio1_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_mdio1_resources),
+       .dev = {
+               .platform_data = &ar71xx_mdio1_data,
+       },
+};
+
+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+
+       t = __raw_readl(base + cfg_reg);
+       t &= ~(3 << shift);
+       t |=  (2 << shift);
+       __raw_writel(t, base + cfg_reg);
+       udelay(100);
+
+       __raw_writel(pll_val, base + pll_reg);
+
+       t |= (3 << shift);
+       __raw_writel(t, base + cfg_reg);
+       udelay(100);
+
+       t &= ~(3 << shift);
+       __raw_writel(t, base + cfg_reg);
+       udelay(100);
+
+       printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
+               (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
+
+       iounmap(base);
+}
+
+static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
+                                         unsigned int mii_if)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+       t = __raw_readl(base + reg);
+       t &= ~(MII_CTRL_IF_MASK);
+       t |= (mii_if & MII_CTRL_IF_MASK);
+       __raw_writel(t, base + reg);
+
+       iounmap(base);
+}
+
+static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
+{
+       void __iomem *base;
+       unsigned int mii_speed;
+       u32 t;
+
+       switch (speed) {
+       case SPEED_10:
+               mii_speed =  MII_CTRL_SPEED_10;
+               break;
+       case SPEED_100:
+               mii_speed =  MII_CTRL_SPEED_100;
+               break;
+       case SPEED_1000:
+               mii_speed =  MII_CTRL_SPEED_1000;
+               break;
+       default:
+               BUG();
+       }
+
+       base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+       t = __raw_readl(base + reg);
+       t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+       t |= mii_speed  << MII_CTRL_SPEED_SHIFT;
+       __raw_writel(t, base + reg);
+
+       iounmap(base);
+}
+
+void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
+{
+       struct platform_device *mdio_dev;
+       struct ag71xx_mdio_platform_data *mdio_data;
+       unsigned int max_id;
+
+       if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+           ar71xx_soc == AR71XX_SOC_AR9342 ||
+           ar71xx_soc == AR71XX_SOC_AR9344)
+               max_id = 1;
+       else
+               max_id = 0;
+
+       if (id > max_id) {
+               printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
+               return;
+       }
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               mdio_dev = &ar71xx_mdio1_device;
+               mdio_data = &ar71xx_mdio1_data;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               if (id == 0) {
+                       mdio_dev = &ar71xx_mdio0_device;
+                       mdio_data = &ar71xx_mdio0_data;
+               } else {
+                       mdio_dev = &ar71xx_mdio1_device;
+                       mdio_data = &ar71xx_mdio1_data;
+               }
+               break;
+
+       case AR71XX_SOC_AR7242:
+               ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
+                              AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
+                              AR71XX_ETH0_PLL_SHIFT);
+               /* fall through */
+       default:
+               mdio_dev = &ar71xx_mdio0_device;
+               mdio_data = &ar71xx_mdio0_data;
+               break;
+       }
+
+       mdio_data->phy_mask = phy_mask;
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               mdio_data->is_ar7240 = 1;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               if (id == 1)
+                       mdio_data->is_ar7240 = 1;
+               break;
+
+       default:
+               break;
+       }
+
+       platform_device_register(mdio_dev);
+}
+
+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
+
+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
+{
+       struct ar71xx_eth_pll_data *pll_data;
+       u32 pll_val;
+
+       switch (mac) {
+       case 0:
+               pll_data = &ar71xx_eth0_pll_data;
+               break;
+       case 1:
+               pll_data = &ar71xx_eth1_pll_data;
+               break;
+       default:
+               BUG();
+       }
+
+       switch (speed) {
+       case SPEED_10:
+               pll_val = pll_data->pll_10;
+               break;
+       case SPEED_100:
+               pll_val = pll_data->pll_100;
+               break;
+       case SPEED_1000:
+               pll_val = pll_data->pll_1000;
+               break;
+       default:
+               BUG();
+       }
+
+       return pll_val;
+}
+
+static void ar71xx_set_speed_ge0(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(0, speed);
+
+       ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
+                       val, AR71XX_ETH0_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
+}
+
+static void ar71xx_set_speed_ge1(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(1, speed);
+
+       ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
+                        val, AR71XX_ETH1_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
+}
+
+static void ar724x_set_speed_ge0(int speed)
+{
+       /* TODO */
+}
+
+static void ar724x_set_speed_ge1(int speed)
+{
+       /* TODO */
+}
+
+static void ar7242_set_speed_ge0(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(0, speed);
+       void __iomem *base;
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
+       iounmap(base);
+}
+
+static void ar91xx_set_speed_ge0(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(0, speed);
+
+       ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
+                        val, AR91XX_ETH0_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
+}
+
+static void ar91xx_set_speed_ge1(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(1, speed);
+
+       ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
+                        val, AR91XX_ETH1_PLL_SHIFT);
+       ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
+}
+
+static void ar933x_set_speed_ge0(int speed)
+{
+       /* TODO */
+}
+
+static void ar933x_set_speed_ge1(int speed)
+{
+       /* TODO */
+}
+
+static void ar934x_set_speed_ge0(int speed)
+{
+       /* TODO */
+}
+
+static void ar934x_set_speed_ge1(int speed)
+{
+       /* TODO */
+}
+
+static void ar71xx_ddr_flush_ge0(void)
+{
+       ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
+}
+
+static void ar71xx_ddr_flush_ge1(void)
+{
+       ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
+}
+
+static void ar724x_ddr_flush_ge0(void)
+{
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar724x_ddr_flush_ge1(void)
+{
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
+}
+
+static void ar91xx_ddr_flush_ge0(void)
+{
+       ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
+}
+
+static void ar91xx_ddr_flush_ge1(void)
+{
+       ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
+}
+
+static void ar933x_ddr_flush_ge0(void)
+{
+       ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar933x_ddr_flush_ge1(void)
+{
+       ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
+}
+
+static void ar934x_ddr_flush_ge0(void)
+{
+       ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar934x_ddr_flush_ge1(void)
+{
+       ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
+}
+
+static struct resource ar71xx_eth0_resources[] = {
+       {
+               .name   = "mac_base",
+               .flags  = IORESOURCE_MEM,
+               .start  = AR71XX_GE0_BASE,
+               .end    = AR71XX_GE0_BASE + 0x200 - 1,
+       }, {
+               .name   = "mac_irq",
+               .flags  = IORESOURCE_IRQ,
+               .start  = AR71XX_CPU_IRQ_GE0,
+               .end    = AR71XX_CPU_IRQ_GE0,
+       },
+};
+
+struct ag71xx_platform_data ar71xx_eth0_data = {
+       .reset_bit      = RESET_MODULE_GE0_MAC,
+};
+
+struct platform_device ar71xx_eth0_device = {
+       .name           = "ag71xx",
+       .id             = 0,
+       .resource       = ar71xx_eth0_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_eth0_resources),
+       .dev = {
+               .platform_data = &ar71xx_eth0_data,
+       },
+};
+
+static struct resource ar71xx_eth1_resources[] = {
+       {
+               .name   = "mac_base",
+               .flags  = IORESOURCE_MEM,
+               .start  = AR71XX_GE1_BASE,
+               .end    = AR71XX_GE1_BASE + 0x200 - 1,
+       }, {
+               .name   = "mac_irq",
+               .flags  = IORESOURCE_IRQ,
+               .start  = AR71XX_CPU_IRQ_GE1,
+               .end    = AR71XX_CPU_IRQ_GE1,
+       },
+};
+
+struct ag71xx_platform_data ar71xx_eth1_data = {
+       .reset_bit      = RESET_MODULE_GE1_MAC,
+};
+
+struct platform_device ar71xx_eth1_device = {
+       .name           = "ag71xx",
+       .id             = 1,
+       .resource       = ar71xx_eth1_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_eth1_resources),
+       .dev = {
+               .platform_data = &ar71xx_eth1_data,
+       },
+};
+
+struct ag71xx_switch_platform_data ar71xx_switch_data;
+
+#define AR71XX_PLL_VAL_1000    0x00110000
+#define AR71XX_PLL_VAL_100     0x00001099
+#define AR71XX_PLL_VAL_10      0x00991099
+
+#define AR724X_PLL_VAL_1000    0x00110000
+#define AR724X_PLL_VAL_100     0x00001099
+#define AR724X_PLL_VAL_10      0x00991099
+
+#define AR7242_PLL_VAL_1000    0x16000000
+#define AR7242_PLL_VAL_100     0x00000101
+#define AR7242_PLL_VAL_10      0x00001616
+
+#define AR91XX_PLL_VAL_1000    0x1a000000
+#define AR91XX_PLL_VAL_100     0x13000a44
+#define AR91XX_PLL_VAL_10      0x00441099
+
+#define AR933X_PLL_VAL_1000    0x00110000
+#define AR933X_PLL_VAL_100     0x00001099
+#define AR933X_PLL_VAL_10      0x00991099
+
+#define AR934X_PLL_VAL_1000    0x00110000
+#define AR934X_PLL_VAL_100     0x00001099
+#define AR934X_PLL_VAL_10      0x00991099
+
+static void __init ar71xx_init_eth_pll_data(unsigned int id)
+{
+       struct ar71xx_eth_pll_data *pll_data;
+       u32 pll_10, pll_100, pll_1000;
+
+       switch (id) {
+       case 0:
+               pll_data = &ar71xx_eth0_pll_data;
+               break;
+       case 1:
+               pll_data = &ar71xx_eth1_pll_data;
+               break;
+       default:
+               BUG();
+       }
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               pll_10 = AR71XX_PLL_VAL_10;
+               pll_100 = AR71XX_PLL_VAL_100;
+               pll_1000 = AR71XX_PLL_VAL_1000;
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+               pll_10 = AR724X_PLL_VAL_10;
+               pll_100 = AR724X_PLL_VAL_100;
+               pll_1000 = AR724X_PLL_VAL_1000;
+               break;
+
+       case AR71XX_SOC_AR7242:
+               pll_10 = AR7242_PLL_VAL_10;
+               pll_100 = AR7242_PLL_VAL_100;
+               pll_1000 = AR7242_PLL_VAL_1000;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               pll_10 = AR91XX_PLL_VAL_10;
+               pll_100 = AR91XX_PLL_VAL_100;
+               pll_1000 = AR91XX_PLL_VAL_1000;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               pll_10 = AR933X_PLL_VAL_10;
+               pll_100 = AR933X_PLL_VAL_100;
+               pll_1000 = AR933X_PLL_VAL_1000;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               pll_10 = AR934X_PLL_VAL_10;
+               pll_100 = AR934X_PLL_VAL_100;
+               pll_1000 = AR934X_PLL_VAL_1000;
+               break;
+
+       default:
+               BUG();
+       }
+
+       if (!pll_data->pll_10)
+               pll_data->pll_10 = pll_10;
+
+       if (!pll_data->pll_100)
+               pll_data->pll_100 = pll_100;
+
+       if (!pll_data->pll_1000)
+               pll_data->pll_1000 = pll_1000;
+}
+
+static int __init ar71xx_setup_phy_if_mode(unsigned int id,
+                                          struct ag71xx_platform_data *pdata)
+{
+       unsigned int mii_if;
+
+       switch (id) {
+       case 0:
+               switch (ar71xx_soc) {
+               case AR71XX_SOC_AR7130:
+               case AR71XX_SOC_AR7141:
+               case AR71XX_SOC_AR7161:
+               case AR71XX_SOC_AR9130:
+               case AR71XX_SOC_AR9132:
+                       switch (pdata->phy_if_mode) {
+                       case PHY_INTERFACE_MODE_MII:
+                               mii_if = MII0_CTRL_IF_MII;
+                               break;
+                       case PHY_INTERFACE_MODE_GMII:
+                               mii_if = MII0_CTRL_IF_GMII;
+                               break;
+                       case PHY_INTERFACE_MODE_RGMII:
+                               mii_if = MII0_CTRL_IF_RGMII;
+                               break;
+                       case PHY_INTERFACE_MODE_RMII:
+                               mii_if = MII0_CTRL_IF_RMII;
+                               break;
+                       default:
+                               return -EINVAL;
+                       }
+                       ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
+                       break;
+
+               case AR71XX_SOC_AR7240:
+               case AR71XX_SOC_AR7241:
+               case AR71XX_SOC_AR9330:
+               case AR71XX_SOC_AR9331:
+                       pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
+                       break;
+
+               case AR71XX_SOC_AR7242:
+                       /* FIXME */
+
+               case AR71XX_SOC_AR9341:
+               case AR71XX_SOC_AR9342:
+               case AR71XX_SOC_AR9344:
+                       switch (pdata->phy_if_mode) {
+                       case PHY_INTERFACE_MODE_MII:
+                       case PHY_INTERFACE_MODE_GMII:
+                       case PHY_INTERFACE_MODE_RGMII:
+                       case PHY_INTERFACE_MODE_RMII:
+                               break;
+                       default:
+                               return -EINVAL;
+                       }
+                       break;
+
+               default:
+                       BUG();
+               }
+               break;
+       case 1:
+               switch (ar71xx_soc) {
+               case AR71XX_SOC_AR7130:
+               case AR71XX_SOC_AR7141:
+               case AR71XX_SOC_AR7161:
+               case AR71XX_SOC_AR9130:
+               case AR71XX_SOC_AR9132:
+                       switch (pdata->phy_if_mode) {
+                       case PHY_INTERFACE_MODE_RMII:
+                               mii_if = MII1_CTRL_IF_RMII;
+                               break;
+                       case PHY_INTERFACE_MODE_RGMII:
+                               mii_if = MII1_CTRL_IF_RGMII;
+                               break;
+                       default:
+                               return -EINVAL;
+                       }
+                       ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
+                       break;
+
+               case AR71XX_SOC_AR7240:
+               case AR71XX_SOC_AR7241:
+               case AR71XX_SOC_AR9330:
+               case AR71XX_SOC_AR9331:
+                       pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
+                       break;
+
+               case AR71XX_SOC_AR7242:
+                       /* FIXME */
+
+               case AR71XX_SOC_AR9341:
+               case AR71XX_SOC_AR9342:
+               case AR71XX_SOC_AR9344:
+                       switch (pdata->phy_if_mode) {
+                       case PHY_INTERFACE_MODE_MII:
+                       case PHY_INTERFACE_MODE_GMII:
+                               break;
+                       default:
+                               return -EINVAL;
+                       }
+                       break;
+
+               default:
+                       BUG();
+               }
+               break;
+       }
+
+       return 0;
+}
+
+static int ar71xx_eth_instance __initdata;
+void __init ar71xx_add_device_eth(unsigned int id)
+{
+       struct platform_device *pdev;
+       struct ag71xx_platform_data *pdata;
+       int err;
+
+       if (id > 1) {
+               printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
+               return;
+       }
+
+       ar71xx_init_eth_pll_data(id);
+
+       if (id == 0)
+               pdev = &ar71xx_eth0_device;
+       else
+               pdev = &ar71xx_eth1_device;
+
+       pdata = pdev->dev.platform_data;
+
+       err = ar71xx_setup_phy_if_mode(id, pdata);
+       if (err) {
+               printk(KERN_ERR
+                      "ar71xx: invalid PHY interface mode for GE%u\n", id);
+               return;
+       }
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+               if (id == 0) {
+                       pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+                       pdata->set_speed = ar71xx_set_speed_ge0;
+               } else {
+                       pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+                       pdata->set_speed = ar71xx_set_speed_ge1;
+               }
+               break;
+
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               if (id == 0) {
+                       pdata->ddr_flush = ar71xx_ddr_flush_ge0;
+                       pdata->set_speed = ar71xx_set_speed_ge0;
+               } else {
+                       pdata->ddr_flush = ar71xx_ddr_flush_ge1;
+                       pdata->set_speed = ar71xx_set_speed_ge1;
+               }
+               pdata->has_gbit = 1;
+               break;
+
+       case AR71XX_SOC_AR7242:
+               if (id == 0) {
+                       pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
+                                           RESET_MODULE_GE0_PHY;
+                       pdata->ddr_flush = ar724x_ddr_flush_ge0;
+                       pdata->set_speed = ar7242_set_speed_ge0;
+               } else {
+                       pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
+                                           RESET_MODULE_GE1_PHY;
+                       pdata->ddr_flush = ar724x_ddr_flush_ge1;
+                       pdata->set_speed = ar724x_set_speed_ge1;
+               }
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
+       case AR71XX_SOC_AR7241:
+               if (id == 0)
+                       pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
+               else
+                       pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
+               /* fall through */
+       case AR71XX_SOC_AR7240:
+               if (id == 0) {
+                       pdata->reset_bit |= RESET_MODULE_GE0_PHY;
+                       pdata->ddr_flush = ar724x_ddr_flush_ge0;
+                       pdata->set_speed = ar724x_set_speed_ge0;
+
+                       pdata->phy_mask = BIT(4);
+               } else {
+                       pdata->reset_bit |= RESET_MODULE_GE1_PHY;
+                       pdata->ddr_flush = ar724x_ddr_flush_ge1;
+                       pdata->set_speed = ar724x_set_speed_ge1;
+
+                       pdata->speed = SPEED_1000;
+                       pdata->duplex = DUPLEX_FULL;
+                       pdata->switch_data = &ar71xx_switch_data;
+               }
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+               if (ar71xx_soc == AR71XX_SOC_AR7240)
+                       pdata->is_ar7240 = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
+       case AR71XX_SOC_AR9130:
+               if (id == 0) {
+                       pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+                       pdata->set_speed = ar91xx_set_speed_ge0;
+               } else {
+                       pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+                       pdata->set_speed = ar91xx_set_speed_ge1;
+               }
+               pdata->is_ar91xx = 1;
+               break;
+
+       case AR71XX_SOC_AR9132:
+               if (id == 0) {
+                       pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+                       pdata->set_speed = ar91xx_set_speed_ge0;
+               } else {
+                       pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+                       pdata->set_speed = ar91xx_set_speed_ge1;
+               }
+               pdata->is_ar91xx = 1;
+               pdata->has_gbit = 1;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               if (id == 0) {
+                       pdata->reset_bit = AR933X_RESET_GE0_MAC |
+                                          AR933X_RESET_GE0_MDIO;
+                       pdata->ddr_flush = ar933x_ddr_flush_ge0;
+                       pdata->set_speed = ar933x_set_speed_ge0;
+
+                       pdata->phy_mask = BIT(4);
+               } else {
+                       pdata->reset_bit = AR933X_RESET_GE1_MAC |
+                                          AR933X_RESET_GE1_MDIO;
+                       pdata->ddr_flush = ar933x_ddr_flush_ge1;
+                       pdata->set_speed = ar933x_set_speed_ge1;
+
+                       pdata->speed = SPEED_1000;
+                       pdata->duplex = DUPLEX_FULL;
+                       pdata->switch_data = &ar71xx_switch_data;
+               }
+
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               if (id == 0) {
+                       pdata->reset_bit = AR934X_RESET_GE0_MAC |
+                                          AR934X_RESET_GE0_MDIO;
+                       pdata->ddr_flush =ar934x_ddr_flush_ge0;
+                       pdata->set_speed = ar934x_set_speed_ge0;
+               } else {
+                       pdata->reset_bit = AR934X_RESET_GE1_MAC |
+                                          AR934X_RESET_GE1_MDIO;
+                       pdata->ddr_flush = ar934x_ddr_flush_ge1;
+                       pdata->set_speed = ar934x_set_speed_ge1;
+
+                       pdata->switch_data = &ar71xx_switch_data;
+               }
+
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
+       default:
+               BUG();
+       }
+
+       switch (pdata->phy_if_mode) {
+       case PHY_INTERFACE_MODE_GMII:
+       case PHY_INTERFACE_MODE_RGMII:
+               if (!pdata->has_gbit) {
+                       printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
+                                       id);
+                       return;
+               }
+               /* fallthrough */
+       default:
+               break;
+       }
+
+       if (!is_valid_ether_addr(pdata->mac_addr)) {
+               random_ether_addr(pdata->mac_addr);
+               printk(KERN_DEBUG
+                       "ar71xx: using random MAC address for eth%d\n",
+                       ar71xx_eth_instance);
+       }
+
+       if (pdata->mii_bus_dev == NULL) {
+               switch (ar71xx_soc) {
+               case AR71XX_SOC_AR9341:
+               case AR71XX_SOC_AR9342:
+               case AR71XX_SOC_AR9344:
+                       if (id == 0)
+                               pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
+                       else
+                               pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
+                       break;
+
+               case AR71XX_SOC_AR7241:
+               case AR71XX_SOC_AR9330:
+               case AR71XX_SOC_AR9331:
+                       pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
+                       break;
+
+               default:
+                       pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
+                       break;
+               }
+       }
+
+       /* Reset the device */
+       ar71xx_device_stop(pdata->reset_bit);
+       mdelay(100);
+
+       ar71xx_device_start(pdata->reset_bit);
+       mdelay(100);
+
+       platform_device_register(pdev);
+       ar71xx_eth_instance++;
+}
+
+static struct resource ar71xx_spi_resources[] = {
+       [0] = {
+               .start  = AR71XX_SPI_BASE,
+               .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device ar71xx_spi_device = {
+       .name           = "ar71xx-spi",
+       .id             = -1,
+       .resource       = ar71xx_spi_resources,
+       .num_resources  = ARRAY_SIZE(ar71xx_spi_resources),
+};
+
+void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
+                               struct spi_board_info const *info,
+                               unsigned n)
+{
+       spi_register_board_info(info, n);
+       ar71xx_spi_device.dev.platform_data = pdata;
+       platform_device_register(&ar71xx_spi_device);
+}
+
+void __init ar71xx_add_device_wdt(void)
+{
+       platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
+}
+
+void __init ar71xx_set_mac_base(unsigned char *mac)
+{
+       memcpy(ar71xx_mac_base, mac, ETH_ALEN);
+}
+
+void __init ar71xx_parse_mac_addr(char *mac_str)
+{
+       u8 tmp[ETH_ALEN];
+       int t;
+
+       t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+                       &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+
+       if (t != ETH_ALEN)
+               t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
+                       &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+
+       if (t == ETH_ALEN)
+               ar71xx_set_mac_base(tmp);
+       else
+               printk(KERN_DEBUG "ar71xx: failed to parse mac address "
+                               "\"%s\"\n", mac_str);
+}
+
+static int __init ar71xx_ethaddr_setup(char *str)
+{
+       ar71xx_parse_mac_addr(str);
+       return 1;
+}
+__setup("ethaddr=", ar71xx_ethaddr_setup);
+
+static int __init ar71xx_kmac_setup(char *str)
+{
+       ar71xx_parse_mac_addr(str);
+       return 1;
+}
+__setup("kmac=", ar71xx_kmac_setup);
+
+void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
+                           int offset)
+{
+       int t;
+
+       if (!is_valid_ether_addr(src)) {
+               memset(dst, '\0', ETH_ALEN);
+               return;
+       }
+
+       t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
+       t += offset;
+
+       dst[0] = src[0];
+       dst[1] = src[1];
+       dst[2] = src[2];
+       dst[3] = (t >> 16) & 0xff;
+       dst[4] = (t >> 8) & 0xff;
+       dst[5] = t & 0xff;
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.h b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/devices.h
new file mode 100644 (file)
index 0000000..0f75fe7
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ *  Atheros AR71xx SoC device definitions
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AR71XX_DEVICES_H
+#define __AR71XX_DEVICES_H
+
+#include <asm/mach-ar71xx/platform.h>
+
+struct platform_device;
+
+void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
+                          struct spi_board_info const *info,
+                          unsigned n) __init;
+
+extern unsigned char ar71xx_mac_base[] __initdata;
+void ar71xx_parse_mac_addr(char *mac_str) __init;
+void ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
+                    int offset) __init;
+
+struct ar71xx_eth_pll_data {
+       u32     pll_10;
+       u32     pll_100;
+       u32     pll_1000;
+};
+
+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
+
+extern struct ag71xx_platform_data ar71xx_eth0_data;
+extern struct ag71xx_platform_data ar71xx_eth1_data;
+extern struct platform_device ar71xx_eth0_device;
+extern struct platform_device ar71xx_eth1_device;
+void ar71xx_add_device_eth(unsigned int id) __init;
+
+extern struct ag71xx_switch_platform_data ar71xx_switch_data;
+
+extern struct platform_device ar71xx_mdio0_device;
+extern struct platform_device ar71xx_mdio1_device;
+void ar71xx_add_device_mdio(unsigned int id, u32 phy_mask) __init;
+
+void ar71xx_add_device_uart(void) __init;
+
+void ar71xx_add_device_wdt(void) __init;
+
+#endif /* __AR71XX_DEVICES_H */
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/early_printk.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/early_printk.c
new file mode 100644 (file)
index 0000000..c85a04d
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ *  Atheros AR7xxx/AR9xxx SoC early printk support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/ar933x_uart.h>
+
+static void (*_prom_putchar) (unsigned char);
+
+static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
+{
+       u32 t;
+
+       do {
+               t = __raw_readl(reg);
+               if ((t & mask) == val)
+                       break;
+       } while (1);
+}
+
+static void prom_putchar_ar71xx(unsigned char ch)
+{
+       void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
+
+       prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+       __raw_writel(ch, base + UART_TX * 4);
+       prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+}
+
+static void prom_putchar_ar933x(unsigned char ch)
+{
+       void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
+
+       prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                         AR933X_UART_DATA_TX_CSR);
+       __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
+       prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                         AR933X_UART_DATA_TX_CSR);
+}
+
+static void prom_putchar_dummy(unsigned char ch)
+{
+       /* nothing to do */
+}
+
+static void prom_putchar_init(void)
+{
+       void __iomem *base;
+       u32 id;
+
+       base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
+       id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
+       id &= REV_ID_MAJOR_MASK;
+
+       switch (id) {
+       case REV_ID_MAJOR_AR71XX:
+       case REV_ID_MAJOR_AR7240:
+       case REV_ID_MAJOR_AR7241:
+       case REV_ID_MAJOR_AR7242:
+       case REV_ID_MAJOR_AR913X:
+       case REV_ID_MAJOR_AR9341:
+       case REV_ID_MAJOR_AR9342:
+       case REV_ID_MAJOR_AR9344:
+               _prom_putchar = prom_putchar_ar71xx;
+               break;
+
+       case REV_ID_MAJOR_AR9330:
+       case REV_ID_MAJOR_AR9331:
+               _prom_putchar = prom_putchar_ar933x;
+               break;
+
+       default:
+               _prom_putchar = prom_putchar_dummy;
+               break;
+       }
+}
+
+void prom_putchar(unsigned char ch)
+{
+       if (!_prom_putchar)
+               prom_putchar_init();
+
+       _prom_putchar(ch);
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/gpio.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/gpio.c
new file mode 100644 (file)
index 0000000..91c8383
--- /dev/null
@@ -0,0 +1,302 @@
+/*
+ *  Atheros AR7XXX/AR9XXX SoC GPIO API support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+static DEFINE_SPINLOCK(ar71xx_gpio_lock);
+
+unsigned long ar71xx_gpio_count;
+EXPORT_SYMBOL(ar71xx_gpio_count);
+
+void __ar71xx_gpio_set_value(unsigned gpio, int value)
+{
+       void __iomem *base = ar71xx_gpio_base;
+
+       if (value)
+               __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
+       else
+               __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
+}
+EXPORT_SYMBOL(__ar71xx_gpio_set_value);
+
+int __ar71xx_gpio_get_value(unsigned gpio)
+{
+       return (__raw_readl(ar71xx_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
+}
+EXPORT_SYMBOL(__ar71xx_gpio_get_value);
+
+static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+       return __ar71xx_gpio_get_value(offset);
+}
+
+static void ar71xx_gpio_set_value(struct gpio_chip *chip,
+                                 unsigned offset, int value)
+{
+       __ar71xx_gpio_set_value(offset, value);
+}
+
+static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
+                                      unsigned offset)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
+                    base + AR71XX_GPIO_REG_OE);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+
+       return 0;
+}
+
+static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       if (value)
+               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
+       else
+               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
+
+       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
+                    base + AR71XX_GPIO_REG_OE);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+
+       return 0;
+}
+
+static int ar934x_gpio_direction_input(struct gpio_chip *chip,
+                                      unsigned offset)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
+                    base + AR71XX_GPIO_REG_OE);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+
+       return 0;
+}
+
+static int ar934x_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       if (value)
+               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
+       else
+               __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
+
+       __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
+                    base + AR71XX_GPIO_REG_OE);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+
+       return 0;
+}
+
+static struct gpio_chip ar71xx_gpio_chip = {
+       .label                  = "ar71xx",
+       .get                    = ar71xx_gpio_get_value,
+       .set                    = ar71xx_gpio_set_value,
+       .direction_input        = ar71xx_gpio_direction_input,
+       .direction_output       = ar71xx_gpio_direction_output,
+       .base                   = 0,
+       .ngpio                  = AR71XX_GPIO_COUNT,
+};
+
+void ar71xx_gpio_function_enable(u32 mask)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+       unsigned int reg;
+
+       if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+           ar71xx_soc == AR71XX_SOC_AR9342 ||
+           ar71xx_soc == AR71XX_SOC_AR9344) {
+               reg = AR934X_GPIO_REG_FUNC;
+       } else {
+               reg = AR71XX_GPIO_REG_FUNC;
+       }
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel(__raw_readl(base + reg) | mask, base + reg);
+       /* flush write */
+       (void) __raw_readl(base + reg);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
+void ar71xx_gpio_function_disable(u32 mask)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+       unsigned int reg;
+
+       if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+           ar71xx_soc == AR71XX_SOC_AR9342 ||
+           ar71xx_soc == AR71XX_SOC_AR9344) {
+               reg = AR934X_GPIO_REG_FUNC;
+       } else {
+               reg = AR71XX_GPIO_REG_FUNC;
+       }
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel(__raw_readl(base + reg) & ~mask, base + reg);
+       /* flush write */
+       (void) __raw_readl(base + reg);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
+void ar71xx_gpio_function_setup(u32 set, u32 clear)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+       unsigned int reg;
+
+       if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+           ar71xx_soc == AR71XX_SOC_AR9342 ||
+           ar71xx_soc == AR71XX_SOC_AR9344) {
+               reg = AR934X_GPIO_REG_FUNC;
+       } else {
+               reg = AR71XX_GPIO_REG_FUNC;
+       }
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel((__raw_readl(base + reg) & ~clear) | set, base + reg);
+       /* flush write */
+       (void) __raw_readl(base + reg);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+EXPORT_SYMBOL(ar71xx_gpio_function_setup);
+
+void __init ar71xx_gpio_output_select(unsigned gpio, u8 val)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+       unsigned int reg;
+       u32 t, s;
+
+       if (ar71xx_soc != AR71XX_SOC_AR9341 &&
+           ar71xx_soc != AR71XX_SOC_AR9342 &&
+           ar71xx_soc != AR71XX_SOC_AR9344)
+               return;
+
+       if (gpio >= AR934X_GPIO_COUNT)
+               return;
+
+       reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+       s = 8 * (gpio % 4);
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       t = __raw_readl(base + reg);
+       t &= ~(0xff << s);
+       t |= val << s;
+       __raw_writel(t, base + reg);
+
+       /* flush write */
+       (void) __raw_readl(base + reg);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
+void __init ar71xx_gpio_init(void)
+{
+       int err;
+
+       if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+                               "AR71xx GPIO controller"))
+               panic("cannot allocate AR71xx GPIO registers page");
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR7240:
+               ar71xx_gpio_chip.ngpio = AR7240_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               ar71xx_gpio_chip.ngpio = AR7241_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT;
+               ar71xx_gpio_chip.direction_input = ar934x_gpio_direction_input;
+               ar71xx_gpio_chip.direction_output = ar934x_gpio_direction_output;
+               break;
+
+       default:
+               BUG();
+       }
+
+       err = gpiochip_add(&ar71xx_gpio_chip);
+       if (err)
+               panic("cannot add AR71xx GPIO chip, error=%d", err);
+}
+
+int gpio_to_irq(unsigned gpio)
+{
+       return AR71XX_GPIO_IRQ(gpio);
+}
+EXPORT_SYMBOL(gpio_to_irq);
+
+int irq_to_gpio(unsigned irq)
+{
+       return irq - AR71XX_GPIO_IRQ_BASE;
+}
+EXPORT_SYMBOL(irq_to_gpio);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/irq.c
new file mode 100644 (file)
index 0000000..6d744da
--- /dev/null
@@ -0,0 +1,416 @@
+/*
+ *  Atheros AR71xx SoC specific interrupt handling
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros 2.6.15 BSP
+ *  Parts of this file are based on Atheros 2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+static void ar71xx_gpio_irq_dispatch(void)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       u32 pending;
+
+       pending = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING) &
+                 __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+
+       if (pending)
+               do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
+       else
+               spurious_interrupt();
+}
+
+static void ar71xx_gpio_irq_unmask(struct irq_data *d)
+{
+       unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
+       void __iomem *base = ar71xx_gpio_base;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+       __raw_writel(t | (1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+}
+
+static void ar71xx_gpio_irq_mask(struct irq_data *d)
+{
+       unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE;
+       void __iomem *base = ar71xx_gpio_base;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+       __raw_writel(t & ~(1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+}
+
+static struct irq_chip ar71xx_gpio_irq_chip = {
+       .name           = "AR71XX GPIO",
+       .irq_unmask     = ar71xx_gpio_irq_unmask,
+       .irq_mask       = ar71xx_gpio_irq_mask,
+       .irq_mask_ack   = ar71xx_gpio_irq_mask,
+};
+
+static struct irqaction ar71xx_gpio_irqaction = {
+       .handler        = no_action,
+       .name           = "cascade [AR71XX GPIO]",
+};
+
+#define GPIO_INT_ALL   0xffff
+
+static void __init ar71xx_gpio_irq_init(void)
+{
+       void __iomem *base = ar71xx_gpio_base;
+       int i;
+
+       __raw_writel(0, base + AR71XX_GPIO_REG_INT_ENABLE);
+       __raw_writel(0, base + AR71XX_GPIO_REG_INT_PENDING);
+
+       /* setup type of all GPIO interrupts to level sensitive */
+       __raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_TYPE);
+
+       /* setup polarity of all GPIO interrupts to active high */
+       __raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_POLARITY);
+
+       for (i = AR71XX_GPIO_IRQ_BASE;
+            i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
+               irq_set_chip_and_handler(i, &ar71xx_gpio_irq_chip,
+                                        handle_level_irq);
+
+       setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
+}
+
+static void ar71xx_misc_irq_dispatch(void)
+{
+       u32 pending;
+
+       pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
+           & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       if (pending & MISC_INT_UART)
+               do_IRQ(AR71XX_MISC_IRQ_UART);
+
+       else if (pending & MISC_INT_DMA)
+               do_IRQ(AR71XX_MISC_IRQ_DMA);
+
+       else if (pending & MISC_INT_PERFC)
+               do_IRQ(AR71XX_MISC_IRQ_PERFC);
+
+       else if (pending & MISC_INT_TIMER)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER);
+
+       else if (pending & MISC_INT_OHCI)
+               do_IRQ(AR71XX_MISC_IRQ_OHCI);
+
+       else if (pending & MISC_INT_ERROR)
+               do_IRQ(AR71XX_MISC_IRQ_ERROR);
+
+       else if (pending & MISC_INT_GPIO)
+               ar71xx_gpio_irq_dispatch();
+
+       else if (pending & MISC_INT_WDOG)
+               do_IRQ(AR71XX_MISC_IRQ_WDOG);
+
+       else if (pending & MISC_INT_TIMER2)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER2);
+
+       else if (pending & MISC_INT_TIMER3)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER3);
+
+       else if (pending & MISC_INT_TIMER4)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER4);
+
+       else if (pending & MISC_INT_DDR_PERF)
+               do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
+
+       else if (pending & MISC_INT_ENET_LINK)
+               do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
+
+       else
+               spurious_interrupt();
+}
+
+static void ar71xx_misc_irq_unmask(struct irq_data *d)
+{
+       unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+}
+
+static void ar71xx_misc_irq_mask(struct irq_data *d)
+{
+       unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+}
+
+static void ar724x_misc_irq_ack(struct irq_data *d)
+{
+       unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE;
+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
+       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
+}
+
+static struct irq_chip ar71xx_misc_irq_chip = {
+       .name           = "AR71XX MISC",
+       .irq_unmask     = ar71xx_misc_irq_unmask,
+       .irq_mask       = ar71xx_misc_irq_mask,
+};
+
+static struct irqaction ar71xx_misc_irqaction = {
+       .handler        = no_action,
+       .name           = "cascade [AR71XX MISC]",
+};
+
+static void __init ar71xx_misc_irq_init(void)
+{
+       void __iomem *base = ar71xx_reset_base;
+       int i;
+
+       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ar71xx_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+               break;
+       default:
+               ar71xx_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+               break;
+       }
+
+       for (i = AR71XX_MISC_IRQ_BASE;
+            i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
+               irq_set_chip_and_handler(i, &ar71xx_misc_irq_chip,
+                                        handle_level_irq);
+
+       setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
+}
+
+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+{
+       u32 status;
+
+       disable_irq_nosync(irq);
+
+       status = ar71xx_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
+
+       if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
+               ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
+               generic_handle_irq(AR934X_IP2_IRQ_PCIE);
+       } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
+               ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
+               generic_handle_irq(AR934X_IP2_IRQ_WMAC);
+       } else {
+               spurious_interrupt();
+       }
+
+       enable_irq(irq);
+}
+
+static void ar934x_ip2_irq_init(void)
+{
+       int i;
+
+       for (i = AR934X_IP2_IRQ_BASE;
+            i < AR934X_IP2_IRQ_BASE + AR934X_IP2_IRQ_COUNT; i++)
+               irq_set_chip_and_handler(i, &dummy_irq_chip,
+                                        handle_level_irq);
+
+       irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
+}
+
+
+/*
+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
+ * these devices typically allocate coherent DMA memory, however the
+ * DMA controller may still have some unsynchronized data in the FIFO.
+ * Issue a flush in the handlers to ensure that the driver sees
+ * the update.
+ */
+static void ar71xx_ip2_handler(void)
+{
+       ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI);
+       do_IRQ(AR71XX_CPU_IRQ_IP2);
+}
+
+static void ar724x_ip2_handler(void)
+{
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
+       do_IRQ(AR71XX_CPU_IRQ_IP2);
+}
+
+static void ar913x_ip2_handler(void)
+{
+       ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
+       do_IRQ(AR71XX_CPU_IRQ_IP2);
+}
+
+static void ar933x_ip2_handler(void)
+{
+       ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
+       do_IRQ(AR71XX_CPU_IRQ_IP2);
+}
+
+static void ar934x_ip2_handler(void)
+{
+       do_IRQ(AR71XX_CPU_IRQ_IP2);
+}
+
+static void ar71xx_ip3_handler(void)
+{
+       ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB);
+       do_IRQ(AR71XX_CPU_IRQ_USB);
+}
+
+static void ar724x_ip3_handler(void)
+{
+       ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
+       do_IRQ(AR71XX_CPU_IRQ_USB);
+}
+
+static void ar913x_ip3_handler(void)
+{
+       ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
+       do_IRQ(AR71XX_CPU_IRQ_USB);
+}
+
+static void ar933x_ip3_handler(void)
+{
+       ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
+       do_IRQ(AR71XX_CPU_IRQ_USB);
+}
+
+static void ar934x_ip3_handler(void)
+{
+       do_IRQ(AR71XX_CPU_IRQ_USB);
+}
+
+static void (*ip2_handler)(void);
+static void (*ip3_handler)(void);
+
+asmlinkage void plat_irq_dispatch(void)
+{
+       unsigned long pending;
+
+       pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+       if (pending & STATUSF_IP7)
+               do_IRQ(AR71XX_CPU_IRQ_TIMER);
+
+       else if (pending & STATUSF_IP2)
+               ip2_handler();
+
+       else if (pending & STATUSF_IP4)
+               do_IRQ(AR71XX_CPU_IRQ_GE0);
+
+       else if (pending & STATUSF_IP5)
+               do_IRQ(AR71XX_CPU_IRQ_GE1);
+
+       else if (pending & STATUSF_IP3)
+               ip3_handler();
+
+       else if (pending & STATUSF_IP6)
+               ar71xx_misc_irq_dispatch();
+
+       else
+               spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               ip2_handler = ar71xx_ip2_handler;
+               ip3_handler = ar71xx_ip3_handler;
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               ip2_handler = ar724x_ip2_handler;
+               ip3_handler = ar724x_ip3_handler;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ip2_handler = ar913x_ip2_handler;
+               ip3_handler = ar913x_ip3_handler;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ip2_handler = ar933x_ip2_handler;
+               ip3_handler = ar933x_ip3_handler;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ip2_handler = ar934x_ip2_handler;
+               ip3_handler = ar934x_ip3_handler;
+               break;
+
+       default:
+               BUG();
+       }
+
+       mips_cpu_irq_init();
+
+       ar71xx_misc_irq_init();
+
+       if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+           ar71xx_soc == AR71XX_SOC_AR9342 ||
+           ar71xx_soc == AR71XX_SOC_AR9344)
+               ar934x_ip2_irq_init();
+
+       cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
+
+       ar71xx_gpio_irq_init();
+}
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-ap96.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-ap96.c
new file mode 100644 (file)
index 0000000..f22db50
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ *  ALFA Network AP96 board support
+ *
+ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/mmc_spi.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-pb42-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-usb.h"
+
+#define ALFA_AP96_GPIO_MICROSD_CS      0
+#define ALFA_AP96_GPIO_RTC_CS          1
+#define ALFA_AP96_GPIO_PCIE_RESET      2
+#define ALFA_AP96_GPIO_SIM_DETECT      3
+#define ALFA_AP96_GPIO_MICROSD_CD      4
+#define ALFA_AP96_GPIO_PCIE_W_DISABLE  5
+
+#define ALFA_AP96_GPIO_BUTTON_RESET    11
+
+#define ALFA_AP96_KEYS_POLL_INTERVAL           20      /* msecs */
+#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL       (3 * ALFA_AP96_KEYS_POLL_INTERVAL)
+
+static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = {
+       {
+               .desc           = "Reset button",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = ALFA_AP96_GPIO_BUTTON_RESET,
+               .active_low     = 1,
+       }
+};
+
+static int alfa_ap96_mmc_get_cd(struct device *dev)
+{
+        return !gpio_get_value(ALFA_AP96_GPIO_MICROSD_CD);
+}
+
+static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
+       .get_cd         = alfa_ap96_mmc_get_cd,
+       .caps           = MMC_CAP_NEEDS_POLL,
+       .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+
+static struct spi_board_info alfa_ap96_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "m25p80",
+       }, {
+               .bus_num        = 0,
+               .chip_select    = 1,
+               .max_speed_hz   = 25000000,
+               .modalias       = "mmc_spi",
+               .platform_data  = &alfa_ap96_mmc_data,
+               .controller_data = (void *) ALFA_AP96_GPIO_MICROSD_CS,
+       }, {
+               .bus_num        = 0,
+               .chip_select    = 2,
+               .max_speed_hz   = 6250000,
+               .modalias       = "rtc-pcf2123",
+               .controller_data = (void *) ALFA_AP96_GPIO_RTC_CS,
+       },
+};
+
+static struct resource alfa_ap96_spi_resources[] = {
+       [0] = {
+               .start  = AR71XX_SPI_BASE,
+               .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct ar71xx_spi_platform_data alfa_ap96_spi_data = {
+       .bus_num                = 0,
+       .num_chipselect         = 3,
+};
+
+static struct platform_device alfa_ap96_spi_device = {
+       .name           = "pb44-spi",
+       .id             = -1,
+       .resource       = alfa_ap96_spi_resources,
+       .num_resources  = ARRAY_SIZE(alfa_ap96_spi_resources),
+       .dev = {
+               .platform_data = &alfa_ap96_spi_data,
+       },
+};
+
+static void __init alfa_ap96_gpio_setup(void)
+{
+       ar71xx_gpio_function_disable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
+                                    AR71XX_GPIO_FUNC_SPI_CS2_EN);
+
+       gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
+       gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
+       gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
+       gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
+       gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
+       gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
+}
+
+#define ALFA_AP96_WAN_PHYMASK  BIT(4)
+#define ALFA_AP96_LAN_PHYMASK  BIT(5)
+#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK)
+
+static void __init alfa_ap96_init(void)
+{
+       alfa_ap96_gpio_setup();
+
+       ar71xx_add_device_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
+       ar71xx_eth1_pll_data.pll_1000 = 0x110000;
+
+       ar71xx_add_device_eth(0);
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
+       ar71xx_eth1_pll_data.pll_1000 = 0x110000;
+
+       ar71xx_add_device_eth(1);
+
+       pb42_pci_init();
+
+       spi_register_board_info(alfa_ap96_spi_info,
+                               ARRAY_SIZE(alfa_ap96_spi_info));
+       platform_device_register(&alfa_ap96_spi_device);
+
+       ar71xx_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(alfa_ap96_gpio_keys),
+                                        alfa_ap96_gpio_keys);
+       ar71xx_add_device_usb();
+}
+
+MIPS_MACHINE(AR71XX_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96",
+            alfa_ap96_init);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-nx.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-alfa-nx.c
new file mode 100644 (file)
index 0000000..6e28080
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ *  ALFA Network N2/N5 board support
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ap91-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+
+#define ALFA_NX_GPIO_LED_2             17
+#define ALFA_NX_GPIO_LED_3             16
+#define ALFA_NX_GPIO_LED_5             12
+#define ALFA_NX_GPIO_LED_6             8
+#define ALFA_NX_GPIO_LED_7             6
+#define ALFA_NX_GPIO_LED_8             7
+
+#define ALFA_NX_GPIO_BTN_RESET         11
+
+#define ALFA_NX_KEYS_POLL_INTERVAL     20      /* msecs */
+#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL)
+
+#define ALFA_NX_MAC0_OFFSET            0
+#define ALFA_NX_MAC1_OFFSET            6
+#define ALFA_NX_CALDATA_OFFSET         0x1000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition alfa_nx_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x050000,
+               .size           = 0x600000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x650000,
+               .size           = 0x190000,
+       }, {
+               .name           = "nvram",
+               .offset         = 0x7e0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "art",
+               .offset         = 0x7f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x050000,
+               .size           = 0x780000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data alfa_nx_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = alfa_nx_partitions,
+       .nr_parts       = ARRAY_SIZE(alfa_nx_partitions),
+#endif
+};
+
+static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = {
+       {
+               .desc           = "Reset button",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = ALFA_NX_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_led alfa_nx_leds_gpio[] __initdata = {
+       {
+               .name           = "alfa:green:led_2",
+               .gpio           = ALFA_NX_GPIO_LED_2,
+               .active_low     = 1,
+       }, {
+               .name           = "alfa:green:led_3",
+               .gpio           = ALFA_NX_GPIO_LED_3,
+               .active_low     = 1,
+       }, {
+               .name           = "alfa:red:led_5",
+               .gpio           = ALFA_NX_GPIO_LED_5,
+               .active_low     = 1,
+       }, {
+               .name           = "alfa:amber:led_6",
+               .gpio           = ALFA_NX_GPIO_LED_6,
+               .active_low     = 1,
+       }, {
+               .name           = "alfa:green:led_7",
+               .gpio           = ALFA_NX_GPIO_LED_7,
+               .active_low     = 1,
+       }, {
+               .name           = "alfa:green:led_8",
+               .gpio           = ALFA_NX_GPIO_LED_8,
+               .active_low     = 1,
+       }
+};
+
+static void __init alfa_nx_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+       ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
+                                  AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+                                  AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+                                  AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+                                  AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+                                  AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+       ar71xx_add_device_m25p80(&alfa_nx_flash_data);
+
+       ar71xx_add_device_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio),
+                                       alfa_nx_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(alfa_nx_gpio_keys),
+                                        alfa_nx_gpio_keys);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr,
+                       art + ALFA_NX_MAC0_OFFSET, 0);
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr,
+                       art + ALFA_NX_MAC1_OFFSET, 0);
+
+       /* WAN port */
+       ar71xx_add_device_eth(0);
+       /* LAN port */
+       ar71xx_add_device_eth(1);
+
+       ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL);
+}
+
+MIPS_MACHINE(AR71XX_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5",
+            alfa_nx_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-all0258n.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-all0258n.c
new file mode 100644 (file)
index 0000000..18d0a93
--- /dev/null
@@ -0,0 +1,140 @@
+/*
+ *  Allnet ALL0258N support
+ *
+ *  Copyright (C) 2011 Daniel Golle <dgolle@allnet.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ap91-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+
+/* found via /sys/gpio/... try and error */
+#define ALL0258N_GPIO_BTN_RESET                1
+#define ALL0258N_GPIO_LED_RSSIHIGH     13
+#define ALL0258N_GPIO_LED_RSSIMEDIUM   15
+#define ALL0258N_GPIO_LED_RSSILOW      14
+
+/* defaults taken from others machs */
+#define ALL0258N_KEYS_POLL_INTERVAL    20      /* msecs */
+#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL)
+
+/* showed up in the original firmware's bootlog */
+#define ALL0258N_SEC_PHYMASK BIT(3)
+
+/*
+ * from U-Boot bootargs of original firmware:
+ * mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),320k(custom),1024k(kernel),4928k(rootfs),1536k(failsafe),64k(ART)
+ * we use a more OpenWrt-friendly layout now:
+ * mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),896k(kernel),5376k(rootfs),1536k(failsafe),64k(ART)
+ */
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition all0258n_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x050000,
+               .size           = 0x0E0000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x130000,
+               .size           = 0x540000,
+       }, {
+               .name           = "failsafe",
+               .offset         = 0x670000,
+               .size           = 0x180000,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x050000,
+               .size           = 0x620000,
+       }, {
+               .name           = "art",
+               .offset         = 0x7F0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data all0258n_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = all0258n_partitions,
+       .nr_parts       = ARRAY_SIZE(all0258n_partitions),
+#endif
+};
+
+static struct gpio_led all0258n_leds_gpio[] __initdata = {
+       {
+               .name           = "all0258n:green:rssihigh",
+               .gpio           = ALL0258N_GPIO_LED_RSSIHIGH,
+               .active_low     = 1,
+       }, {
+               .name           = "all0258n:yellow:rssimedium",
+               .gpio           = ALL0258N_GPIO_LED_RSSIMEDIUM,
+               .active_low     = 1,
+       }, {
+               .name           = "all0258n:red:rssilow",
+               .gpio           = ALL0258N_GPIO_LED_RSSILOW,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button all0258n_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = ALL0258N_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }
+};
+
+static void __init all0258n_setup(void)
+{
+       u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000);
+       u8 *ee =  (u8 *) KSEG1ADDR(0x1f7f1000);
+
+       ar71xx_add_device_m25p80(&all0258n_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio),
+                                       all0258n_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(all0258n_gpio_keys),
+                                        all0258n_gpio_keys);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0);
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 0);
+
+       ar71xx_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK;
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(AR71XX_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N",
+            all0258n_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap121.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap121.c
new file mode 100644 (file)
index 0000000..d14996f
--- /dev/null
@@ -0,0 +1,237 @@
+/*
+ *  Atheros AP121 board support
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/flash.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+
+#define AP121_GPIO_LED_WLAN            0
+#define AP121_GPIO_LED_USB             1
+
+#define AP121_GPIO_BTN_JUMPSTART       11
+#define AP121_GPIO_BTN_RESET           12
+
+#define AP121_KEYS_POLL_INTERVAL       20      /* msecs */
+#define AP121_KEYS_DEBOUNCE_INTERVAL   (3 * AP121_KEYS_POLL_INTERVAL)
+
+#define AP121_MAC0_OFFSET      0x0000
+#define AP121_MAC1_OFFSET      0x0006
+#define AP121_CALDATA_OFFSET   0x1000
+#define AP121_WMAC_MAC_OFFSET  0x1002
+
+#define AP121_MINI_GPIO_LED_WLAN       0
+#define AP121_MINI_GPIO_BTN_JUMPSTART  12
+#define AP121_MINI_GPIO_BTN_RESET      11
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition ap121_parts[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "rootfs",
+               .offset         = 0x010000,
+               .size           = 0x130000,
+       },
+       {
+               .name           = "uImage",
+               .offset         = 0x140000,
+               .size           = 0x0a0000,
+       },
+       {
+               .name           = "NVRAM",
+               .offset         = 0x1e0000,
+               .size           = 0x010000,
+       },
+       {
+               .name           = "ART",
+               .offset         = 0x1f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+};
+#define ap121_nr_parts         ARRAY_SIZE(ap121_parts)
+
+static struct mtd_partition ap121_mini_parts[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+       {
+               .name           = "rootfs",
+               .offset         = 0x050000,
+               .size           = 0x2b0000,
+       },
+       {
+               .name           = "uImage",
+               .offset         = 0x300000,
+               .size           = 0x0e0000,
+       },
+       {
+               .name           = "NVRAM",
+               .offset         = 0x3e0000,
+               .size           = 0x010000,
+       },
+       {
+               .name           = "ART",
+               .offset         = 0x3f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       },
+};
+
+#define ap121_mini_nr_parts    ARRAY_SIZE(ap121_parts)
+
+#else
+#define ap121_parts            NULL
+#define ap121_nr_parts         0
+#define ap121_mini_parts       NULL
+#define ap121_mini_nr_parts    0
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data ap121_flash_data = {
+       .parts          = ap121_parts,
+       .nr_parts       = ap121_nr_parts,
+};
+
+static struct gpio_led ap121_leds_gpio[] __initdata = {
+       {
+               .name           = "ap121:green:usb",
+               .gpio           = AP121_GPIO_LED_USB,
+               .active_low     = 0,
+       },
+       {
+               .name           = "ap121:green:wlan",
+               .gpio           = AP121_GPIO_LED_WLAN,
+               .active_low     = 0,
+       },
+};
+
+static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
+       {
+               .desc           = "jumpstart button",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP121_GPIO_BTN_JUMPSTART,
+               .active_low     = 1,
+       },
+       {
+               .desc           = "reset button",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP121_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
+       {
+               .name           = "ap121:green:wlan",
+               .gpio           = AP121_MINI_GPIO_LED_WLAN,
+               .active_low     = 0,
+       },
+};
+
+static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
+       {
+               .desc           = "jumpstart button",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP121_MINI_GPIO_BTN_JUMPSTART,
+               .active_low     = 1,
+       },
+       {
+               .desc           = "reset button",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP121_MINI_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }
+};
+
+static void __init ap121_common_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+       ar71xx_add_device_m25p80(&ap121_flash_data);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       /* LAN ports */
+       ar71xx_add_device_eth(1);
+
+       /* WAN port */
+       ar71xx_add_device_eth(0);
+
+       ar9xxx_add_device_wmac(art + AP121_CALDATA_OFFSET,
+                              art + AP121_WMAC_MAC_OFFSET);
+}
+
+static void __init ap121_setup(void)
+{
+       ap121_flash_data.parts = ap121_parts;
+       ap121_flash_data.nr_parts = ap121_nr_parts;
+
+       ap121_common_setup();
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+                                       ap121_leds_gpio);
+       ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap121_gpio_keys),
+                                        ap121_gpio_keys);
+
+       ar71xx_add_device_usb();
+}
+
+static void __init ap121_mini_setup(void)
+{
+       ap121_flash_data.parts = ap121_mini_parts;
+       ap121_flash_data.nr_parts = ap121_mini_nr_parts;
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
+                                       ap121_mini_leds_gpio);
+       ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap121_mini_gpio_keys),
+                                        ap121_mini_gpio_keys);
+
+       ap121_common_setup();
+}
+
+MIPS_MACHINE(AR71XX_MACH_AP121, "AP121", "Atheros AP121",
+            ap121_setup);
+
+MIPS_MACHINE(AR71XX_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
+            ap121_mini_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap81.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap81.c
new file mode 100644 (file)
index 0000000..802dbec
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ *  Atheros AP81 board support
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+
+#define AP81_GPIO_LED_STATUS   1
+#define AP81_GPIO_LED_AOSS     3
+#define AP81_GPIO_LED_WLAN     6
+#define AP81_GPIO_LED_POWER    14
+
+#define AP81_GPIO_BTN_SW4      12
+#define AP81_GPIO_BTN_SW1      21
+
+#define AP81_KEYS_POLL_INTERVAL                20 /* msecs */
+#define AP81_KEYS_DEBOUNCE_INTERVAL    (3 * AP81_KEYS_POLL_INTERVAL)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition ap81_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x050000,
+               .size           = 0x500000,
+       }, {
+               .name           = "uImage",
+               .offset         = 0x550000,
+               .size           = 0x100000,
+       }, {
+               .name           = "ART",
+               .offset         = 0x650000,
+               .size           = 0x1b0000,
+               .mask_flags     = MTD_WRITEABLE,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data ap81_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = ap81_partitions,
+       .nr_parts       = ARRAY_SIZE(ap81_partitions),
+#endif
+};
+
+static struct gpio_led ap81_leds_gpio[] __initdata = {
+       {
+               .name           = "ap81:green:status",
+               .gpio           = AP81_GPIO_LED_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "ap81:amber:aoss",
+               .gpio           = AP81_GPIO_LED_AOSS,
+               .active_low     = 1,
+       }, {
+               .name           = "ap81:green:wlan",
+               .gpio           = AP81_GPIO_LED_WLAN,
+               .active_low     = 1,
+       }, {
+               .name           = "ap81:green:power",
+               .gpio           = AP81_GPIO_LED_POWER,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button ap81_gpio_keys[] __initdata = {
+       {
+               .desc           = "sw1",
+               .type           = EV_KEY,
+               .code           = BTN_0,
+               .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP81_GPIO_BTN_SW1,
+               .active_low     = 1,
+       }, {
+               .desc           = "sw4",
+               .type           = EV_KEY,
+               .code           = BTN_1,
+               .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP81_GPIO_BTN_SW4,
+               .active_low     = 1,
+       }
+};
+
+static void __init ap81_setup(void)
+{
+       u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth0_data.speed = SPEED_100;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.has_ar8216 = 1;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth1_data.phy_mask = 0x10;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_usb();
+
+       ar71xx_add_device_m25p80(&ap81_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio),
+                                       ap81_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap81_gpio_keys),
+                                        ap81_gpio_keys);
+
+       ar9xxx_add_device_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap83.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap83.c
new file mode 100644 (file)
index 0000000..2eab994
--- /dev/null
@@ -0,0 +1,267 @@
+/*
+ *  Atheros AP83 board support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/spi/vsc7385.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/ar91xx_flash.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+
+#define AP83_GPIO_LED_WLAN     6
+#define AP83_GPIO_LED_POWER    14
+#define AP83_GPIO_LED_JUMPSTART        15
+#define AP83_GPIO_BTN_JUMPSTART        12
+#define AP83_GPIO_BTN_RESET    21
+
+#define AP83_050_GPIO_VSC7385_CS       1
+#define AP83_050_GPIO_VSC7385_MISO     3
+#define AP83_050_GPIO_VSC7385_MOSI     16
+#define AP83_050_GPIO_VSC7385_SCK      17
+
+#define AP83_KEYS_POLL_INTERVAL                20      /* msecs */
+#define AP83_KEYS_DEBOUNCE_INTERVAL    (3 * AP83_KEYS_POLL_INTERVAL)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition ap83_flash_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x020000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x060000,
+               .size           = 0x140000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x1a0000,
+               .size           = 0x650000,
+       }, {
+               .name           = "art",
+               .offset         = 0x7f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x060000,
+               .size           = 0x790000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct ar91xx_flash_platform_data ap83_flash_data = {
+       .width          = 2,
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = ap83_flash_partitions,
+       .nr_parts       = ARRAY_SIZE(ap83_flash_partitions),
+#endif
+};
+
+static struct resource ap83_flash_resources[] = {
+       [0] = {
+               .start  = AR71XX_SPI_BASE,
+               .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device ap83_flash_device = {
+       .name           = "ar91xx-flash",
+       .id             = -1,
+       .resource       = ap83_flash_resources,
+       .num_resources  = ARRAY_SIZE(ap83_flash_resources),
+       .dev            = {
+               .platform_data = &ap83_flash_data,
+       }
+};
+
+static struct gpio_led ap83_leds_gpio[] __initdata = {
+       {
+               .name           = "ap83:green:jumpstart",
+               .gpio           = AP83_GPIO_LED_JUMPSTART,
+               .active_low     = 0,
+       }, {
+               .name           = "ap83:green:power",
+               .gpio           = AP83_GPIO_LED_POWER,
+               .active_low     = 0,
+       }, {
+               .name           = "ap83:green:wlan",
+               .gpio           = AP83_GPIO_LED_WLAN,
+               .active_low     = 0,
+       },
+};
+
+static struct gpio_keys_button ap83_gpio_keys[] __initdata = {
+       {
+               .desc           = "soft_reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP83_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "jumpstart",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP83_GPIO_BTN_JUMPSTART,
+               .active_low     = 1,
+       }
+};
+
+static struct resource ap83_040_spi_resources[] = {
+       [0] = {
+               .start  = AR71XX_SPI_BASE,
+               .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device ap83_040_spi_device = {
+       .name           = "ap83-spi",
+       .id             = 0,
+       .resource       = ap83_040_spi_resources,
+       .num_resources  = ARRAY_SIZE(ap83_040_spi_resources),
+};
+
+static struct spi_gpio_platform_data ap83_050_spi_data = {
+       .miso   = AP83_050_GPIO_VSC7385_MISO,
+       .mosi   = AP83_050_GPIO_VSC7385_MOSI,
+       .sck    = AP83_050_GPIO_VSC7385_SCK,
+       .num_chipselect = 1,
+};
+
+static struct platform_device ap83_050_spi_device = {
+       .name           = "spi_gpio",
+       .id             = 0,
+       .dev            = {
+               .platform_data = &ap83_050_spi_data,
+       }
+};
+
+static void ap83_vsc7385_reset(void)
+{
+       ar71xx_device_stop(RESET_MODULE_GE1_PHY);
+       udelay(10);
+       ar71xx_device_start(RESET_MODULE_GE1_PHY);
+       mdelay(50);
+}
+
+static struct vsc7385_platform_data ap83_vsc7385_data = {
+       .reset          = ap83_vsc7385_reset,
+       .ucode_name     = "vsc7385_ucode_ap83.bin",
+       .mac_cfg = {
+               .tx_ipg         = 6,
+               .bit2           = 0,
+               .clk_sel        = 3,
+       },
+};
+
+static struct spi_board_info ap83_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "spi-vsc7385",
+               .platform_data  = &ap83_vsc7385_data,
+               .controller_data = (void *) AP83_050_GPIO_VSC7385_CS,
+       }
+};
+
+static void __init ap83_generic_setup(void)
+{
+       u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+       ar71xx_add_device_mdio(0, 0xfffffffe);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.phy_mask = 0x1;
+
+       ar71xx_add_device_eth(0);
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth1_data.speed = SPEED_1000;
+       ar71xx_eth1_data.duplex = DUPLEX_FULL;
+
+       ar71xx_eth1_pll_data.pll_1000 = 0x1f000000;
+
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio),
+                                       ap83_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap83_gpio_keys),
+                                        ap83_gpio_keys);
+
+       ar71xx_add_device_usb();
+
+       ar9xxx_add_device_wmac(eeprom, NULL);
+
+       platform_device_register(&ap83_flash_device);
+
+       spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info));
+}
+
+static void __init ap83_040_setup(void)
+{
+       ap83_flash_data.is_shared = 1;
+       ap83_generic_setup();
+       platform_device_register(&ap83_040_spi_device);
+}
+
+static void __init ap83_050_setup(void)
+{
+       ap83_generic_setup();
+       platform_device_register(&ap83_050_spi_device);
+}
+
+static void __init ap83_setup(void)
+{
+       u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244);
+       unsigned int board_version;
+
+       board_version = (unsigned int)(board_id[0] - '0');
+       board_version += ((unsigned int)(board_id[1] - '0')) * 10;
+
+       switch (board_version) {
+       case 40:
+               ap83_040_setup();
+               break;
+       case 50:
+               ap83_050_setup();
+               break;
+       default:
+               printk(KERN_WARNING "AP83-%03u board is not yet supported\n",
+                      board_version);
+       }
+}
+
+MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap96.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ap96.c
new file mode 100644 (file)
index 0000000..5882af2
--- /dev/null
@@ -0,0 +1,180 @@
+/*
+ *  Atheros AP96 board support
+ *
+ *  Copyright (C) 2009 Marco Porsch
+ *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2010 Atheros Communications
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ap94-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+
+#define AP96_GPIO_LED_12_GREEN         0
+#define AP96_GPIO_LED_3_GREEN          1
+#define AP96_GPIO_LED_2_GREEN          2
+#define AP96_GPIO_LED_WPS_GREEN                4
+#define AP96_GPIO_LED_5_GREEN          5
+#define AP96_GPIO_LED_4_ORANGE         6
+
+/* Reset button - next to the power connector */
+#define AP96_GPIO_BTN_RESET            3
+/* WPS button - next to a led on right */
+#define AP96_GPIO_BTN_WPS              8
+
+#define AP96_KEYS_POLL_INTERVAL                20      /* msecs */
+#define AP96_KEYS_DEBOUNCE_INTERVAL    (3 * AP96_KEYS_POLL_INTERVAL)
+
+#define AP96_WMAC0_MAC_OFFSET          0x120c
+#define AP96_WMAC1_MAC_OFFSET          0x520c
+#define AP96_CALDATA0_OFFSET           0x1000
+#define AP96_CALDATA1_OFFSET           0x5000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition ap96_partitions[] = {
+       {
+               .name           = "uboot",
+               .offset         = 0,
+               .size           = 0x030000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "env",
+               .offset         = 0x030000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x040000,
+               .size           = 0x600000,
+       }, {
+               .name           = "uImage",
+               .offset         = 0x640000,
+               .size           = 0x1b0000,
+       }, {
+               .name           = "caldata",
+               .offset         = 0x7f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data ap96_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = ap96_partitions,
+       .nr_parts       = ARRAY_SIZE(ap96_partitions),
+#endif
+};
+
+/*
+ * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12
+ * below (from left to right on the board). Led 1 seems to be on whenever the
+ * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange;
+ * others are green.
+ *
+ * In addition, there is one led next to a button on the right side for WPS.
+ */
+static struct gpio_led ap96_leds_gpio[] __initdata = {
+       {
+               .name           = "ap96:green:led2",
+               .gpio           = AP96_GPIO_LED_2_GREEN,
+               .active_low     = 1,
+       }, {
+               .name           = "ap96:green:led3",
+               .gpio           = AP96_GPIO_LED_3_GREEN,
+               .active_low     = 1,
+       }, {
+               .name           = "ap96:orange:led4",
+               .gpio           = AP96_GPIO_LED_4_ORANGE,
+               .active_low     = 1,
+       }, {
+               .name           = "ap96:green:led5",
+               .gpio           = AP96_GPIO_LED_5_GREEN,
+               .active_low     = 1,
+       }, {
+               .name           = "ap96:green:led12",
+               .gpio           = AP96_GPIO_LED_12_GREEN,
+               .active_low     = 1,
+       }, { /* next to a button on right */
+               .name           = "ap96:green:wps",
+               .gpio           = AP96_GPIO_LED_WPS_GREEN,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button ap96_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP96_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AP96_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+#define AP96_WAN_PHYMASK 0x10
+#define AP96_LAN_PHYMASK 0x0f
+
+static void __init ap96_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+       ar71xx_add_device_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK));
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.phy_mask = AP96_LAN_PHYMASK;
+       ar71xx_eth0_data.speed = SPEED_1000;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+
+       ar71xx_add_device_eth(0);
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth1_data.phy_mask = AP96_WAN_PHYMASK;
+
+       ar71xx_eth1_pll_data.pll_1000 = 0x1f000000;
+
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_usb();
+
+       ar71xx_add_device_m25p80(&ap96_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio),
+                                       ap96_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap96_gpio_keys),
+                                        ap96_gpio_keys);
+
+       ap94_pci_init(art + AP96_CALDATA0_OFFSET,
+                     art + AP96_WMAC0_MAC_OFFSET,
+                     art + AP96_CALDATA1_OFFSET,
+                     art + AP96_WMAC1_MAC_OFFSET);
+}
+
+MIPS_MACHINE(AR71XX_MACH_AP96, "AP96", "Atheros AP96", ap96_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c
new file mode 100644 (file)
index 0000000..54dc96c
--- /dev/null
@@ -0,0 +1,108 @@
+/*
+ *  AzureWave AW-NR580 board support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <asm/mips_machine.h>
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-pb42-pci.h"
+#include "dev-leds-gpio.h"
+
+#define AW_NR580_GPIO_LED_READY_RED    0
+#define AW_NR580_GPIO_LED_WLAN         1
+#define AW_NR580_GPIO_LED_READY_GREEN  2
+#define AW_NR580_GPIO_LED_WPS_GREEN    4
+#define AW_NR580_GPIO_LED_WPS_AMBER    5
+
+#define AW_NR580_GPIO_BTN_WPS          3
+#define AW_NR580_GPIO_BTN_RESET                11
+
+#define AW_NR580_KEYS_POLL_INTERVAL    20      /* msecs */
+#define AW_NR580_KEYS_DEBOUNCE_INTERVAL        (3 * AW_NR580_KEYS_POLL_INTERVAL)
+
+static struct gpio_led aw_nr580_leds_gpio[] __initdata = {
+       {
+               .name           = "aw-nr580:red:ready",
+               .gpio           = AW_NR580_GPIO_LED_READY_RED,
+               .active_low     = 0,
+       }, {
+               .name           = "aw-nr580:green:ready",
+               .gpio           = AW_NR580_GPIO_LED_READY_GREEN,
+               .active_low     = 0,
+       }, {
+               .name           = "aw-nr580:green:wps",
+               .gpio           = AW_NR580_GPIO_LED_WPS_GREEN,
+               .active_low     = 0,
+       }, {
+               .name           = "aw-nr580:amber:wps",
+               .gpio           = AW_NR580_GPIO_LED_WPS_AMBER,
+               .active_low     = 0,
+       }, {
+               .name           = "aw-nr580:green:wlan",
+               .gpio           = AW_NR580_GPIO_LED_WLAN,
+               .active_low     = 0,
+       }
+};
+
+static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AW_NR580_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = AW_NR580_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static const char *aw_nr580_part_probes[] = {
+       "RedBoot",
+       NULL,
+};
+
+static struct flash_platform_data aw_nr580_flash_data = {
+       .part_probes    = aw_nr580_part_probes,
+};
+
+static void __init aw_nr580_setup(void)
+{
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+       ar71xx_eth0_data.speed = SPEED_100;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+
+       ar71xx_add_device_eth(0);
+
+       pb42_pci_init();
+
+       ar71xx_add_device_m25p80(&aw_nr580_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio),
+                                       aw_nr580_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(aw_nr580_gpio_keys),
+                                        aw_nr580_gpio_keys);
+}
+
+MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580",
+            aw_nr580_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-db120.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-db120.c
new file mode 100644 (file)
index 0000000..3a95fa2
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+ *  Atheros DB120 board (WASP SoC) support
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-db120-pci.h"
+
+#define DB120_GPIO_LED_USB     11
+#define DB120_GPIO_LED_WLAN_5G 12
+#define DB120_GPIO_LED_WLAN_2G 13
+#define DB120_GPIO_LED_STATUS  14
+#define DB120_GPIO_LED_WPS     15
+
+#define DB120_GPIO_BTN_WPS     16
+
+#define DB120_MAC0_OFFSET      0
+#define DB120_MAC1_OFFSET      6
+#define DB120_WMAC_CALDATA_OFFSET 0x1000
+#define DB120_PCIE_CALDATA_OFFSET 0x5000
+
+#define DB120_KEYS_POLL_INTERVAL       20      /* msecs */
+#define DB120_KEYS_DEBOUNCE_INTERVAL   (3 * DB120_KEYS_POLL_INTERVAL)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition db120_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x050000,
+               .size           = 0x630000,
+       }, {
+               .name           = "uImage",
+               .offset         = 0x680000,
+               .size           = 0x160000,
+       }, {
+               .name           = "NVRAM",
+               .offset         = 0x7E0000,
+               .size           = 0x010000,
+       }, {
+               .name           = "ART",
+               .offset         = 0x7F0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data db120_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = db120_partitions,
+       .nr_parts       = ARRAY_SIZE(db120_partitions),
+#endif
+};
+
+static struct gpio_led db120_leds_gpio[] __initdata = {
+       {
+               .name           = "db120:green:status",
+               .gpio           = DB120_GPIO_LED_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "db120:green:wps",
+               .gpio           = DB120_GPIO_LED_WPS,
+               .active_low     = 1,
+       }, {
+               .name           = "db120:green:wlan-5g",
+               .gpio           = DB120_GPIO_LED_WLAN_5G,
+               .active_low     = 1,
+       }, {
+               .name           = "db120:green:wlan-2g",
+               .gpio           = DB120_GPIO_LED_WLAN_2G,
+               .active_low     = 1,
+       }, {
+               .name           = "db120:green:usb",
+               .gpio           = DB120_GPIO_LED_USB,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+       {
+               .desc           = "WPS button",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DB120_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static void __init db120_gmac_setup(void)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
+              AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
+       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+
+       iounmap(base);
+}
+
+static void __init db120_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+       ar71xx_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
+
+       ar71xx_add_device_usb();
+
+       ar71xx_add_device_m25p80(&db120_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+                                       db120_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(db120_gpio_keys),
+                                        db120_gpio_keys);
+
+       db120_gmac_setup();
+
+       ar71xx_add_device_mdio(0, 0x0);
+       ar71xx_add_device_mdio(1, 0x0);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
+#if 0
+       /* GMAC0 is connected to an AR8327 switch */
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.speed = SPEED_1000;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+#else
+       /* GMAC0 is connected to PHY4 of the internal switch */
+       ar71xx_switch_data.phy4_mii_en = 1;
+
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+       ar71xx_eth0_data.phy_mask = BIT(4);
+       ar71xx_eth0_data.mii_bus_dev = &ar71xx_mdio1_device.dev;
+#endif
+
+       ar71xx_add_device_eth(0);
+
+       /* GMAC1 is connected to the internal switch */
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+       ar71xx_eth1_data.speed = SPEED_1000;
+       ar71xx_eth1_data.duplex = DUPLEX_FULL;
+
+       ar71xx_add_device_eth(1);
+
+       ar9xxx_add_device_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+
+       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
+}
+
+MIPS_MACHINE(AR71XX_MACH_DB120, "DB120", "Atheros DB120", db120_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c
new file mode 100644 (file)
index 0000000..ba833e8
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ *  D-Link DIR-600 rev. A1 board support
+ *
+ *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ap91-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "nvram.h"
+
+#define DIR_600_A1_GPIO_LED_WPS                        0
+#define DIR_600_A1_GPIO_LED_POWER_AMBER                1
+#define DIR_600_A1_GPIO_LED_POWER_GREEN                6
+
+#define DIR_600_A1_GPIO_BTN_RESET              8
+#define DIR_600_A1_GPIO_BTN_WPS                        12
+
+#define DIR_600_A1_KEYS_POLL_INTERVAL  20      /* msecs */
+#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL)
+
+#define DIR_600_A1_NVRAM_ADDR  0x1f030000
+#define DIR_600_A1_NVRAM_SIZE  0x10000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition dir_600_a1_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x030000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "nvram",
+               .offset         = 0x030000,
+               .size           = 0x010000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x040000,
+               .size           = 0x0e0000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x120000,
+               .size           = 0x2c0000,
+       }, {
+               .name           = "mac",
+               .offset         = 0x3e0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "art",
+               .offset         = 0x3f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x040000,
+               .size           = 0x3a0000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data dir_600_a1_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = dir_600_a1_partitions,
+       .nr_parts       = ARRAY_SIZE(dir_600_a1_partitions),
+#endif
+};
+
+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = {
+       {
+               .name           = "dir-600-a1:green:power",
+               .gpio           = DIR_600_A1_GPIO_LED_POWER_GREEN,
+       }, {
+               .name           = "dir-600-a1:amber:power",
+               .gpio           = DIR_600_A1_GPIO_LED_POWER_AMBER,
+       }, {
+               .name           = "dir-600-a1:blue:wps",
+               .gpio           = DIR_600_A1_GPIO_LED_WPS,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR_600_A1_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR_600_A1_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static void __init dir_600_a1_setup(void)
+{
+       const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
+       u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+       u8 mac_buff[6];
+       u8 *mac = NULL;
+
+       if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
+                               "lan_mac=", mac_buff) == 0) {
+               ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac_buff, 0);
+               ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_buff, 1);
+               mac = mac_buff;
+       }
+
+       ar71xx_add_device_m25p80(&dir_600_a1_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
+                                       dir_600_a1_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(dir_600_a1_gpio_keys),
+                                        dir_600_a1_gpio_keys);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0);
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       /* LAN ports */
+       ar71xx_add_device_eth(1);
+
+       /* WAN port */
+       ar71xx_add_device_eth(0);
+
+       ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1",
+            dir_600_a1_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c
new file mode 100644 (file)
index 0000000..fcadc6f
--- /dev/null
@@ -0,0 +1,175 @@
+/*
+ *  D-Link DIR-615 rev C1 board support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "nvram.h"
+
+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1     /* ORANGE:STATUS:TRICOLOR */
+#define DIR_615C1_GPIO_LED_BLUE_WPS    3       /* BLUE:WPS */
+#define DIR_615C1_GPIO_LED_GREEN_WAN   4       /* GREEN:WAN:TRICOLOR */
+#define DIR_615C1_GPIO_LED_GREEN_WANCPU        5       /* GREEN:WAN:CPU:TRICOLOR */
+#define DIR_615C1_GPIO_LED_GREEN_WLAN  6       /* GREEN:WLAN */
+#define DIR_615C1_GPIO_LED_GREEN_STATUS        14      /* GREEN:STATUS:TRICOLOR */
+#define DIR_615C1_GPIO_LED_ORANGE_WAN  15      /* ORANGE:WAN:TRICOLOR */
+
+/* buttons may need refinement */
+
+#define DIR_615C1_GPIO_BTN_WPS         12
+#define DIR_615C1_GPIO_BTN_RESET       21
+
+#define DIR_615C1_KEYS_POLL_INTERVAL   20      /* msecs */
+#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL)
+
+#define DIR_615C1_CONFIG_ADDR          0x1f020000
+#define DIR_615C1_CONFIG_SIZE          0x10000
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition dir_615c1_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x020000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "config",
+               .offset         = 0x020000,
+               .size           = 0x010000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x030000,
+               .size           = 0x0e0000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x110000,
+               .size           = 0x2e0000,
+       }, {
+               .name           = "art",
+               .offset         = 0x3f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x030000,
+               .size           = 0x3c0000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data dir_615c1_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = dir_615c1_partitions,
+       .nr_parts       = ARRAY_SIZE(dir_615c1_partitions),
+#endif
+};
+
+static struct gpio_led dir_615c1_leds_gpio[] __initdata = {
+       {
+               .name           = "dir-615c1:orange:status",
+               .gpio           = DIR_615C1_GPIO_LED_ORANGE_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:blue:wps",
+               .gpio           = DIR_615C1_GPIO_LED_BLUE_WPS,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:green:wan",
+               .gpio           = DIR_615C1_GPIO_LED_GREEN_WAN,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:green:wancpu",
+               .gpio           = DIR_615C1_GPIO_LED_GREEN_WANCPU,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:green:wlan",
+               .gpio           = DIR_615C1_GPIO_LED_GREEN_WLAN,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:green:status",
+               .gpio           = DIR_615C1_GPIO_LED_GREEN_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "dir-615c1:orange:wan",
+               .gpio           = DIR_615C1_GPIO_LED_ORANGE_WAN,
+               .active_low     = 1,
+       }
+
+};
+
+static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR_615C1_GPIO_BTN_RESET,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR_615C1_GPIO_BTN_WPS,
+       }
+};
+
+#define DIR_615C1_LAN_PHYMASK  BIT(0)
+#define DIR_615C1_WAN_PHYMASK  BIT(4)
+#define DIR_615C1_MDIO_MASK    (~(DIR_615C1_LAN_PHYMASK | \
+                                  DIR_615C1_WAN_PHYMASK))
+
+static void __init dir_615c1_setup(void)
+{
+       const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR);
+       u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+       u8 mac[6];
+       u8 *wlan_mac = NULL;
+
+       if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE,
+                                       "lan_mac=", mac) == 0) {
+               ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0);
+               ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1);
+               wlan_mac = mac;
+       }
+
+       ar71xx_add_device_mdio(0, DIR_615C1_MDIO_MASK);
+
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK;
+
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_m25p80(&dir_615c1_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio),
+                                       dir_615c1_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(dir_615c1_gpio_keys),
+                                        dir_615c1_gpio_keys);
+
+       ar9xxx_add_device_wmac(eeprom, wlan_mac);
+}
+
+MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1",
+            dir_615c1_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c
new file mode 100644 (file)
index 0000000..fe672ff
--- /dev/null
@@ -0,0 +1,211 @@
+/*
+ *  D-Link DIR-825 rev. B1 board support
+ *
+ *  Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o.
+ *
+ *  based on mach-wndr3700.c
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+#include <linux/rtl8366.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ap94-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+
+#define DIR825B1_GPIO_LED_BLUE_USB             0
+#define DIR825B1_GPIO_LED_ORANGE_POWER         1
+#define DIR825B1_GPIO_LED_BLUE_POWER           2
+#define DIR825B1_GPIO_LED_BLUE_WPS             4
+#define DIR825B1_GPIO_LED_ORANGE_PLANET                6
+#define DIR825B1_GPIO_LED_BLUE_PLANET          11
+
+#define DIR825B1_GPIO_BTN_RESET                        3
+#define DIR825B1_GPIO_BTN_WPS                  8
+
+#define DIR825B1_GPIO_RTL8366_SDA              5
+#define DIR825B1_GPIO_RTL8366_SCK              7
+
+#define DIR825B1_KEYS_POLL_INTERVAL            20      /* msecs */
+#define DIR825B1_KEYS_DEBOUNCE_INTERVAL                (3 * DIR825B1_KEYS_POLL_INTERVAL)
+
+#define DIR825B1_CAL_LOCATION_0                        0x1f661000
+#define DIR825B1_CAL_LOCATION_1                        0x1f665000
+
+#define DIR825B1_MAC_LOCATION_0                        0x1f66ffa0
+#define DIR825B1_MAC_LOCATION_1                        0x1f66ffb4
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition dir825b1_partitions[] = {
+       {
+               .name           = "uboot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "config",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x050000,
+               .size           = 0x610000,
+       }, {
+               .name           = "caldata",
+               .offset         = 0x660000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "unknown",
+               .offset         = 0x670000,
+               .size           = 0x190000,
+               .mask_flags     = MTD_WRITEABLE,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data dir825b1_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = dir825b1_partitions,
+       .nr_parts       = ARRAY_SIZE(dir825b1_partitions),
+#endif
+};
+
+static struct gpio_led dir825b1_leds_gpio[] __initdata = {
+       {
+               .name           = "dir825b1:blue:usb",
+               .gpio           = DIR825B1_GPIO_LED_BLUE_USB,
+               .active_low     = 1,
+       }, {
+               .name           = "dir825b1:orange:power",
+               .gpio           = DIR825B1_GPIO_LED_ORANGE_POWER,
+               .active_low     = 1,
+       }, {
+               .name           = "dir825b1:blue:power",
+               .gpio           = DIR825B1_GPIO_LED_BLUE_POWER,
+               .active_low     = 1,
+       }, {
+               .name           = "dir825b1:blue:wps",
+               .gpio           = DIR825B1_GPIO_LED_BLUE_WPS,
+               .active_low     = 1,
+       }, {
+               .name           = "dir825b1:orange:planet",
+               .gpio           = DIR825B1_GPIO_LED_ORANGE_PLANET,
+               .active_low     = 1,
+       }, {
+               .name           = "dir825b1:blue:planet",
+               .gpio           = DIR825B1_GPIO_LED_BLUE_PLANET,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR825B1_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = DIR825B1_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = {
+       { .reg = 0x06, .val = 0x0108 },
+};
+
+static struct rtl8366_platform_data dir825b1_rtl8366s_data = {
+       .gpio_sda       = DIR825B1_GPIO_RTL8366_SDA,
+       .gpio_sck       = DIR825B1_GPIO_RTL8366_SCK,
+       .num_initvals   = ARRAY_SIZE(dir825b1_rtl8366s_initvals),
+       .initvals       = dir825b1_rtl8366s_initvals,
+};
+
+static struct platform_device dir825b1_rtl8366s_device = {
+       .name           = RTL8366S_DRIVER_NAME,
+       .id             = -1,
+       .dev = {
+               .platform_data  = &dir825b1_rtl8366s_data,
+       }
+};
+
+static void dir825b1_read_ascii_mac(u8 *dest, unsigned int src_addr)
+{
+       int ret;
+       u8 *src = (u8 *)KSEG1ADDR(src_addr);
+
+       ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+                    &dest[0], &dest[1], &dest[2],
+                    &dest[3], &dest[4], &dest[5]);
+
+       if (ret != ETH_ALEN) memset(dest, 0, ETH_ALEN);
+}
+
+static void __init dir825b1_setup(void)
+{
+       u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
+
+       dir825b1_read_ascii_mac(mac1, DIR825B1_MAC_LOCATION_0);
+       dir825b1_read_ascii_mac(mac2, DIR825B1_MAC_LOCATION_1);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 2);
+       ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.speed = SPEED_1000;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac1, 3);
+       ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth1_data.phy_mask = 0x10;
+       ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_m25p80(&dir825b1_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
+                                       dir825b1_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(dir825b1_gpio_keys),
+                                        dir825b1_gpio_keys);
+
+       ar71xx_add_device_usb();
+
+       platform_device_register(&dir825b1_rtl8366s_device);
+
+       ap94_pci_setup_wmac_led_pin(0, 5);
+       ap94_pci_setup_wmac_led_pin(1, 5);
+
+       ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), mac1,
+                     (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), mac2);
+}
+
+MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1",
+            dir825b1_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-eap7660d.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-eap7660d.c
new file mode 100644 (file)
index 0000000..d1e49ee
--- /dev/null
@@ -0,0 +1,189 @@
+/*
+ *  Senao EAP7660D board support
+ *
+ *  Copyright (C) 2010 Daniel Golle <daniel.golle@gmail.com>
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath5k_platform.h>
+#include <linux/delay.h>
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/pci.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+
+#define EAP7660D_KEYS_POLL_INTERVAL    20      /* msecs */
+#define EAP7660D_KEYS_DEBOUNCE_INTERVAL        (3 * EAP7660D_KEYS_POLL_INTERVAL)
+
+#define EAP7660D_GPIO_DS4              7
+#define EAP7660D_GPIO_DS5              2
+#define EAP7660D_GPIO_DS7              0
+#define EAP7660D_GPIO_DS8              4
+#define EAP7660D_GPIO_SW1              3
+#define EAP7660D_GPIO_SW3              8
+#define EAP7660D_PHYMASK               BIT(20)
+#define EAP7660D_BOARDCONFIG           0x1F7F0000
+#define EAP7660D_GBIC_MAC_OFFSET       0x1000
+#define EAP7660D_WMAC0_MAC_OFFSET      0x1010
+#define EAP7660D_WMAC1_MAC_OFFSET      0x1016
+#define EAP7660D_WMAC0_CALDATA_OFFSET  0x2000
+#define EAP7660D_WMAC1_CALDATA_OFFSET  0x3000
+
+static struct ath5k_platform_data eap7660d_wmac0_data;
+static struct ath5k_platform_data eap7660d_wmac1_data;
+static char eap7660d_wmac0_mac[6];
+static char eap7660d_wmac1_mac[6];
+static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
+static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
+
+#ifdef CONFIG_PCI
+static struct ar71xx_pci_irq eap7660d_pci_irqs[] __initdata = {
+       {
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV0,
+       }, {
+               .slot   = 1,
+               .pin    = 1,
+               .irq    = AR71XX_PCI_IRQ_DEV1,
+       }
+};
+
+static int eap7660d_pci_plat_dev_init(struct pci_dev *dev)
+{
+       switch (PCI_SLOT(dev->devfn)) {
+       case 17:
+               dev->dev.platform_data = &eap7660d_wmac0_data;
+               break;
+
+       case 18:
+               dev->dev.platform_data = &eap7660d_wmac1_data;
+               break;
+       }
+
+       return 0;
+}
+
+void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
+                             u8 *cal_data1, u8 *mac_addr1)
+{
+       if (cal_data0 && *cal_data0 == 0xa55a) {
+               memcpy(eap7660d_wmac0_eeprom, cal_data0,
+                       ATH5K_PLAT_EEP_MAX_WORDS);
+               eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom;
+       }
+
+       if (cal_data1 && *cal_data1 == 0xa55a) {
+               memcpy(eap7660d_wmac1_eeprom, cal_data1,
+                       ATH5K_PLAT_EEP_MAX_WORDS);
+               eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom;
+       }
+
+       if (mac_addr0) {
+               memcpy(eap7660d_wmac0_mac, mac_addr0,
+                       sizeof(eap7660d_wmac0_mac));
+               eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac;
+       }
+
+       if (mac_addr1) {
+               memcpy(eap7660d_wmac1_mac, mac_addr1,
+                       sizeof(eap7660d_wmac1_mac));
+               eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac;
+       }
+
+       ar71xx_pci_plat_dev_init = eap7660d_pci_plat_dev_init;
+       ar71xx_pci_init(ARRAY_SIZE(eap7660d_pci_irqs), eap7660d_pci_irqs);
+}
+#else
+static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
+                                    u8 *cal_data1, u8 *mac_addr1)
+{
+}
+#endif /* CONFIG_PCI */
+
+static struct gpio_led eap7660d_leds_gpio[] __initdata = {
+       {
+               .name           = "eap7660d:green:ds8",
+               .gpio           = EAP7660D_GPIO_DS8,
+               .active_low     = 0,
+       },
+       {
+               .name           = "eap7660d:green:ds5",
+               .gpio           = EAP7660D_GPIO_DS5,
+               .active_low     = 0,
+       },
+       {
+               .name           = "eap7660d:green:ds7",
+               .gpio           = EAP7660D_GPIO_DS7,
+               .active_low     = 0,
+       },
+       {
+               .name           = "eap7660d:green:ds4",
+               .gpio           = EAP7660D_GPIO_DS4,
+               .active_low     = 0,
+       }
+};
+
+static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = EAP7660D_GPIO_SW1,
+               .active_low     = 1,
+       },
+       {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = EAP7660D_GPIO_SW3,
+               .active_low     = 1,
+       }
+};
+
+static const char *eap7660d_part_probes[] = {
+       "RedBoot",
+       NULL,
+};
+
+static struct flash_platform_data eap7660d_flash_data = {
+       .part_probes    = eap7660d_part_probes,
+};
+
+static void __init eap7660d_setup(void)
+{
+       u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG);
+
+       ar71xx_add_device_mdio(0, ~EAP7660D_PHYMASK);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr,
+                       boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.phy_mask = EAP7660D_PHYMASK;
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_m25p80(&eap7660d_flash_data);
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio),
+                                       eap7660d_leds_gpio);
+       ar71xx_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(eap7660d_gpio_keys),
+                                        eap7660d_gpio_keys);
+       eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET,
+                       boardconfig + EAP7660D_WMAC0_MAC_OFFSET,
+                       boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET,
+                       boardconfig + EAP7660D_WMAC1_MAC_OFFSET);
+};
+
+MIPS_MACHINE(AR71XX_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D",
+            eap7660d_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-hornet-ub.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-hornet-ub.c
new file mode 100644 (file)
index 0000000..6173d22
--- /dev/null
@@ -0,0 +1,134 @@
+/*
+ *  ALFA NETWORKS Hornet-UB board support
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+
+#define HORNET_UB_GPIO_LED_WLAN                0
+#define HORNET_UB_GPIO_LED_USB         1
+#define HORNET_UB_GPIO_LED_LAN         13
+#define HORNET_UB_GPIO_LED_WAN         17
+#define HORNET_UB_GPIO_LED_WPS         27
+
+#define HORNET_UB_GPIO_BTN_RESET       11
+#define HORNET_UB_GPIO_BTN_WPS         12
+
+#define HORNET_UB_GPIO_USB_POWER       26
+
+#define HORNET_UB_KEYS_POLL_INTERVAL   20      /* msecs */
+#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL       (3 * HORNET_UB_KEYS_POLL_INTERVAL)
+
+#define HORNET_UB_MAC0_OFFSET          0x0000
+#define HORNET_UB_MAC1_OFFSET          0x0006
+#define HORNET_UB_CALDATA_OFFSET       0x1000
+
+static struct gpio_led hornet_ub_leds_gpio[] __initdata = {
+       {
+               .name           = "alfa:blue:lan",
+               .gpio           = HORNET_UB_GPIO_LED_LAN,
+               .active_low     = 0,
+       },
+       {
+               .name           = "alfa:blue:usb",
+               .gpio           = HORNET_UB_GPIO_LED_USB,
+               .active_low     = 0,
+       },
+       {
+               .name           = "alfa:blue:wan",
+               .gpio           = HORNET_UB_GPIO_LED_WAN,
+               .active_low     = 1,
+       },
+       {
+               .name           = "alfa:blue:wlan",
+               .gpio           = HORNET_UB_GPIO_LED_WLAN,
+               .active_low     = 0,
+       },
+       {
+               .name           = "alfa:blue:wps",
+               .gpio           = HORNET_UB_GPIO_LED_WPS,
+               .active_low     = 1,
+       },
+};
+
+static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = {
+       {
+               .desc           = "WPS button",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = HORNET_UB_GPIO_BTN_WPS,
+               .active_low     = 1,
+       },
+       {
+               .desc           = "Reset button",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = HORNET_UB_GPIO_BTN_RESET,
+               .active_low     = 0,
+       }
+};
+
+static void __init hornet_ub_gpio_setup(void)
+{
+       u32 t;
+
+       ar71xx_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+                                    AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+                                    AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+                                    AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+                                    AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+       t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+       t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
+       ar71xx_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
+
+       gpio_request(HORNET_UB_GPIO_USB_POWER, "USB power");
+       gpio_direction_output(HORNET_UB_GPIO_USB_POWER, 1);
+}
+
+static void __init hornet_ub_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+       hornet_ub_gpio_setup();
+
+       ar71xx_add_device_m25p80(NULL);
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio),
+                                       hornet_ub_leds_gpio);
+       ar71xx_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(hornet_ub_gpio_keys),
+                                        hornet_ub_gpio_keys);
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr,
+                       art + HORNET_UB_MAC0_OFFSET, 0);
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr,
+                       art + HORNET_UB_MAC1_OFFSET, 0);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_add_device_eth(1);
+       ar71xx_add_device_eth(0);
+
+       ar9xxx_add_device_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL);
+       ar71xx_add_device_usb();
+}
+
+MIPS_MACHINE(AR71XX_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORKS Hornet-UB",
+            hornet_ub_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ja76pf.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-ja76pf.c
new file mode 100644 (file)
index 0000000..9f56c3f
--- /dev/null
@@ -0,0 +1,113 @@
+/*
+ *  jjPlus JA76PF board support
+ */
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-pb42-pci.h"
+#include "dev-usb.h"
+#include "dev-leds-gpio.h"
+
+#define JA76PF_KEYS_POLL_INTERVAL      20      /* msecs */
+#define JA76PF_KEYS_DEBOUNCE_INTERVAL  (3 * JA76PF_KEYS_POLL_INTERVAL)
+
+#define JA76PF_GPIO_I2C_SCL            0
+#define JA76PF_GPIO_I2C_SDA            1
+#define JA76PF_GPIO_LED_1              5
+#define JA76PF_GPIO_LED_2              4
+#define JA76PF_GPIO_LED_3              3
+#define JA76PF_GPIO_BTN_RESET          11
+
+static struct gpio_led ja76pf_leds_gpio[] __initdata = {
+       {
+               .name           = "ja76pf:green:led1",
+               .gpio           = JA76PF_GPIO_LED_1,
+               .active_low     = 1,
+       }, {
+               .name           = "ja76pf:green:led2",
+               .gpio           = JA76PF_GPIO_LED_2,
+               .active_low     = 1,
+       }, {
+               .name           = "ja76pf:green:led3",
+               .gpio           = JA76PF_GPIO_LED_3,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = JA76PF_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }
+};
+
+static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = {
+       .sda_pin        = JA76PF_GPIO_I2C_SDA,
+       .scl_pin        = JA76PF_GPIO_I2C_SCL,
+};
+
+static struct platform_device ja76pf_i2c_gpio_device = {
+       .name           = "i2c-gpio",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &ja76pf_i2c_gpio_data,
+       }
+};
+
+static const char *ja76pf_part_probes[] = {
+       "RedBoot",
+       NULL,
+};
+
+static struct flash_platform_data ja76pf_flash_data = {
+       .part_probes    = ja76pf_part_probes,
+};
+
+#define JA76PF_WAN_PHYMASK     (1 << 4)
+#define JA76PF_LAN_PHYMASK     ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3))
+#define JA76PF_MDIO_PHYMASK    (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK)
+
+static void __init ja76pf_init(void)
+{
+       ar71xx_add_device_m25p80(&ja76pf_flash_data);
+
+       ar71xx_add_device_mdio(0, ~JA76PF_MDIO_PHYMASK);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth0_data.phy_mask = JA76PF_LAN_PHYMASK;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+       ar71xx_eth1_data.phy_mask = JA76PF_WAN_PHYMASK;
+       ar71xx_eth1_data.speed = SPEED_1000;
+       ar71xx_eth1_data.duplex = DUPLEX_FULL;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       platform_device_register(&ja76pf_i2c_gpio_device);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio),
+                                       ja76pf_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ja76pf_gpio_keys),
+                                        ja76pf_gpio_keys);
+
+       ar71xx_add_device_usb();
+       pb42_pci_init();
+}
+
+MIPS_MACHINE(AR71XX_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-jwap003.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-jwap003.c
new file mode 100644 (file)
index 0000000..3af4204
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ *  jjPlus JWAP003 board support
+ *
+ */
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_device.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-pb42-pci.h"
+#include "dev-usb.h"
+
+#define JWAP003_KEYS_POLL_INTERVAL     20      /* msecs */
+#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL)
+
+#define JWAP003_GPIO_WPS       11
+#define JWAP003_GPIO_I2C_SCL   0
+#define JWAP003_GPIO_I2C_SDA   1
+
+static struct gpio_keys_button jwap003_gpio_keys[] __initdata = {
+       {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = JWAP003_GPIO_WPS,
+               .active_low     = 1,
+       }
+};
+
+static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = {
+       .sda_pin        = JWAP003_GPIO_I2C_SDA,
+       .scl_pin        = JWAP003_GPIO_I2C_SCL,
+};
+
+static struct platform_device jwap003_i2c_gpio_device = {
+       .name           = "i2c-gpio",
+       .id             = 0,
+       .dev = {
+               .platform_data  = &jwap003_i2c_gpio_data,
+       }
+};
+
+static const char *jwap003_part_probes[] = {
+       "RedBoot",
+       NULL,
+};
+
+static struct flash_platform_data jwap003_flash_data = {
+       .part_probes    = jwap003_part_probes,
+};
+
+#define JWAP003_WAN_PHYMASK    BIT(0)
+#define JWAP003_LAN_PHYMASK    BIT(4)
+
+static void __init jwap003_init(void)
+{
+       ar71xx_add_device_m25p80(&jwap003_flash_data);
+
+       ar71xx_add_device_mdio(0, 0x0);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth0_data.phy_mask = JWAP003_WAN_PHYMASK;
+       ar71xx_eth0_data.speed = SPEED_100;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.has_ar8216 = 1;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth1_data.phy_mask = JWAP003_LAN_PHYMASK;
+       ar71xx_eth1_data.speed = SPEED_100;
+       ar71xx_eth1_data.duplex = DUPLEX_FULL;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       platform_device_register(&jwap003_i2c_gpio_device);
+
+       ar71xx_add_device_usb();
+
+       ar71xx_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(jwap003_gpio_keys),
+                                        jwap003_gpio_keys);
+
+       pb42_pci_init();
+}
+
+MIPS_MACHINE(AR71XX_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c
new file mode 100644 (file)
index 0000000..dbb408c
--- /dev/null
@@ -0,0 +1,166 @@
+/*
+ *  Planex MZK-W04NU board support
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+
+#define MZK_W04NU_GPIO_LED_USB         0
+#define MZK_W04NU_GPIO_LED_STATUS      1
+#define MZK_W04NU_GPIO_LED_WPS         3
+#define MZK_W04NU_GPIO_LED_WLAN                6
+#define MZK_W04NU_GPIO_LED_AP          15
+#define MZK_W04NU_GPIO_LED_ROUTER      16
+
+#define MZK_W04NU_GPIO_BTN_APROUTER    5
+#define MZK_W04NU_GPIO_BTN_WPS         12
+#define MZK_W04NU_GPIO_BTN_RESET       21
+
+#define MZK_W04NU_KEYS_POLL_INTERVAL   20      /* msecs */
+#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition mzk_w04nu_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x050000,
+               .size           = 0x160000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x1b0000,
+               .size           = 0x630000,
+       }, {
+               .name           = "art",
+               .offset         = 0x7e0000,
+               .size           = 0x020000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x050000,
+               .size           = 0x790000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data mzk_w04nu_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = mzk_w04nu_partitions,
+       .nr_parts       = ARRAY_SIZE(mzk_w04nu_partitions),
+#endif
+};
+
+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = {
+       {
+               .name           = "planex:green:status",
+               .gpio           = MZK_W04NU_GPIO_LED_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:blue:wps",
+               .gpio           = MZK_W04NU_GPIO_LED_WPS,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:wlan",
+               .gpio           = MZK_W04NU_GPIO_LED_WLAN,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:usb",
+               .gpio           = MZK_W04NU_GPIO_LED_USB,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:ap",
+               .gpio           = MZK_W04NU_GPIO_LED_AP,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:router",
+               .gpio           = MZK_W04NU_GPIO_LED_ROUTER,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W04NU_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W04NU_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }, {
+               .desc           = "aprouter",
+               .type           = EV_KEY,
+               .code           = BTN_2,
+               .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W04NU_GPIO_BTN_APROUTER,
+               .active_low     = 0,
+       }
+};
+
+#define MZK_W04NU_WAN_PHYMASK  BIT(4)
+#define MZK_W04NU_MDIO_MASK    (~MZK_W04NU_WAN_PHYMASK)
+
+static void __init mzk_w04nu_setup(void)
+{
+       u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+       ar71xx_add_device_mdio(0, MZK_W04NU_MDIO_MASK);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth0_data.speed = SPEED_100;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.has_ar8216 = 1;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_m25p80(&mzk_w04nu_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio),
+                                       mzk_w04nu_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(mzk_w04nu_gpio_keys),
+                                        mzk_w04nu_gpio_keys);
+       ar71xx_add_device_usb();
+
+       ar9xxx_add_device_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU",
+            mzk_w04nu_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c
new file mode 100644 (file)
index 0000000..98b3f00
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ *  Planex MZK-W300NH board support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+
+#define MZK_W300NH_GPIO_LED_STATUS     1
+#define MZK_W300NH_GPIO_LED_WPS                3
+#define MZK_W300NH_GPIO_LED_WLAN       6
+#define MZK_W300NH_GPIO_LED_AP         15
+#define MZK_W300NH_GPIO_LED_ROUTER     16
+
+#define MZK_W300NH_GPIO_BTN_APROUTER   5
+#define MZK_W300NH_GPIO_BTN_WPS                12
+#define MZK_W300NH_GPIO_BTN_RESET      21
+
+#define MZK_W300NH_KEYS_POLL_INTERVAL  20      /* msecs */
+#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition mzk_w300nh_partitions[] = {
+       {
+               .name           = "u-boot",
+               .offset         = 0,
+               .size           = 0x040000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "u-boot-env",
+               .offset         = 0x040000,
+               .size           = 0x010000,
+       }, {
+               .name           = "kernel",
+               .offset         = 0x050000,
+               .size           = 0x160000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x1b0000,
+               .size           = 0x630000,
+       }, {
+               .name           = "art",
+               .offset         = 0x7e0000,
+               .size           = 0x020000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x050000,
+               .size           = 0x790000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data mzk_w300nh_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = mzk_w300nh_partitions,
+       .nr_parts       = ARRAY_SIZE(mzk_w300nh_partitions),
+#endif
+};
+
+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = {
+       {
+               .name           = "planex:green:status",
+               .gpio           = MZK_W300NH_GPIO_LED_STATUS,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:blue:wps",
+               .gpio           = MZK_W300NH_GPIO_LED_WPS,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:wlan",
+               .gpio           = MZK_W300NH_GPIO_LED_WLAN,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:ap",
+               .gpio           = MZK_W300NH_GPIO_LED_AP,
+               .active_low     = 1,
+       }, {
+               .name           = "planex:green:router",
+               .gpio           = MZK_W300NH_GPIO_LED_ROUTER,
+               .active_low     = 1,
+       }
+};
+
+static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W300NH_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W300NH_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }, {
+               .desc           = "aprouter",
+               .type           = EV_KEY,
+               .code           = BTN_2,
+               .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = MZK_W300NH_GPIO_BTN_APROUTER,
+               .active_low     = 0,
+       }
+};
+
+#define MZK_W300NH_WAN_PHYMASK BIT(4)
+#define MZK_W300NH_MDIO_MASK   (~MZK_W300NH_WAN_PHYMASK)
+
+static void __init mzk_w300nh_setup(void)
+{
+       u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+       ar71xx_add_device_mdio(0, MZK_W300NH_MDIO_MASK);
+
+       ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0);
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth0_data.speed = SPEED_100;
+       ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.has_ar8216 = 1;
+
+       ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1);
+       ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+       ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK;
+
+       ar71xx_add_device_eth(0);
+       ar71xx_add_device_eth(1);
+
+       ar71xx_add_device_m25p80(&mzk_w300nh_flash_data);
+
+       ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio),
+                                       mzk_w300nh_leds_gpio);
+
+       ar71xx_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(mzk_w300nh_gpio_keys),
+                                        mzk_w300nh_gpio_keys);
+       ar9xxx_add_device_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH",
+            mzk_w300nh_setup);
diff --git a/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-nbg460n.c b/target/linux/ar71xx/files-2.6.39/arch/mips/ar71xx/mach-nbg460n.c
new file mode 100644 (file)
index 0000000..e1d9592
--- /dev/null
@@ -0,0 +1,225 @@
+/*
+ *  Zyxel NBG 460N/550N/550NH board support
+ *
+ *  Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
+ *
+ *  based on mach-tl-wr1043nd.c
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+#include <linux/rtl8366.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+#include "machtype.h"
+#include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-ar9xxx-wmac.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+
+/* LEDs */
+#define NBG460N_GPIO_LED_WPS           3
+#define NBG460N_GPIO_LED_WAN           6
+#define NBG460N_GPIO_LED_POWER         14
+#define NBG460N_GPIO_LED_WLAN          15
+
+/* Buttons */
+#define NBG460N_GPIO_BTN_WPS           12
+#define NBG460N_GPIO_BTN_RESET         21
+
+#define NBG460N_KEYS_POLL_INTERVAL     20      /* msecs */
+#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL)
+
+/* RTC chip PCF8563 I2C interface */
+#define NBG460N_GPIO_PCF8563_SDA       8
+#define NBG460N_GPIO_PCF8563_SCK       7
+
+/* Switch configuration I2C interface */
+#define NBG460N_GPIO_RTL8366_SDA       16
+#define NBG460N_GPIO_RTL8366_SCK       18
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition nbg460n_partitions[] = {
+       {
+               .name           = "Bootbase",
+               .offset         = 0,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "U-Boot Config",
+               .offset         = 0x010000,
+               .size           = 0x030000,
+       }, {
+               .name           = "U-Boot",
+               .offset         = 0x040000,
+               .size           = 0x030000,
+       }, {
+               .name           = "linux",
+               .offset         = 0x070000,
+               .size           = 0x0e0000,
+       }, {
+               .name           = "rootfs",
+               .offset         = 0x150000,
+               .size           = 0x2a0000,
+       }, {
+               .name           = "CalibData",
+               .offset         = 0x3f0000,
+               .size           = 0x010000,
+               .mask_flags     = MTD_WRITEABLE,
+       }, {
+               .name           = "firmware",
+               .offset         = 0x070000,
+               .size           = 0x380000,
+       }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct flash_platform_data nbg460n_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+       .parts          = nbg460n_partitions,
+       .nr_parts       = ARRAY_SIZE(nbg460n_partitions),
+#endif
+};
+
+static struct gpio_led nbg460n_leds_gpio[] __initdata = {
+       {
+               .name           = "nbg460n:green:power",
+               .gpio           = NBG460N_GPIO_LED_POWER,
+               .active_low     = 0,
+               .default_trigger = "default-on",
+       }, {
+               .name           = "nbg460n:green:wps",
+               .gpio           = NBG460N_GPIO_LED_WPS,
+               .active_low     = 0,
+       }, {
+               .name           = "nbg460n:green:wlan",
+               .gpio           = NBG460N_GPIO_LED_WLAN,
+               .active_low     = 0,
+       }, {
+               /* Not really for controlling the LED,
+                  when set low the LED blinks uncontrollable  */
+               .name           = "nbg460n:green:wan",
+               .gpio           = NBG460N_GPIO_LED_WAN,
+               .active_low     = 0,
+       }
+};
+
+static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = NBG460N_GPIO_BTN_RESET,
+               .active_low     = 1,
+       }, {
+               .desc           = "wps",
+               .type           = EV_KEY,
+               .code           = KEY_WPS_BUTTON,
+               .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = NBG460N_GPIO_BTN_WPS,
+               .active_low     = 1,
+       }
+};
+
+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = {
+       .sda_pin        = NBG460N_GPIO_PCF8563_SDA,
+       .scl_pin        = NBG460N_GPIO_PCF8563_SCK,
+       .udelay         = 10,
+};
+
+static struct platform_device nbg460n_i2c_device = {
+       .name           = "i2c-gpio",
+       .id             = -1,
+       .num_resources  = 0,
+       .resource       = NULL,
+       .dev            = {
+               .platform_data  = &nbg460n_i2c_device_platdata,
+       },
+};
+
+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       },
+};
+
+static void __devinit nbg460n_i2c_init(void)
+{
+       /* The gpio interface */
+       platform_device_register(&nbg460n_i2c_device);
+       /* I2C devices */
+       i2c_register_board_info(0, nbg460n_i2c_devs,
+                               ARRAY_SIZE(nbg460n_i2c_devs));
+}
+
+
+static struct rtl8366_platform_data nbg460n_rtl8366s_data = {
+       .gpio_sda       = NBG460N_GPIO_RTL8366_SDA,
+       .gpio_sck       = NBG460N_GPIO_RTL8366_SCK,
+};
+
+static struct platform_device nbg460n_rtl8366s_device = {
+       .name           = RTL8366S_DRIVER_NAME,
+       .id             = -1,
+       .dev = {
+               .platform_data  = &nbg460n_rtl8366s_data,
+       }
+};
+
+static void __init nbg460n_setup(void)
+{
+       /* end of bootloader sector c