[ifxmips] adds dsl support, thank you infineon/lantiq
authorJohn Crispin <john@openwrt.org>
Sun, 1 Nov 2009 18:52:35 +0000 (18:52 +0000)
committerJohn Crispin <john@openwrt.org>
Sun, 1 Nov 2009 18:52:35 +0000 (18:52 +0000)
SVN-Revision: 18259

36 files changed:
package/ifxmips-atm/Makefile [deleted file]
package/ifxmips-atm/src/Makefile [deleted file]
package/ifxmips-atm/src/common.h [deleted file]
package/ifxmips-atm/src/core.c [deleted file]
package/ifxmips-atm/src/ifx_ppe_fw.h [deleted file]
package/ifxmips-atm/src/irq.c [deleted file]
package/ifxmips-atm/src/ppe.c [deleted file]
package/ifxmips-atm/src/proc.c [deleted file]
package/ifxmips-atm/src/proc.h [deleted file]
package/ifxmips-atm/src/skb.c [deleted file]
package/ifxmips-dsl-api/Config.in [new file with mode: 0644]
package/ifxmips-dsl-api/Makefile [new file with mode: 0644]
package/ifxmips-dsl-api/patches/100-dsl_compat.patch [new file with mode: 0644]
package/ifxmips-dsl-api/patches/200-mei_compat.patch [new file with mode: 0644]
package/ifxmips-dsl-api/patches/300-atm_compat.patch [new file with mode: 0644]
package/ifxmips-dsl-api/src/Makefile [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifx_atm.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_core.c [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_core.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_danube.c [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_mei.c [new file with mode: 0644]
package/ifxmips-dsl-api/src/ifxmips_mei_interface.h [new file with mode: 0644]
package/ifxmips-dsl-control/Makefile [new file with mode: 0644]
package/ifxmips-dsl-control/files/ifx_cpe_control_init.sh [new file with mode: 0644]
target/linux/generic-2.6/patches-2.6.30/251-atm.patch [new file with mode: 0644]
target/linux/ifxmips/Makefile
target/linux/ifxmips/base-files/etc/config/network
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h
target/linux/ifxmips/patches-2.6.30/201-atm.patch [deleted file]
target/linux/ifxmips/patches-2.6.30/400-atm_hack.patch [new file with mode: 0644]

diff --git a/package/ifxmips-atm/Makefile b/package/ifxmips-atm/Makefile
deleted file mode 100644 (file)
index 68b77b6..0000000
+++ /dev/null
@@ -1,49 +0,0 @@
-# Copyright (C) 2009 OpenWrt.org
-# All rights reserved.
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# blogic@openwrt.org
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=ifxmips-atm
-PKG_RELEASE:=1
-
-include $(INCLUDE_DIR)/package.mk
-
-define KernelPackage/ifxmips-atm
-  SUBMENU:=Network Devices
-  DEPENDS:=@BROKEN @TARGET_ifxmips +kmod-atm
-  TITLE:=ifxmips atm driver
-  FILES:=$(PKG_BUILD_DIR)/ifx-atm.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,50,ifx-atm)
-endef
-
-define Kernel/Package/ifxmips-atm/description
-       This package provides the atm driver needed to make dsl work on ifxmips based boards
-endef
-
-define Build/Prepare
-       mkdir -p $(PKG_BUILD_DIR)
-       $(CP) ./src/* $(PKG_BUILD_DIR)/
-endef
-
-define Build/Compile
-       $(MAKE) -C "$(LINUX_DIR)" \
-       CROSS_COMPILE="$(TARGET_CROSS)" \
-       ARCH="$(LINUX_KARCH)" \
-       SUBDIRS="$(PKG_BUILD_DIR)" \
-       modules
-endef
-
-define KernelPackage/ifxmips-atm/install
-       $(INSTALL_DIR) $(1)/lib/modules/$(LINUX_VERSION) 
-       $(CP) $(PKG_BUILD_DIR)/ifx-atm.ko $(1)/lib/modules/$(LINUX_VERSION)
-endef
-
-$(eval $(call KernelPackage,ifxmips-atm))
-
diff --git a/package/ifxmips-atm/src/Makefile b/package/ifxmips-atm/src/Makefile
deleted file mode 100644 (file)
index 23e0ea0..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-m += ifx-atm.o
-ifx-atm-objs := skb.o irq.o proc.o core.o ppe.o
-
-EXTRA_CFLAGS += -DENABLE_RX_QOS=1
diff --git a/package/ifxmips-atm/src/common.h b/package/ifxmips-atm/src/common.h
deleted file mode 100644 (file)
index aad6a98..0000000
+++ /dev/null
@@ -1,896 +0,0 @@
-#include <linux/atmdev.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <linux/irq.h>
-#include <linux/sem.h>
-#include <linux/coda.h>
-
-#define RX_DMA_CH_CBR                   0
-#define RX_DMA_CH_VBR_RT                1
-#define RX_DMA_CH_VBR_NRT               2
-#define RX_DMA_CH_AVR                   3
-#define RX_DMA_CH_UBR                   4
-#define RX_DMA_CH_OAM                   5
-#define RX_DMA_CH_TOTAL                 6
-
-#define WRX_DMA_CHANNEL_INTERRUPT_MODE  0x00
-#define WRX_DMA_CHANNEL_POLLING_MODE    0x01
-//#define WRX_DMA_CHANNEL_COUNTER_MODE    0x02
-#define WRX_DMA_CHANNEL_COUNTER_MODE    WRX_DMA_CHANNEL_INTERRUPT_MODE
-#define WRX_DMA_BUF_LEN_PER_DESCRIPTOR  0x00
-#define WRX_DMA_BUF_LEN_PER_CHANNEL     0x01
-
-#define ATM_VBR_RT     6
-#define ATM_VBR_NRT    ATM_VBR
-#define ATM_UBR_PLUS   7
-
-#define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
-
-#define GET_ATM_PRIV(dev)       ((Atm_Priv *)dev->priv)
-
-#define CDM_CFG                         PPE_REG_ADDR(0x0100)
-
-#define CDM_CFG_RAM1                    GET_BITS(*CDM_CFG, 3, 2)
-#define CDM_CFG_RAM0                    (*CDM_CFG & (1 << 1))
-
-#define CDM_CFG_RAM1_SET(value)         SET_BITS(0, 3, 2, value)
-#define CDM_CFG_RAM0_SET(value)         ((value) ? (1 << 1) : 0)
-
-/*
- *  EMA Registers
- */
-#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
-#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
-#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
-#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
-#define EMA_ISR                         PPE_REG_ADDR(0x0A04)
-#define EMA_IER                         PPE_REG_ADDR(0x0A05)
-#define EMA_CFG                         PPE_REG_ADDR(0x0A06)
-#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
-
-
-/*
- *  QSB RAM Access Register
- */
-#define QSB_RAMAC                       QSB_CONF_REG(0x000D)
-
-#define QSB_RAMAC_RW                    (*QSB_RAMAC & (1 << 31))
-#define QSB_RAMAC_TSEL                  GET_BITS(*QSB_RAMAC, 27, 24)
-#define QSB_RAMAC_LH                    (*QSB_RAMAC & (1 << 16))
-#define QSB_RAMAC_TESEL                 GET_BITS(*QSB_RAMAC, 9, 0)
-
-#define QSB_RAMAC_RW_SET(value)         ((value) ? (1 << 31) : 0)
-#define QSB_RAMAC_TSEL_SET(value)       SET_BITS(0, 27, 24, value)
-#define QSB_RAMAC_LH_SET(value)         ((value) ? (1 << 16) : 0)
-#define QSB_RAMAC_TESEL_SET(value)      SET_BITS(0, 9, 0, value)
-
-/*  QSB */
-#define QSB_RAMAC_RW_READ               0
-#define QSB_RAMAC_RW_WRITE              1
-
-#define QSB_RAMAC_TSEL_QPT              0x01
-#define QSB_RAMAC_TSEL_SCT              0x02
-#define QSB_RAMAC_TSEL_SPT              0x03
-#define QSB_RAMAC_TSEL_VBR              0x08
-
-#define QSB_RAMAC_LH_LOW                0
-#define QSB_RAMAC_LH_HIGH               1
-
-#define QSB_QPT_SET_MASK                0x0
-#define QSB_QVPT_SET_MASK               0x0
-#define QSB_SET_SCT_MASK                0x0
-#define QSB_SET_SPT_MASK                0x0
-#define QSB_SET_SPT_SBVALID_MASK        0x7FFFFFFF
-
-#define QSB_SPT_SBV_VALID               (1 << 31)
-#define QSB_SPT_PN_SET(value)           (((value) & 0x01) ? (1 << 16) : 0)
-#define QSB_SPT_INTRATE_SET(value)      SET_BITS(0, 13, 0, value)
-
-/*
- *  QSB Internal Cell Delay Variation Register
- */
-#define QSB_ICDV                        QSB_CONF_REG(0x0007)
-
-#define QSB_ICDV_TAU                    GET_BITS(*QSB_ICDV, 5, 0)
-
-#define QSB_ICDV_TAU_SET(value)         SET_BITS(0, 5, 0, value)
-
-/*
- *  QSB Scheduler Burst Limit Register
- */
-#define QSB_SBL                         QSB_CONF_REG(0x0009)
-
-#define QSB_SBL_SBL                     GET_BITS(*QSB_SBL, 3, 0)
-
-#define QSB_SBL_SBL_SET(value)          SET_BITS(0, 3, 0, value)
-
-/*
- *  QSB Configuration Register
- */
-#define QSB_CFG                         QSB_CONF_REG(0x000A)
-
-#define QSB_CFG_TSTEPC                  GET_BITS(*QSB_CFG, 1, 0)
-
-#define QSB_CFG_TSTEPC_SET(value)       SET_BITS(0, 1, 0, value)
-
-/*
- *  QSB RAM Transfer Table Register
- */
-#define QSB_RTM                         QSB_CONF_REG(0x000B)
-
-#define QSB_RTM_DM                      (*QSB_RTM)
-
-#define QSB_RTM_DM_SET(value)           ((value) & 0xFFFFFFFF)
-
-/*
- *  QSB RAM Transfer Data Register
- */
-#define QSB_RTD                         QSB_CONF_REG(0x000C)
-
-#define QSB_RTD_TTV                     (*QSB_RTD)
-
-#define QSB_RTD_TTV_SET(value)          ((value) & 0xFFFFFFFF)
-
-/*
- *  PP32 Debug Control Register
- */
-#define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0x0000)
-
-#define DBG_CTRL_START_SET(value)       ((value) ? (1 << 0) : 0)
-#define DBG_CTRL_STOP_SET(value)        ((value) ? (1 << 1) : 0)
-#define DBG_CTRL_STEP_SET(value)        ((value) ? (1 << 2) : 0)
-
-#define SB_RAM0_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8000) << 2)))
-#define UPDATE_VCC_STAT(conn, item, num)    do { ppe_dev.connection[conn].item += num; } while (0)
-/*
- *  EMA Settings
- */
-#define EMA_CMD_BUF_LEN      0x0040
-#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
-#define EMA_DATA_BUF_LEN     0x0100
-#define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
-#define EMA_WRITE_BURST      0x2
-#define EMA_READ_BURST       0x2
-
-
-#define CELL_SIZE                       ATM_AAL0_SDU
-#define IDLE_CYCLE_NUMBER               30000
-
-#define MBOX_IGU1_ISR                   PPE_REG_ADDR(0x0206)
-#define MBOX_IGU3_ISRS                  PPE_REG_ADDR(0x0214)
-#define MBOX_IGU1_ISRC                  PPE_REG_ADDR(0x0205)
-#define MBOX_IGU3_ISR                   PPE_REG_ADDR(0x0216)
-#define MBOX_IGU3_ISRS_SET(n)           (1 << (n))
-#define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))
-/*
- *  *  Mailbox IGU1 Registers
- *   */
-#define MBOX_IGU1_ISRS                  PPE_REG_ADDR(0x0204)
-#define MBOX_IGU1_IER                   PPE_REG_ADDR(0x0207)
-
-#define MBOX_IGU1_ISRS_SET(n)           (1 << (n))
-#define MBOX_IGU1_ISRC_CLEAR(n)         (1 << (n))
-#define MBOX_IGU1_ISR_ISR(n)            (*MBOX_IGU1_ISR & (1 << (n)))
-#define MBOX_IGU1_IER_EN(n)             (*MBOX_IGU1_IER & (1 << (n)))
-#define MBOX_IGU1_IER_EN_SET(n)         (1 << (n))
-
-/*
- *  *  Mailbox IGU3 Registers
- *   */
-#define MBOX_IGU3_ISRC                  PPE_REG_ADDR(0x0215)
-#define MBOX_IGU3_IER                   PPE_REG_ADDR(0x0217)
-
-#define MBOX_IGU3_ISRS_SET(n)           (1 << (n))
-#define MBOX_IGU3_ISRC_CLEAR(n)         (1 << (n))
-#define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))
-#define MBOX_IGU3_IER_EN(n)             (*MBOX_IGU3_IER & (1 << (n)))
-#define MBOX_IGU3_IER_EN_SET(n)         (1 << (n))
-
-
-// RX Frame Definitions
-#define MAX_RX_PACKET_ALIGN_BYTES       3
-#define MAX_RX_PACKET_PADDING_BYTES     3
-#define RX_INBAND_TRAILER_LENGTH        8
-#define MAX_RX_FRAME_EXTRA_BYTES        (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
-
-// TX Frame Definitions
-#define MAX_TX_HEADER_ALIGN_BYTES       12
-#define MAX_TX_PACKET_ALIGN_BYTES       3
-#define MAX_TX_PACKET_PADDING_BYTES     3
-#define TX_INBAND_HEADER_LENGTH         8
-#define MAX_TX_FRAME_EXTRA_BYTES        (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
-
-
-// DWORD-Length of Memory Blocks
-#define PP32_DEBUG_REG_DWLEN            0x0030
-#define PPM_INT_REG_DWLEN               0x0010
-#define PP32_INTERNAL_RES_DWLEN         0x00C0
-#define PPE_CLOCK_CONTROL_DWLEN         0x0F00
-#define CDM_CODE_MEMORY_RAM0_DWLEN      0x1000
-#define CDM_CODE_MEMORY_RAM1_DWLEN      0x0800
-#define PPE_REG_DWLEN                   0x1000
-#define PP32_DATA_MEMORY_RAM1_DWLEN     0x0800
-#define PPM_INT_UNIT_DWLEN              0x0100
-#define PPM_TIMER0_DWLEN                0x0100
-#define PPM_TASK_IND_REG_DWLEN          0x0100
-#define PPS_BRK_DWLEN                   0x0100
-#define PPM_TIMER1_DWLEN                0x0100
-#define SB_RAM0_DWLEN                   0x0400
-#define SB_RAM1_DWLEN                   0x0800
-#define SB_RAM2_DWLEN                   0x0A00
-#define SB_RAM3_DWLEN                   0x0400
-#define QSB_CONF_REG_DWLEN              0x0100
-/*
- *  QSB Queue Scheduling and Shaping Definitions
- */
-#define QSB_WFQ_NONUBR_MAX              0x3f00
-#define QSB_WFQ_UBR_BYPASS              0x3fff
-#define QSB_TP_TS_MAX                   65472
-#define QSB_TAUS_MAX                    64512
-#define QSB_GCR_MIN                     18
-
-
-
-// OAM Definitions
-#define OAM_RX_QUEUE_NUMBER             1
-#define OAM_TX_QUEUE_NUMBER_PER_PORT    0
-#define OAM_RX_DMA_CHANNEL_NUMBER       OAM_RX_QUEUE_NUMBER
-#define OAM_HTU_ENTRY_NUMBER            3
-#define OAM_F4_SEG_HTU_ENTRY            0
-#define OAM_F4_TOT_HTU_ENTRY            1
-#define OAM_F5_HTU_ENTRY                2
-#define OAM_F4_CELL_ID                  0
-#define OAM_F5_CELL_ID                  15
-
-// ATM Port, QSB Queue, DMA RX/TX Channel Parameters
-#define ATM_PORT_NUMBER                 2
-#define MAX_QUEUE_NUMBER                16
-#define QSB_QUEUE_NUMBER_BASE           1
-#define MAX_QUEUE_NUMBER_PER_PORT       (MAX_QUEUE_NUMBER - QSB_QUEUE_NUMBER_BASE)
-#define MAX_CONNECTION_NUMBER           MAX_QUEUE_NUMBER
-#define MAX_RX_DMA_CHANNEL_NUMBER       8
-#define MAX_TX_DMA_CHANNEL_NUMBER       16
-#define DMA_ALIGNMENT                   4
-
-#define DEFAULT_RX_HUNT_BITTH           4
-
-/*
- *  FPI Configuration Bus Register and Memory Address Mapping
- */
-#define DANUBE_PPE                      (KSEG1 + 0x1E180000)
-#define PP32_DEBUG_REG_ADDR(x)          ((volatile u32*)(DANUBE_PPE + (((x) + 0x0000) << 2)))
-#define PPM_INT_REG_ADDR(x)             ((volatile u32*)(DANUBE_PPE + (((x) + 0x0030) << 2)))
-#define PP32_INTERNAL_RES_ADDR(x)       ((volatile u32*)(DANUBE_PPE + (((x) + 0x0040) << 2)))
-#define PPE_CLOCK_CONTROL_ADDR(x)       ((volatile u32*)(DANUBE_PPE + (((x) + 0x0100) << 2)))
-#define CDM_CODE_MEMORY_RAM0_ADDR(x)    ((volatile u32*)(DANUBE_PPE + (((x) + 0x1000) << 2)))
-#define CDM_CODE_MEMORY_RAM1_ADDR(x)    ((volatile u32*)(DANUBE_PPE + (((x) + 0x2000) << 2)))
-#define PPE_REG_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x4000) << 2)))
-#define PP32_DATA_MEMORY_RAM1_ADDR(x)   ((volatile u32*)(DANUBE_PPE + (((x) + 0x5000) << 2)))
-#define PPM_INT_UNIT_ADDR(x)            ((volatile u32*)(DANUBE_PPE + (((x) + 0x6000) << 2)))
-#define PPM_TIMER0_ADDR(x)              ((volatile u32*)(DANUBE_PPE + (((x) + 0x6100) << 2)))
-#define PPM_TASK_IND_REG_ADDR(x)        ((volatile u32*)(DANUBE_PPE + (((x) + 0x6200) << 2)))
-#define PPS_BRK_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x6300) << 2)))
-#define PPM_TIMER1_ADDR(x)              ((volatile u32*)(DANUBE_PPE + (((x) + 0x6400) << 2)))
-#define SB_RAM0_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8000) << 2)))
-#define SB_RAM1_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8400) << 2)))
-#define SB_RAM2_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x8C00) << 2)))
-#define SB_RAM3_ADDR(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0x9600) << 2)))
-#define QSB_CONF_REG(x)                 ((volatile u32*)(DANUBE_PPE + (((x) + 0xC000) << 2)))
-
-/*
- *  Host-PPE Communication Data Address Mapping
- */
-#define CFG_WRX_HTUTS                   PPM_INT_UNIT_ADDR(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */
-#define CFG_WRX_QNUM                    PPM_INT_UNIT_ADDR(0x2401)   /*  WAN RX Queue Number */
-#define CFG_WRX_DCHNUM                  PPM_INT_UNIT_ADDR(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */
-#define CFG_WTX_DCHNUM                  PPM_INT_UNIT_ADDR(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */
-#define CFG_WRDES_DELAY                 PPM_INT_UNIT_ADDR(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */
-#define WRX_DMACH_ON                    PPM_INT_UNIT_ADDR(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */
-#define WTX_DMACH_ON                    PPM_INT_UNIT_ADDR(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */
-#define WRX_HUNT_BITTH                  PPM_INT_UNIT_ADDR(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */
-#define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)PPM_INT_UNIT_ADDR(0x2500 + (i) * 20))
-#define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)PPM_INT_UNIT_ADDR(0x2640 + (i) * 7))
-#define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)PPM_INT_UNIT_ADDR(0x2440 + (i)))
-#define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)PPM_INT_UNIT_ADDR(0x2710 + (i) * 27))
-#define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)PPM_INT_UNIT_ADDR(0x2711 + (i) * 27))
-#define WAN_MIB_TABLE                   ((struct wan_mib_table*)PPM_INT_UNIT_ADDR(0x2410))
-#define HTU_ENTRY(i)                    ((struct htu_entry*)PPM_INT_UNIT_ADDR(0x2000 + (i)))
-#define HTU_MASK(i)                     ((struct htu_mask*)PPM_INT_UNIT_ADDR(0x2020 + (i)))
-#define HTU_RESULT(i)                   ((struct htu_result*)PPM_INT_UNIT_ADDR(0x2040 + (i)))
-
-// DREG Idle Counters
-#define DREG_AT_CELL0                   PPE_REG_ADDR(0x0D24)
-#define DREG_AT_CELL1                   PPE_REG_ADDR(0x0D25)
-#define DREG_AT_IDLE_CNT0               PPE_REG_ADDR(0x0D26)
-#define DREG_AT_IDLE_CNT1               PPE_REG_ADDR(0x0D27)
-#define DREG_AR_CELL0                   PPE_REG_ADDR(0x0D68)
-#define DREG_AR_CELL1                   PPE_REG_ADDR(0x0D69)
-#define DREG_AR_IDLE_CNT0               PPE_REG_ADDR(0x0D6A)
-#define DREG_AR_IDLE_CNT1               PPE_REG_ADDR(0x0D6B)
-#define DREG_AR_AIIDLE_CNT0             PPE_REG_ADDR(0x0D6C)
-#define DREG_AR_AIIDLE_CNT1             PPE_REG_ADDR(0x0D6D)
-#define DREG_AR_BE_CNT0                 PPE_REG_ADDR(0x0D6E)
-#define DREG_AR_BE_CNT1                 PPE_REG_ADDR(0x0D6F)
-
-
-/*
- *  64-bit Data Type
- */
-typedef struct {
-    unsigned int    h: 32;
-    unsigned int    l: 32;
-} ppe_u64_t;
-
-/*
- *  PPE ATM Cell Header
- */
-#if defined(__BIG_ENDIAN)
-    struct uni_cell_header {
-        unsigned int        gfc     :4;
-        unsigned int        vpi     :8;
-        unsigned int        vci     :16;
-        unsigned int        pti     :3;
-        unsigned int        clp     :1;
-    };
-#else
-    struct uni_cell_header {
-        unsigned int        clp     :1;
-        unsigned int        pti     :3;
-        unsigned int        vci     :16;
-        unsigned int        vpi     :8;
-        unsigned int        gfc     :4;
-    };
-#endif  //  defined(__BIG_ENDIAN)
-
-/*
- *  Inband Header and Trailer
- */
-#if defined(__BIG_ENDIAN)
-    struct rx_inband_trailer {
-        /*  0 - 3h  */
-        unsigned int        uu      :8;
-        unsigned int        cpi     :8;
-        unsigned int        stw_res1:4;
-        unsigned int        stw_clp :1;
-        unsigned int        stw_ec  :1;
-        unsigned int        stw_uu  :1;
-        unsigned int        stw_cpi :1;
-        unsigned int        stw_ovz :1;
-        unsigned int        stw_mfl :1;
-        unsigned int        stw_usz :1;
-        unsigned int        stw_crc :1;
-        unsigned int        stw_il  :1;
-        unsigned int        stw_ra  :1;
-        unsigned int        stw_res2:2;
-        /*  4 - 7h  */
-        unsigned int        gfc     :4;
-        unsigned int        vpi     :8;
-        unsigned int        vci     :16;
-        unsigned int        pti     :3;
-        unsigned int        clp     :1;
-    };
-
-    struct tx_inband_header {
-        /*  0 - 3h  */
-        unsigned int        gfc     :4;
-        unsigned int        vpi     :8;
-        unsigned int        vci     :16;
-        unsigned int        pti     :3;
-        unsigned int        clp     :1;
-        /*  4 - 7h  */
-        unsigned int        uu      :8;
-        unsigned int        cpi     :8;
-        unsigned int        pad     :8;
-        unsigned int        res1    :8;
-    };
-#else
-    struct rx_inband_trailer {
-        /*  0 - 3h  */
-        unsigned int        stw_res2:2;
-        unsigned int        stw_ra  :1;
-        unsigned int        stw_il  :1;
-        unsigned int        stw_crc :1;
-        unsigned int        stw_usz :1;
-        unsigned int        stw_mfl :1;
-        unsigned int        stw_ovz :1;
-        unsigned int        stw_cpi :1;
-        unsigned int        stw_uu  :1;
-        unsigned int        stw_ec  :1;
-        unsigned int        stw_clp :1;
-        unsigned int        stw_res1:4;
-        unsigned int        cpi     :8;
-        unsigned int        uu      :8;
-        /*  4 - 7h  */
-        unsigned int        clp     :1;
-        unsigned int        pti     :3;
-        unsigned int        vci     :16;
-        unsigned int        vpi     :8;
-        unsigned int        gfc     :4;
-    };
-
-    struct tx_inband_header {
-        /*  0 - 3h  */
-        unsigned int        clp     :1;
-        unsigned int        pti     :3;
-        unsigned int        vci     :16;
-        unsigned int        vpi     :8;
-        unsigned int        gfc     :4;
-        /*  4 - 7h  */
-        unsigned int        res1    :8;
-        unsigned int        pad     :8;
-        unsigned int        cpi     :8;
-        unsigned int        uu      :8;
-    };
-#endif  //  defined(__BIG_ENDIAN)
-
-struct wan_mib_table {
-    unsigned int                     res1;
-    unsigned int                     wrx_drophtu_cell;
-    unsigned int                     wrx_dropdes_pdu;
-    unsigned int                     wrx_correct_pdu;
-    unsigned int                     wrx_err_pdu;
-    unsigned int                     wrx_dropdes_cell;
-    unsigned int                     wrx_correct_cell;
-    unsigned int                     wrx_err_cell;
-    unsigned int                     wrx_total_byte;
-    unsigned int                     wtx_total_pdu;
-    unsigned int                     wtx_total_cell;
-    unsigned int                     wtx_total_byte;
-};
-
-/*
- *  Internal Structure of Device
- */
-struct port {
-    int                     connection_base;        /*  first connection ID (RX/TX queue ID)    */
-    unsigned int                     max_connections;        /*  maximum connection number               */
-    unsigned int                     connection_table;       /*  connection opened status, every bit     */
-    unsigned int                     tx_max_cell_rate;       /*  maximum cell rate                       */
-    unsigned int                     tx_current_cell_rate;   /*  currently used cell rate                */
-#if !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-    int                     rx_dma_channel_base;    /*  first RX DMA channel ID                 */
-    unsigned int                     rx_dma_channel_assigned;/*  totally RX DMA channels used            */
-#endif  //  !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-    int                     oam_tx_queue;           /*  first TX queue ID of OAM cell           */
-    struct atm_dev          *dev;
-
-};
-
-struct connection {
-    struct atm_vcc          *vcc;                   /*  opened VCC                              */
-    struct timespec         access_time;            /*  time when last F4/F5 user cell arrives  */
-    unsigned int                     aal5_vcc_crc_err;       /*  number of packets with CRC error        */
-    unsigned int                     aal5_vcc_oversize_sdu;  /*  number of packets with oversize error   */
-    int                     rx_dma_channel;         /*  RX DMA channel ID assigned              */
-    int                     port;                   /*  to which port the connection belongs    */
-    unsigned int                     rx_pdu;
-    unsigned int                     rx_err_pdu;
-    unsigned int                     rx_sw_drop_pdu;
-    unsigned int                     tx_pdu;
-    unsigned int                     tx_err_pdu;
-    unsigned int                     tx_hw_drop_pdu;
-    unsigned int                     tx_sw_drop_pdu;
-};
-
-struct ppe_dev {
-    struct connection       connection[MAX_CONNECTION_NUMBER];
-    struct port             port[ATM_PORT_NUMBER];
-
-    struct aal5 {
-        unsigned char              padding_byte;               /*  padding byte pattern of AAL5 packet     */
-        unsigned int             rx_max_packet_size;         /*  max AAL5 packet length                  */
-        unsigned int             rx_min_packet_size;         /*  min AAL5 packet length                  */
-        unsigned int             rx_buffer_size;             /*  max memory allocated for a AAL5 packet  */
-        unsigned int             tx_max_packet_size;         /*  max AAL5 packet length                  */
-        unsigned int             tx_min_packet_size;         /*  min AAL5 packet length                  */
-        unsigned int             tx_buffer_size;             /*  max memory allocated for a AAL5 packet  */
-        unsigned int    rx_drop_error_packet;       /*  1: drop error packet, 0: ignore errors  */
-    }                       aal5;
-
-    struct qsb {
-        unsigned int             tau;                        /*  cell delay variation due to concurrency */
-        unsigned int             tstepc;                     /*  shceduler burst length                  */
-        unsigned int             sbl;                        /*  time step                               */
-    }                       qsb;
-
-    struct dma {
-        unsigned int             rx_descriptor_number;       /*  number of RX descriptors                */
-        unsigned int             tx_descriptor_number;       /*  number of TX descriptors                */
-        unsigned int             rx_clp1_desc_threshold;     /*  threshold to drop cells with CLP1       */
-        unsigned int             write_descriptor_delay;     /*  delay on descriptor write path          */
-        unsigned int             rx_total_channel_used;      /*  total RX channel used                   */
-        void            *rx_descriptor_addr;        /*  base address of memory allocated for    */
-        struct rx_descriptor
-                        *rx_descriptor_base;        /*  base address of RX descriptors          */
-        int             rx_desc_read_pos[MAX_RX_DMA_CHANNEL_NUMBER];    /*  first RX descriptor */
-                                                                        /*  to be read          */
-//        struct sk_buff  **rx_skb_pointers;          /*  base address of RX sk_buff pointers     */
-
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-        long            rx_weight[MAX_RX_DMA_CHANNEL_NUMBER];           /*  RX schedule weight  */
-        long            rx_default_weight[MAX_RX_DMA_CHANNEL_NUMBER];   /*  default weight      */
-#endif
-
-        unsigned int             tx_total_channel_used;      /*  total TX channel used                   */
-        void            *tx_descriptor_addr;        /*  base address of memory allocated for    */
-                                                    /*  TX descriptors                          */
-        struct tx_descriptor
-                        *tx_descriptor_base;        /*  base address of TX descriptors          */
-        int             tx_desc_alloc_pos[MAX_TX_DMA_CHANNEL_NUMBER];   /*  first TX descriptor */
-                                                                        /*  could be allocated  */
-//        int             tx_desc_alloc_num[MAX_TX_DMA_CHANNEL_NUMBER];   /*  number of allocated */
-//                                                                        /*  TX descriptors      */
-        int             tx_desc_alloc_flag[MAX_TX_DMA_CHANNEL_NUMBER];  /*  at least one TX     */
-                                                                        /*  descriptor is alloc */
-//        int             tx_desc_send_pos[MAX_TX_DMA_CHANNEL_NUMBER];    /*  first TX descriptor */
-//                                                                        /*  to be send          */
-        int             tx_desc_release_pos[MAX_TX_DMA_CHANNEL_NUMBER]; /*  first TX descriptor */
-                                                                        /*  to be released      */
-        struct sk_buff  **tx_skb_pointers;          /*  base address of TX sk_buff pointers     */
-    }                       dma;
-
-    struct mib {
-        ppe_u64_t       wrx_total_byte;             /*  bit-64 extention of MIB table member    */
-        ppe_u64_t       wtx_total_byte;             /*  bit-64 extention of MIB talbe member    */
-
-        unsigned int             wrx_pdu;                    /*  successfully received AAL5 packet       */
-        unsigned int             wrx_drop_pdu;               /*  AAL5 packet dropped by driver on RX     */
-        unsigned int             wtx_err_pdu;                /*  error AAL5 packet                       */
-        unsigned int             wtx_drop_pdu;               /*  AAL5 packet dropped by driver on TX     */
-    }                       mib;
-    struct wan_mib_table    prev_mib;
-
-    int                     oam_rx_queue;           /*  RX queue ID of OAM cell                 */
-    int                     oam_rx_dma_channel;     /*  RX DMA channel ID of OAM cell           */
-    int                     max_connections;        /*  total connections available             */
-
-    struct semaphore        sem;                    /*  lock used by open/close function        */
-};
-
-/*
- *  Host-PPE Communication Data Structure
- */
-#if defined(__BIG_ENDIAN)
-    struct wrx_queue_config {
-        /*  0h  */
-        unsigned int    res2        :27;
-        unsigned int    dmach       :4;
-        unsigned int    errdp       :1;
-        /*  1h  */
-        unsigned int    oversize    :16;
-        unsigned int    undersize   :16;
-        /*  2h  */
-        unsigned int    res1        :16;
-        unsigned int    mfs         :16;
-        /*  3h  */
-        unsigned int    uumask      :8;
-        unsigned int    cpimask     :8;
-        unsigned int    uuexp       :8;
-        unsigned int    cpiexp      :8;
-    };
-
-    struct wtx_port_config {
-        unsigned int    res1        :27;
-        unsigned int    qid         :4;
-        unsigned int    qsben       :1;
-    };
-
-    struct wtx_queue_config {
-        unsigned int    res1        :25;
-        unsigned int    sbid        :1;
-        unsigned int    res2        :3;
-        unsigned int    type        :2;
-        unsigned int    qsben       :1;
-    };
-
-    struct wrx_dma_channel_config {
-        /*  0h  */
-        unsigned int    res1        :1;
-        unsigned int    mode        :2;
-        unsigned int    rlcfg       :1;
-        unsigned int    desba       :28;
-        /*  1h  */
-        unsigned int    chrl        :16;
-        unsigned int    clp1th      :16;
-        /*  2h  */
-        unsigned int    deslen      :16;
-        unsigned int    vlddes      :16;
-    };
-
-    struct wtx_dma_channel_config {
-        /*  0h  */
-        unsigned int    res2        :1;
-        unsigned int    mode        :2;
-        unsigned int    res3        :1;
-        unsigned int    desba       :28;
-        /*  1h  */
-        unsigned int    res1        :32;
-        /*  2h  */
-        unsigned int    deslen      :16;
-        unsigned int    vlddes      :16;
-    };
-
-    struct htu_entry {
-        unsigned int    res1        :2;
-        unsigned int    pid         :2;
-        unsigned int    vpi         :8;
-        unsigned int    vci         :16;
-        unsigned int    pti         :3;
-        unsigned int    vld         :1;
-    };
-
-    struct htu_mask {
-        unsigned int    set         :2;
-        unsigned int    pid_mask    :2;
-        unsigned int    vpi_mask    :8;
-        unsigned int    vci_mask    :16;
-        unsigned int    pti_mask    :3;
-        unsigned int    clear       :1;
-    };
-
-   struct htu_result {
-        unsigned int    res1        :12;
-        unsigned int    cellid      :4;
-        unsigned int    res2        :5;
-        unsigned int    type        :1;
-        unsigned int    ven         :1;
-        unsigned int    res3        :5;
-        unsigned int    qid         :4;
-    };
-
-    struct rx_descriptor {
-        /*  0 - 3h  */
-        unsigned int    own         :1;
-        unsigned int    c           :1;
-        unsigned int    sop         :1;
-        unsigned int    eop         :1;
-        unsigned int    res1        :3;
-        unsigned int    byteoff     :2;
-        unsigned int    res2        :2;
-        unsigned int    id          :4;
-        unsigned int    err         :1;
-        unsigned int    datalen     :16;
-        /*  4 - 7h  */
-        unsigned int    res3        :4;
-        unsigned int    dataptr     :28;
-    };
-
-    struct tx_descriptor {
-        /*  0 - 3h  */
-        unsigned int    own         :1;
-        unsigned int    c           :1;
-        unsigned int    sop         :1;
-        unsigned int    eop         :1;
-        unsigned int    byteoff     :5;
-        unsigned int    res1        :5;
-        unsigned int    iscell      :1;
-        unsigned int    clp         :1;
-        unsigned int    datalen     :16;
-        /*  4 - 7h  */
-        unsigned int    res2        :4;
-        unsigned int    dataptr     :28;
-    };
-#else
-    struct wrx_queue_config {
-        /*  0h  */
-        unsigned int    errdp       :1;
-        unsigned int    dmach       :4;
-        unsigned int    res2        :27;
-        /*  1h  */
-        unsigned int    undersize   :16;
-        unsigned int    oversize    :16;
-        /*  2h  */
-        unsigned int    mfs         :16;
-        unsigned int    res1        :16;
-        /*  3h  */
-        unsigned int    cpiexp      :8;
-        unsigned int    uuexp       :8;
-        unsigned int    cpimask     :8;
-        unsigned int    uumask      :8;
-    };
-
-    struct wtx_port_config {
-        unsigned int    qsben       :1;
-        unsigned int    qid         :4;
-        unsigned int    res1        :27;
-    };
-
-    struct wtx_queue_config {
-        unsigned int    qsben       :1;
-        unsigned int    type        :2;
-        unsigned int    res2        :3;
-        unsigned int    sbid        :1;
-        unsigned int    res1        :25;
-    };
-
-    struct wrx_dma_channel_config
-    {
-        /*  0h  */
-        unsigned int    desba       :28;
-        unsigned int    rlcfg       :1;
-        unsigned int    mode        :2;
-        unsigned int    res1        :1;
-        /*  1h  */
-        unsigned int    clp1th      :16;
-        unsigned int    chrl        :16;
-        /*  2h  */
-        unsigned int    vlddes      :16;
-        unsigned int    deslen      :16;
-    };
-
-    struct wtx_dma_channel_config {
-        /*  0h  */
-        unsigned int    desba       :28;
-        unsigned int    res3        :1;
-        unsigned int    mode        :2;
-        unsigned int    res2        :1;
-        /*  1h  */
-        unsigned int    res1        :32;
-        /*  2h  */
-        unsigned int    vlddes      :16;
-        unsigned int    deslen      :16;
-    };
-
-    struct rx_descriptor {
-        /*  4 - 7h  */
-        unsigned int    dataptr     :28;
-        unsigned int    res3        :4;
-        /*  0 - 3h  */
-        unsigned int    datalen     :16;
-        unsigned int    err         :1;
-        unsigned int    id          :4;
-        unsigned int    res2        :2;
-        unsigned int    byteoff     :2;
-        unsigned int    res1        :3;
-        unsigned int    eop         :1;
-        unsigned int    sop         :1;
-        unsigned int    c           :1;
-        unsigned int    own         :1;
-    };
-
-    struct tx_descriptor {
-        /*  4 - 7h  */
-        unsigned int    dataptr     :28;
-        unsigned int    res2        :4;
-        /*  0 - 3h  */
-        unsigned int    datalen     :16;
-        unsigned int    clp         :1;
-        unsigned int    iscell      :1;
-        unsigned int    res1        :5;
-        unsigned int    byteoff     :5;
-        unsigned int    eop         :1;
-        unsigned int    sop         :1;
-        unsigned int    c           :1;
-        unsigned int    own         :1;
-    };
-#endif  //  defined(__BIG_ENDIAN)
-
-/*
- *  QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
- */
-#if defined(__BIG_ENDIAN)
-    union qsb_queue_parameter_table {
-        struct {
-            unsigned int    res1    :1;
-            unsigned int    vbr     :1;
-            unsigned int    wfqf    :14;
-            unsigned int    tp      :16;
-        }               bit;
-        unsigned int             dword;
-    };
-
-    union qsb_queue_vbr_parameter_table {
-        struct {
-            unsigned int    taus    :16;
-            unsigned int    ts      :16;
-        }               bit;
-        unsigned int             dword;
-    };
-#else
-    union qsb_queue_parameter_table {
-        struct {
-            unsigned int    tp      :16;
-            unsigned int    wfqf    :14;
-            unsigned int    vbr     :1;
-            unsigned int    res1    :1;
-        }               bit;
-        unsigned int             dword;
-    };
-
-    union qsb_queue_vbr_parameter_table {
-        struct {
-            unsigned int    ts      :16;
-            unsigned int    taus    :16;
-        }               bit;
-        unsigned int             dword;
-    };
-#endif  //  defined(__BIG_ENDIAN)
-
-
-typedef enum
-{
-    IAD_ATM_CBR     = 6,                                               /* IAD_ATM_PRI_HIGH,                                                    */
-    IAD_ATM_VBR_RT  = 4,                                               /* IAD_ATM_PRI_MED_HIGH,        VBR, Real-Time          */
-    IAD_ATM_VBR_NRT = 2,                                               /* IAD_ATM_PRI_MED_LOW,     VBR, Non-Real-Time  */
-    IAD_ATM_UBR     = 0,                                               /* IAD_ATM_PRI_LOW                                                              */
-} iad_atmServiceCategory;
-
-typedef        unsigned int iad_atmDiffServCategory;
-
-typedef struct 
-{
-   int cellRate;
-   int round;   /* IAD_ATM_RATE_CEILING, IAD_ATM_RATE_FLOOR */
-} iad_atmCellRateDesc;
-
-typedef struct 
-{
-    unsigned int               phyID;          /* IAD_ATM_PHY0, IAD_ATM_PHY1 */
-    unsigned int               txQHnd;         /* Tx HW Q */
-    union _pri
-    {
-        int                     priority;       /* TS Q:    4 priorities: IAD_ATM_PRI_HIGH, IAD_ATM_PRI_MED_HIGH, IAD_ATM_PRI_MED_LOW, IAD_ATM_PRI_LOW
-                                                  non-TS Q: 8 priorities: IAD_ATM_PRI_LEVEL_7, IAD_ATM_PRI_LEVEL_6,..., IAD_ATM_PRI_LEVEL_0 */
-        iad_atmServiceCategory  qosClass;       /* IAD_ATM_CBR, IAD_ATM_VBR_RT, IAD_ATM_VBR_NRT, IAD_ATM_UBR */
-        iad_atmDiffServCategory diffServClass;  /* IP_QOS */
-    } srvCat; /* service category */
-    iad_atmCellRateDesc         pcr;            /* Peak Cell Rate */
-    iad_atmCellRateDesc         scr;            /* Sustained Cell Rate. */
-    iad_atmCellRateDesc         mcr;            /* Minimum Cell Rate, not used */
-    int                         mbs;            /* maximum bursting size in cells */
-    int                         isPrioritize;   /* TRUE: This flow is of the higher priority than the flows of the same QOS category.(Use MCR to boost priority) */
-} iad_atmTrfPar; /* Tx Traffic Parameters */
-
-typedef struct
-{
-    unsigned int    txGrpId;
-    unsigned int    flowId;
-    iad_atmTrfPar   trfPar;
-} Atm_Ictl_Flow_Set;
-
-typedef struct
-{
-    unsigned int    txGrpId;
-    unsigned int    vpi;
-    unsigned int    vci;
-
-    unsigned int    encaps;
-    unsigned int    proto;
-
-} Atm_Ictl_Open_Vcc;
-
-typedef struct
-{
-    struct atm_vcc                     vcc;
-       unsigned int                    valid;
-       unsigned int                    on;
-    unsigned int                       vccIndex; /* 0~7 */
-       unsigned int                    itf;
-    struct net_device_stats    stats; 
-} Atm_Priv;
-
-
-extern struct ppe_dev ppe_dev;
-
-
-int pp32_start(void);
-void pp32_stop(void);
-void init_rx_tables(void);
-void init_tx_tables(void);
-struct sk_buff* alloc_skb_rx(void);
-struct sk_buff* alloc_skb_tx(unsigned int);
-void resize_skb_rx(struct sk_buff *, unsigned int, int);
-struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
-void atm_free_tx_skb_vcc(struct sk_buff *);
-int alloc_tx_connection(int);
-int ppe_open(struct atm_vcc *vcc);
-void ppe_close(struct atm_vcc *vcc);
-int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg);
-int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb);
-int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags);
-int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags);
-irqreturn_t mailbox_irq_handler(int, void *);
-int find_vcc(struct atm_vcc *vcc);
-int find_vpi(unsigned int vpi);
-int find_vpivci(unsigned int vpi, unsigned int vci);
-void mailbox_signal(unsigned int channel, int is_tx);
-
diff --git a/package/ifxmips-atm/src/core.c b/package/ifxmips-atm/src/core.c
deleted file mode 100644 (file)
index 95b05f3..0000000
+++ /dev/null
@@ -1,800 +0,0 @@
-#include <asm/mach-ifxmips/cgu.h>
-#include <linux/module.h>
-#include <linux/atmdev.h>
-#include <linux/irq.h>
-
-#include "common.h"
-#include "proc.h"
-
-// our main struct
-struct ppe_dev ppe_dev;
-
-static int port_max_connection[2] = {7, 7};     /*  Maximum number of connections for ports (0-14)  */
-static int port_cell_rate_up[2] = {3200, 3200}; /*  Maximum TX cell rate for ports                  */
-static int qsb_tau = 1;
-static int qsb_srvm = 0x0f;
-static int qsb_tstep = 4;
-static int write_descriptor_delay = 0x20;
-static int aal5_fill_pattern = 0x007E;
-static int aal5r_max_packet_size = 0x0700;
-static int aal5r_min_packet_size = 0x0000;
-static int aal5s_max_packet_size = 0x0700;
-static int aal5s_min_packet_size = 0x0000;
-static int aal5r_drop_error_packet = 1;
-static int dma_rx_descriptor_length = 48;
-static int dma_tx_descriptor_length = 64;
-static int dma_rx_clp1_descriptor_threshold = 38;
-
-//module_param(port_max_connection, "2-2i");
-//module_param(port_cell_rate_up, "2-2i");
-module_param(qsb_tau, int, 0);
-module_param(qsb_srvm, int, 0);
-module_param(qsb_tstep, int, 0);
-module_param(write_descriptor_delay, int, 0);
-module_param(aal5_fill_pattern, int, 0);
-module_param(aal5r_max_packet_size, int, 0);
-module_param(aal5r_min_packet_size, int, 0);
-module_param(aal5s_max_packet_size, int, 0);
-module_param(aal5s_min_packet_size, int, 0);
-module_param(aal5r_drop_error_packet, int, 0);
-module_param(dma_rx_descriptor_length, int, 0);
-module_param(dma_tx_descriptor_length, int, 0);
-module_param(dma_rx_clp1_descriptor_threshold, int, 0);
-
-MODULE_PARM_DESC(port_cell_rate_up, "ATM port upstream rate in cells/s");
-MODULE_PARM_DESC(port_max_connection, "Maximum atm connection for port (0-1)");
-MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
-MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
-MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
-MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
-MODULE_PARM_DESC(a5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
-MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
-MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
-MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
-MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
-MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
-MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
-MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
-MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
-
-void init_rx_tables(void)
-{
-    int i, j;
-    struct wrx_queue_config wrx_queue_config = {0};
-    struct wrx_dma_channel_config wrx_dma_channel_config = {0};
-    struct htu_entry htu_entry = {0};
-    struct htu_result htu_result = {0};
-
-    struct htu_mask htu_mask = {    set:        0x03,
-                                    pid_mask:   0x00,
-                                    vpi_mask:   0x00,
-                                    vci_mask:   0x00,
-                                    pti_mask:   0x00,
-                                    clear:      0x00};
-
-    /*
-     *  General Registers
-     */
-    *CFG_WRX_HTUTS  = ppe_dev.max_connections + OAM_HTU_ENTRY_NUMBER;
-    *CFG_WRX_QNUM   = ppe_dev.max_connections + OAM_RX_QUEUE_NUMBER + QSB_QUEUE_NUMBER_BASE;
-    *CFG_WRX_DCHNUM = ppe_dev.dma.rx_total_channel_used;
-    *WRX_DMACH_ON   = (1 << ppe_dev.dma.rx_total_channel_used) - 1;
-    *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
-
-    /*
-     *  WRX Queue Configuration Table
-     */
-    wrx_queue_config.uumask    = 0;
-    wrx_queue_config.cpimask   = 0;
-    wrx_queue_config.uuexp     = 0;
-    wrx_queue_config.cpiexp    = 0;
-    wrx_queue_config.mfs       = ppe_dev.aal5.rx_max_packet_size;   // rx_buffer_size
-    wrx_queue_config.oversize  = ppe_dev.aal5.rx_max_packet_size;
-    wrx_queue_config.undersize = ppe_dev.aal5.rx_min_packet_size;
-    wrx_queue_config.errdp     = ppe_dev.aal5.rx_drop_error_packet;
-    for ( i = 0; i < QSB_QUEUE_NUMBER_BASE; i++ )
-        *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
-    for ( j = 0; j < ppe_dev.max_connections; j++ )
-    {
-#if !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-        /*  If RX QoS is disabled, the DMA channel must be fixed.   */
-        wrx_queue_config.dmach = ppe_dev.connection[i].rx_dma_channel;
-#endif  //  !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-        *WRX_QUEUE_CONFIG(i++) = wrx_queue_config;
-    }
-    /*  OAM RX Queue    */
-    for ( j = 0; j < OAM_RX_DMA_CHANNEL_NUMBER; j++ )
-    {
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-        wrx_queue_config.dmach = RX_DMA_CH_OAM;
-#else
-        wrx_queue_config.dmach = ppe_dev.oam_rx_dma_channel + j;
-#endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-        *WRX_QUEUE_CONFIG(i++) = wrx_queue_config;
-    }
-
-    wrx_dma_channel_config.deslen = ppe_dev.dma.rx_descriptor_number;
-    wrx_dma_channel_config.chrl   = 0;
-    wrx_dma_channel_config.clp1th = ppe_dev.dma.rx_clp1_desc_threshold;
-    wrx_dma_channel_config.mode   = WRX_DMA_CHANNEL_COUNTER_MODE;
-    wrx_dma_channel_config.rlcfg  = WRX_DMA_BUF_LEN_PER_DESCRIPTOR;
-    for ( i = 0; i < ppe_dev.dma.rx_total_channel_used; i++ )
-    {
-        wrx_dma_channel_config.desba = (((u32)ppe_dev.dma.rx_descriptor_base >> 2) & 0x0FFFFFFF) + ppe_dev.dma.rx_descriptor_number * i * (sizeof(struct rx_descriptor) >> 2);
-        *WRX_DMA_CHANNEL_CONFIG(i) = wrx_dma_channel_config;
-    }
-
-    /*
-     *  HTU Tables
-     */
-    for ( i = 0; i < ppe_dev.max_connections; i++ )
-    {
-        htu_result.qid = (unsigned int)i;
-
-        *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
-        *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
-        *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
-    }
-    /*  OAM HTU Entry   */
-    htu_entry.vci     = 0x03;
-    htu_mask.pid_mask = 0x03;
-    htu_mask.vpi_mask = 0xFF;
-    htu_mask.vci_mask = 0x0000;
-    htu_mask.pti_mask = 0x07;
-    htu_result.cellid = ppe_dev.oam_rx_queue;
-    htu_result.type   = 1;
-    htu_result.ven    = 1;
-    htu_result.qid    = ppe_dev.oam_rx_queue;
-    *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
-    *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
-    *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
-    htu_entry.vci     = 0x04;
-    htu_result.cellid = ppe_dev.oam_rx_queue;
-    htu_result.type   = 1;
-    htu_result.ven    = 1;
-    htu_result.qid    = ppe_dev.oam_rx_queue;
-    *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
-    *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
-    *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
-    htu_entry.vci     = 0x00;
-    htu_entry.pti     = 0x04;
-    htu_mask.vci_mask = 0xFFFF;
-    htu_mask.pti_mask = 0x01;
-    htu_result.cellid = ppe_dev.oam_rx_queue;
-    htu_result.type   = 1;
-    htu_result.ven    = 1;
-    htu_result.qid    = ppe_dev.oam_rx_queue;
-    *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
-    *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
-    *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
-}
-
-void init_tx_tables(void)
-{
-    int i, j;
-    struct wtx_queue_config wtx_queue_config = {0};
-    struct wtx_dma_channel_config wtx_dma_channel_config = {0};
-
-    struct wtx_port_config wtx_port_config = {  res1:   0,
-                                                qid:    0,
-                                                qsben:  1};
-
-    /*
-     *  General Registers
-     */
-    *CFG_WTX_DCHNUM     = ppe_dev.dma.tx_total_channel_used + QSB_QUEUE_NUMBER_BASE;
-    *WTX_DMACH_ON       = ((1 << (ppe_dev.dma.tx_total_channel_used + QSB_QUEUE_NUMBER_BASE)) - 1) ^ ((1 << QSB_QUEUE_NUMBER_BASE) - 1);
-    *CFG_WRDES_DELAY    = ppe_dev.dma.write_descriptor_delay;
-
-    /*
-     *  WTX Port Configuration Table
-     */
-#if !defined(DISABLE_QSB) || !DISABLE_QSB
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        *WTX_PORT_CONFIG(i) = wtx_port_config;
-#else
-    wtx_port_config.qsben = 0;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-    {
-        wtx_port_config.qid = ppe_dev.port[i].connection_base;
-        *WTX_PORT_CONFIG(i) = wtx_port_config;
-
-printk("port %d: qid = %d, qsb disabled\n", i, wtx_port_config.qid);
-    }
-#endif
-
-    /*
-     *  WTX Queue Configuration Table
-     */
-    wtx_queue_config.res1  = 0;
-    wtx_queue_config.res2  = 0;
-//    wtx_queue_config.type  = 0x03;
-    wtx_queue_config.type  = 0x0;
-#if !defined(DISABLE_QSB) || !DISABLE_QSB
-    wtx_queue_config.qsben = 1;
-#else
-    wtx_queue_config.qsben = 0;
-#endif
-    wtx_queue_config.sbid  = 0;
-    for ( i = 0; i < QSB_QUEUE_NUMBER_BASE; i++ )
-        *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
-    for ( j = 0; j < ppe_dev.max_connections; j++ )
-    {
-        wtx_queue_config.sbid = ppe_dev.connection[i].port & 0x01;  /*  assign QSB to TX queue  */
-        *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
-        i++;
-    }
-    /*  OAM TX Queue    */
-//    wtx_queue_config.type = 0x01;
-    wtx_queue_config.type  = 0x00;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-    {
-        wtx_queue_config.sbid = i & 0x01;
-        for ( j = 0; j < OAM_TX_QUEUE_NUMBER_PER_PORT; j++ )
-            *WTX_QUEUE_CONFIG(ppe_dev.port[i].oam_tx_queue + j) = wtx_queue_config;
-    }
-
-    wtx_dma_channel_config.mode   = WRX_DMA_CHANNEL_COUNTER_MODE;
-    wtx_dma_channel_config.deslen = 0;
-    wtx_dma_channel_config.desba = 0;
-    for ( i = 0; i < QSB_QUEUE_NUMBER_BASE; i++ )
-        *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
-    /*  normal connection and OAM channel   */
-    wtx_dma_channel_config.deslen = ppe_dev.dma.tx_descriptor_number;
-    for ( j = 0; j < ppe_dev.dma.tx_total_channel_used; j++ )
-    {
-        wtx_dma_channel_config.desba = (((u32)ppe_dev.dma.tx_descriptor_base >> 2) & 0x0FFFFFFF) + ppe_dev.dma.tx_descriptor_number * j * (sizeof(struct tx_descriptor) >> 2);
-        *WTX_DMA_CHANNEL_CONFIG(i++) = wtx_dma_channel_config;
-    }
-}
-
-static inline void qsb_global_set(void)
-{
-    int i, j;
-    u32 qsb_clk = cgu_get_fpi_bus_clock(2);
-   u32 tmp1, tmp2, tmp3;
-    union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
-    union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
-    int qsb_qid;
-
-    *QSB_ICDV = QSB_ICDV_TAU_SET(ppe_dev.qsb.tau);
-    *QSB_SBL  = QSB_SBL_SBL_SET(ppe_dev.qsb.sbl);
-    *QSB_CFG  = QSB_CFG_TSTEPC_SET(ppe_dev.qsb.tstepc >> 1);
-
-    /*
-     *  set SCT and SPT per port
-     */
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( ppe_dev.port[i].max_connections != 0 && ppe_dev.port[i].tx_max_cell_rate != 0 )
-        {
-            tmp1 = ((qsb_clk * ppe_dev.qsb.tstepc) >> 1) / ppe_dev.port[i].tx_max_cell_rate;
-            tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
-            tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
-            /*  carry over to integer part (?)  */
-            if ( tmp3 == (1 << 6) )
-            {
-                tmp3 = 0;
-                tmp2++;
-            }
-            if ( tmp2 == 0 )
-                tmp2 = tmp3 = 1;
-            /*  1. set mask                                 */
-            /*  2. write value to data transfer register    */
-            /*  3. start the tranfer                        */
-            /*  SCT (FracRate)  */
-            *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
-            *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
-            *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-            /*  SPT (SBV + PN + IntRage)    */
-            *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
-            *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
-            *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-        }
-
-       /*
-       *  set OAM TX queue
-       */
-       for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-               if ( ppe_dev.port[i].max_connections != 0 )
-               {
-                       tmp1 = ((qsb_clk * ppe_dev.qsb.tstepc) >> 1) / ppe_dev.port[i].tx_max_cell_rate;
-                       tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
-                       tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
-                       /*  carry over to integer part (?)  */
-                       if ( tmp3 == (1 << 6) )
-                       {
-                               tmp3 = 0;
-                               tmp2++;
-                       }
-                       if ( tmp2 == 0 )
-                               tmp2 = tmp3 = 1;
-                               /*  1. set mask                                 */
-                               /*  2. write value to data transfer register    */
-                               /*  3. start the tranfer                        */
-                               /*  SCT (FracRate)  */
-                               *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
-                               *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
-                               *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-
-                               /*  SPT (SBV + PN + IntRage)    */
-                               *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
-                               *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
-                               *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
-               }
-
-               /*
-               *      *  set OAM TX queue
-               *           */
-               for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-                       if ( ppe_dev.port[i].max_connections != 0 )
-                               for ( j = 0; j < OAM_TX_QUEUE_NUMBER_PER_PORT; j++ )
-                               {
-                                       qsb_qid = ppe_dev.port[i].oam_tx_queue + j;
-
-                                       /*  disable PCR limiter */
-                                       qsb_queue_parameter_table.bit.tp = 0;
-                                       /*  set WFQ as real time queue  */
-                                       qsb_queue_parameter_table.bit.wfqf = 0;
-                                       /*  disable leaky bucket shaper */
-                                       qsb_queue_vbr_parameter_table.bit.taus = 0;
-                                       qsb_queue_vbr_parameter_table.bit.ts = 0;
-
-                                       /*  Queue Parameter Table (QPT) */
-                                       *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
-                                       *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
-                                       *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
-                                       /*  Queue VBR Paramter Table (QVPT) */
-                                       *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
-                                       *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
-                                       *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
-                               }
-}
-
-static inline void clear_ppe_dev(void)
-{
-       int i;
-
-       for (i = 0; i < ppe_dev.dma.tx_total_channel_used; i++ )
-       {
-               int conn = i + QSB_QUEUE_NUMBER_BASE;
-               int desc_base;
-               struct sk_buff *skb;
-
-               while(ppe_dev.dma.tx_desc_release_pos[conn] != ppe_dev.dma.tx_desc_alloc_pos[conn])
-               {
-                       desc_base = ppe_dev.dma.tx_descriptor_number * (conn - QSB_QUEUE_NUMBER_BASE) + ppe_dev.dma.tx_desc_release_pos[conn];
-                       if(!ppe_dev.dma.tx_descriptor_base[desc_base].own)
-                       {
-                               skb = ppe_dev.dma.tx_skb_pointers[desc_base];
-                               atm_free_tx_skb_vcc(skb);
-
-                               //  pretend PP32 hold owner bit, so that won't be released more than once, so allocation process don't check this bit
-                               ppe_dev.dma.tx_descriptor_base[desc_base].own = 1;
-                       }
-                       if (++ppe_dev.dma.tx_desc_release_pos[conn] == ppe_dev.dma.tx_descriptor_number)
-                               ppe_dev.dma.tx_desc_release_pos[conn] = 0;
-               }
-       }
-
-       for (i = ppe_dev.dma.rx_total_channel_used * ppe_dev.dma.rx_descriptor_number - 1; i >= 0; i--)
-               dev_kfree_skb_any(*(struct sk_buff **)(((ppe_dev.dma.rx_descriptor_base[i].dataptr << 2) | KSEG0) - 4));
-
-       kfree(ppe_dev.dma.tx_skb_pointers);
-       kfree(ppe_dev.dma.tx_descriptor_addr);
-       kfree(ppe_dev.dma.rx_descriptor_addr);
-}
-
-static inline int init_ppe_dev(void)
-{
-    int i, j;
-    int rx_desc, tx_desc;
-    int conn;
-    int oam_tx_queue;
-#if !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-    int rx_dma_channel_base;
-    int rx_dma_channel_assigned;
-#endif  //  !defined(ENABLE_RX_QOS) || !ENABLE_RX_QOS
-
-    struct rx_descriptor rx_descriptor = {  own:    1,
-                                            c:      0,
-                                            sop:    1,
-                                            eop:    1,
-                                            res1:   0,
-                                            byteoff:0,
-                                            res2:   0,
-                                            id:     0,
-                                            err:    0,
-                                            datalen:0,
-                                            res3:   0,
-                                            dataptr:0};
-
-    struct tx_descriptor tx_descriptor = {  own:    1,  //  pretend it's hold by PP32
-                                            c:      0,
-                                            sop:    1,
-                                            eop:    1,
-                                            byteoff:0,
-                                            res1:   0,
-                                            iscell: 0,
-                                            clp:    0,
-                                            datalen:0,
-                                            res2:   0,
-                                            dataptr:0};
-
-    memset(&ppe_dev, 0, sizeof(ppe_dev));
-
-    /*
-     *  Setup AAL5 members, buffer size must be larger than max packet size plus overhead.
-     */
-    ppe_dev.aal5.padding_byte         = (u8)aal5_fill_pattern;
-    ppe_dev.aal5.rx_max_packet_size   = (u32)aal5r_max_packet_size;
-    ppe_dev.aal5.rx_min_packet_size   = (u32)aal5r_min_packet_size;
-    ppe_dev.aal5.rx_buffer_size       = ((u32)(aal5r_max_packet_size > CELL_SIZE ? aal5r_max_packet_size + MAX_RX_FRAME_EXTRA_BYTES : CELL_SIZE + MAX_RX_FRAME_EXTRA_BYTES) + DMA_ALIGNMENT - 1) & ~(DMA_ALIGNMENT - 1);
-    ppe_dev.aal5.tx_max_packet_size   = (u32)aal5s_max_packet_size;
-    ppe_dev.aal5.tx_min_packet_size   = (u32)aal5s_min_packet_size;
-    ppe_dev.aal5.tx_buffer_size       = ((u32)(aal5s_max_packet_size > CELL_SIZE ? aal5s_max_packet_size + MAX_TX_FRAME_EXTRA_BYTES : CELL_SIZE + MAX_TX_FRAME_EXTRA_BYTES) + DMA_ALIGNMENT - 1) & ~(DMA_ALIGNMENT - 1);
-    ppe_dev.aal5.rx_drop_error_packet = aal5r_drop_error_packet ? 1 : 0;
-
-    /*
-     *  Setup QSB members, please refer to Amazon spec 15.4 to get the value calculation formula.
-     */
-    ppe_dev.qsb.tau     = (u32)qsb_tau;
-    ppe_dev.qsb.tstepc  = (u32)qsb_tstep;
-    ppe_dev.qsb.sbl     = (u32)qsb_srvm;
-
-    /*
-     *  Setup port, connection, other members.
-     */
-    conn = 0;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-    {
-        /*  first connection ID of port */
-        ppe_dev.port[i].connection_base  = conn + QSB_QUEUE_NUMBER_BASE;
-        /*  max number of connections of port   */
-        ppe_dev.port[i].max_connections  = (u32)port_max_connection[i];
-        /*  max cell rate the port has  */
-        ppe_dev.port[i].tx_max_cell_rate = (u32)port_cell_rate_up[i];
-
-        /*  link connection ID to port ID   */
-        for ( j = port_max_connection[i] - 1; j >= 0; j-- )
-            ppe_dev.connection[conn++ + QSB_QUEUE_NUMBER_BASE].port = i;
-    }
-    /*  total connection numbers of all ports   */
-    ppe_dev.max_connections = conn;
-    /*  OAM RX queue ID, which is the first available connection ID after */
-    /*  connections assigned to ports.                                    */
-    ppe_dev.oam_rx_queue = conn + QSB_QUEUE_NUMBER_BASE;
-
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    oam_tx_queue = conn;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( port_max_connection[i] != 0 )
-        {
-            ppe_dev.port[i].oam_tx_queue = oam_tx_queue + QSB_QUEUE_NUMBER_BASE;
-
-            for ( j = 0; j < OAM_TX_QUEUE_NUMBER_PER_PORT; j++ )
-                /*  Since connection ID is one to one mapped to RX/TX queue ID, the connection  */
-                /*  structure must be reserved for OAM RX/TX queues, and member "port" is set   */
-                /*  according to port to which OAM TX queue is connected.                       */
-                ppe_dev.connection[oam_tx_queue++ + QSB_QUEUE_NUMBER_BASE].port = i;
-        }
-    /*  DMA RX channel assigned to OAM RX queue */
-    ppe_dev.oam_rx_dma_channel = RX_DMA_CH_OAM;
-    /*  DMA RX channel will be assigned dynamically when VCC is open.   */
-#else   //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    rx_dma_channel_base = 0;
-    oam_tx_queue = conn;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( port_max_connection[i] != 0 )
-        {
-            /*  Calculate the number of DMA RX channels could be assigned to port.  */
-            rx_dma_channel_assigned = i == ATM_PORT_NUMBER - 1
-                                      ? (MAX_RX_DMA_CHANNEL_NUMBER - OAM_RX_DMA_CHANNEL_NUMBER) - rx_dma_channel_base
-                                      : (ppe_dev.port[i].max_connections * (MAX_RX_DMA_CHANNEL_NUMBER - OAM_RX_DMA_CHANNEL_NUMBER) + ppe_dev.max_connections / 2) / ppe_dev.max_connections;
-            /*  Amend the number, which could be zero.  */
-            if ( rx_dma_channel_assigned == 0 )
-                rx_dma_channel_assigned = 1;
-            /*  Calculate the first DMA RX channel ID could be assigned to port.    */
-            if ( rx_dma_channel_base + rx_dma_channel_assigned > MAX_RX_DMA_CHANNEL_NUMBER - OAM_RX_DMA_CHANNEL_NUMBER )
-                rx_dma_channel_base = MAX_RX_DMA_CHANNEL_NUMBER - OAM_RX_DMA_CHANNEL_NUMBER - rx_dma_channel_assigned;
-
-            /*  first DMA RX channel ID */
-            ppe_dev.port[i].rx_dma_channel_base     = rx_dma_channel_base;
-            /*  number of DMA RX channels assigned to this port */
-            ppe_dev.port[i].rx_dma_channel_assigned = rx_dma_channel_assigned;
-            /*  OAM TX queue ID, which must be assigned after connections assigned to ports */
-            ppe_dev.port[i].oam_tx_queue            = oam_tx_queue + QSB_QUEUE_NUMBER_BASE;
-
-            rx_dma_channel_base += rx_dma_channel_assigned;
-
-            for ( j = 0; j < OAM_TX_QUEUE_NUMBER_PER_PORT; j++ )
-                /*  Since connection ID is one to one mapped to RX/TX queue ID, the connection  */
-                /*  structure must be reserved for OAM RX/TX queues, and member "port" is set   */
-                /*  according to port to which OAM TX queue is connected.                       */
-                ppe_dev.connection[oam_tx_queue++ + QSB_QUEUE_NUMBER_BASE].port = i;
-        }
-    /*  DMA RX channel assigned to OAM RX queue */
-    ppe_dev.oam_rx_dma_channel = rx_dma_channel_base;
-
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-       for ( j = 0; j < port_max_connection[i]; j++ )
-            /*  Assign DMA RX channel to RX queues. One channel could be assigned to more than one queue.   */
-            ppe_dev.connection[ppe_dev.port[i].connection_base + j].rx_dma_channel = ppe_dev.port[i].rx_dma_channel_base + j % ppe_dev.port[i].rx_dma_channel_assigned;
-#endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-
-    /*  initialize semaphore used by open and close */
-    sema_init(&ppe_dev.sem, 1);
-    /*  descriptor number of RX DMA channel */
-    ppe_dev.dma.rx_descriptor_number         = dma_rx_descriptor_length;
-    /*  descriptor number of TX DMA channel */
-    ppe_dev.dma.tx_descriptor_number         = dma_tx_descriptor_length;
-    /*  If used descriptors are more than this value, cell with CLP1 is dropped.    */
-    ppe_dev.dma.rx_clp1_desc_threshold = dma_rx_clp1_descriptor_threshold;
-
-    /*  delay on descriptor write path  */
-    ppe_dev.dma.write_descriptor_delay       = write_descriptor_delay;
-
-    /*  total DMA RX channel used   */
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    ppe_dev.dma.rx_total_channel_used = RX_DMA_CH_TOTAL;
-#else
-    ppe_dev.dma.rx_total_channel_used = rx_dma_channel_base + OAM_RX_DMA_CHANNEL_NUMBER;
-#endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    /*  total DMA TX channel used (exclude channel reserved by QSB) */
-    ppe_dev.dma.tx_total_channel_used = oam_tx_queue;
-
-    /*  allocate memory for RX descriptors  */
-    ppe_dev.dma.rx_descriptor_addr = kmalloc(ppe_dev.dma.rx_total_channel_used * ppe_dev.dma.rx_descriptor_number * sizeof(struct rx_descriptor) + 4, GFP_KERNEL | GFP_DMA);
-    if ( !ppe_dev.dma.rx_descriptor_addr )
-        goto RX_DESCRIPTOR_BASE_ALLOCATE_FAIL;
-    /*  do alignment (DWORD)    */
-    ppe_dev.dma.rx_descriptor_base = (struct rx_descriptor *)(((u32)ppe_dev.dma.rx_descriptor_addr + 0x03) & ~0x03);
-    ppe_dev.dma.rx_descriptor_base = (struct rx_descriptor *)((u32)ppe_dev.dma.rx_descriptor_base | KSEG1);    //  no cache
-
-    /*  allocate memory for TX descriptors  */
-    ppe_dev.dma.tx_descriptor_addr = kmalloc(ppe_dev.dma.tx_total_channel_used * ppe_dev.dma.tx_descriptor_number * sizeof(struct tx_descriptor) + 4, GFP_KERNEL | GFP_DMA);
-    if ( !ppe_dev.dma.tx_descriptor_addr )
-        goto TX_DESCRIPTOR_BASE_ALLOCATE_FAIL;
-    /*  do alignment (DWORD)    */
-    ppe_dev.dma.tx_descriptor_base = (struct tx_descriptor *)(((u32)ppe_dev.dma.tx_descriptor_addr + 0x03) & ~0x03);
-    ppe_dev.dma.tx_descriptor_base = (struct tx_descriptor *)((u32)ppe_dev.dma.tx_descriptor_base | KSEG1);    //  no cache
-    /*  allocate pointers to TX sk_buff */
-    ppe_dev.dma.tx_skb_pointers = kmalloc(ppe_dev.dma.tx_total_channel_used * ppe_dev.dma.tx_descriptor_number * sizeof(struct sk_buff *), GFP_KERNEL);
-    if ( !ppe_dev.dma.tx_skb_pointers )
-        goto TX_SKB_POINTER_ALLOCATE_FAIL;
-    memset(ppe_dev.dma.tx_skb_pointers, 0, ppe_dev.dma.tx_total_channel_used * ppe_dev.dma.tx_descriptor_number * sizeof(struct sk_buff *));
-
-    /*  Allocate RX sk_buff and fill up RX descriptors. */
-    rx_descriptor.datalen = ppe_dev.aal5.rx_buffer_size;
-    for ( rx_desc = ppe_dev.dma.rx_total_channel_used * ppe_dev.dma.rx_descriptor_number - 1; rx_desc >= 0; rx_desc-- )
-    {
-        struct sk_buff *skb;
-        skb = alloc_skb_rx();
-        if ( skb == NULL )
-            panic("sk buffer is used up\n");
-        rx_descriptor.dataptr = (u32)skb->data >> 2;
-        ppe_dev.dma.rx_descriptor_base[rx_desc] = rx_descriptor;
-
-    }
-
-    /*  Fill up TX descriptors. */
-    tx_descriptor.datalen = ppe_dev.aal5.tx_buffer_size;
-    for ( tx_desc = ppe_dev.dma.tx_total_channel_used * ppe_dev.dma.tx_descriptor_number - 1; tx_desc >= 0; tx_desc-- )
-        ppe_dev.dma.tx_descriptor_base[tx_desc] = tx_descriptor;
-
-    return 0;
-
-TX_SKB_POINTER_ALLOCATE_FAIL:
-    kfree(ppe_dev.dma.tx_descriptor_addr);
-TX_DESCRIPTOR_BASE_ALLOCATE_FAIL:
-    kfree(ppe_dev.dma.rx_descriptor_addr);
-RX_DESCRIPTOR_BASE_ALLOCATE_FAIL:
-    return -ENOMEM;
-}
-
-
-static inline void clear_share_buffer(void)
-{
-    volatile u32 *p = SB_RAM0_ADDR(0);
-    unsigned int i;
-
-    /*  write all zeros only    */
-    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
-        *p++ = 0;
-}
-
-
-static inline void check_parameters(void)
-{
-    int i;
-    int enabled_port_number;
-    int unassigned_queue_number;
-    int assigned_queue_number;
-
-    enabled_port_number = 0;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( port_max_connection[i] < 1 )
-            port_max_connection[i] = 0;
-        else
-            enabled_port_number++;
-    /*  If the max connection number of a port is not 0, the port is enabled  */
-    /*  and at lease two connection ID must be reserved for this port. One of */
-    /*  them is used as OAM TX path.                                          */
-    unassigned_queue_number = MAX_QUEUE_NUMBER - QSB_QUEUE_NUMBER_BASE;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( port_max_connection[i] > 0 )
-        {
-            enabled_port_number--;
-            assigned_queue_number = unassigned_queue_number - enabled_port_number * (1 + OAM_TX_QUEUE_NUMBER_PER_PORT) - OAM_TX_QUEUE_NUMBER_PER_PORT;
-            if ( assigned_queue_number > MAX_QUEUE_NUMBER_PER_PORT - OAM_TX_QUEUE_NUMBER_PER_PORT )
-                assigned_queue_number = MAX_QUEUE_NUMBER_PER_PORT - OAM_TX_QUEUE_NUMBER_PER_PORT;
-            if ( port_max_connection[i] > assigned_queue_number )
-            {
-                port_max_connection[i] = assigned_queue_number;
-                unassigned_queue_number -= assigned_queue_number;
-            }
-            else
-                unassigned_queue_number -= port_max_connection[i];
-        }
-
-    /*  Please refer to Amazon spec 15.4 for setting these values.  */
-    if ( qsb_tau < 1 )
-        qsb_tau = 1;
-    if ( qsb_tstep < 1 )
-        qsb_tstep = 1;
-    else if ( qsb_tstep > 4 )
-        qsb_tstep = 4;
-    else if ( qsb_tstep == 3 )
-        qsb_tstep = 2;
-
-    /*  There is a delay between PPE write descriptor and descriptor is       */
-    /*  really stored in memory. Host also has this delay when writing        */
-    /*  descriptor. So PPE will use this value to determine if the write      */
-    /*  operation makes effect.                                               */
-    if ( write_descriptor_delay < 0 )
-        write_descriptor_delay = 0;
-
-    if ( aal5_fill_pattern < 0 )
-        aal5_fill_pattern = 0;
-    else
-        aal5_fill_pattern &= 0xFF;
-
-    /*  Because of the limitation of length field in descriptors, the packet  */
-    /*  size could not be larger than 64K minus overhead size.                */
-    if ( aal5r_max_packet_size < 0 )
-        aal5r_max_packet_size = 0;
-    else if ( aal5r_max_packet_size >= 65536 - MAX_RX_FRAME_EXTRA_BYTES )
-        aal5r_max_packet_size = 65536 - MAX_RX_FRAME_EXTRA_BYTES;
-    if ( aal5r_min_packet_size < 0 )
-        aal5r_min_packet_size = 0;
-    else if ( aal5r_min_packet_size > aal5r_max_packet_size )
-        aal5r_min_packet_size = aal5r_max_packet_size;
-    if ( aal5s_max_packet_size < 0 )
-        aal5s_max_packet_size = 0;
-    else if ( aal5s_max_packet_size >= 65536 - MAX_TX_FRAME_EXTRA_BYTES )
-        aal5s_max_packet_size = 65536 - MAX_TX_FRAME_EXTRA_BYTES;
-    if ( aal5s_min_packet_size < 0 )
-        aal5s_min_packet_size = 0;
-    else if ( aal5s_min_packet_size > aal5s_max_packet_size )
-        aal5s_min_packet_size = aal5s_max_packet_size;
-
-    if ( dma_rx_descriptor_length < 2 )
-        dma_rx_descriptor_length = 2;
-    if ( dma_tx_descriptor_length < 2 )
-        dma_tx_descriptor_length = 2;
-    if ( dma_rx_clp1_descriptor_threshold < 0 )
-        dma_rx_clp1_descriptor_threshold = 0;
-    else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
-        dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
-}
-
-static struct atmdev_ops ppe_atm_ops = {
-    owner:      THIS_MODULE,
-    open:       ppe_open,
-    close:      ppe_close,
-    ioctl:      ppe_ioctl,
-    send:       ppe_send,
-    send_oam:   ppe_send_oam,
-    change_qos: ppe_change_qos,
-};
-
-int __init danube_ppe_init(void)
-{
-    int ret;
-    int port_num;
-
-    check_parameters();
-
-    ret = init_ppe_dev();
-    if ( ret )
-        goto INIT_PPE_DEV_FAIL;
-
-    clear_share_buffer();
-    init_rx_tables();
-    init_tx_tables();
-printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
-
-    for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
-        if ( ppe_dev.port[port_num].max_connections != 0 )
-        {
-            printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
-                       ppe_dev.port[port_num].dev = atm_dev_register("danube_atm", &ppe_atm_ops, -1, 0UL);
-            if ( !ppe_dev.port[port_num].dev )
-            {
-                printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
-                               ret = -EIO;
-                goto ATM_DEV_REGISTER_FAIL;
-            }
-            else
-            {
-                printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
-                               ppe_dev.port[port_num].dev->ci_range.vpi_bits = 8;
-                ppe_dev.port[port_num].dev->ci_range.vci_bits = 16;
-                ppe_dev.port[port_num].dev->link_rate = ppe_dev.port[port_num].tx_max_cell_rate;
-                ppe_dev.port[port_num].dev->dev_data = (void*)port_num;
-            }
-        }
-    /*  register interrupt handler  */
-    ret = request_irq(IFXMIPS_PPE_MBOX_INT, mailbox_irq_handler, IRQF_DISABLED, "ppe_mailbox_isr", NULL);
-    if ( ret )
-    {
-        if ( ret == -EBUSY )
-            printk("ppe: IRQ may be occupied by ETH2 driver, please reconfig to disable it.\n");
-        goto REQUEST_IRQ_IFXMIPS_PPE_MBOX_INT_FAIL;
-    }
-    disable_irq(IFXMIPS_PPE_MBOX_INT);
-
-  #if defined(CONFIG_PCI) && defined(USE_FIX_FOR_PCI_PPE) && USE_FIX_FOR_PCI_PPE
-    ret = request_irq(PPE_MAILBOX_IGU0_INT, pci_fix_irq_handler, SA_INTERRUPT, "ppe_pci_fix_isr", NULL);
-    if ( ret )
-        printk("failed in registering mailbox 0 interrupt (pci fix)\n");
-  #endif  //  defined(CONFIG_PCI) && defined(USE_FIX_FOR_PCI_PPE) && USE_FIX_FOR_PCI_PPE
-
-    ret = pp32_start();
-    if ( ret )
-        goto PP32_START_FAIL;
-
-    qsb_global_set();
-       HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
-    HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
-    HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
-
-    /*  create proc file    */
-    proc_file_create();
-
-    printk("ppe: ATM init succeeded (firmware version 1.1.0.2.1.13\n");
-    return 0;
-
-PP32_START_FAIL:
-
-    free_irq(IFXMIPS_PPE_MBOX_INT, NULL);
-REQUEST_IRQ_IFXMIPS_PPE_MBOX_INT_FAIL:
-ATM_DEV_REGISTER_FAIL:
-    clear_ppe_dev();
-INIT_PPE_DEV_FAIL:
-    printk("ppe: ATM init failed\n");
-    return ret;
-}
-
-void __exit danube_ppe_exit(void)
-{
-    int port_num;
-       register int l;
-       proc_file_delete();
-    HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
-    HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
-    HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
-    /*  idle for a while to finish running HTU search   */
-    for (l = 0; l < IDLE_CYCLE_NUMBER; l++ );
-    pp32_stop();
-    free_irq(IFXMIPS_PPE_MBOX_INT, NULL);
-    for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
-        if ( ppe_dev.port[port_num].max_connections != 0 )
-            atm_dev_deregister(ppe_dev.port[port_num].dev);
-    clear_ppe_dev();
-}
-
-module_init(danube_ppe_init);
-module_exit(danube_ppe_exit);
-
-MODULE_LICENSE("GPL");
-
diff --git a/package/ifxmips-atm/src/ifx_ppe_fw.h b/package/ifxmips-atm/src/ifx_ppe_fw.h
deleted file mode 100644 (file)
index af250f3..0000000
+++ /dev/null
@@ -1,426 +0,0 @@
-#ifndef __DANUBE_PPE_FW_H__2005_08_04__12_00__
-#define __DANUBE_PPE_FW_H__2005_08_04__12_00__
-
-
-/******************************************************************************
-**
-** FILE NAME    : danube_ppe_fw.h
-** PROJECT      : Danube
-** MODULES             : ATM (ADSL)
-**
-** DATE         : 1 AUG 2005
-** AUTHOR       : Xu Liang
-** DESCRIPTION  : ATM Driver (PP32 Firmware)
-** COPYRIGHT    :      Copyright (c) 2006
-**                     Infineon Technologies AG
-**                     Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-**    This program is free software; you can redistribute it and/or modify
-**    it under the terms of the GNU General Public License as published by
-**    the Free Software Foundation; either version 2 of the License, or
-**    (at your option) any later version.
-**
-** HISTORY
-** $Date        $Author         $Comment
-**  4 AUG 2005  Xu Liang        Initiate Version
-** 23 OCT 2006  Xu Liang        Add GPL header.
-*******************************************************************************/
-
-
-static u32 firmware_binary_code[] = {
-    0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
-    0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,
-    0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,
-    0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,
-    0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,
-    0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,
-    0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,
-    0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,
-    0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,
-    0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,
-    0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,
-    0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,
-    0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,
-    0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,
-    0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,
-    0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000,
-    0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080,
-    0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020,
-    0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,
-    0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000,
-    0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000,
-    0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848,
-    0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C,
-    0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A,
-    0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000,
-    0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE,
-    0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000,
-    0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002,
-    0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002,
-    0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000,
-    0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002,
-    0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2,
-    0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000,
-    0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960,
-    0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600,
-    0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000,
-    0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030,
-    0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031,
-    0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000,
-    0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604,
-    0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960,
-    0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A,
-    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912,
-    0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE,
-    0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000,
-    0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966,
-    0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
-    0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080,
-    0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000,
-    0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000,
-    0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000,
-    0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000,
-    0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C,
-    0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA,
-    0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000,
-    0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010,
-    0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000,
-    0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000,
-    0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822,
-    0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008,
-    0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000,
-    0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000,
-    0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018,
-    0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A,
-    0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002,
-    0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,
-    0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000,
-    0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
-    0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932,
-    0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000,
-    0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000,
-    0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080,
-    0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930,
-    0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916,
-    0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022,
-    0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8,
-    0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A,
-    0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000,
-    0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040,
-    0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000,
-    0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8,
-    0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000,
-    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000,
-    0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,
-    0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C,
-    0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C,
-    0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000,
-    0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA,
-    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000,
-    0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932,
-    0xCA400000, 0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000,
-    0xC0004934, 0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002,
-    0x6E684000, 0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002,
-    0x6E642000, 0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0,
-    0xDBA80000, 0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080,
-    0x00000000, 0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002,
-    0x6E640000, 0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030,
-    0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80,
-    0xC2800000, 0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006,
-    0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000,
-    0xC000100A, 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930,
-    0xCA02E010, 0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990053B0, 0xDA980000, 0xC6140000,
-    0xC6580000, 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000,
-    0x80000300, 0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000,
-    0x40100000, 0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000,
-    0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940,
-    0xCE400040, 0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172,
-    0x5A6C0010, 0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000,
-    0xC0004940, 0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040,
-    0x46610000, 0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000,
-    0xC2000000, 0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080,
-    0x46E50000, 0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2,
-    0x00000000, 0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068,
-    0xC7700208, 0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028,
-    0xC7700908, 0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944,
-    0xCF000000, 0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E,
-    0xCB400000, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004,
-    0xCB000080, 0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078,
-    0x00000000, 0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000,
-    0xC6E00010, 0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000,
-    0x8800FFFA, 0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930,
-    0xCA42E010, 0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000,
-    0xC2000000, 0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0,
-    0xC0004862, 0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C,
-    0xCE400000, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A,
-    0xCFC00000, 0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8,
-    0xC1220002, 0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000,
-    0xC0004934, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000,
-    0x58380008, 0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002,
-    0x7235A000, 0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000,
-    0xC760E718, 0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990060A8,
-    0xC0004828, 0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112,
-    0xC0004940, 0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A,
-    0xCA400000, 0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400,
-    0x8800FFFA, 0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 0x5C000200, 0xCE800000,
-    0xC000493E, 0xCA000000, 0xC2400000, 0x5838000C, 0xCE400000, 0x990060A8, 0xC0004830, 0xC9400000,
-    0xC6180000, 0xC0004930, 0xC6100080, 0xCD000080, 0x80000090, 0xC2400002, 0x58380008, 0xCE400008,
-    0xC0004944, 0xCF400000, 0x80000260, 0xC000493C, 0xCA400000, 0xDFE80000, 0x5A300018, 0xC0007200,
-    0x40200000, 0xCA000000, 0x58380008, 0xC6501080, 0xCD001080, 0x5838000A, 0xCE800000, 0x58380026,
-    0xCE000000, 0xC0004944, 0xCF400000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x80000020,
-    0x00000000, 0x990060A8, 0xC0004826, 0xC9400000, 0xC1800002, 0x8000FDC0, 0xC2000000, 0xC2400200,
-    0xDF600040, 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000,
-    0xDA980001, 0x00000000, 0xC0004934, 0xCA000000, 0x00000000, 0xC2800000, 0xA6020140, 0xC2400004,
-    0xC2000200, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFC2, 0x00000000, 0xC000491A, 0xC9800000,
-    0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, 0xD9980001,
-    0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xC2400200, 0xDF600040,
-    0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000, 0xDA980001,
-    0x00000000, 0x58380008, 0xCA400000, 0xC2000000, 0xCE000020, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE001080,
-    0x5838000A, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0000838, 0xC2500002,
-    0xCE440808, 0xC0004848, 0xCB840000, 0xC2000000, 0xC000082C, 0xCA040030, 0x5FB80002, 0xC0004848,
-    0xCF840000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840000, 0x00000000,
-    0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000DEC0, 0xC2000000, 0xDF600040, 0x5E200080, 0x84000252,
-    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480C, 0xCA000000, 0xC0004910,
-    0xCA400000, 0xC000492C, 0xCA800000, 0xC0004968, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0x76610000, 0x76A10000, 0x762D6000, 0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE,
-    0x762D6000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000,
-    0x62014008, 0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968,
-    0xCA400000, 0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
-    0x5911FE14, 0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002,
-    0xC2000000, 0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000,
-    0x46B18000, 0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20,
-    0x99005930, 0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400028A,
-    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC000492A,
-    0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0x76318000, 0x76718000, 0x840001EA, 0xC201FFFE, 0x76318000, 0x5AEC0002, 0x6B2D0010,
-    0x5EA00000, 0x84000002, 0x6A2D0000, 0x8000FFF8, 0xC7200000, 0x62016008, 0xC0004956, 0xCEC00000,
-    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000,
-    0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6EF4A000,
-    0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834000E, 0xC2000000, 0xCA0000E0, 0x58340008,
-    0xC2400000, 0xCA420080, 0x5834000C, 0xC2800000, 0xCA832018, 0x6E644010, 0x42250000, 0x4229E000,
-    0xC39A8008, 0x58340008, 0xCB809020, 0x58340008, 0xC2800000, 0xCA810018, 0x6EE0A000, 0x6EE44000,
-    0x46610000, 0x46E10000, 0x5A200008, 0x5A200E28, 0x42290000, 0xC6380068, 0xC6F81C20, 0x99005930,
-    0xDB980000, 0xDBD80001, 0x00000000, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,
-    0xCC400000, 0xC0001A1C, 0xCA000000, 0xC2400008, 0x6A452000, 0x76610000, 0x8400D91A, 0xC0000A28,
-    0xC3800000, 0xCB840030, 0xC0000A14, 0xC3400000, 0xCB440030, 0xC0004880, 0xCB040000, 0xB7B4D8CA,
-    0x58041802, 0xCAC00000, 0xA7000018, 0x00000000, 0x00000000, 0xA6C8D898, 0xC2800000, 0xC6E80020,
-    0x80000030, 0xC2800000, 0xC7282020, 0xC000490E, 0xCA400000, 0x6BE9E000, 0x00000000, 0x77E52000,
-    0x8400D848, 0x6EA0A000, 0x6E944000, 0x45610000, 0x46A10000, 0x5A204E20, 0x5820000C, 0xCA000000,
-    0xC0004946, 0xCE800000, 0xA6220348, 0x00000000, 0xC2200060, 0xC0004948, 0xCE000010, 0xCE001040,
-    0xC240000A, 0xC000494A, 0xCE400000, 0xC2B60002, 0xC0004964, 0xCE801B08, 0x99005C00, 0xC00048A0,
-    0xC8840000, 0x00000000, 0xC0004946, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000,
-    0x4579C000, 0x47F9C000, 0x5BB84E20, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005708,
-    0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000, 0x00000000,
-    0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,
-    0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
-    0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874,
-    0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000,
-    0xC7400000, 0xCE000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
-    0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
-    0x990060A8, 0xC0004836, 0xC9400000, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8,
-    0x00000000, 0xC1220002, 0xD90C0000, 0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002,
-    0xCE440808, 0x58880002, 0xB608FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D498, 0xC0004946,
-    0xCBC00000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002,
-    0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000,
-    0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000,
-    0xC3400000, 0xC6340008, 0xC000494E, 0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020,
-    0x6F304000, 0x43298000, 0xC000493C, 0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000,
-    0xC2800000, 0xC66AE028, 0xC0004954, 0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000,
-    0x84000152, 0x462D2000, 0x8800011A, 0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A,
-    0x00000000, 0x800000A8, 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC3400002,
-    0xC000494E, 0xCF400000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
-    0xC2800002, 0x6ABD4000, 0x7E814000, 0x76A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0xC2200060, 0xC0004948, 0xCE001040, 0xC2000000, 0xC000494C, 0xCE000000, 0x80000068,
-    0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001,
-    0xC7800000, 0xC2200058, 0xC0004948, 0xCE001040, 0xC2000002, 0xC000494C, 0xCE000000, 0xC2000006,
-    0xC0001006, 0xCE000000, 0x5838000A, 0xCA400000, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE000000,
-    0xC000100A, 0xCE400000, 0xC0004954, 0xCA800000, 0xC200000C, 0xC000494A, 0xCE000000, 0xC0004948,
-    0xCE800010, 0xC2B60000, 0xC0004964, 0xCE800000, 0x99005C00, 0xC00048A0, 0xC8840000, 0x00000000,
-    0xC0004946, 0xCBC00000, 0xC000494C, 0xCA000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,
-    0x5BB84E20, 0x5E200000, 0x840000E2, 0x00000000, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000,
-    0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000,
-    0x00000000, 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
-    0x00000000, 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14,
-    0x15000000, 0xC000493C, 0xCA800000, 0xC000494E, 0xCAC00000, 0xC3000018, 0xC3400006, 0x5E200000,
-    0x84000012, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1080, 0xC72C0420, 0xC76C0818,
-    0x58380010, 0xCA800000, 0x58380008, 0xCEC00000, 0xC6280108, 0xC0004874, 0xC8040000, 0x6C908000,
-    0x44908000, 0x44908000, 0x40100000, 0xCB000000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE800000,
-    0xC0004952, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0xC000494C,
-    0xCA000000, 0xC0004950, 0xCAC00000, 0x5E200000, 0x84000052, 0xDFE80000, 0x7E814000, 0x5834001A,
-    0xCE800000, 0x990060A8, 0xC0004834, 0xC9400000, 0xC1800002, 0x990060A8, 0xC0004838, 0xC9400000,
-    0xC6D80000, 0xC1220002, 0xD90C0000, 0x5E200000, 0x84000028, 0x5838002C, 0xCB000000, 0xDFE80000,
-    0x00000000, 0x58380014, 0xCF000000, 0x80000000, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE800000,
-    0xC3000000, 0xC0000A14, 0xCB040030, 0xC2D00002, 0xC0000A28, 0xCEC40808, 0xC000494E, 0xCA800000,
-    0x58880002, 0xB4B0FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x5EA80000, 0x8400013A, 0x5E200000,
-    0x84000128, 0xC000493C, 0xCA800000, 0x00000000, 0x00000000, 0x5AA80060, 0xCE800000, 0x99005D40,
-    0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC0004952,
-    0xCAC00000, 0x58380000, 0xCA800000, 0xC30C0002, 0xC7F00020, 0xA6800078, 0x00000000, 0x00000000,
-    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0001800, 0xCA000000, 0x00000000, 0x00000000,
-    0xA60CFFCA, 0xC6F00508, 0xC6B0C408, 0xCF000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
-    0x8000CB48, 0xDCBC0001, 0x5FFC0000, 0x8400003A, 0xC3800002, 0xDB880001, 0x5FFC0004, 0x8400C4B2,
-    0xC3800000, 0xDB880001, 0xC3CE0002, 0xC0000800, 0xCFC00708, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14,
-    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
-    0x40080000, 0xCBC00000, 0xC4380000, 0x00000000, 0xC000480E, 0xCA000000, 0xC0004858, 0xCB440000,
-    0x00000000, 0x00000000, 0x46350000, 0x88000098, 0x00000000, 0xA7C00028, 0xC0004854, 0xC1000002,
-    0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x800000C0, 0x00000000, 0xA7D20118, 0x00000000,
-    0xC7E14048, 0xC2400000, 0xC6246030, 0xC200006A, 0x46610000, 0xC6240038, 0xC0000810, 0xCE440038,
-    0x8000FF58, 0xC2000000, 0xC0000808, 0xCA040018, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x5A200002,
-    0x5E600010, 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002,
-    0xC0000818, 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005348, 0xC0004848, 0xC9440000,
-    0xC1800000, 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005C8, 0x5B740002, 0xC0004858, 0xCF440000,
-    0xC7800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030,
-    0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980540, 0x00000000, 0xC0800000, 0x80000530,
-    0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000,
-    0xA7C00110, 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C,
-    0xCE040000, 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000,
-    0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980430, 0x00000000,
-    0xC0800000, 0x80000420, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000,
-    0xC2000000, 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000,
-    0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000,
-    0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C,
-    0xCE040000, 0x80000320, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
-    0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA780022A, 0x00000000, 0x00000000, 0xA7C001EA,
-    0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, 0x00000000, 0xC0004850, 0xCA040000,
-    0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, 0xCE040000, 0xB624008A, 0x00000000,
-    0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, 0xCE040008, 0xC0004848, 0xC9440000,
-    0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8,
-    0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C,
-    0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000,
-    0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000,
-    0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70,
-    0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008,
-    0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002,
-    0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0,
-    0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838,
-    0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000,
-    0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8,
-    0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712,
-    0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000,
-    0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000,
-    0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004,
-    0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914,
-    0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8,
-    0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000,
-    0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900,
-    0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000,
-    0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000,
-    0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80,
-    0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080,
-    0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000,
-    0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080,
-    0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8,
-    0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000,
-    0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000,
-    0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002,
-    0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020,
-    0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,
-    0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000,
-    0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080,
-    0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8,
-    0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080,
-    0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000,
-    0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000,
-    0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000,
-    0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C,
-    0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000,
-    0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028,
-    0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100,
-    0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000,
-    0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
-    0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000,
-    0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508,
-    0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002,
-    0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004,
-    0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E,
-    0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000,
-    0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002,
-    0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912,
-    0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A,
-    0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020,
-    0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000,
-    0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000,
-    0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000,
-    0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
-    0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18,
-    0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200,
-    0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000,
-    0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200,
-    0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010,
-    0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000,
-    0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80,
-    0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000,
-    0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000,
-    0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080,
-    0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028,
-    0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A,
-    0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000,
-    0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C,
-    0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000,
-    0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000,
-    0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA,
-    0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08,
-    0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20,
-    0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002,
-    0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080,
-    0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000,
-    0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000,
-    0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000,
-    0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000,
-    0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8,
-    0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808,
-    0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C,
-    0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000,
-    0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002,
-    0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0,
-    0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001,
-    0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001,
-    0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002,
-    0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000,
-    0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
-    0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E,
-    0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000,
-    0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000,
-    0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948,
-    0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000,
-    0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080,
-    0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000,
-    0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002,
-    0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000,
-    0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001,
-    0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008,
-    0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,
-    0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
-    0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028,
-    0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0,
-    0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1,
-    0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000,
-    0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA,
-    0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000,
-    0x00000000,
-};
-
-static u32 firmware_binary_data[] = {
-};
-
-
-#endif  //  __DANUBE_PPE_FW_H__2005_08_04__12_00__
-
diff --git a/package/ifxmips-atm/src/irq.c b/package/ifxmips-atm/src/irq.c
deleted file mode 100644 (file)
index 0265168..0000000
+++ /dev/null
@@ -1,506 +0,0 @@
-#include <linux/atmdev.h>
-#include <linux/irq.h>
-
-#include "common.h"
-
-void mailbox_signal(unsigned int channel, int is_tx)
-{
-    if(is_tx)
-    {
-        while(MBOX_IGU3_ISR_ISR(channel + 16));
-        *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(channel + 16);
-    } else  {
-        while(MBOX_IGU3_ISR_ISR(channel));
-        *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(channel);
-    }
-}
-
-static int mailbox_rx_irq_handler(unsigned int channel, unsigned int *len)
-{
-    int conn;
-    int skb_base;
-    register struct rx_descriptor reg_desc;
-    struct rx_descriptor *desc;
-    struct sk_buff *skb;
-    struct atm_vcc *vcc;
-    struct rx_inband_trailer *trailer;
-
-    /*  get sk_buff pointer and descriptor  */
-    skb_base = ppe_dev.dma.rx_descriptor_number * channel + ppe_dev.dma.rx_desc_read_pos[channel];
-    desc = &ppe_dev.dma.rx_descriptor_base[skb_base];
-    reg_desc = *desc;
-    if ( reg_desc.own || !reg_desc.c )
-        return -EAGAIN;
-
-    if ( ++ppe_dev.dma.rx_desc_read_pos[channel] == ppe_dev.dma.rx_descriptor_number )
-        ppe_dev.dma.rx_desc_read_pos[channel] = 0;
-
-    skb = *(struct sk_buff **)((((u32)reg_desc.dataptr << 2) | KSEG0) - 4);
-    if ( (u32)skb <= 0x80000000 )
-    {
-        int key = 0;
-        printk("skb problem: skb = %08X, system is panic!\n", (u32)skb);
-        for ( ; !key; );
-    }
-
-    conn = reg_desc.id;
-
-    if ( conn == ppe_dev.oam_rx_queue )
-    {
-        /*  OAM */
-        struct uni_cell_header *header = (struct uni_cell_header *)skb->data;
-
-        if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
-            conn = find_vpivci(header->vpi, header->vci);
-        else if ( header->vci == 0x03 || header->vci == 0x04 )
-            conn = find_vpi(header->vpi);
-        else
-            conn = -1;
-
-        if ( conn >= 0 && ppe_dev.connection[conn].vcc != NULL )
-        {
-            vcc = ppe_dev.connection[conn].vcc;
-            ppe_dev.connection[conn].access_time = xtime;
-            if ( vcc->push_oam != NULL )
-                vcc->push_oam(vcc, skb->data);
-        }
-
-        /*  don't need resize   */
-    }
-    else
-    {
-        if ( len )
-            *len = 0;
-
-        if ( ppe_dev.connection[conn].vcc != NULL )
-        {
-            vcc = ppe_dev.connection[conn].vcc;
-
-            if ( !reg_desc.err )
-                if ( vcc->qos.aal == ATM_AAL5 )
-                {
-                    /*  AAL5 packet */
-                    resize_skb_rx(skb, reg_desc.datalen + reg_desc.byteoff, 0);
-                    skb_reserve(skb, reg_desc.byteoff);
-                    skb_put(skb, reg_desc.datalen);
-
-                    if ( (u32)ATM_SKB(skb) <= 0x80000000 )
-                    {
-                        int key = 0;
-                        printk("ATM_SKB(skb) problem: ATM_SKB(skb) = %08X, system is panic!\n", (u32)ATM_SKB(skb));
-                        for ( ; !key; );
-                    }
-                    ATM_SKB(skb)->vcc = vcc;
-                    ppe_dev.connection[conn].access_time = xtime;
-                    if ( atm_charge(vcc, skb->truesize) )
-                    {
-                        struct sk_buff *new_skb;
-
-                        new_skb = alloc_skb_rx();
-                        if ( new_skb )
-                        {
-
-                            UPDATE_VCC_STAT(conn, rx_pdu, 1);
-
-                            ppe_dev.mib.wrx_pdu++;
-                            if ( vcc->stats )
-                                atomic_inc(&vcc->stats->rx);
-                            vcc->push(vcc, skb);
-                            {
-                                struct k_atm_aal_stats stats = *vcc->stats;
-                                int flag = 0;
-
-                                vcc->push(vcc, skb);
-                                if ( vcc->stats->rx.counter != stats.rx.counter )
-                                {
-                                    printk("vcc->stats->rx (diff) = %d", vcc->stats->rx.counter - stats.rx.counter);
-                                    flag++;
-                                }
-                                if ( vcc->stats->rx_err.counter != stats.rx_err.counter )
-                                {
-                                    printk("vcc->stats->rx_err (diff) = %d", vcc->stats->rx_err.counter - stats.rx_err.counter);
-                                    flag++;
-                                }
-                                if ( vcc->stats->rx_drop.counter != stats.rx_drop.counter )
-                                {
-                                    printk("vcc->stats->rx_drop (diff) = %d", vcc->stats->rx_drop.counter - stats.rx_drop.counter);
-                                    flag++;
-                                }
-                                if ( vcc->stats->tx.counter != stats.tx.counter )
-                                {
-                                    printk("vcc->stats->tx (diff) = %d", vcc->stats->tx.counter - stats.tx.counter);
-                                    flag++;
-                                }
-                                if ( vcc->stats->tx_err.counter != stats.tx_err.counter )
-                                {
-                                    printk("vcc->stats->tx_err (diff) = %d", vcc->stats->tx_err.counter - stats.tx_err.counter);
-                                    flag++;
-                                }
-                                if ( !flag )
-                                    printk("vcc->stats not changed");
-                            }
-                            reg_desc.dataptr = (u32)new_skb->data >> 2;
-
-                            if ( len )
-                                *len = reg_desc.datalen;
-                        }
-                        else
-                        {
-                            /*  no sk buffer    */
-                            UPDATE_VCC_STAT(conn, rx_sw_drop_pdu, 1);
-
-                            ppe_dev.mib.wrx_drop_pdu++;
-                            if ( vcc->stats )
-                                atomic_inc(&vcc->stats->rx_drop);
-
-                            resize_skb_rx(skb, ppe_dev.aal5.rx_buffer_size, 0);
-                        }
-                    }
-                    else
-                    {
-                        /*  no enough space */
-                        UPDATE_VCC_STAT(conn, rx_sw_drop_pdu, 1);
-
-                        ppe_dev.mib.wrx_drop_pdu++;
-                        if ( vcc->stats )
-                            atomic_inc(&vcc->stats->rx_drop);
-
-                        resize_skb_rx(skb, ppe_dev.aal5.rx_buffer_size, 0);
-                    }
-                }
-                else
-                {
-                    /*  AAL0 cell   */
-                    resize_skb_rx(skb, CELL_SIZE, 1);
-                    skb_put(skb, CELL_SIZE);
-
-                    ATM_SKB(skb)->vcc = vcc;
-                    ppe_dev.connection[conn].access_time = xtime;
-                    if ( atm_charge(vcc, skb->truesize) )
-                    {
-                        struct sk_buff *new_skb;
-
-                        new_skb = alloc_skb_rx();
-                        if ( new_skb )
-                        {
-                            if ( vcc->stats )
-                                atomic_inc(&vcc->stats->rx);
-                            vcc->push(vcc, skb);
-                            reg_desc.dataptr = (u32)new_skb->data >> 2;
-
-                            if ( len )
-                                *len = CELL_SIZE;
-                        }
-                        else
-                        {
-                            if ( vcc->stats )
-                                atomic_inc(&vcc->stats->rx_drop);
-                            resize_skb_rx(skb, ppe_dev.aal5.rx_buffer_size, 0);
-                        }
-                    }
-                    else
-                    {
-                        if ( vcc->stats )
-                            atomic_inc(&vcc->stats->rx_drop);
-                        resize_skb_rx(skb, ppe_dev.aal5.rx_buffer_size, 0);
-                    }
-                }
-            else
-            {
-printk("reg_desc.err\n");
-
-                /*  drop packet/cell    */
-                if ( vcc->qos.aal == ATM_AAL5 )
-                {
-                    UPDATE_VCC_STAT(conn, rx_err_pdu, 1);
-
-                    trailer = (struct rx_inband_trailer *)((u32)skb->data + ((reg_desc.byteoff + reg_desc.datalen + DMA_ALIGNMENT - 1) & ~ (DMA_ALIGNMENT - 1)));
-                    if ( trailer->stw_crc )
-                        ppe_dev.connection[conn].aal5_vcc_crc_err++;
-                    if ( trailer->stw_ovz )
-                        ppe_dev.connection[conn].aal5_vcc_oversize_sdu++;
-                }
-                if ( vcc->stats )
-                    atomic_inc(&vcc->stats->rx_err);
-                /*  don't need resize   */
-            }
-        }
-        else
-        {
-printk("ppe_dev.connection[%d].vcc == NULL\n", conn);
-
-            ppe_dev.mib.wrx_drop_pdu++;
-
-            /*  don't need resize   */
-        }
-    }
-
-    reg_desc.byteoff = 0;
-    reg_desc.datalen = ppe_dev.aal5.rx_buffer_size;
-    reg_desc.own = 1;
-    reg_desc.c   = 0;
-
-    /*  write discriptor to memory  */
-    *desc = reg_desc;
-
-printk("leave mailbox_rx_irq_handler");
-
-    return 0;
-}
-
-static inline void mailbox_tx_irq_handler(unsigned int conn)
-{
-       if ( ppe_dev.dma.tx_desc_alloc_flag[conn] )
-    {
-        int desc_base;
-        int *release_pos;
-        struct sk_buff *skb;
-
-        release_pos = &ppe_dev.dma.tx_desc_release_pos[conn];
-        desc_base = ppe_dev.dma.tx_descriptor_number * (conn - QSB_QUEUE_NUMBER_BASE) + *release_pos;
-        while ( !ppe_dev.dma.tx_descriptor_base[desc_base].own )
-        {
-            skb = ppe_dev.dma.tx_skb_pointers[desc_base];
-
-            ppe_dev.dma.tx_descriptor_base[desc_base].own = 1;  //  pretend PP32 hold owner bit, so that won't be released more than once, so allocation process don't check this bit
-
-            if ( ++*release_pos == ppe_dev.dma.tx_descriptor_number )
-                *release_pos = 0;
-
-            if ( *release_pos == ppe_dev.dma.tx_desc_alloc_pos[conn] )
-            {
-                ppe_dev.dma.tx_desc_alloc_flag[conn] = 0;
-
-               atm_free_tx_skb_vcc(skb);
-                break;
-            }
-
-            if ( *release_pos == 0 )
-                desc_base = ppe_dev.dma.tx_descriptor_number * (conn - QSB_QUEUE_NUMBER_BASE);
-            else
-                desc_base++;
-
-           atm_free_tx_skb_vcc(skb);
-        }
-    }
-}
-
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-static inline int check_desc_valid(unsigned int channel)
-{
-    int skb_base;
-    struct rx_descriptor *desc;
-
-    skb_base = ppe_dev.dma.rx_descriptor_number * channel + ppe_dev.dma.rx_desc_read_pos[channel];
-    desc = &ppe_dev.dma.rx_descriptor_base[skb_base];
-    return !desc->own && desc->c ? 1 : 0;
-}
-#endif
-
-irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
-{
-    int channel_mask;   /*  DMA channel accordant IRQ bit mask  */
-    int channel;
-    unsigned int rx_irq_number[MAX_RX_DMA_CHANNEL_NUMBER] = {0};
-    unsigned int total_rx_irq_number = 0;
-
-printk("mailbox_irq_handler");
-
-    if ( !*MBOX_IGU1_ISR )
-        return IRQ_RETVAL(1);
-
-    channel_mask = 1;
-    channel = 0;
-    while ( channel < ppe_dev.dma.rx_total_channel_used )
-    {
-        if ( (*MBOX_IGU1_ISR & channel_mask) )
-        {
-            /*  RX  */
-            /*  clear IRQ   */
-            *MBOX_IGU1_ISRC = channel_mask;
-printk("  RX: *MBOX_IGU1_ISR = 0x%08X\n", *MBOX_IGU1_ISR);
-            /*  wait for mailbox cleared    */
-            while ( (*MBOX_IGU3_ISR & channel_mask) );
-
-            /*  shadow the number of valid descriptor   */
-            rx_irq_number[channel] = WRX_DMA_CHANNEL_CONFIG(channel)->vlddes;
-
-            total_rx_irq_number += rx_irq_number[channel];
-
-printk("total_rx_irq_number = %d", total_rx_irq_number);
-printk("vlddes = %d, rx_irq_number[%d] = %d, total_rx_irq_number = %d\n", WRX_DMA_CHANNEL_CONFIG(channel)->vlddes, channel, rx_irq_number[channel], total_rx_irq_number);
-        }
-
-        channel_mask <<= 1;
-        channel++;
-    }
-
-    channel_mask = 1 << (16 + QSB_QUEUE_NUMBER_BASE);
-    channel = QSB_QUEUE_NUMBER_BASE;
-    while ( channel - QSB_QUEUE_NUMBER_BASE < ppe_dev.dma.tx_total_channel_used )
-    {
-        if ( (*MBOX_IGU1_ISR & channel_mask) )
-        {
-//            if ( channel != 1 )
-//            {
-printk("TX irq error\n");
-//                while ( 1 )
-//                {
-//                }
-//            }
-            /*  TX  */
-            /*  clear IRQ   */
-            *MBOX_IGU1_ISRC = channel_mask;
-printk("  TX: *MBOX_IGU1_ISR = 0x%08X\n", *MBOX_IGU1_ISR);
-            mailbox_tx_irq_handler(channel);
-        }
-
-        channel_mask <<= 1;
-        channel++;
-    }
-
-  #if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    channel = 0;
-    while ( total_rx_irq_number )
-    {
-        switch ( channel )
-        {
-        case RX_DMA_CH_CBR:
-        case RX_DMA_CH_OAM:
-            /*  handle it as soon as possible   */
-            while ( rx_irq_number[channel] != 0 && mailbox_rx_irq_handler(channel, NULL) == 0 )
-            {
-                rx_irq_number[channel]--;
-                total_rx_irq_number--;
-printk("RX_DMA_CH_CBR, total_rx_irq_number = %d", total_rx_irq_number);
-printk("RX_DMA_CH_CBR, total_rx_irq_number = %d, rx_irq_number[%d] = %d\n", total_rx_irq_number, channel, rx_irq_number[channel]);
-                /*  signal firmware that descriptor is updated */
-                mailbox_signal(channel, 0);
-            }
-//            if ( rx_irq_number[channel] != 0 )
-printk("RX_DMA_CH_CBR, rx_irq_number[channel] = %d", rx_irq_number[channel]);
-            break;
-        case RX_DMA_CH_VBR_RT:
-            /*  WFQ */
-            if ( rx_irq_number[RX_DMA_CH_VBR_RT] != 0
-                && (rx_irq_number[RX_DMA_CH_VBR_NRT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_NRT) || ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] < ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT])
-                && (rx_irq_number[RX_DMA_CH_AVR] == 0 || !check_desc_valid(RX_DMA_CH_AVR) || ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] < ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT])
-            )
-            {
-                unsigned int len;
-
-                if ( mailbox_rx_irq_handler(RX_DMA_CH_VBR_RT, &len) == 0 )
-                {
-                    rx_irq_number[RX_DMA_CH_VBR_RT]--;
-                    total_rx_irq_number--;
-printk("RX_DMA_CH_VBR_RT, total_rx_irq_number = %d", total_rx_irq_number);
-printk("RX_DMA_CH_VBR_RT, total_rx_irq_number = %d, rx_irq_number[%d] = %d\n", total_rx_irq_number, channel, rx_irq_number[channel]);
-                    /*  signal firmware that descriptor is updated */
-                    mailbox_signal(channel, 0);
-
-                    len = (len + CELL_SIZE - 1) / CELL_SIZE;
-                    if ( ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] <= len )
-                        ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_RT] + ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] - len;
-                }
-            }
-//            if ( rx_irq_number[channel] != 0 )
-//            {
-printk("RX_DMA_CH_VBR_RT, rx_irq_number[channel] = %d, total_rx_irq_number = %d", rx_irq_number[channel], total_rx_irq_number);
-//                rx_irq_number[channel] = 0;
-//                total_rx_irq_number = 0;
-//            }
-            break;
-        case RX_DMA_CH_VBR_NRT:
-            /*  WFQ */
-            if ( rx_irq_number[RX_DMA_CH_VBR_NRT] != 0
-                && (rx_irq_number[RX_DMA_CH_VBR_RT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_RT) || ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] < ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT])
-                && (rx_irq_number[RX_DMA_CH_AVR] == 0 || !check_desc_valid(RX_DMA_CH_AVR) || ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] < ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT])
-            )
-            {
-                unsigned int len;
-
-                if ( mailbox_rx_irq_handler(RX_DMA_CH_VBR_NRT, &len) == 0 )
-                {
-                    rx_irq_number[RX_DMA_CH_VBR_NRT]--;
-                    total_rx_irq_number--;
-printk("RX_DMA_CH_VBR_NRT, total_rx_irq_number = %d", total_rx_irq_number);
-printk("RX_DMA_CH_VBR_NRT, total_rx_irq_number = %d, rx_irq_number[%d] = %d\n", total_rx_irq_number, channel, rx_irq_number[channel]);
-                    /*  signal firmware that descriptor is updated */
-                    mailbox_signal(channel, 0);
-
-                    len = (len + CELL_SIZE - 1) / CELL_SIZE;
-                    if ( ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] <= len )
-                        ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_NRT] + ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] - len;
-                }
-            }
-//            if ( rx_irq_number[channel] != 0 )
-printk("RX_DMA_CH_VBR_NRT, rx_irq_number[channel] = %d", rx_irq_number[channel]);
-            break;
-        case RX_DMA_CH_AVR:
-            /*  WFQ */
-            if ( rx_irq_number[RX_DMA_CH_AVR] != 0
-                && (rx_irq_number[RX_DMA_CH_VBR_RT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_RT) || ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] < ppe_dev.dma.rx_weight[RX_DMA_CH_AVR])
-                && (rx_irq_number[RX_DMA_CH_VBR_NRT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_NRT) || ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] < ppe_dev.dma.rx_weight[RX_DMA_CH_AVR])
-            )
-            {
-                unsigned int len;
-
-                if ( mailbox_rx_irq_handler(RX_DMA_CH_AVR, &len) == 0 )
-                {
-                    rx_irq_number[RX_DMA_CH_AVR]--;
-                    total_rx_irq_number--;
-printk("RX_DMA_CH_AVR, total_rx_irq_number = %d", total_rx_irq_number);
-printk("RX_DMA_CH_AVR, total_rx_irq_number = %d, rx_irq_number[%d] = %d\n", total_rx_irq_number, channel, rx_irq_number[channel]);
-                    /*  signal firmware that descriptor is updated */
-                    mailbox_signal(channel, 0);
-
-                    len = (len + CELL_SIZE - 1) / CELL_SIZE;
-                    if ( ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] <= len )
-                        ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_AVR] + ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] - len;
-                }
-            }
-//            if ( rx_irq_number[channel] != 0 )
-printk("RX_DMA_CH_AVR, rx_irq_number[channel] = %d", rx_irq_number[channel]);
-            break;
-        case RX_DMA_CH_UBR:
-        default:
-            /*  Handle it when all others are handled or others are not available to handle.    */
-            if ( rx_irq_number[channel] != 0
-                && (rx_irq_number[RX_DMA_CH_VBR_RT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_RT))
-                && (rx_irq_number[RX_DMA_CH_VBR_NRT] == 0 || !check_desc_valid(RX_DMA_CH_VBR_NRT))
-                && (rx_irq_number[RX_DMA_CH_AVR] == 0 || !check_desc_valid(RX_DMA_CH_AVR)) )
-                if ( mailbox_rx_irq_handler(channel, NULL) == 0 )
-                {
-                    rx_irq_number[channel]--;
-                    total_rx_irq_number--;
-printk("RX_DMA_CH_UBR, total_rx_irq_number = %d, rx_irq_number[%d] = %d", total_rx_irq_number, channel, rx_irq_number[channel]);
-printk("RX_DMA_CH_UBR, total_rx_irq_number = %d, rx_irq_number[%d] = %d\n", total_rx_irq_number, channel, rx_irq_number[channel]);
-                    /*  signal firmware that descriptor is updated */
-                    mailbox_signal(channel, 0);
-                }
-printk("RX_DMA_CH_UBR, rx_irq_number[channel] = %d", rx_irq_number[channel]);
-        }
-
-        if ( ++channel == ppe_dev.dma.rx_total_channel_used )
-            channel = 0;
-    }
-  #else
-    channel = 0;
-    while ( total_rx_irq_number )
-    {
-        while ( rx_irq_number[channel] != 0 && mailbox_rx_irq_handler(channel, NULL) == 0 )
-        {
-            rx_irq_number[channel]--;
-            total_rx_irq_number--;
-            /*  signal firmware that descriptor is updated */
-            mailbox_signal(channel, 0);
-        }
-
-        if ( ++channel == ppe_dev.dma.rx_total_channel_used )
-            channel = 0;
-    }
-  #endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-       return IRQ_RETVAL(1);
-}
-
-
diff --git a/package/ifxmips-atm/src/ppe.c b/package/ifxmips-atm/src/ppe.c
deleted file mode 100644 (file)
index 65e4be9..0000000
+++ /dev/null
@@ -1,838 +0,0 @@
-#include <asm/mach-ifxmips/cgu.h>
-#include "common.h"
-
-#include "ifx_ppe_fw.h"
-static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int connection)
-{
-
-    u32 qsb_clk = cgu_get_fpi_bus_clock(2);         /*  FPI configuration 2 (slow FPI bus) */
-       union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
-    union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
-    u32 tmp;
-
-    /*
-     *  Peak Cell Rate (PCR) Limiter
-     */
-    if ( qos->txtp.max_pcr == 0 )
-        qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
-    else
-    {
-        /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
-        tmp = ((qsb_clk * ppe_dev.qsb.tstepc) >> 5) / qos->txtp.max_pcr + 1;
-        /*  check if overflow takes place   */
-        qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
-    }
-    /*
-     *  Weighted Fair Queueing Factor (WFQF)
-     */
-    switch ( qos->txtp.traffic_class )
-    {
-    case ATM_CBR:
-    case ATM_VBR_RT:
-        /*  real time queue gets weighted fair queueing bypass  */
-        qsb_queue_parameter_table.bit.wfqf = 0;
-        break;
-    case ATM_VBR_NRT:
-    case ATM_UBR_PLUS:
-        /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
-        /*  WFQF is maximum cell rate / garenteed cell rate                                             */
-        /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
-        if ( qos->txtp.min_pcr == 0 )
-            qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
-        else
-        {
-            tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
-            if ( tmp == 0 )
-                qsb_queue_parameter_table.bit.wfqf = 1;
-            else if ( tmp > QSB_WFQ_NONUBR_MAX )
-                qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
-            else
-                qsb_queue_parameter_table.bit.wfqf = tmp;
-        }
-        break;
-    default:
-    case ATM_UBR:
-        qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
-    }
-    /*
-     *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
-     */
-    if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT )
-    {
-        if ( qos->txtp.scr == 0 )
-        {
-            /*  disable shaper  */
-            qsb_queue_vbr_parameter_table.bit.taus = 0;
-            qsb_queue_vbr_parameter_table.bit.ts = 0;
-        }
-        else
-        {
-            /*  Cell Loss Priority  (CLP)   */
-            if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
-                /*  CLP1    */
-                qsb_queue_parameter_table.bit.vbr = 1;
-            else
-                /*  CLP0    */
-                qsb_queue_parameter_table.bit.vbr = 0;
-            /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
-            tmp = ((qsb_clk * ppe_dev.qsb.tstepc) >> 5) / qos->txtp.scr + 1;
-            qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
-            tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
-            if ( tmp == 0 )
-                qsb_queue_vbr_parameter_table.bit.taus = 1;
-            else if ( tmp > QSB_TAUS_MAX )
-                qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
-            else
-                qsb_queue_vbr_parameter_table.bit.taus = tmp;
-        }
-    }
-    else
-    {
-        qsb_queue_vbr_parameter_table.bit.taus = 0;
-        qsb_queue_vbr_parameter_table.bit.ts = 0;
-    }
-
-    /*  Queue Parameter Table (QPT) */
-    *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
-    *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
-    *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(connection);
-    /*  Queue VBR Paramter Table (QVPT) */
-    *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
-    *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
-    *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(connection);
-
-}
-
-
-static inline void u64_add_u32(ppe_u64_t opt1, u32 opt2,ppe_u64_t *ret)
-{
-    ret->l = opt1.l + opt2;
-    if ( ret->l < opt1.l || ret->l < opt2 )
-        ret->h++;
-}
-
-int find_vcc(struct atm_vcc *vcc)
-{
-       int i;
-       struct connection *connection = ppe_dev.connection;
-       int max_connections = ppe_dev.port[(int)vcc->dev->dev_data].max_connections;
-       u32 occupation_table = ppe_dev.port[(int)vcc->dev->dev_data].connection_table;
-       int base = ppe_dev.port[(int)vcc->dev->dev_data].connection_base;
-       for ( i = 0; i < max_connections; i++, base++ )
-               if ( (occupation_table & (1 << i))
-                       && connection[base].vcc == vcc )
-                       return base;
-       return -1;
-}
-
-int find_vpi(unsigned int vpi)
-{
-    int i, j;
-    struct connection *connection = ppe_dev.connection;
-    struct port *port;
-    int base;
-
-    port = ppe_dev.port;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++, port++ )
-    {
-        base = port->connection_base;
-        for ( j = 0; j < port->max_connections; j++, base++ )
-            if ( (port->connection_table & (1 << j))
-                && connection[base].vcc != NULL
-                && vpi == connection[base].vcc->vpi )
-                return base;
-    }
-    return -1;
-}
-
-int find_vpivci(unsigned int vpi, unsigned int vci)
-{
-    int i, j;
-    struct connection *connection = ppe_dev.connection;
-    struct port *port;
-    int base;
-
-    port = ppe_dev.port;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++, port++ )
-    {
-        base = port->connection_base;
-        for ( j = 0; j < port->max_connections; j++, base++ )
-            if ( (port->connection_table & (1 << j))
-                && connection[base].vcc != NULL
-                && vpi == connection[base].vcc->vpi
-                && vci == connection[base].vcc->vci )
-                return base;
-    }
-    return -1;
-}
-
-
-static inline void clear_htu_entry(unsigned int connection)
-{
-    HTU_ENTRY(connection - QSB_QUEUE_NUMBER_BASE + OAM_HTU_ENTRY_NUMBER)->vld = 0;
-}
-
-static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int connection, int aal5)
-{
-    struct htu_entry htu_entry = {  res1:       0x00,
-                                    pid:        ppe_dev.connection[connection].port & 0x01,
-                                    vpi:        vpi,
-                                    vci:        vci,
-                                    pti:        0x00,
-                                    vld:        0x01};
-
-    struct htu_mask htu_mask = {    set:        0x03,
-                                    pid_mask:   0x02,
-                                    vpi_mask:   0x00,
-                                    vci_mask:   0x0000,
-                                    pti_mask:   0x03,   //  0xx, user data
-                                    clear:      0x00};
-
-    struct htu_result htu_result = {res1:       0x00,
-                                    cellid:     connection,
-                                    res2:       0x00,
-                                    type:       aal5 ? 0x00 : 0x01,
-                                    ven:        0x01,
-                                    res3:       0x00,
-                                    qid:        connection};
-
-    *HTU_RESULT(connection - QSB_QUEUE_NUMBER_BASE + OAM_HTU_ENTRY_NUMBER) = htu_result;
-    *HTU_MASK(connection - QSB_QUEUE_NUMBER_BASE + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
-    *HTU_ENTRY(connection - QSB_QUEUE_NUMBER_BASE + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
-}
-
-int alloc_tx_connection(int connection)
-{
-    unsigned long sys_flag;
-    int desc_base;
-
-    if ( ppe_dev.dma.tx_desc_alloc_pos[connection] == ppe_dev.dma.tx_desc_release_pos[connection] && ppe_dev.dma.tx_desc_alloc_flag[connection] )
-        return -1;
-
-    /*  amend descriptor pointer and allocation number  */
-    local_irq_save(sys_flag);
-    desc_base = ppe_dev.dma.tx_descriptor_number * (connection - QSB_QUEUE_NUMBER_BASE) + ppe_dev.dma.tx_desc_alloc_pos[connection];
-    if ( ++ppe_dev.dma.tx_desc_alloc_pos[connection] == ppe_dev.dma.tx_descriptor_number )
-        ppe_dev.dma.tx_desc_alloc_pos[connection] = 0;
-    ppe_dev.dma.tx_desc_alloc_flag[connection] = 1;
-    local_irq_restore(sys_flag);
-
-    return desc_base;
-}
-
-
-int ppe_open(struct atm_vcc *vcc)
-{
-    int ret;
-    struct port *port = &ppe_dev.port[(int)vcc->dev->dev_data];
-    int conn;
-    int f_enable_irq = 0;
-    int i;
-printk("%s:%s[%d] removed 2 args from signature\n", __FILE__, __func__, __LINE__);
-
-printk("ppe_open");
-
-    if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
-        return -EPROTONOSUPPORT;
-
-    down(&ppe_dev.sem);
-
-    /*  check bandwidth */
-    if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
-      || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
-      || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
-      || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
-    {
-        ret = -EINVAL;
-        goto PPE_OPEN_EXIT;
-    }
-
-    printk("alloc vpi = %d, vci = %d\n", vcc->vpi, vcc->vci);
-
-    /*  check existing vpi,vci  */
-    conn = find_vpivci(vcc->vpi, vcc->vci);
-    if ( conn >= 0 )
-    {
-        ret = -EADDRINUSE;
-        goto PPE_OPEN_EXIT;
-    }
-
-    /*  check whether it need to enable irq */
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( ppe_dev.port[i].max_connections != 0 && ppe_dev.port[i].connection_table != 0 )
-            break;
-    if ( i == ATM_PORT_NUMBER )
-        f_enable_irq = 1;
-
-    /*  allocate connection */
-    for ( i = 0, conn = port->connection_base; i < port->max_connections; i++, conn++ )
-        if ( !(port->connection_table & (1 << i)) )
-        {
-            port->connection_table |= 1 << i;
-            ppe_dev.connection[conn].vcc = vcc;
-            break;
-        }
-    if ( i == port->max_connections )
-    {
-        ret = -EINVAL;
-        goto PPE_OPEN_EXIT;
-    }
-
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    /*  assign DMA channel and setup weight value for RX QoS    */
-    switch ( vcc->qos.rxtp.traffic_class )
-    {
-    case ATM_CBR:
-        ppe_dev.connection[conn].rx_dma_channel = RX_DMA_CH_CBR;
-        break;
-    case ATM_VBR_RT:
-        ppe_dev.connection[conn].rx_dma_channel = RX_DMA_CH_VBR_RT;
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_RT] += vcc->qos.rxtp.max_pcr;
-        ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] += vcc->qos.rxtp.max_pcr;
-        break;
-    case ATM_VBR_NRT:
-        ppe_dev.connection[conn].rx_dma_channel = RX_DMA_CH_VBR_NRT;
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_NRT] += vcc->qos.rxtp.pcr;
-        ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] += vcc->qos.rxtp.pcr;
-        break;
-    case ATM_ABR:
-        ppe_dev.connection[conn].rx_dma_channel = RX_DMA_CH_AVR;
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_AVR] += vcc->qos.rxtp.min_pcr;
-        ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] += vcc->qos.rxtp.min_pcr;
-        break;
-    case ATM_UBR_PLUS:
-    default:
-        ppe_dev.connection[conn].rx_dma_channel = RX_DMA_CH_UBR;
-        break;
-    }
-
-    /*  update RX queue configuration table */
-    WRX_QUEUE_CONFIG(conn)->dmach = ppe_dev.connection[conn].rx_dma_channel;
-
-    printk("ppe_open: QID %d, DMA %d\n", conn, WRX_QUEUE_CONFIG(conn)->dmach);
-
-    printk("conn = %d, dmach = %d", conn, WRX_QUEUE_CONFIG(conn)->dmach);
-#endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-
-    /*  reserve bandwidth   */
-    switch ( vcc->qos.txtp.traffic_class )
-    {
-    case ATM_CBR:
-    case ATM_VBR_RT:
-        port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
-        break;
-    case ATM_VBR_NRT:
-        port->tx_current_cell_rate += vcc->qos.txtp.pcr;
-        break;
-    case ATM_UBR_PLUS:
-        port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
-        break;
-    }
-
-    /*  set qsb */
-    set_qsb(vcc, &vcc->qos, conn);
-
-    /*  update atm_vcc structure    */
-    vcc->itf = (int)vcc->dev->dev_data;
-
-    set_bit(ATM_VF_READY, &vcc->flags);
-
-    /*  enable irq  */
-    printk("ppe_open: enable_irq\n");
-    if ( f_enable_irq )
-        enable_irq(IFXMIPS_PPE_MBOX_INT);
-
-    /*  enable mailbox  */
-    *MBOX_IGU1_ISRC =  (1 << conn) | (1 << (conn + 16));
-    *MBOX_IGU1_IER  |= (1 << conn) | (1 << (conn + 16));
-    *MBOX_IGU3_ISRC =  (1 << conn) | (1 << (conn + 16));
-    *MBOX_IGU3_IER  |= (1 << conn) | (1 << (conn + 16));
-
-    /*  set htu entry   */
-    set_htu_entry(vcc->vpi, vcc->vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0);
-
-    ret = 0;
-
-    printk("ppe_open(%d.%d): conn = %d, ppe_dev.dma = %08X\n", vcc->vpi, vcc->vci, conn, (u32)&ppe_dev.dma.rx_descriptor_number);
-
-
-PPE_OPEN_EXIT:
-    up(&ppe_dev.sem);
-
-    printk("open ATM itf = %d, vpi = %d, vci = %d, ret = %d", (int)vcc->dev->dev_data, (int)vcc->vpi, vcc->vci, ret);
-    return ret;
-}
-
-void ppe_close(struct atm_vcc *vcc)
-{
-    int conn;
-    struct port *port;
-    struct connection *connection;
-    int i;
-
-    if ( vcc == NULL )
-        return;
-
-    down(&ppe_dev.sem);
-
-    /*  get connection id   */
-    conn = find_vcc(vcc);
-    if ( conn < 0 )
-    {
-        printk("can't find vcc\n");
-        goto PPE_CLOSE_EXIT;
-    }
-    if(!((Atm_Priv *)vcc)->on)
-               goto PPE_CLOSE_EXIT;
-       connection = &ppe_dev.connection[conn];
-    port = &ppe_dev.port[connection->port];
-
-    /*  clear htu   */
-    clear_htu_entry(conn);
-
-    /*  release connection  */
-    port->connection_table &= ~(1 << (conn - port->connection_base));
-    connection->vcc = NULL;
-    connection->access_time.tv_sec = 0;
-    connection->access_time.tv_nsec = 0;
-    connection->aal5_vcc_crc_err = 0;
-    connection->aal5_vcc_oversize_sdu = 0;
-
-    /*  disable irq */
-    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
-        if ( ppe_dev.port[i].max_connections != 0 && ppe_dev.port[i].connection_table != 0 )
-            break;
-    if ( i == ATM_PORT_NUMBER )
-        disable_irq(IFXMIPS_PPE_MBOX_INT);
-
-    *MBOX_IGU1_ISRC =  (1 << conn) | (1 << (conn + 16));
-
-#if defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-    /*  remove weight value from RX DMA channel */
-    switch ( vcc->qos.rxtp.traffic_class )
-    {
-    case ATM_VBR_RT:
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_RT] -= vcc->qos.rxtp.max_pcr;
-        if ( ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] > ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_RT] )
-            ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_RT] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_RT];
-        break;
-    case ATM_VBR_NRT:
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_NRT] -= vcc->qos.rxtp.pcr;
-        if ( ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] > ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_NRT] )
-            ppe_dev.dma.rx_weight[RX_DMA_CH_VBR_NRT] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_VBR_NRT];
-        break;
-    case ATM_ABR:
-        ppe_dev.dma.rx_default_weight[RX_DMA_CH_AVR] -= vcc->qos.rxtp.min_pcr;
-        if ( ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] > ppe_dev.dma.rx_default_weight[RX_DMA_CH_AVR] )
-            ppe_dev.dma.rx_weight[RX_DMA_CH_AVR] = ppe_dev.dma.rx_default_weight[RX_DMA_CH_AVR];
-        break;
-    case ATM_CBR:
-    case ATM_UBR_PLUS:
-    default:
-        break;
-    }
-#endif  //  defined(ENABLE_RX_QOS) && ENABLE_RX_QOS
-
-    /*  release bandwidth   */
-    switch ( vcc->qos.txtp.traffic_class )
-    {
-    case ATM_CBR:
-    case ATM_VBR_RT:
-        port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
-        break;
-    case ATM_VBR_NRT:
-        port->tx_current_cell_rate -= vcc->qos.txtp.pcr;
-        break;
-    case ATM_UBR_PLUS:
-        port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
-        break;
-    }
-
-    /*  idle for a while to let parallel operation finish   */
-    for ( i = 0; i < IDLE_CYCLE_NUMBER; i++ );
-       ((Atm_Priv *)vcc)->on = 0;
-
-PPE_CLOSE_EXIT:
-    up(&ppe_dev.sem);
-}
-
-int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
-{
-       return -ENOTTY;
-}
-
-int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
-{
-    int ret;
-    int conn;
-    int desc_base;
-    register struct tx_descriptor reg_desc;
-    struct tx_descriptor *desc;
-
-
-printk("ppe_send");
-printk("ppe_send\n");
-printk("skb->users = %d\n", skb->users.counter);
-
-    if ( vcc == NULL || skb == NULL )
-        return -EINVAL;
-
-//    down(&ppe_dev.sem);
-
-    ATM_SKB(skb)->vcc = vcc;
-    conn = find_vcc(vcc);
-//    if ( conn != 1 )
-printk("ppe_send: conn = %d\n", conn);
-    if ( conn < 0 )
-    {
-        ret = -EINVAL;
-        goto FIND_VCC_FAIL;
-    }
-
-printk("find_vcc");
-
-    if ( vcc->qos.aal == ATM_AAL5 )
-    {
-        int byteoff;
-        int datalen;
-        struct tx_inband_header *header;
-
-    /*  allocate descriptor */
-           desc_base = alloc_tx_connection(conn);
-           if ( desc_base < 0 )
-           {
-               ret = -EIO;
-               //goto ALLOC_TX_CONNECTION_FAIL;
-           }
-           desc = &ppe_dev.dma.tx_descriptor_base[desc_base];
-
-    /*  load descriptor from memory */
-           reg_desc = *desc;
-
-        datalen = skb->len;
-        byteoff = (u32)skb->data & (DMA_ALIGNMENT - 1);
-        if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH )
-        {
-            struct sk_buff *new_skb;
-
-printk("skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH");
-printk("skb_headroom(skb 0x%08X, skb->data 0x%08X) (%d) < byteoff (%d) + TX_INBAND_HEADER_LENGTH (%d)\n", (u32)skb, (u32)skb->data, skb_headroom(skb), byteoff, TX_INBAND_HEADER_LENGTH);
-
-            new_skb = alloc_skb_tx(datalen);
-            if ( new_skb == NULL )
-            {
-                printk("alloc_skb_tx: fail\n");
-                ret = -ENOMEM;
-                goto ALLOC_SKB_TX_FAIL;
-            }
-            ATM_SKB(new_skb)->vcc = NULL;
-            skb_put(new_skb, datalen);
-            memcpy(new_skb->data, skb->data, datalen);
-            atm_free_tx_skb_vcc(skb);
-            skb = new_skb;
-            byteoff = (u32)skb->data & (DMA_ALIGNMENT - 1);
-        }
-        else
-        {
-printk("skb_headroom(skb) >= byteoff + TX_INBAND_HEADER_LENGTH");
-        }
-printk("before skb_push, skb->data = 0x%08X", (u32)skb->data);
-        skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
-printk("after skb_push, skb->data = 0x%08X", (u32)skb->data);
-
-        header = (struct tx_inband_header *)(u32)skb->data;
-printk("header = 0x%08X", (u32)header);
-
-        /*  setup inband trailer    */
-        header->uu   = 0;
-        header->cpi  = 0;
-        header->pad  = ppe_dev.aal5.padding_byte;
-        header->res1 = 0;
-
-        /*  setup cell header   */
-        header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
-        header->pti  = ATM_PTI_US0;
-        header->vci  = vcc->vci;
-        header->vpi  = vcc->vpi;
-        header->gfc  = 0;
-
-        /*  setup descriptor    */
-        reg_desc.dataptr = (u32)skb->data >> 2;
-        reg_desc.datalen = datalen;
-        reg_desc.byteoff = byteoff;
-        reg_desc.iscell  = 0;
-
-printk("setup header, datalen = %d, byteoff = %d", reg_desc.datalen, reg_desc.byteoff);
-
-        UPDATE_VCC_STAT(conn, tx_pdu, 1);
-
-        if ( vcc->stats )
-            atomic_inc(&vcc->stats->tx);
-    }
-    else
-    {
-    /*  allocate descriptor */
-           desc_base = alloc_tx_connection(conn);
-           if ( desc_base < 0 )
-    {
-               ret = -EIO;
-               goto ALLOC_TX_CONNECTION_FAIL;
-    }
-           desc = &ppe_dev.dma.tx_descriptor_base[desc_base];
-
-    /*  load descriptor from memory */
-           reg_desc = *desc;
-
-        /*  if data pointer is not aligned, allocate new sk_buff    */
-        if ( ((u32)skb->data & (DMA_ALIGNMENT - 1)) )
-        {
-            struct sk_buff *new_skb;
-
-            printk("skb->data not aligned\n");
-
-            new_skb = alloc_skb_tx(skb->len);
-            if ( new_skb == NULL )
-            {
-                ret = -ENOMEM;
-                goto ALLOC_SKB_TX_FAIL;
-            }
-            ATM_SKB(new_skb)->vcc = NULL;
-            skb_put(new_skb, skb->len);
-            memcpy(new_skb->data, skb->data, skb->len);
-            atm_free_tx_skb_vcc(skb);
-            skb = new_skb;
-        }
-
-        reg_desc.dataptr = (u32)skb->data >> 2;
-        reg_desc.datalen = skb->len;
-        reg_desc.byteoff = 0;
-        reg_desc.iscell  = 1;
-
-        if ( vcc->stats )
-            atomic_inc(&vcc->stats->tx);
-    }
-
-    reg_desc.own = 1;
-    reg_desc.c = 1;
-
-printk("update descriptor send pointer, desc = 0x%08X", (u32)desc);
-
-    ppe_dev.dma.tx_skb_pointers[desc_base] = skb;
-    *desc = reg_desc;
-    dma_cache_wback((unsigned long)skb->data, skb->len);
-
-    mailbox_signal(conn, 1);
-
-printk("ppe_send: success");
-//    up(&ppe_dev.sem);
-
-    return 0;
-
-FIND_VCC_FAIL:
-    printk("FIND_VCC_FAIL\n");
-
-//    up(&ppe_dev.sem);
-    ppe_dev.mib.wtx_err_pdu++;
-    atm_free_tx_skb_vcc(skb);
-
-    return ret;
-
-ALLOC_SKB_TX_FAIL:
-    printk("ALLOC_SKB_TX_FAIL\n");
-
-//    up(&ppe_dev.sem);
-    if ( vcc->qos.aal == ATM_AAL5 )
-    {
-        UPDATE_VCC_STAT(conn, tx_err_pdu, 1);
-        ppe_dev.mib.wtx_err_pdu++;
-    }
-    if ( vcc->stats )
-        atomic_inc(&vcc->stats->tx_err);
-    atm_free_tx_skb_vcc(skb);
-
-    return ret;
-
-ALLOC_TX_CONNECTION_FAIL:
-    printk("ALLOC_TX_CONNECTION_FAIL\n");
-
-//    up(&ppe_dev.sem);
-    if ( vcc->qos.aal == ATM_AAL5 )
-    {
-        UPDATE_VCC_STAT(conn, tx_sw_drop_pdu, 1);
-        ppe_dev.mib.wtx_drop_pdu++;
-    }
-    if ( vcc->stats )
-        atomic_inc(&vcc->stats->tx_err);
-    atm_free_tx_skb_vcc(skb);
-
-    return ret;
-}
-
-int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
-{
-    int conn;
-    struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
-    int desc_base;
-    struct sk_buff *skb;
-    register struct tx_descriptor reg_desc;
-    struct tx_descriptor *desc;
-
-printk("ppe_send_oam");
-
-    if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
-        && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
-        || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
-        && find_vpi(uni_cell_header->vpi) < 0) )
-        return -EINVAL;
-
-#if OAM_TX_QUEUE_NUMBER_PER_PORT != 0
-    /*  get queue ID of OAM TX queue, and the TX DMA channel ID is the same as queue ID */
-    conn = ppe_dev.port[(int)vcc->dev->dev_data].oam_tx_queue;
-#else
-    /*  find queue ID   */
-    conn = find_vcc(vcc);
-    if ( conn < 0 )
-    {
-        printk("OAM not find queue\n");
-//        up(&ppe_dev.sem);
-        return -EINVAL;
-    }
-#endif  //  OAM_TX_QUEUE_NUMBER_PER_PORT != 0
-
-    /*  allocate descriptor */
-    desc_base = alloc_tx_connection(conn);
-    if ( desc_base < 0 )
-    {
-        printk("OAM not alloc tx connection\n");
-//        up(&ppe_dev.sem);
-        return -EIO;
-    }
-
-    desc = &ppe_dev.dma.tx_descriptor_base[desc_base];
-
-    /*  load descriptor from memory */
-    reg_desc = *(struct tx_descriptor *)desc;
-
-    /*  allocate sk_buff    */
-    skb = alloc_skb_tx(CELL_SIZE);
-    if ( skb == NULL )
-    {
-//        up(&ppe_dev.sem);
-        return -ENOMEM;
-    }
-#if OAM_TX_QUEUE_NUMBER_PER_PORT != 0
-    ATM_SKB(skb)->vcc = NULL;
-#else
-    ATM_SKB(skb)->vcc = vcc;
-#endif  //  OAM_TX_QUEUE_NUMBER_PER_PORT != 0
-
-    /*  copy data   */
-    skb_put(skb, CELL_SIZE);
-    memcpy(skb->data, cell, CELL_SIZE);
-
-    /*  setup descriptor    */
-    reg_desc.dataptr = (u32)skb->data >> 2;
-    reg_desc.datalen = CELL_SIZE;
-    reg_desc.byteoff = 0;
-    reg_desc.iscell  = 1;
-    reg_desc.own = 1;
-    reg_desc.c = 1;
-
-    /*  update descriptor send pointer  */
-    ppe_dev.dma.tx_skb_pointers[desc_base] = skb;
-
-    /*  write discriptor to memory and write back cache */
-    *(struct tx_descriptor *)desc = reg_desc;
-    dma_cache_wback((unsigned long)skb->data, skb->len);
-
-    /*  signal PPE  */
-    mailbox_signal(conn, 1);
-
-    return 0;
-}
-
-int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
-{
-    int conn;
-       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
-
-    if(vcc == NULL || qos == NULL )
-        return -EINVAL;
-    conn = find_vcc(vcc);
-    if ( conn < 0 )
-        return -EINVAL;
-    set_qsb(vcc, qos, conn);
-
-       return 0;
-}
-
-static inline void init_chip(void)
-{
-    /*  enable PPE module in PMU    */
-    *(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
-
-    *EMA_CMDCFG  = (EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2);
-    *EMA_DATACFG = (EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2);
-    *EMA_IER     = 0x000000FF;
-       *EMA_CFG     = EMA_READ_BURST | (EMA_WRITE_BURST << 2);
-
-    /*  enable mailbox  */
-    *MBOX_IGU1_ISRC = 0xFFFFFFFF;
-    *MBOX_IGU1_IER  = 0x00000000;
-    *MBOX_IGU3_ISRC = 0xFFFFFFFF;
-    *MBOX_IGU3_IER  = 0x00000000;
-}
-
-int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
-{
-    u32 reg_old_value;
-    volatile u32 *dest;
-
-    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
-        || data_src == 0 || ((unsigned long)data_src & 0x03) )
-        return -EINVAL;
-
-    /*  save the old value of CDM_CFG and set PPE code memory to FPI bus access mode    */
-    reg_old_value = *CDM_CFG;
-    if ( code_dword_len <= 4096 )
-        *CDM_CFG = CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00);
-    else
-        *CDM_CFG = CDM_CFG_RAM1_SET(0x01) | CDM_CFG_RAM0_SET(0x00);
-
-    /*  copy code   */
-    dest = CDM_CODE_MEMORY_RAM0_ADDR(0);
-    while ( code_dword_len-- > 0 )
-        *dest++ = *code_src++;
-
-    /*  copy data   */
-    dest = PP32_DATA_MEMORY_RAM1_ADDR(0);
-    while ( data_dword_len-- > 0 )
-        *dest++ = *data_src++;
-
-    return 0;
-}
-
-int pp32_start(void)
-{
-    int ret;
-    register int i;
-       init_chip();
-    /*  download firmware   */
-    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
-    if ( ret )
-        return ret;
-
-    /*  run PP32    */
-    *PP32_DBG_CTRL = DBG_CTRL_START_SET(1);
-
-    /*  idle for a while to let PP32 init itself    */
-    for ( i = 0; i < IDLE_CYCLE_NUMBER; i++ );
-
-    return 0;
-}
-
-void pp32_stop(void)
-{
-    /*  halt PP32   */
-    *PP32_DBG_CTRL = DBG_CTRL_STOP_SET(1);
-}
diff --git a/package/ifxmips-atm/src/proc.c b/package/ifxmips-atm/src/proc.c
deleted file mode 100644 (file)
index 47b8820..0000000
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <linux/atm.h>
-#include <linux/proc_fs.h>
-
-#include "proc.h"
-#include "common.h"
-
-struct proc_dir_entry *ppe_proc_dir;
-
-int proc_read_idle_counter(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
-    int len = 0;
-
-    len += sprintf(page + off,       "Channel 0\n");
-    len += sprintf(page + off + len, "  TX\n");
-    len += sprintf(page + off + len,
-               "    DREG_AT_CELL0       = %d\n", *DREG_AT_CELL0 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AT_IDLE_CNT0   = %d\n", *DREG_AT_IDLE_CNT0 & 0xFFFF);
-    len += sprintf(page + off + len, "  RX\n");
-    len += sprintf(page + off + len,
-               "    DREG_AR_CELL0       = %d\n", *DREG_AR_CELL0 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_IDLE_CNT0   = %d\n", *DREG_AR_IDLE_CNT0 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_AIIDLE_CNT0 = %d\n", *DREG_AR_AIIDLE_CNT0 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_BE_CNT0     = %d\n", *DREG_AR_BE_CNT0 & 0xFFFF);
-    len += sprintf(page + off + len, "Channel 1\n");
-    len += sprintf(page + off + len, "  TX\n");
-    len += sprintf(page + off + len,
-               "    DREG_AT_CELL1       = %d\n", *DREG_AT_CELL1 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AT_IDLE_CNT1   = %d\n", *DREG_AT_IDLE_CNT1 & 0xFFFF);
-    len += sprintf(page + off + len, "  RX\n");
-    len += sprintf(page + off + len,
-               "    DREG_AR_CELL1       = %d\n", *DREG_AR_CELL1 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_IDLE_CNT1   = %d\n", *DREG_AR_IDLE_CNT1 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_AIIDLE_CNT1 = %d\n", *DREG_AR_AIIDLE_CNT1 & 0xFFFF);
-    len += sprintf(page + off + len,
-               "    DREG_AR_BE_CNT1     = %d\n", *DREG_AR_BE_CNT1 & 0xFFFF);
-
-    return len;
-}
-
-int proc_read_stats(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
-    int len = 0;
-
-    int i, j;
-    struct connection *connection;
-    struct port *port;
-    int base;
-
-    len += sprintf(page + off, "ATM Stats:\n");
-
-    connection = ppe_dev.connection;
-    port = ppe_dev.port;
-    for ( i = 0; i < ATM_PORT_NUMBER; i++, port++ )
-    {
-        base = port->connection_base;
-        for ( j = 0; j < port->max_connections; j++, base++ )
-            if ( (port->connection_table & (1 << j))
-                && connection[base].vcc != NULL )
-            {
-                if ( connection[base].vcc->stats )
-                {
-                    struct k_atm_aal_stats *stats = connection[base].vcc->stats;
-
-                    len += sprintf(page + off + len, "  VCC %d.%d.%d (stats)\n", i, connection[base].vcc->vpi, connection[base].vcc->vci);
-                    len += sprintf(page + off + len, "    rx      = %d\n", stats->rx.counter);
-                    len += sprintf(page + off + len, "    rx_err  = %d\n", stats->rx_err.counter);
-                    len += sprintf(page + off + len, "    rx_drop = %d\n", stats->rx_drop.counter);
-                    len += sprintf(page + off + len, "    tx      = %d\n", stats->tx.counter);
-                    len += sprintf(page + off + len, "    tx_err  = %d\n", stats->tx_err.counter);
-                }
-                else
-                    len += sprintf(page + off + len, "  VCC %d.%d.%d\n", i, connection[base].vcc->vpi, connection[base].vcc->vci);
-            }
-    }
-
-    return len;
-}
-
-void proc_file_create(void)
-{
-    ppe_proc_dir = proc_mkdir("ppe", NULL);
-       create_proc_read_entry("idle_counter", 0, ppe_proc_dir, proc_read_idle_counter, NULL);
-    create_proc_read_entry("stats", 0, ppe_proc_dir, proc_read_stats, NULL);
-}
-
-void proc_file_delete(void)
-{
-    remove_proc_entry("idle_counter", ppe_proc_dir);
-    remove_proc_entry("stats", ppe_proc_dir);
-    remove_proc_entry("ppe", NULL);
-}
diff --git a/package/ifxmips-atm/src/proc.h b/package/ifxmips-atm/src/proc.h
deleted file mode 100644 (file)
index c632c0c..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _IFXMIPS_PPE_PROC_H__
-#define _IFXMIPS_PPE_PROC_H__
-
-void proc_file_create(void);
-void proc_file_delete(void);
-int proc_read_idle_counter(char *page, char **start, off_t off, int count, int *eof, void *data);
-int proc_read_stats(char *page, char **start, off_t off, int count, int *eof, void *data);
-
-#endif
diff --git a/package/ifxmips-atm/src/skb.c b/package/ifxmips-atm/src/skb.c
deleted file mode 100644 (file)
index 7ad60fd..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-#include <linux/skbuff.h>
-
-#include "common.h"
-
-void resize_skb_rx(struct sk_buff *skb, unsigned int size, int is_cell)
-{
-    if((u32)skb < 0x80000000)
-    {
-        int key = 0;
-        printk("resize_skb_rx problem: skb = %08X, size = %d, is_cell = %d\n", (u32)skb, size, is_cell);
-        while(!key){}
-    }
-    skb->data = (unsigned char*)(((u32)skb->head + 16 + (DMA_ALIGNMENT - 1)) & ~(DMA_ALIGNMENT - 1));
-    skb->tail = skb->data;
-
-    /*  Set up other state  */
-    skb->len = 0;
-    skb->cloned = 0;
-#if defined(CONFIG_IMQ) || defined (CONFIG_IMQ_MODULE)
-    skb->imq_flags = 0;
-    skb->nf_info = NULL;
-#endif
-    skb->data_len = 0;
-}
-
-struct sk_buff* alloc_skb_rx(void)
-{
-    struct sk_buff *skb;
-
-    /*  allocate memroy including trailer and padding   */
-    skb = dev_alloc_skb(ppe_dev.aal5.rx_buffer_size + DMA_ALIGNMENT);
-    if (skb)
-    {
-        /*  must be burst length alignment  */
-        if ( ((u32)skb->data & (DMA_ALIGNMENT - 1)) != 0 )
-            skb_reserve(skb, ~((u32)skb->data + (DMA_ALIGNMENT - 1)) & (DMA_ALIGNMENT - 1));
-        /*  put skb in reserved area "skb->data - 4"    */
-        *((u32*)skb->data - 1) = (u32)skb;
-        /*  invalidate cache    */
-        dma_cache_inv((unsigned long)skb->head, (u32)skb->end - (u32)skb->head);
-    }
-    return skb;
-}
-
-void atm_free_tx_skb_vcc(struct sk_buff *skb)
-{
-    struct atm_vcc* vcc;
-
-    if ( (u32)skb <= 0x80000000 )
-    {
-        volatile int key = 0;
-        printk("atm_free_tx_skb_vcc: skb = %08X\n", (u32)skb);
-        for ( ; !key; );
-    }
-
-    vcc = ATM_SKB(skb)->vcc;
-    if ( vcc != NULL && vcc->pop != NULL )
-    {
-        if ( atomic_read(&skb->users) == 0 )
-        {
-            volatile int key = 0;
-            printk("atm_free_tx_skb_vcc(vcc->pop): skb->users == 0, skb = %08X\n", (u32)skb);
-            for ( ; !key; );
-        }
-        vcc->pop(vcc, skb);
-    }
-    else
-    {
-        if ( atomic_read(&skb->users) == 0 )
-        {
-            volatile int key = 0;
-            printk("atm_free_tx_skb_vcc(dev_kfree_skb_any): skb->users == 0, skb = %08X\n", (u32)skb);
-            for ( ; !key; );
-        }
-        dev_kfree_skb_any(skb);
-    }
-}
-
-struct sk_buff* alloc_skb_tx(unsigned int size)
-{
-    struct sk_buff *skb;
-
-    /*  allocate memory including header and padding    */
-    size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
-    size &= ~(DMA_ALIGNMENT - 1);
-    skb = dev_alloc_skb(size + DMA_ALIGNMENT);
-    /*  must be burst length alignment  */
-    if ( skb )
-        skb_reserve(skb, (~((u32)skb->data + (DMA_ALIGNMENT - 1)) & (DMA_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
-    return skb;
-}
-
-struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
-{
-    int conn;
-    struct sk_buff *skb;
-
-    /*  oversize packet */
-    if ( ((size + TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES) & ~(DMA_ALIGNMENT - 1))  > ppe_dev.aal5.tx_max_packet_size )
-    {
-        printk("atm_alloc_tx: oversize packet\n");
-        return NULL;
-    }
-    /*  send buffer overflow    */
-    if ( atomic_read(&vcc->sk.sk_wmem_alloc) && !atm_may_send(vcc, size) )
-    {
-        printk("atm_alloc_tx: send buffer overflow\n");
-        return NULL;
-    }
-    conn = find_vcc(vcc);
-    if ( conn < 0 )
-    {
-        printk("atm_alloc_tx: unknown VCC\n");
-        return NULL;
-    }
-
-    skb = dev_alloc_skb(size);
-    if ( skb == NULL )
-    {
-        printk("atm_alloc_tx: sk buffer is used up\n");
-        return NULL;
-    }
-#define ATM_PDU_OVHD 0
-    atomic_add(skb->truesize + ATM_PDU_OVHD, &vcc->sk.sk_wmem_alloc);
-
-    return skb;
-}
-
diff --git a/package/ifxmips-dsl-api/Config.in b/package/ifxmips-dsl-api/Config.in
new file mode 100644 (file)
index 0000000..a1c3cd4
--- /dev/null
@@ -0,0 +1,18 @@
+choice
+       prompt "Firmware"
+       depends on PACKAGE_kmod-ifxmips-dsl-api
+       default IFXMIPS_ANNEX_B
+       help
+         This option controls which firmware is loaded
+
+config IFXMIPS_ANNEX_A
+       bool "Annex-A"
+       help
+         Annex-A
+
+config IFXMIPS_ANNEX_B
+       bool "Annex-B"
+       help
+         Annex-B
+
+endchoice
diff --git a/package/ifxmips-dsl-api/Makefile b/package/ifxmips-dsl-api/Makefile
new file mode 100644 (file)
index 0000000..73d6f4f
--- /dev/null
@@ -0,0 +1,140 @@
+#
+# Copyright (C) 2009 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+# ralph / blogic
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=ifxmips-dsl-api
+PKG_BASE_NAME:=drv_dsl_cpe_api_danube
+PKG_VERSION:=3.24.4.4
+PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/drv_dsl_cpe_api-$(PKG_VERSION)
+PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/
+PKG_MD5SUM:=c45bc531c1ed2ac80f68fb986b63bb87
+
+FW_BASE_NAME:=dsl_danube_firmware_adsl
+FW_A_VER:=02.04.04.00.00.01
+FW_B_VER:=02.04.01.07.00.02
+FW_A_FILE_VER:=244001
+FW_B_FILE_VER:=241702
+FW_A_MD5:=f717db3067a0049a26e233ab11238710
+FW_B_MD5:=349de7cd20368f4ac9b7e8322114a512
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/ifxmips-dsl-api
+  SECTION:=driver
+  CATEGORY:=Infineon
+  TITLE:=DSL CPE API driver
+  URL:=http://www.infineon.com/
+  MAINTAINER:=Infineon Technologies AG / Lantiq / blogic@openwrt.org
+  DEPENDS:=@TARGET_ifxmips
+  FILES:=$(PKG_BUILD_DIR)/src/mei/ifxmips_mei.$(LINUX_KMOD_SUFFIX) \
+       $(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.$(LINUX_KMOD_SUFFIX) \
+       $(PKG_BUILD_DIR)/src/mei/ifxmips_atm.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,50,ifxmips_mei drv_dsl_cpe_api ifxmips_atm)
+endef
+
+define KernelPackage/ifxmips-dsl-api/description
+       Infineon DSL CPE API for Amazon SE, Danube and Vinax.
+
+       This package contains the DSL CPE API driver for Amazon SE & Danube.
+       
+       Supported Devices:
+               - Amazon SE
+               - Danube 
+
+       This package was kindly contributed to openwrt by Infineon/Lantiq
+endef
+
+define KernelPackage/ifxmips-dsl-api/config
+       source "$(SOURCE)/Config.in"
+endef
+
+define Download/annex-a
+       FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
+       URL:=http://mirror2.openwrt.org/sources/
+       MD5SUM:=$(FW_A_MD5)
+endef
+$(eval $(call Download,annex-a))
+
+define Download/annex-b
+       FILE:=$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
+       URL:=http://mirror2.openwrt.org/sources/
+       MD5SUM:=$(FW_B_MD5)
+endef
+$(eval $(call Download,annex-b))
+
+IFX_DSL_MAX_DEVICE=1
+IFX_DSL_LINES_PER_DEVICE=1
+IFX_DSL_CHANNELS_PER_LINE=1
+
+CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \
+       --with-max-device="$(IFX_DSL_MAX_DEVICE)" \
+       --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \
+       --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \
+       --enable-danube \
+       --enable-add-drv-cflags="-DMODULE" \
+       --enable-debug=yes \
+       --enable-debug-prints=yes \
+       --disable-dsl-delt-static \
+       --disable-adsl-led \
+       --enable-dsl-ceoc \
+       --enable-dsl-pm \
+       --enable-dsl-pm-total \
+       --enable-dsl-pm-history \
+       --enable-dsl-pm-showtime \
+       --enable-dsl-pm-channel-counters \
+       --enable-dsl-pm-datapath-counters \
+       --enable-dsl-pm-line-counters \
+       --enable-dsl-pm-channel-thresholds \
+       --enable-dsl-pm-datapath-thresholds \
+       --enable-dsl-pm-line-thresholds \
+       --enable-dsl-pm-optional-parameters \
+       --enable-linux-26 \
+       --enable-kernelbuild="$(LINUX_DIR)" \
+       ARCH=$(LINUX_KARCH)
+
+EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0
+
+define Build/Prepare
+       $(PKG_UNPACK)
+       $(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/ 
+       $(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/
+       $(Build/Patch)
+       $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz
+       $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz
+endef
+
+define Build/Compile
+       cd $(LINUX_DIR); \
+               ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \
+               $(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules
+       $(call Build/Compile/Default)
+endef
+
+define Build/InstallDev
+       $(INSTALL_DIR) $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_ioctl.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib_ioctl.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_g997.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_types.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_pm.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_error.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_danube_ctx.h $(1)/usr/include
+       $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include
+endef
+
+define KernelPackage/ifxmips-dsl-api/install
+       $(INSTALL_DIR) $(1)/lib/firmware/
+       $(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_$(if $(CONFIG_IFXMIPS_ANNEX_A),a_$(FW_A_FILE_VER),b_$(FW_B_FILE_VER)).bin $(1)/lib/firmware/ModemHWE.bin
+endef
+
+$(eval $(call KernelPackage,ifxmips-dsl-api))
diff --git a/package/ifxmips-dsl-api/patches/100-dsl_compat.patch b/package/ifxmips-dsl-api/patches/100-dsl_compat.patch
new file mode 100644 (file)
index 0000000..a3b9930
--- /dev/null
@@ -0,0 +1,43 @@
+Index: drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/include/drv_dsl_cpe_device_danube.h      2009-05-12 20:02:16.000000000 +0200
++++ drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h   2009-11-01 00:57:23.000000000 +0100
+@@ -24,7 +24,7 @@
+    #include "drv_dsl_cpe_simulator_danube.h"
+ #else
+ /* Include for the low level driver interface header file */
+-#include "asm/ifx/ifx_mei_bsp.h"
++#include "mei/ifxmips_mei_interface.h"
+ #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
+ #define DSL_MAX_LINE_NUMBER 1
+Index: drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/common/drv_dsl_cpe_os_linux.c    2009-11-01 01:00:08.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c 2009-11-01 01:03:51.000000000 +0100
+@@ -11,6 +11,7 @@
+ #ifdef __LINUX__
+ #define DSL_INTERN
++#include <linux/device.h>
+ #include "drv_dsl_cpe_api.h"
+ #include "drv_dsl_cpe_api_ioctl.h"
+@@ -1058,6 +1059,7 @@
+ /* Entry point of driver */
+ int __init DSL_ModuleInit(void)
+ {
++   struct class *dsl_class;
+    DSL_int_t i;
+    printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
+@@ -1104,7 +1106,8 @@
+    }
+    DSL_DRV_DevNodeInit();
+-
++   dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
++   device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
+    return 0;
+ }
diff --git a/package/ifxmips-dsl-api/patches/200-mei_compat.patch b/package/ifxmips-dsl-api/patches/200-mei_compat.patch
new file mode 100644 (file)
index 0000000..ae2d593
--- /dev/null
@@ -0,0 +1,95 @@
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_mei.c
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_mei.c        2009-10-31 23:30:20.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_mei.c     2009-11-01 04:41:58.000000000 +0100
+@@ -41,18 +41,19 @@
+ #include <linux/init.h>
+ #include <linux/ioport.h>
+ #include <linux/delay.h>
++#include <linux/device.h>
+ #include <asm/uaccess.h>
+ #include <asm/hardirq.h>
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/irq.h>
+-#include <asm/ifx/ifx_gpio.h>
+-//#include <asm/ifx/ifx_led.h>
+-#include <asm/ifx/ifx_pmu.h>
+-#include <asm/ifx/ifx_atm.h>
++
++#include <ifxmips.h>
++#include <ifxmips_irq.h>
++#include <ifxmips_gpio.h>
++#include <ifxmips_pmu.h>
++#include "ifxmips_atm.h"
+ #define IFX_MEI_BSP
+ #include "ifxmips_mei_interface.h"
+-#define IFXMIPS_RCU_RST                   IFX_RCU_RST_REQ
++/*#define IFXMIPS_RCU_RST                   IFX_RCU_RST_REQ
+ #define IFXMIPS_RCU_RST_REQ_ARC_JTAG      IFX_RCU_RST_REQ_ARC_JTAG
+ #define IFXMIPS_RCU_RST_REQ_DFE                 IFX_RCU_RST_REQ_DFE
+ #define IFXMIPS_RCU_RST_REQ_AFE                 IFX_RCU_RST_REQ_AFE
+@@ -76,7 +77,7 @@
+ #define ifxmips_r32(reg)                        __raw_readl(reg)
+ #define ifxmips_w32(val, reg)                   __raw_writel(val, reg)
+ #define ifxmips_w32_mask(clear, set, reg)       ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
+-
++*/
+ #define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR  "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
+ #define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
+@@ -173,7 +174,8 @@
+ extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
+ #define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq
+-static int dev_major = 105;
++#define MEI_MAJOR     105
++static int dev_major = MEI_MAJOR;
+ static struct file_operations bsp_mei_operations = {
+       owner:THIS_MODULE,
+@@ -2294,10 +2296,10 @@
+               IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
+               return -1;
+       }
+-      if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
++      /*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
+               IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
+               return -1;
+-      }
++      }*/
+ //    IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
+       return 0;
+ }
+@@ -2922,6 +2924,7 @@
+ IFX_MEI_ModuleInit (void)
+ {
+       int i = 0;
++      static struct class *dsl_class;
+       printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
+@@ -2935,14 +2938,15 @@
+               IFX_MEI_InitProcFS (i);
+ #endif
+       }
+-        for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
++              for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
+               dsl_bsp_event_callback[i].function = NULL;
+ #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
+       printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__);
+       DFE_Loopback_Test ();
+ #endif
+-
++      dsl_class = class_create(THIS_MODULE, "ifx_mei");
++      device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei");
+       return 0;
+ }
+@@ -2996,3 +3000,5 @@
+ module_init (IFX_MEI_ModuleInit);
+ module_exit (IFX_MEI_ModuleExit);
++
++MODULE_LICENSE("Dual BSD/GPL");
diff --git a/package/ifxmips-dsl-api/patches/300-atm_compat.patch b/package/ifxmips-dsl-api/patches/300-atm_compat.patch
new file mode 100644 (file)
index 0000000..35c7b13
--- /dev/null
@@ -0,0 +1,168 @@
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.c
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_core.c   2009-11-01 14:29:05.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.c        2009-11-01 16:07:46.000000000 +0100
+@@ -58,9 +58,8 @@
+ /*
+  *  Chip Specific Head File
+  */
+-#include <asm/ifx/ifx_types.h>
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/common_routines.h>
++#include <ifxmips.h>
++#include <ifxmips_cgu.h>
+ #include "ifxmips_atm_core.h"
+@@ -1146,7 +1145,7 @@
+ static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
+ {
+-    unsigned int qsb_clk = ifx_get_fpi_hz();
++    unsigned int qsb_clk = ifxmips_get_fpi_hz();
+     unsigned int qsb_qid = queue + FIRST_QSB_QID;
+     union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
+     union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
+@@ -1318,7 +1317,7 @@
+ static void qsb_global_set(void)
+ {
+-    unsigned int qsb_clk = ifx_get_fpi_hz();
++    unsigned int qsb_clk = ifxmips_get_fpi_hz();
+     int i;
+     unsigned int tmp1, tmp2, tmp3;
+@@ -2505,3 +2504,4 @@
+ module_init(ifx_atm_init);
+ module_exit(ifx_atm_exit);
++MODULE_LICENSE("Dual BSD/GPL");
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_common.h
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_ppe_common.h     2009-11-01 14:30:55.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_common.h  2009-11-01 15:58:50.000000000 +0100
+@@ -1,9 +1,10 @@
+ #ifndef IFXMIPS_ATM_PPE_COMMON_H
+ #define IFXMIPS_ATM_PPE_COMMON_H
+-
+-
+-#if defined(CONFIG_DANUBE)
++#if defined(CONFIG_IFXMIPS)
++  #include "ifxmips_atm_ppe_danube.h"
++  #define CONFIG_DANUBE
++#elif defined(CONFIG_DANUBE) 
+   #include "ifxmips_atm_ppe_danube.h"
+ #elif defined(CONFIG_AMAZON_SE)
+   #include "ifxmips_atm_ppe_amazon_se.h"
+@@ -16,7 +17,6 @@
+ #endif
+-
+ /*
+  *  Code/Data Memory (CDM) Interface Configuration Register
+  */
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.h
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_core.h   2009-11-01 14:30:55.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.h        2009-11-01 15:58:50.000000000 +0100
+@@ -25,8 +25,8 @@
+ #define IFXMIPS_ATM_CORE_H
+-
+-#include <asm/ifx/ifx_atm.h>
++#include "ifxmips_compat.h"
++#include "ifx_atm.h"
+ #include "ifxmips_atm_ppe_common.h"
+ #include "ifxmips_atm_fw_regs_common.h"
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_compat.h
+===================================================================
+--- /dev/null  1970-01-01 00:00:00.000000000 +0000
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_compat.h  2009-11-01 15:58:50.000000000 +0100
+@@ -0,0 +1,43 @@
++#ifndef _IFXMIPS_COMPAT_H__
++#define _IFXMIPS_COMPAT_H__
++
++#define       IFX_SUCCESS     0
++#define IFX_ERROR     (-1)
++
++#define ATM_VBR_NRT     ATM_VBR
++#define ATM_VBR_RT      6
++#define ATM_UBR_PLUS    7
++#define ATM_GFR         8
++
++#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
++
++#define SET_BITS(x, msb, lsb, value)  \
++    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
++
++
++#define IFX_PMU_ENABLE    1
++#define IFX_PMU_DISABLE   0
++
++#define IFX_PMU_MODULE_DSL_DFE    (1 << 9)
++#define IFX_PMU_MODULE_AHBS             (1 << 13)
++#define IFX_PMU_MODULE_PPE_QSB    (1 << 18)
++#define IFX_PMU_MODULE_PPE_SLL01  (1 << 19)
++#define IFX_PMU_MODULE_PPE_TC     (1 << 21)
++#define IFX_PMU_MODULE_PPE_EMA    (1 << 22)
++#define IFX_PMU_MODULE_PPE_TOP    (1 << 29)
++
++#define ifx_pmu_set(a,b)      {if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);}
++
++#define PPE_TOP_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
++#define PPE_SLL01_PMU_SETUP(__x)  ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
++#define PPE_TC_PMU_SETUP(__x)     ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
++#define PPE_EMA_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
++#define PPE_QSB_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
++#define PPE_TPE_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
++#define DSL_DFE_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
++
++#define IFX_REG_W32(_v, _r)               __raw_writel((_v), (_r))
++
++#define CONFIG_IFXMIPS_DSL_CPE_MEI    y
++
++#endif
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_danube.h
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_ppe_danube.h     2009-11-01 14:30:55.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_danube.h  2009-11-01 15:58:50.000000000 +0100
+@@ -1,7 +1,7 @@
+ #ifndef IFXMIPS_ATM_PPE_DANUBE_H
+ #define IFXMIPS_ATM_PPE_DANUBE_H
+-
++#include <ifxmips_irq.h>
+ /*
+  *  FPI Configuration Bus Register and Memory Address Mapping
+@@ -93,7 +93,7 @@
+ /*
+  *  Mailbox IGU1 Interrupt
+  */
+-#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24
++#define PPE_MAILBOX_IGU1_INT            IFXMIPS_PPE_MBOX_INT
+Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_danube.c
+===================================================================
+--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_danube.c 2009-11-01 14:29:18.000000000 +0100
++++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_danube.c      2009-11-01 15:58:50.000000000 +0100
+@@ -45,10 +45,9 @@
+ /*
+  *  Chip Specific Head File
+  */
+-#include <asm/ifx/ifx_types.h>
+-#include <asm/ifx/ifx_regs.h>
+-#include <asm/ifx/common_routines.h>
+-#include <asm/ifx/ifx_pmu.h>
++#include <ifxmips.h>
++#include <ifxmips_pmu.h>
++#include "ifxmips_compat.h"
+ #include "ifxmips_atm_core.h"
+ #include "ifxmips_atm_fw_danube.h"
diff --git a/package/ifxmips-dsl-api/src/Makefile b/package/ifxmips-dsl-api/src/Makefile
new file mode 100644 (file)
index 0000000..c8211d3
--- /dev/null
@@ -0,0 +1,3 @@
+obj-m = ifxmips_mei.o ifxmips_atm.o
+
+ifxmips_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o
diff --git a/package/ifxmips-dsl-api/src/ifx_atm.h b/package/ifxmips-dsl-api/src/ifx_atm.h
new file mode 100644 (file)
index 0000000..ed90b5d
--- /dev/null
@@ -0,0 +1,172 @@
+/******************************************************************************
+**
+** FILE NAME    : ifx_atm.h
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 17 Jun 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : Global ATM driver header file
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+#ifndef IFX_ATM_H
+#define IFX_ATM_H
+
+
+
+/*!
+  \defgroup IFX_ATM UEIP Project - ATM driver module
+  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+  \defgroup IFX_ATM_IOCTL IOCTL Commands
+  \ingroup IFX_ATM
+  \brief IOCTL Commands used by user application.
+ */
+
+/*!
+  \defgroup IFX_ATM_STRUCT Structures
+  \ingroup IFX_ATM
+  \brief Structures used by user application.
+ */
+
+/*!
+  \file ifx_atm.h
+  \ingroup IFX_ATM
+  \brief ATM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_STRUCT
+ */
+/*@{*/
+
+/*
+ *  ATM MIB
+ */
+
+typedef struct {
+       __u32   ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
+       __u32   ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
+       __u32   ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
+       __u32   ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
+       __u32   ifInErrors;         /*!< counter of error ingress cells     */
+       __u32   ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
+       __u32   ifOutErrors;        /*!< counter of error egress cells      */
+} atm_cell_ifEntry_t;
+
+typedef struct {
+       __u32   ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
+       __u32   ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
+       __u32   ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
+       __u32   ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
+       __u32   ifInUcastPkts;      /*!< counter of ingress packets         */
+       __u32   ifOutUcastPkts;     /*!< counter of egress packets          */
+       __u32   ifInErrors;         /*!< counter of error ingress packets   */
+       __u32   ifInDiscards;       /*!< counter of dropped ingress packets */
+       __u32   ifOutErros;         /*!< counter of error egress packets    */
+       __u32   ifOutDiscards;      /*!< counter of dropped egress packets  */
+} atm_aal5_ifEntry_t;
+
+typedef struct {
+       __u32   aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
+       __u32   aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
+       __u32   aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
+} atm_aal5_vcc_t;
+
+typedef struct {
+       int             vpi;        /*!< VPI of the VCC to get MIB counters */
+       int             vci;        /*!< VCI of the VCC to get MIB counters */
+       atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
+} atm_aal5_vcc_x_t;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                IOCTL
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_IOCTL
+ */
+/*@{*/
+
+/*
+ *  ioctl Command
+ */
+/*!
+  \brief ATM IOCTL Magic Number
+ */
+#define PPE_ATM_IOC_MAGIC       'o'
+/*!
+  \brief ATM IOCTL Command - Get Cell Level MIB Counters
+
+   This command is obsolete. User can get cell level MIB from DSL API.
+   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
+
+   Get AAL5 packet counters.
+   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get Per PVC MIB Counters
+
+   Get AAL5 packet counters for each PVC.
+   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
+ */
+#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
+/*!
+  \brief Total Number of ATM IOCTL Commands
+ */
+#define PPE_ATM_IOC_MAXNR       3
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                 API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+    unsigned int    port_num;
+    unsigned int    tx_link_rate[2];
+};
+#endif
+
+
+
+#endif  //  IFX_ATM_H
+
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm.h b/package/ifxmips-dsl-api/src/ifxmips_atm.h
new file mode 100644 (file)
index 0000000..ed90b5d
--- /dev/null
@@ -0,0 +1,172 @@
+/******************************************************************************
+**
+** FILE NAME    : ifx_atm.h
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 17 Jun 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : Global ATM driver header file
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+#ifndef IFX_ATM_H
+#define IFX_ATM_H
+
+
+
+/*!
+  \defgroup IFX_ATM UEIP Project - ATM driver module
+  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+  \defgroup IFX_ATM_IOCTL IOCTL Commands
+  \ingroup IFX_ATM
+  \brief IOCTL Commands used by user application.
+ */
+
+/*!
+  \defgroup IFX_ATM_STRUCT Structures
+  \ingroup IFX_ATM
+  \brief Structures used by user application.
+ */
+
+/*!
+  \file ifx_atm.h
+  \ingroup IFX_ATM
+  \brief ATM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_STRUCT
+ */
+/*@{*/
+
+/*
+ *  ATM MIB
+ */
+
+typedef struct {
+       __u32   ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
+       __u32   ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
+       __u32   ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
+       __u32   ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
+       __u32   ifInErrors;         /*!< counter of error ingress cells     */
+       __u32   ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
+       __u32   ifOutErrors;        /*!< counter of error egress cells      */
+} atm_cell_ifEntry_t;
+
+typedef struct {
+       __u32   ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
+       __u32   ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
+       __u32   ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
+       __u32   ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
+       __u32   ifInUcastPkts;      /*!< counter of ingress packets         */
+       __u32   ifOutUcastPkts;     /*!< counter of egress packets          */
+       __u32   ifInErrors;         /*!< counter of error ingress packets   */
+       __u32   ifInDiscards;       /*!< counter of dropped ingress packets */
+       __u32   ifOutErros;         /*!< counter of error egress packets    */
+       __u32   ifOutDiscards;      /*!< counter of dropped egress packets  */
+} atm_aal5_ifEntry_t;
+
+typedef struct {
+       __u32   aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
+       __u32   aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
+       __u32   aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
+} atm_aal5_vcc_t;
+
+typedef struct {
+       int             vpi;        /*!< VPI of the VCC to get MIB counters */
+       int             vci;        /*!< VCI of the VCC to get MIB counters */
+       atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
+} atm_aal5_vcc_x_t;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                IOCTL
+ * ####################################
+ */
+
+/*!
+  \addtogroup IFX_ATM_IOCTL
+ */
+/*@{*/
+
+/*
+ *  ioctl Command
+ */
+/*!
+  \brief ATM IOCTL Magic Number
+ */
+#define PPE_ATM_IOC_MAGIC       'o'
+/*!
+  \brief ATM IOCTL Command - Get Cell Level MIB Counters
+
+   This command is obsolete. User can get cell level MIB from DSL API.
+   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
+
+   Get AAL5 packet counters.
+   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
+/*!
+  \brief ATM IOCTL Command - Get Per PVC MIB Counters
+
+   Get AAL5 packet counters for each PVC.
+   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
+ */
+#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
+/*!
+  \brief Total Number of ATM IOCTL Commands
+ */
+#define PPE_ATM_IOC_MAXNR       3
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ *                 API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+    unsigned int    port_num;
+    unsigned int    tx_link_rate[2];
+};
+#endif
+
+
+
+#endif  //  IFX_ATM_H
+
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_core.c b/package/ifxmips-dsl-api/src/ifxmips_atm_core.c
new file mode 100644 (file)
index 0000000..5d1af1f
--- /dev/null
@@ -0,0 +1,2507 @@
+/******************************************************************************
+**
+** FILE NAME    : ifxmips_atm_core.c
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 7 Jul 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : ATM driver common source file (core functions)
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+
+
+/*
+ * ####################################
+ *              Version No.
+ * ####################################
+ */
+
+#define IFX_ATM_VER_MAJOR               1
+#define IFX_ATM_VER_MID                 0
+#define IFX_ATM_VER_MINOR               8
+
+
+
+/*
+ * ####################################
+ *              Head File
+ * ####################################
+ */
+
+/*
+ *  Common Head File
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <linux/atmdev.h>
+#include <linux/atm.h>
+
+/*
+ *  Chip Specific Head File
+ */
+#include <asm/ifx/ifx_types.h>
+#include <asm/ifx/ifx_regs.h>
+#include <asm/ifx/common_routines.h>
+#include "ifxmips_atm_core.h"
+
+
+
+/*
+ * ####################################
+ *        Kernel Version Adaption
+ * ####################################
+ */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
+  #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
+  #define MODULE_PARM(a, b)         module_param(a, int, 0)
+#else
+  #define MODULE_PARM_ARRAY(a, b)   MODULE_PARM(a, b)
+#endif
+
+
+
+/*!
+  \addtogroup IFXMIPS_ATM_MODULE_PARAMS
+ */
+/*@{*/
+/*
+ * ####################################
+ *   Parameters to Configure PPE
+ * ####################################
+ */
+/*!
+  \brief QSB cell delay variation due to concurrency
+ */
+static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
+/*!
+  \brief QSB scheduler burst length
+ */
+static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
+/*!
+  \brief QSB time step, all legal values are 1, 2, 4
+ */
+static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
+
+/*!
+  \brief Write descriptor delay
+ */
+static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
+
+/*!
+  \brief AAL5 padding byte ('~')
+ */
+static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
+/*!
+  \brief Max frame size for RX
+ */
+static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
+/*!
+  \brief Min frame size for RX
+ */
+static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
+/*!
+  \brief Max frame size for TX
+ */
+static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
+/*!
+  \brief Min frame size for TX
+ */
+static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
+/*!
+  \brief Drop error packet in RX path
+ */
+static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
+
+/*!
+  \brief Number of descriptors per DMA RX channel
+ */
+static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
+/*!
+  \brief Number of descriptors per DMA TX channel
+ */
+static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
+/*!
+  \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
+ */
+static int dma_rx_clp1_descriptor_threshold = 38;
+/*@}*/
+
+MODULE_PARM(qsb_tau, "i");
+MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
+MODULE_PARM(qsb_srvm, "i");
+MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
+MODULE_PARM(qsb_tstep, "i");
+MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
+
+MODULE_PARM(write_descriptor_delay, "i");
+MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
+
+MODULE_PARM(aal5_fill_pattern, "i");
+MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
+MODULE_PARM(aal5r_max_packet_size, "i");
+MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
+MODULE_PARM(aal5r_min_packet_size, "i");
+MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
+MODULE_PARM(aal5s_max_packet_size, "i");
+MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
+MODULE_PARM(aal5s_min_packet_size, "i");
+MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
+MODULE_PARM(aal5r_drop_error_packet, "i");
+MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
+
+MODULE_PARM(dma_rx_descriptor_length, "i");
+MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
+MODULE_PARM(dma_tx_descriptor_length, "i");
+MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
+MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
+MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+#define DUMP_SKB_LEN                          ~0
+
+
+
+/*
+ * ####################################
+ *             Declaration
+ * ####################################
+ */
+
+/*
+ *  Network Operations
+ */
+static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
+static int ppe_open(struct atm_vcc *);
+static void ppe_close(struct atm_vcc *);
+static int ppe_send(struct atm_vcc *, struct sk_buff *);
+static int ppe_send_oam(struct atm_vcc *, void *, int);
+static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
+
+/*
+ *  ADSL LED
+ */
+static INLINE int adsl_led_flash(void);
+
+/*
+ *  64-bit operation used by MIB calculation
+ */
+static INLINE void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
+
+/*
+ *  buffer manage functions
+ */
+static INLINE struct sk_buff* alloc_skb_rx(void);
+static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
+struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
+static INLINE void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
+static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int);
+static INLINE int get_tx_desc(unsigned int);
+
+/*
+ *  mailbox handler and signal function
+ */
+static INLINE void mailbox_oam_rx_handler(void);
+static INLINE void mailbox_aal_rx_handler(void);
+#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
+  static void do_ppe_tasklet(unsigned long);
+#endif
+static irqreturn_t mailbox_irq_handler(int, void *);
+static INLINE void mailbox_signal(unsigned int, int);
+
+/*
+ *  QSB & HTU setting functions
+ */
+static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
+static void qsb_global_set(void);
+static INLINE void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
+static INLINE void clear_htu_entry(unsigned int);
+static void validate_oam_htu_entry(void);
+static void invalidate_oam_htu_entry(void);
+
+/*
+ *  look up for connection ID
+ */
+static INLINE int find_vpi(unsigned int);
+static INLINE int find_vpivci(unsigned int, unsigned int);
+static INLINE int find_vcc(struct atm_vcc *);
+
+/*
+ *  Debug Functions
+ */
+#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
+  static void dump_skb(struct sk_buff *, u32, char *, int, int, int);
+#else
+  #define dump_skb(skb, len, title, port, ch, is_tx)    do {} while (0)
+#endif
+
+/*
+ *  Proc File Functions
+ */
+static INLINE void proc_file_create(void);
+static INLINE void proc_file_delete(void);
+static int proc_read_version(char *, char **, off_t, int, int *, void *);
+static int proc_read_mib(char *, char **, off_t, int, int *, void *);
+static int proc_write_mib(struct file *, const char *, unsigned long, void *);
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+  static int proc_read_dbg(char *, char **, off_t, int, int *, void *);
+  static int proc_write_dbg(struct file *, const char *, unsigned long, void *);
+#endif
+#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
+  static int proc_read_htu(char *, char **, off_t, int, int *, void *);
+  static int proc_read_txq(char *, char **, off_t, int, int *, void *);
+#endif
+
+/*
+ *  Proc Help Functions
+ */
+static int stricmp(const char *, const char *);
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+  static int strincmp(const char *, const char *, int);
+#endif
+static INLINE int ifx_atm_version(char *);
+//static INLINE int print_reset_domain(char *, int);
+//static INLINE int print_reset_handler(char *, int, ifx_rcu_handler_t *);
+
+/*
+ *  Init & clean-up functions
+ */
+#ifdef MODULE
+  static INLINE void reset_ppe(void);
+#endif
+static INLINE void check_parameters(void);
+static INLINE int init_priv_data(void);
+static INLINE void clear_priv_data(void);
+static INLINE void init_rx_tables(void);
+static INLINE void init_tx_tables(void);
+
+/*
+ *  Exteranl Function
+ */
+#if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
+  extern void ifx_push_oam(unsigned char *);
+#else
+  static inline void ifx_push_oam(unsigned char *dummy) {}
+#endif
+#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
+  extern int ifx_mei_atm_led_blink(void);
+  extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
+#else
+  static inline int ifx_mei_atm_led_blink(void) { return IFX_SUCCESS; }
+  static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
+  {
+    if ( is_showtime != NULL )
+        *is_showtime = 0;
+    return IFX_SUCCESS;
+  }
+#endif
+
+/*
+ *  External variable
+ */
+extern struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int);
+#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
+  extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
+  extern int (*ifx_mei_atm_showtime_exit)(void);
+#else
+  int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
+  EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
+  int (*ifx_mei_atm_showtime_exit)(void) = NULL;
+  EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
+#endif
+
+
+
+/*
+ * ####################################
+ *            Local Variable
+ * ####################################
+ */
+
+static struct atm_priv_data g_atm_priv_data;
+
+static struct atmdev_ops g_ifx_atm_ops = {
+    .open       = ppe_open,
+    .close      = ppe_close,
+    .ioctl      = ppe_ioctl,
+    .send       = ppe_send,
+    .send_oam  = ppe_send_oam,
+    .change_qos        = ppe_change_qos,
+    .owner      = THIS_MODULE,
+};
+
+#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
+  DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
+#endif
+
+static int g_showtime = 0;
+static void *g_xdata_addr = NULL;
+
+unsigned int ifx_atm_dbg_enable = 0;
+
+static struct proc_dir_entry* g_atm_dir = NULL;
+
+
+
+/*
+ * ####################################
+ *            Local Function
+ * ####################################
+ */
+
+static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
+{
+    int ret = 0;
+    atm_cell_ifEntry_t mib_cell;
+    atm_aal5_ifEntry_t mib_aal5;
+    atm_aal5_vcc_x_t mib_vcc;
+    unsigned int value;
+    int conn;
+
+    if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
+        || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
+        return -ENOTTY;
+
+    if ( _IOC_DIR(cmd) & _IOC_READ )
+        ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
+    else if ( _IOC_DIR(cmd) & _IOC_WRITE )
+        ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
+    if ( ret )
+        return -EFAULT;
+
+    switch ( cmd )
+    {
+    case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
+        /*  These MIB should be read at ARC side, now put zero only.    */
+        mib_cell.ifHCInOctets_h = 0;
+        mib_cell.ifHCInOctets_l = 0;
+        mib_cell.ifHCOutOctets_h = 0;
+        mib_cell.ifHCOutOctets_l = 0;
+        mib_cell.ifInErrors = 0;
+        mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
+        mib_cell.ifOutErrors = 0;
+
+        ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
+        break;
+
+    case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
+        value = WAN_MIB_TABLE->wrx_total_byte;
+        u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
+        g_atm_priv_data.prev_wrx_total_byte = value;
+        mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
+        mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
+
+        value = WAN_MIB_TABLE->wtx_total_byte;
+        u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
+        g_atm_priv_data.prev_wtx_total_byte = value;
+        mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
+        mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
+
+        mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
+        mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
+        mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
+        mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
+        mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
+        mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
+
+        ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
+        break;
+
+    case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
+        copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
+        conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
+        if ( conn >= 0 )
+        {
+            mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
+            mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
+            mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
+            ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
+        }
+        else
+            ret = -EINVAL;
+        break;
+
+    default:
+        ret = -ENOIOCTLCMD;
+    }
+
+    return ret;
+}
+
+static int ppe_open(struct atm_vcc *vcc)
+{
+    int ret;
+    short vpi = vcc->vpi;
+    int   vci = vcc->vci;
+    struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
+    int conn;
+    int f_enable_irq = 0;
+#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+    int sys_flag;
+#endif
+
+    if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
+        return -EPROTONOSUPPORT;
+
+    /*  check bandwidth */
+    if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
+      || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
+      || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
+      || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
+    {
+        ret = -EINVAL;
+        goto PPE_OPEN_EXIT;
+    }
+
+    /*  check existing vpi,vci  */
+    conn = find_vpivci(vpi, vci);
+    if ( conn >= 0 ) {
+        ret = -EADDRINUSE;
+        goto PPE_OPEN_EXIT;
+    }
+
+    /*  check whether it need to enable irq */
+    if ( g_atm_priv_data.conn_table == 0 )
+        f_enable_irq = 1;
+
+    /*  allocate connection */
+    for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
+        if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
+            g_atm_priv_data.conn[conn].vcc = vcc;
+            break;
+        }
+    }
+    if ( conn == MAX_PVC_NUMBER )
+    {
+        ret = -EINVAL;
+        goto PPE_OPEN_EXIT;
+    }
+
+    /*  reserve bandwidth   */
+    switch ( vcc->qos.txtp.traffic_class ) {
+    case ATM_CBR:
+    case ATM_VBR_RT:
+        port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
+        break;
+    case ATM_VBR_NRT:
+        port->tx_current_cell_rate += vcc->qos.txtp.scr;
+        break;
+    case ATM_UBR_PLUS:
+        port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
+        break;
+    }
+
+    /*  set qsb */
+    set_qsb(vcc, &vcc->qos, conn);
+
+    /*  update atm_vcc structure    */
+    vcc->itf = (int)vcc->dev->dev_data;
+    vcc->vpi = vpi;
+    vcc->vci = vci;
+    set_bit(ATM_VF_READY, &vcc->flags);
+
+    /*  enable irq  */
+    if (f_enable_irq ) {
+        ifx_atm_alloc_tx = atm_alloc_tx;
+
+        *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
+        *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
+
+        enable_irq(PPE_MAILBOX_IGU1_INT);
+    }
+
+    /*  set port    */
+    WTX_QUEUE_CONFIG(conn)->sbid = (int)vcc->dev->dev_data;
+
+    /*  set htu entry   */
+    set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
+
+#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+    //  ReTX: occupy second QID
+    local_irq_save(sys_flag);
+    if ( g_retx_htu && vcc->qos.aal == ATM_AAL5 )
+    {
+        int retx_conn = (conn + 8) % 16;    //  ReTX queue
+
+        if ( retx_conn < MAX_PVC_NUMBER && test_and_set_bit(retx_conn, &g_atm_priv_data.conn_table) == 0 ) {
+            g_atm_priv_data.conn[retx_conn].vcc = vcc;
+            set_htu_entry(vpi, vci, retx_conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 1);
+        }
+    }
+    local_irq_restore(sys_flag);
+#endif
+
+    ret = 0;
+
+PPE_OPEN_EXIT:
+    return ret;
+}
+
+static void ppe_close(struct atm_vcc *vcc)
+{
+    int conn;
+    struct port *port;
+    struct connection *connection;
+
+    if ( vcc == NULL )
+        return;
+
+    /*  get connection id   */
+    conn = find_vcc(vcc);
+    if ( conn < 0 ) {
+        err("can't find vcc");
+        goto PPE_CLOSE_EXIT;
+    }
+    connection = &g_atm_priv_data.conn[conn];
+    port = &g_atm_priv_data.port[connection->port];
+
+    /*  clear htu   */
+    clear_htu_entry(conn);
+
+    /*  release connection  */
+    clear_bit(conn, &g_atm_priv_data.conn_table);
+    connection->vcc = NULL;
+    connection->aal5_vcc_crc_err = 0;
+    connection->aal5_vcc_oversize_sdu = 0;
+
+    /*  disable irq */
+    if ( g_atm_priv_data.conn_table == 0 ) {
+        disable_irq(PPE_MAILBOX_IGU1_INT);
+        ifx_atm_alloc_tx = NULL;
+    }
+
+    /*  release bandwidth   */
+    switch ( vcc->qos.txtp.traffic_class )
+    {
+    case ATM_CBR:
+    case ATM_VBR_RT:
+        port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
+        break;
+    case ATM_VBR_NRT:
+        port->tx_current_cell_rate -= vcc->qos.txtp.scr;
+        break;
+    case ATM_UBR_PLUS:
+        port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
+        break;
+    }
+
+PPE_CLOSE_EXIT:
+    return;
+}
+
+static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
+{
+    int ret;
+    int conn;
+    int desc_base;
+    struct tx_descriptor reg_desc = {0};
+
+    if ( vcc == NULL || skb == NULL )
+        return -EINVAL;
+
+    skb_get(skb);
+    atm_free_tx_skb_vcc(skb, vcc);
+
+    conn = find_vcc(vcc);
+    if ( conn < 0 ) {
+        ret = -EINVAL;
+        goto FIND_VCC_FAIL;
+    }
+
+    if ( !g_showtime ) {
+        err("not in showtime");
+        ret = -EIO;
+        goto PPE_SEND_FAIL;
+    }
+
+    if ( vcc->qos.aal == ATM_AAL5 ) {
+        int byteoff;
+        int datalen;
+        struct tx_inband_header *header;
+
+        datalen = skb->len;
+        byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
+
+        if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH ) {
+            struct sk_buff *new_skb;
+
+            new_skb = alloc_skb_tx(datalen);
+            if ( new_skb == NULL ) {
+                err("ALLOC_SKB_TX_FAIL");
+                ret = -ENOMEM;
+                goto PPE_SEND_FAIL;
+            }
+            skb_put(new_skb, datalen);
+            memcpy(new_skb->data, skb->data, datalen);
+            dev_kfree_skb_any(skb);
+            skb = new_skb;
+            byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
+        }
+
+        skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
+
+        header = (struct tx_inband_header *)skb->data;
+
+        /*  setup inband trailer    */
+        header->uu   = 0;
+        header->cpi  = 0;
+        header->pad  = aal5_fill_pattern;
+        header->res1 = 0;
+
+        /*  setup cell header   */
+        header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
+        header->pti  = ATM_PTI_US0;
+        header->vci  = vcc->vci;
+        header->vpi  = vcc->vpi;
+        header->gfc  = 0;
+
+        /*  setup descriptor    */
+        reg_desc.dataptr = (unsigned int)skb->data >> 2;
+        reg_desc.datalen = datalen;
+        reg_desc.byteoff = byteoff;
+        reg_desc.iscell  = 0;
+    }
+    else {
+        /*  if data pointer is not aligned, allocate new sk_buff    */
+        if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) {
+            struct sk_buff *new_skb;
+
+            err("skb->data not aligned");
+
+            new_skb = alloc_skb_tx(skb->len);
+            if ( new_skb == NULL ) {
+                err("ALLOC_SKB_TX_FAIL");
+                ret = -ENOMEM;
+                goto PPE_SEND_FAIL;
+            }
+            skb_put(new_skb, skb->len);
+            memcpy(new_skb->data, skb->data, skb->len);
+            dev_kfree_skb_any(skb);
+            skb = new_skb;
+        }
+
+        reg_desc.dataptr = (unsigned int)skb->data >> 2;
+        reg_desc.datalen = skb->len;
+        reg_desc.byteoff = 0;
+        reg_desc.iscell  = 1;
+    }
+
+    reg_desc.own = 1;
+    reg_desc.c = 1;
+    reg_desc.sop = reg_desc.eop = 1;
+
+    desc_base = get_tx_desc(conn);
+    if ( desc_base < 0 ) {
+        err("ALLOC_TX_CONNECTION_FAIL");
+        ret = -EIO;
+        goto PPE_SEND_FAIL;
+    }
+
+    if ( vcc->stats )
+        atomic_inc(&vcc->stats->tx);
+    if ( vcc->qos.aal == ATM_AAL5 )
+        g_atm_priv_data.wtx_pdu++;
+
+    /*  update descriptor send pointer  */
+    if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
+        dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
+    g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
+
+    /*  write discriptor to memory and write back cache */
+    g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
+    dma_cache_wback((unsigned long)skb->data, skb->len);
+
+    dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1);
+
+    mailbox_signal(conn, 1);
+
+    adsl_led_flash();
+
+    return 0;
+
+FIND_VCC_FAIL:
+    err("FIND_VCC_FAIL");
+    g_atm_priv_data.wtx_err_pdu++;
+    dev_kfree_skb_any(skb);
+    return ret;
+
+PPE_SEND_FAIL:
+    if ( vcc->qos.aal == ATM_AAL5 )
+        g_atm_priv_data.wtx_drop_pdu++;
+    if ( vcc->stats )
+        atomic_inc(&vcc->stats->tx_err);
+    dev_kfree_skb_any(skb);
+    return ret;
+}
+
+static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
+{
+    int conn;
+    struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
+    int desc_base;
+    struct sk_buff *skb;
+    struct tx_descriptor reg_desc = {0};
+
+    if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
+        && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
+        || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
+        && find_vpi(uni_cell_header->vpi) < 0) )
+        return -EINVAL;
+
+    if ( !g_showtime ) {
+        err("not in showtime");
+        return -EIO;
+    }
+
+    conn = find_vcc(vcc);
+    if ( conn < 0 ) {
+        err("FIND_VCC_FAIL");
+        return -EINVAL;
+    }
+
+    skb = alloc_skb_tx(CELL_SIZE);
+    if ( skb == NULL ) {
+        err("ALLOC_SKB_TX_FAIL");
+        return -ENOMEM;
+    }
+    memcpy(skb->data, cell, CELL_SIZE);
+
+    reg_desc.dataptr = (unsigned int)skb->data >> 2;
+    reg_desc.datalen = CELL_SIZE;
+    reg_desc.byteoff = 0;
+    reg_desc.iscell  = 1;
+
+    reg_desc.own = 1;
+    reg_desc.c = 1;
+    reg_desc.sop = reg_desc.eop = 1;
+
+    desc_base = get_tx_desc(conn);
+    if ( desc_base < 0 ) {
+        dev_kfree_skb_any(skb);
+        err("ALLOC_TX_CONNECTION_FAIL");
+        return -EIO;
+    }
+
+    if ( vcc->stats )
+        atomic_inc(&vcc->stats->tx);
+
+    /*  update descriptor send pointer  */
+    if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
+        dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
+    g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
+
+    /*  write discriptor to memory and write back cache */
+    g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
+    dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
+
+    dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1);
+
+    mailbox_signal(conn, 1);
+
+    adsl_led_flash();
+
+    return 0;
+}
+
+static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
+{
+    int conn;
+
+    if ( vcc == NULL || qos == NULL )
+        return -EINVAL;
+
+    conn = find_vcc(vcc);
+    if ( conn < 0 )
+        return -EINVAL;
+
+    set_qsb(vcc, qos, conn);
+
+    return 0;
+}
+
+static INLINE int adsl_led_flash(void)
+{
+    return ifx_mei_atm_led_blink();
+}
+
+/*
+ *  Description:
+ *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
+ *  Input:
+ *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
+ *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
+ *    ret  --- ppe_u64_t, pointer to a variable to hold result
+ *  Output:
+ *    none
+ */
+static INLINE void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
+{
+    ret->l = opt1.l + opt2;
+    if ( ret->l < opt1.l || ret->l < opt2 )
+        ret->h++;
+}
+
+static INLINE struct sk_buff* alloc_skb_rx(void)
+{
+    struct sk_buff *skb;
+
+    skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
+    if ( skb != NULL ) {
+        /*  must be burst length alignment  */
+        if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
+            skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
+        /*  pub skb in reserved area "skb->data - 4"    */
+        *((struct sk_buff **)skb->data - 1) = skb;
+        /*  write back and invalidate cache */
+        dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
+        /*  invalidate cache    */
+        dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
+    }
+
+    return skb;
+}
+
+static INLINE struct sk_buff* alloc_skb_tx(unsigned int size)
+{
+    struct sk_buff *skb;
+
+    /*  allocate memory including header and padding    */
+    size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
+    size &= ~(DATA_BUFFER_ALIGNMENT - 1);
+    skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
+    /*  must be burst length alignment  */
+    if ( skb != NULL )
+        skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
+    return skb;
+}
+
+struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
+{
+    int conn;
+    struct sk_buff *skb;
+
+    /*  oversize packet */
+    if ( size > aal5s_max_packet_size ) {
+        err("atm_alloc_tx: oversize packet");
+        return NULL;
+    }
+    /*  send buffer overflow    */
+    if ( atomic_read(&sk_atm(vcc)->sk_wmem_alloc) && !atm_may_send(vcc, size) ) {
+        err("atm_alloc_tx: send buffer overflow");
+        return NULL;
+    }
+    conn = find_vcc(vcc);
+    if ( conn < 0 ) {
+        err("atm_alloc_tx: unknown VCC");
+        return NULL;
+    }
+
+    skb = dev_alloc_skb(size);
+    if ( skb == NULL ) {
+        err("atm_alloc_tx: sk buffer is used up");
+        return NULL;
+    }
+
+    atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
+
+    return skb;
+}
+
+static INLINE void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
+{
+    if ( vcc->pop != NULL )
+        vcc->pop(vcc, skb);
+    else
+        dev_kfree_skb_any(skb);
+}
+
+static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
+{
+    unsigned int skb_dataptr;
+    struct sk_buff *skb;
+
+    skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
+    skb = *(struct sk_buff **)skb_dataptr;
+
+    ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
+    ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
+
+    return skb;
+}
+
+static INLINE int get_tx_desc(unsigned int conn)
+{
+    int desc_base = -1;
+    struct connection *p_conn = &g_atm_priv_data.conn[conn];
+
+    if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
+        desc_base = p_conn->tx_desc_pos;
+        if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
+            p_conn->tx_desc_pos = 0;
+    }
+
+    return desc_base;
+}
+
+static INLINE void mailbox_oam_rx_handler(void)
+{
+    unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
+    struct rx_descriptor reg_desc;
+    struct uni_cell_header *header;
+    int conn;
+    struct atm_vcc *vcc;
+    unsigned int i;
+
+    for ( i = 0; i < vlddes; i++ ) {
+        do {
+            reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
+        } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
+
+        header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
+
+        if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
+            conn = find_vpivci(header->vpi, header->vci);
+        else if ( header->vci == 0x03 || header->vci == 0x04 )
+            conn = find_vpi(header->vpi);
+        else
+            conn = -1;
+
+        if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
+            vcc = g_atm_priv_data.conn[conn].vcc;
+
+            if ( vcc->push_oam != NULL )
+                vcc->push_oam(vcc, header);
+            else
+                ifx_push_oam((unsigned char *)header);
+
+            adsl_led_flash();
+        }
+
+        reg_desc.byteoff = 0;
+        reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
+        reg_desc.own = 1;
+        reg_desc.c   = 0;
+
+        g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
+        if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
+            g_atm_priv_data.oam_desc_pos = 0;
+
+        mailbox_signal(RX_DMA_CH_OAM, 0);
+    }
+}
+
+static INLINE void mailbox_aal_rx_handler(void)
+{
+    unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
+    struct rx_descriptor reg_desc;
+    int conn;
+    struct atm_vcc *vcc;
+    struct sk_buff *skb, *new_skb;
+    struct rx_inband_trailer *trailer;
+    unsigned int i;
+
+    for ( i = 0; i < vlddes; i++ ) {
+        do {
+            reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
+        } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
+
+        conn = reg_desc.id;
+
+        if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
+            vcc = g_atm_priv_data.conn[conn].vcc;
+
+            skb = get_skb_rx_pointer(reg_desc.dataptr);
+
+            if ( reg_desc.err ) {
+                if ( vcc->qos.aal == ATM_AAL5 ) {
+                    trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
+                    if ( trailer->stw_crc )
+                        g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
+                    if ( trailer->stw_ovz )
+                        g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
+                    g_atm_priv_data.wrx_drop_pdu++;
+                }
+                if ( vcc->stats ) {
+                    atomic_inc(&vcc->stats->rx_drop);
+                    atomic_inc(&vcc->stats->rx_err);
+                }
+            }
+            else if ( atm_charge(vcc, skb->truesize) ) {
+                new_skb = alloc_skb_rx();
+                if ( new_skb != NULL ) {
+                    skb_reserve(skb, reg_desc.byteoff);
+                    skb_put(skb, reg_desc.datalen);
+                    ATM_SKB(skb)->vcc = vcc;
+
+                    dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 0);
+
+                    vcc->push(vcc, skb);
+
+                    if ( vcc->qos.aal == ATM_AAL5 )
+                        g_atm_priv_data.wrx_pdu++;
+                    if ( vcc->stats )
+                        atomic_inc(&vcc->stats->rx);
+                    adsl_led_flash();
+
+                    reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
+                }
+                else {
+                    atm_return(vcc, skb->truesize);
+                    if ( vcc->qos.aal == ATM_AAL5 )
+                        g_atm_priv_data.wrx_drop_pdu++;
+                    if ( vcc->stats )
+                        atomic_inc(&vcc->stats->rx_drop);
+                }
+            }
+            else {
+                if ( vcc->qos.aal == ATM_AAL5 )
+                    g_atm_priv_data.wrx_drop_pdu++;
+                if ( vcc->stats )
+                    atomic_inc(&vcc->stats->rx_drop);
+            }
+        }
+        else {
+            g_atm_priv_data.wrx_drop_pdu++;
+        }
+
+        reg_desc.byteoff = 0;
+        reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
+        reg_desc.own = 1;
+        reg_desc.c   = 0;
+
+        g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
+        if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
+            g_atm_priv_data.aal_desc_pos = 0;
+
+        mailbox_signal(RX_DMA_CH_AAL, 0);
+    }
+}
+
+#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
+static void do_ppe_tasklet(unsigned long arg)
+{
+    *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
+    mailbox_oam_rx_handler();
+    mailbox_aal_rx_handler();
+    if ( (*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0 )
+        tasklet_schedule(&g_dma_tasklet);
+    else
+        enable_irq(PPE_MAILBOX_IGU1_INT);
+}
+#endif
+
+static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
+{
+    if ( !*MBOX_IGU1_ISR )
+        return IRQ_HANDLED;
+
+#if defined(ENABLE_TASKLET) && ENABLE_TASKLET
+    disable_irq(PPE_MAILBOX_IGU1_INT);
+    tasklet_schedule(&g_dma_tasklet);
+#else
+    *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
+    mailbox_oam_rx_handler();
+    mailbox_aal_rx_handler();
+#endif
+
+    return IRQ_HANDLED;
+}
+
+static INLINE void mailbox_signal(unsigned int queue, int is_tx)
+{
+    if ( is_tx ) {
+        while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) );
+        *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
+    }
+    else {
+        while ( MBOX_IGU3_ISR_ISR(queue) );
+        *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
+    }
+}
+
+static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
+{
+    unsigned int qsb_clk = ifx_get_fpi_hz();
+    unsigned int qsb_qid = queue + FIRST_QSB_QID;
+    union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
+    union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
+    unsigned int tmp;
+
+#if defined(DEBUG_QOS) && DEBUG_QOS
+    if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
+        static char *str_traffic_class[9] = {
+            "ATM_NONE",
+            "ATM_UBR",
+            "ATM_CBR",
+            "ATM_VBR",
+            "ATM_ABR",
+            "ATM_ANYCLASS",
+            "ATM_VBR_RT",
+            "ATM_UBR_PLUS",
+            "ATM_MAX_PCR"
+        };
+        printk(KERN_INFO  "QoS Parameters:\n");
+        printk(KERN_INFO  "\tAAL          : %d\n", qos->aal);
+        printk(KERN_INFO  "\tTX Traffic Class: %s\n", str_traffic_class[qos->txtp.traffic_class]);
+        printk(KERN_INFO  "\tTX Max PCR      : %d\n", qos->txtp.max_pcr);
+        printk(KERN_INFO  "\tTX Min PCR      : %d\n", qos->txtp.min_pcr);
+        printk(KERN_INFO  "\tTX PCR          : %d\n", qos->txtp.pcr);
+        printk(KERN_INFO  "\tTX Max CDV      : %d\n", qos->txtp.max_cdv);
+        printk(KERN_INFO  "\tTX Max SDU      : %d\n", qos->txtp.max_sdu);
+        printk(KERN_INFO  "\tTX SCR          : %d\n", qos->txtp.scr);
+        printk(KERN_INFO  "\tTX MBS          : %d\n", qos->txtp.mbs);
+        printk(KERN_INFO  "\tTX CDV          : %d\n", qos->txtp.cdv);
+        printk(KERN_INFO  "\tRX Traffic Class: %s\n", str_traffic_class[qos->rxtp.traffic_class]);
+        printk(KERN_INFO  "\tRX Max PCR      : %d\n", qos->rxtp.max_pcr);
+        printk(KERN_INFO  "\tRX Min PCR      : %d\n", qos->rxtp.min_pcr);
+        printk(KERN_INFO  "\tRX PCR          : %d\n", qos->rxtp.pcr);
+        printk(KERN_INFO  "\tRX Max CDV      : %d\n", qos->rxtp.max_cdv);
+        printk(KERN_INFO  "\tRX Max SDU      : %d\n", qos->rxtp.max_sdu);
+        printk(KERN_INFO  "\tRX SCR          : %d\n", qos->rxtp.scr);
+        printk(KERN_INFO  "\tRX MBS          : %d\n", qos->rxtp.mbs);
+        printk(KERN_INFO  "\tRX CDV          : %d\n", qos->rxtp.cdv);
+    }
+#endif  //  defined(DEBUG_QOS) && DEBUG_QOS
+
+    /*
+     *  Peak Cell Rate (PCR) Limiter
+     */
+    if ( qos->txtp.max_pcr == 0 )
+        qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
+    else {
+        /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
+        tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
+        /*  check if overflow takes place   */
+        qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
+    }
+
+    //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
+    //  Send packets to these two PVCs at same time, it trigger strange behavior.
+    //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
+    //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
+    //  To work around, create UBR always with max_pcr.
+    //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
+    if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
+        int port = g_atm_priv_data.conn[queue].port;
+        unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
+
+        tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
+        if ( tmp > QSB_TP_TS_MAX )
+            tmp = QSB_TP_TS_MAX;
+        else if ( tmp < 1 )
+            tmp = 1;
+        qsb_queue_parameter_table.bit.tp = tmp;
+    }
+
+    /*
+     *  Weighted Fair Queueing Factor (WFQF)
+     */
+    switch ( qos->txtp.traffic_class ) {
+    case ATM_CBR:
+    case ATM_VBR_RT:
+        /*  real time queue gets weighted fair queueing bypass  */
+        qsb_queue_parameter_table.bit.wfqf = 0;
+        break;
+    case ATM_VBR_NRT:
+    case ATM_UBR_PLUS:
+        /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
+        /*  WFQF is maximum cell rate / garenteed cell rate                                             */
+        /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
+        if ( qos->txtp.min_pcr == 0 )
+            qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
+        else
+        {
+            tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
+            if ( tmp == 0 )
+                qsb_queue_parameter_table.bit.wfqf = 1;
+            else if ( tmp > QSB_WFQ_NONUBR_MAX )
+                qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
+            else
+                qsb_queue_parameter_table.bit.wfqf = tmp;
+        }
+        break;
+    default:
+    case ATM_UBR:
+        qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
+    }
+
+    /*
+     *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
+     */
+    if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
+        if ( qos->txtp.scr == 0 ) {
+            /*  disable shaper  */
+            qsb_queue_vbr_parameter_table.bit.taus = 0;
+            qsb_queue_vbr_parameter_table.bit.ts = 0;
+        }
+        else {
+            /*  Cell Loss Priority  (CLP)   */
+            if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
+                /*  CLP1    */
+                qsb_queue_parameter_table.bit.vbr = 1;
+            else
+                /*  CLP0    */
+                qsb_queue_parameter_table.bit.vbr = 0;
+            /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
+            tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
+            qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
+            tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
+            if ( tmp == 0 )
+                qsb_queue_vbr_parameter_table.bit.taus = 1;
+            else if ( tmp > QSB_TAUS_MAX )
+                qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
+            else
+                qsb_queue_vbr_parameter_table.bit.taus = tmp;
+        }
+    }
+    else {
+        qsb_queue_vbr_parameter_table.bit.taus = 0;
+        qsb_queue_vbr_parameter_table.bit.ts = 0;
+    }
+
+    /*  Queue Parameter Table (QPT) */
+    *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
+    *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
+    *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
+#if defined(DEBUG_QOS) && DEBUG_QOS
+    if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
+        printk("QPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
+#endif
+    /*  Queue VBR Paramter Table (QVPT) */
+    *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
+    *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
+    *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
+#if defined(DEBUG_QOS) && DEBUG_QOS
+    if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
+        printk("QVPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
+#endif
+
+#if defined(DEBUG_QOS) && DEBUG_QOS
+    if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
+        printk("set_qsb\n");
+        printk("  qsb_clk = %lu\n", (unsigned long)qsb_clk);
+        printk("  qsb_queue_parameter_table.bit.tp       = %d\n", (int)qsb_queue_parameter_table.bit.tp);
+        printk("  qsb_queue_parameter_table.bit.wfqf     = %d (0x%08X)\n", (int)qsb_queue_parameter_table.bit.wfqf, (int)qsb_queue_parameter_table.bit.wfqf);
+        printk("  qsb_queue_parameter_table.bit.vbr      = %d\n", (int)qsb_queue_parameter_table.bit.vbr);
+        printk("  qsb_queue_parameter_table.dword        = 0x%08X\n", (int)qsb_queue_parameter_table.dword);
+        printk("  qsb_queue_vbr_parameter_table.bit.ts   = %d\n", (int)qsb_queue_vbr_parameter_table.bit.ts);
+        printk("  qsb_queue_vbr_parameter_table.bit.taus = %d\n", (int)qsb_queue_vbr_parameter_table.bit.taus);
+        printk("  qsb_queue_vbr_parameter_table.dword    = 0x%08X\n", (int)qsb_queue_vbr_parameter_table.dword);
+    }
+#endif
+}
+
+static void qsb_global_set(void)
+{
+    unsigned int qsb_clk = ifx_get_fpi_hz();
+    int i;
+    unsigned int tmp1, tmp2, tmp3;
+
+    *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
+    *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
+    *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
+#if defined(DEBUG_QOS) && DEBUG_QOS
+    if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) {
+        printk("qsb_clk = %u\n", qsb_clk);
+        printk("QSB_ICDV (%08X) = %d (%d), QSB_SBL (%08X) = %d (%d), QSB_CFG (%08X) = %d (%d)\n", (unsigned int)QSB_ICDV, *QSB_ICDV, QSB_ICDV_TAU_SET(qsb_tau), (unsigned int)QSB_SBL, *QSB_SBL, QSB_SBL_SBL_SET(qsb_srvm), (unsigned int)QSB_CFG, *QSB_CFG, QSB_CFG_TSTEPC_SET(qsb_tstep >> 1));
+    }
+#endif
+
+    /*
+     *  set SCT and SPT per port
+     */
+    for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
+        if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
+            tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
+            tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
+            tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
+            /*  carry over to integer part (?)  */
+            if ( tmp3 == (1 << 6) )
+            {
+                tmp3 = 0;
+                tmp2++;
+            }
+            if ( tmp2 == 0 )
+                tmp2 = tmp3 = 1;
+            /*  1. set mask                                 */
+            /*  2. write value to data transfer register    */
+            /*  3. start the tranfer                        */
+            /*  SCT (FracRate)  */
+            *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
+            *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
+            *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
+#if defined(DEBUG_QOS) && DEBUG_QOS
+            if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
+                printk("SCT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
+#endif
+            /*  SPT (SBV + PN + IntRage)    */
+            *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
+            *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
+            *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01);
+#if defined(DEBUG_QOS) && DEBUG_QOS
+            if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) )
+                printk("SPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC);
+#endif
+        }
+    }
+}
+
+static INLINE void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
+{
+    struct htu_entry htu_entry = {  res1:       0x00,
+                                    clp:        is_retx ? 0x01 : 0x00,
+                                    pid:        g_atm_priv_data.conn[queue].port & 0x01,
+                                    vpi:        vpi,
+                                    vci:        vci,
+                                    pti:        0x00,
+                                    vld:        0x01};
+
+    struct htu_mask htu_mask = {    set:        0x01,
+#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
+                                    clp:        0x01,
+                                    pid_mask:   0x02,
+#else
+                                    clp:        g_retx_htu ? 0x00 : 0x01,
+                                    pid_mask:   RETX_MODE_CFG->retx_en ? 0x03 : 0x02,
+#endif
+                                    vpi_mask:   0x00,
+#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX
+                                    vci_mask:   0x0000,
+#else
+                                    vci_mask:   RETX_MODE_CFG->retx_en ? 0xFF00 : 0x0000,
+#endif
+                                    pti_mask:   0x03,   //  0xx, user data
+                                    clear:      0x00};
+
+    struct htu_result htu_result = {res1:       0x00,
+                                    cellid:     queue,
+                                    res2:       0x00,
+                                    type:       aal5 ? 0x00 : 0x01,
+                                    ven:        0x01,
+                                    res3:       0x00,
+                                    qid:        queue};
+
+    *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
+    *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
+    *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
+}
+
+static INLINE void clear_htu_entry(unsigned int queue)
+{
+    HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
+}
+
+static void validate_oam_htu_entry(void)
+{
+    HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
+    HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
+    HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
+#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+    HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 1;
+#endif
+}
+
+static void invalidate_oam_htu_entry(void)
+{
+    HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
+    HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
+    HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
+#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+    HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 0;
+#endif
+}
+
+static INLINE int find_vpi(unsigned int vpi)
+{
+    int i;
+    unsigned int bit;
+
+    for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
+        if ( (g_atm_priv_data.conn_table & bit) != 0
+            && g_atm_priv_data.conn[i].vcc != NULL
+            && vpi == g_atm_priv_data.conn[i].vcc->vpi )
+            return i;
+    }
+
+    return -1;
+}
+
+static INLINE int find_vpivci(unsigned int vpi, unsigned int vci)
+{
+    int i;
+    unsigned int bit;
+
+    for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
+        if ( (g_atm_priv_data.conn_table & bit) != 0
+            && g_atm_priv_data.conn[i].vcc != NULL
+            && vpi == g_atm_priv_data.conn[i].vcc->vpi
+            && vci == g_atm_priv_data.conn[i].vcc->vci )
+            return i;
+    }
+
+    return -1;
+}
+
+static INLINE int find_vcc(struct atm_vcc *vcc)
+{
+    int i;
+    unsigned int bit;
+
+    for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
+        if ( (g_atm_priv_data.conn_table & bit) != 0
+            && g_atm_priv_data.conn[i].vcc == vcc )
+            return i;
+    }
+
+    return -1;
+}
+
+#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
+static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx)
+{
+    int i;
+
+    if ( !(ifx_atm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) )
+        return;
+
+    if ( skb->len < len )
+        len = skb->len;
+
+    if ( len > RX_DMA_CH_AAL_BUF_SIZE ) {
+        printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len);
+        return;
+    }
+
+    if ( ch >= 0 )
+        printk("%s (port %d, ch %d)\n", title, port, ch);
+    else
+        printk("%s\n", title);
+    printk("  skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len);
+    for ( i = 1; i <= len; i++ ) {
+        if ( i % 16 == 1 )
+            printk("  %4d:", i - 1);
+        printk(" %02X", (int)(*((char*)skb->data + i - 1) & 0xFF));
+        if ( i % 16 == 0 )
+            printk("\n");
+    }
+    if ( (i - 1) % 16 != 0 )
+        printk("\n");
+}
+#endif
+
+static INLINE void proc_file_create(void)
+{
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+    struct proc_dir_entry *res;
+#endif
+
+    g_atm_dir = proc_mkdir("driver/ifx_atm", NULL);
+
+    create_proc_read_entry("version",
+                            0,
+                            g_atm_dir,
+                            proc_read_version,
+                            NULL);
+
+    res = create_proc_entry("mib",
+                            0,
+                            g_atm_dir);
+    if ( res != NULL ) {
+        res->read_proc  = proc_read_mib;
+        res->write_proc = proc_write_mib;
+    }
+
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+    res = create_proc_entry("dbg",
+                            0,
+                            g_atm_dir);
+    if ( res != NULL ) {
+        res->read_proc  = proc_read_dbg;
+        res->write_proc = proc_write_dbg;
+    }
+#endif
+
+#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
+    create_proc_read_entry("htu",
+                            0,
+                            g_atm_dir,
+                            proc_read_htu,
+                            NULL);
+
+    create_proc_read_entry("txq",
+                            0,
+                            g_atm_dir,
+                            proc_read_txq,
+                            NULL);
+#endif
+}
+
+static INLINE void proc_file_delete(void)
+{
+#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
+    remove_proc_entry("txq", g_atm_dir);
+
+    remove_proc_entry("htu", g_atm_dir);
+#endif
+
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+    remove_proc_entry("dbg", g_atm_dir);
+#endif
+
+    remove_proc_entry("version", g_atm_dir);
+
+    remove_proc_entry("driver/ifx_atm", NULL);
+}
+
+static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)
+{
+    int len = 0;
+
+    len += ifx_atm_version(buf + len);
+
+    if ( offset >= len ) {
+        *start = buf;
+        *eof = 1;
+        return 0;
+    }
+    *start = buf + offset;
+    if ( (len -= offset) > count )
+        return count;
+    *eof = 1;
+    return len;
+}
+
+static int proc_read_mib(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+    int len = 0;
+
+    len += sprintf(page + off + len,    "Firmware\n");
+    len += sprintf(page + off + len,    "  wrx_drophtu_cell = %u\n", WAN_MIB_TABLE->wrx_drophtu_cell);
+    len += sprintf(page + off + len,    "  wrx_dropdes_pdu  = %u\n", WAN_MIB_TABLE->wrx_dropdes_pdu);
+    len += sprintf(page + off + len,    "  wrx_correct_pdu  = %u\n", WAN_MIB_TABLE->wrx_correct_pdu);
+    len += sprintf(page + off + len,    "  wrx_err_pdu      = %u\n", WAN_MIB_TABLE->wrx_err_pdu);
+    len += sprintf(page + off + len,    "  wrx_dropdes_cell = %u\n", WAN_MIB_TABLE->wrx_dropdes_cell);
+    len += sprintf(page + off + len,    "  wrx_correct_cell = %u\n", WAN_MIB_TABLE->wrx_correct_cell);
+    len += sprintf(page + off + len,    "  wrx_err_cell     = %u\n", WAN_MIB_TABLE->wrx_err_cell);
+    len += sprintf(page + off + len,    "  wrx_total_byte   = %u\n", WAN_MIB_TABLE->wrx_total_byte);
+    len += sprintf(page + off + len,    "  wtx_total_pdu    = %u\n", WAN_MIB_TABLE->wtx_total_pdu);
+    len += sprintf(page + off + len,    "  wtx_total_cell   = %u\n", WAN_MIB_TABLE->wtx_total_cell);
+    len += sprintf(page + off + len,    "  wtx_total_byte   = %u\n", WAN_MIB_TABLE->wtx_total_byte);
+    len += sprintf(page + off + len,    "Driver\n");
+    len += sprintf(page + off + len,    "  wrx_pdu      = %u\n", g_atm_priv_data.wrx_pdu);
+    len += sprintf(page + off + len,    "  wrx_drop_pdu = %u\n", g_atm_priv_data.wrx_drop_pdu);
+    len += sprintf(page + off + len,    "  wtx_pdu      = %u\n", g_atm_priv_data.wtx_pdu);
+    len += sprintf(page + off + len,    "  wtx_err_pdu  = %u\n", g_atm_priv_data.wtx_err_pdu);
+    len += sprintf(page + off + len,    "  wtx_drop_pdu = %u\n", g_atm_priv_data.wtx_drop_pdu);
+
+    *eof = 1;
+
+    return len;
+}
+
+static int proc_write_mib(struct file *file, const char *buf, unsigned long count, void *data)
+{
+    char str[2048];
+    char *p;
+    int len, rlen;
+
+    len = count < sizeof(str) ? count : sizeof(str) - 1;
+    rlen = len - copy_from_user(str, buf, len);
+    while ( rlen && str[rlen - 1] <= ' ' )
+        rlen--;
+    str[rlen] = 0;
+    for ( p = str; *p && *p <= ' '; p++, rlen-- );
+    if ( !*p )
+        return 0;
+
+    if ( stricmp(p, "clear") == 0 || stricmp(p, "clear all") == 0
+        || stricmp(p, "clean") == 0 || stricmp(p, "clean all") == 0 ) {
+        memset(WAN_MIB_TABLE, 0, sizeof(*WAN_MIB_TABLE));
+        g_atm_priv_data.wrx_pdu      = 0;
+        g_atm_priv_data.wrx_drop_pdu = 0;
+        g_atm_priv_data.wtx_pdu      = 0;
+        g_atm_priv_data.wtx_err_pdu  = 0;
+        g_atm_priv_data.wtx_drop_pdu = 0;
+    }
+
+    return count;
+}
+
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+
+static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+    int len = 0;
+
+    len += sprintf(page + off + len, "error print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR)           ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "debug print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT)   ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "assert      - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT)        ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "dump rx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX)   ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX)   ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "qos         - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS)      ? "enabled" : "disabled");
+    len += sprintf(page + off + len, "dump init   - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_INIT)     ? "enabled" : "disabled");
+
+    *eof = 1;
+
+    return len;
+}
+
+static int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data)
+{
+    static const char *dbg_enable_mask_str[] = {
+        " error print",
+        " err",
+        " debug print",
+        " dbg",
+        " assert",
+        " assert",
+        " dump rx skb",
+        " rx",
+        " dump tx skb",
+        " tx",
+        " dump qos",
+        " qos",
+        " dump init",
+        " init",
+        " all"
+    };
+    static const int dbg_enable_mask_str_len[] = {
+        12, 4,
+        12, 4,
+        7,  7,
+        12, 3,
+        12, 3,
+        9,  4,
+        10, 5,
+        4
+    };
+    u32 dbg_enable_mask[] = {
+        DBG_ENABLE_MASK_ERR,
+        DBG_ENABLE_MASK_DEBUG_PRINT,
+        DBG_ENABLE_MASK_ASSERT,
+        DBG_ENABLE_MASK_DUMP_SKB_RX,
+        DBG_ENABLE_MASK_DUMP_SKB_TX,
+        DBG_ENABLE_MASK_DUMP_QOS,
+        DBG_ENABLE_MASK_DUMP_INIT,
+        DBG_ENABLE_MASK_ALL
+    };
+
+    char str[2048];
+    char *p;
+
+    int len, rlen;
+
+    int f_enable = 0;
+    int i;
+
+    len = count < sizeof(str) ? count : sizeof(str) - 1;
+    rlen = len - copy_from_user(str, buf, len);
+    while ( rlen && str[rlen - 1] <= ' ' )
+        rlen--;
+    str[rlen] = 0;
+    for ( p = str; *p && *p <= ' '; p++, rlen-- );
+    if ( !*p )
+        return 0;
+
+    if ( strincmp(p, "enable", 6) == 0 ) {
+        p += 6;
+        f_enable = 1;
+    }
+    else if ( strincmp(p, "disable", 7) == 0 ) {
+        p += 7;
+        f_enable = -1;
+    }
+    else if ( strincmp(p, "help", 4) == 0 || *p == '?' ) {
+        printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/all] > /proc/eth/dbg\n");
+    }
+
+    if ( f_enable ) {
+        if ( *p == 0 ) {
+            if ( f_enable > 0 )
+                ifx_atm_dbg_enable |= DBG_ENABLE_MASK_ALL;
+            else
+                ifx_atm_dbg_enable &= ~DBG_ENABLE_MASK_ALL;
+        }
+        else {
+            do {
+                for ( i = 0; i < NUM_ENTITY(dbg_enable_mask_str); i++ )
+                    if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) {
+                        if ( f_enable > 0 )
+                            ifx_atm_dbg_enable |= dbg_enable_mask[i >> 1];
+                        else
+                            ifx_atm_dbg_enable &= ~dbg_enable_mask[i >> 1];
+                        p += dbg_enable_mask_str_len[i];
+                        break;
+                    }
+            } while ( i < NUM_ENTITY(dbg_enable_mask_str) );
+        }
+    }
+
+    return count;
+}
+
+#endif
+
+#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
+
+static INLINE int print_htu(char *buf, int i)
+{
+    int len = 0;
+
+    if ( HTU_ENTRY(i)->vld ) {
+        len += sprintf(buf + len, "%2d. valid\n", i);
+        len += sprintf(buf + len, "    entry  0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_ENTRY(i), HTU_ENTRY(i)->pid, HTU_ENTRY(i)->vpi, HTU_ENTRY(i)->vci, HTU_ENTRY(i)->pti);
+        len += sprintf(buf + len, "    mask   0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_MASK(i), HTU_MASK(i)->pid_mask, HTU_MASK(i)->vpi_mask, HTU_MASK(i)->vci_mask, HTU_MASK(i)->pti_mask);
+        len += sprintf(buf + len, "    result 0x%08x - type: %s, qid: %d", *(u32*)HTU_RESULT(i), HTU_RESULT(i)->type ? "cell" : "AAL5", HTU_RESULT(i)->qid);
+        if ( HTU_RESULT(i)->type )
+            len += sprintf(buf + len, ", cell id: %d, verification: %s", HTU_RESULT(i)->cellid, HTU_RESULT(i)->ven ? "on" : "off");
+        len += sprintf(buf + len, "\n");
+    }
+    else
+        len += sprintf(buf + len, "%2d. invalid\n", i);
+
+    return len;
+}
+
+static int proc_read_htu(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+    int len = 0;
+    int len_max = off + count;
+    char *pstr;
+    char str[1024];
+    int llen;
+
+    int htuts = *CFG_WRX_HTUTS;
+    int i;
+
+    pstr = *start = page;
+
+    llen = sprintf(pstr, "HTU Table (Max %d):\n", htuts);
+    pstr += llen;
+    len += llen;
+
+    for ( i = 0; i < htuts; i++ ) {
+        llen = print_htu(str, i);
+        if ( len <= off && len + llen > off ) {
+            memcpy(pstr, str + off - len, len + llen - off);
+            pstr += len + llen - off;
+        }
+        else if ( len > off ) {
+            memcpy(pstr, str, llen);
+            pstr += llen;
+        }
+        len += llen;
+        if ( len >= len_max )
+            goto PROC_READ_HTU_OVERRUN_END;
+    }
+
+    *eof = 1;
+
+    return len - off;
+
+PROC_READ_HTU_OVERRUN_END:
+
+    return len - llen - off;
+}
+
+static INLINE int print_tx_queue(char *buf, int i)
+{
+    int len = 0;
+
+    if ( (*WTX_DMACH_ON & (1 << i)) ) {
+        len += sprintf(buf + len, "%2d. valid\n", i);
+        len += sprintf(buf + len, "    queue 0x%08x - sbid %u, qsb %s\n", *(u32*)WTX_QUEUE_CONFIG(i), (unsigned int)WTX_QUEUE_CONFIG(i)->sbid, WTX_QUEUE_CONFIG(i)->qsben ? "enable" : "disable");
+        len += sprintf(buf + len, "    dma   0x%08x - base %08x, len %u, vlddes %u\n", *(u32*)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes);
+    }
+    else
+        len += sprintf(buf + len, "%2d. invalid\n", i);
+
+    return len;
+}
+
+static int proc_read_txq(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+    int len = 0;
+    int len_max = off + count;
+    char *pstr;
+    char str[1024];
+    int llen;
+
+    int i;
+
+    pstr = *start = page;
+
+    llen = sprintf(pstr, "TX Queue Config (Max %d):\n", *CFG_WTX_DCHNUM);
+    pstr += llen;
+    len += llen;
+
+    for ( i = 0; i < 16; i++ ) {
+        llen = print_tx_queue(str, i);
+        if ( len <= off && len + llen > off ) {
+            memcpy(pstr, str + off - len, len + llen - off);
+            pstr += len + llen - off;
+        }
+        else if ( len > off ) {
+            memcpy(pstr, str, llen);
+            pstr += llen;
+        }
+        len += llen;
+        if ( len >= len_max )
+            goto PROC_READ_HTU_OVERRUN_END;
+    }
+
+    *eof = 1;
+
+    return len - off;
+
+PROC_READ_HTU_OVERRUN_END:
+
+    return len - llen - off;
+}
+
+#endif
+
+static int stricmp(const char *p1, const char *p2)
+{
+    int c1, c2;
+
+    while ( *p1 && *p2 )
+    {
+        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
+        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
+        if ( (c1 -= c2) )
+            return c1;
+        p1++;
+        p2++;
+    }
+
+    return *p1 - *p2;
+}
+
+#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
+static int strincmp(const char *p1, const char *p2, int n)
+{
+    int c1 = 0, c2;
+
+    while ( n && *p1 && *p2 )
+    {
+        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
+        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
+        if ( (c1 -= c2) )
+            return c1;
+        p1++;
+        p2++;
+        n--;
+    }
+
+    return n ? *p1 - *p2 : c1;
+}
+#endif
+
+static INLINE int ifx_atm_version(char *buf)
+{
+    int len = 0;
+    unsigned int major, minor;
+
+    ifx_atm_get_fw_ver(&major, &minor);
+
+    len += sprintf(buf + len, "Infineon Technologies ATM driver version %d.%d.%d\n", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
+    len += sprintf(buf + len, "Infineon Technologies ATM (A1) firmware version %d.%d\n", major, minor);
+
+    return len;
+}
+
+#ifdef MODULE
+static INLINE void reset_ppe(void)
+{
+    //  TODO:
+}
+#endif
+
+static INLINE void check_parameters(void)
+{
+    /*  Please refer to Amazon spec 15.4 for setting these values.  */
+    if ( qsb_tau < 1 )
+        qsb_tau = 1;
+    if ( qsb_tstep < 1 )
+        qsb_tstep = 1;
+    else if ( qsb_tstep > 4 )
+        qsb_tstep = 4;
+    else if ( qsb_tstep == 3 )
+        qsb_tstep = 2;
+
+    /*  There is a delay between PPE write descriptor and descriptor is       */
+    /*  really stored in memory. Host also has this delay when writing        */
+    /*  descriptor. So PPE will use this value to determine if the write      */
+    /*  operation makes effect.                                               */
+    if ( write_descriptor_delay < 0 )
+        write_descriptor_delay = 0;
+
+    if ( aal5_fill_pattern < 0 )
+        aal5_fill_pattern = 0;
+    else
+        aal5_fill_pattern &= 0xFF;
+
+    /*  Because of the limitation of length field in descriptors, the packet  */
+    /*  size could not be larger than 64K minus overhead size.                */
+    if ( aal5r_max_packet_size < 0 )
+        aal5r_max_packet_size = 0;
+    else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
+        aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
+    if ( aal5r_min_packet_size < 0 )
+        aal5r_min_packet_size = 0;
+    else if ( aal5r_min_packet_size > aal5r_max_packet_size )
+        aal5r_min_packet_size = aal5r_max_packet_size;
+    if ( aal5s_max_packet_size < 0 )
+        aal5s_max_packet_size = 0;
+    else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
+        aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
+    if ( aal5s_min_packet_size < 0 )
+        aal5s_min_packet_size = 0;
+    else if ( aal5s_min_packet_size > aal5s_max_packet_size )
+        aal5s_min_packet_size = aal5s_max_packet_size;
+
+    if ( dma_rx_descriptor_length < 2 )
+        dma_rx_descriptor_length = 2;
+    if ( dma_tx_descriptor_length < 2 )
+        dma_tx_descriptor_length = 2;
+    if ( dma_rx_clp1_descriptor_threshold < 0 )
+        dma_rx_clp1_descriptor_threshold = 0;
+    else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
+        dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
+
+    if ( dma_tx_descriptor_length < 2 )
+        dma_tx_descriptor_length = 2;
+}
+
+static INLINE int init_priv_data(void)
+{
+    void *p;
+    int i;
+    struct rx_descriptor rx_desc = {0};
+    struct sk_buff *skb;
+    volatile struct tx_descriptor *p_tx_desc;
+    struct sk_buff **ppskb;
+
+    //  clear atm private data structure
+    memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
+
+    //  allocate memory for RX (AAL) descriptors
+    p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
+    if ( p == NULL )
+        return IFX_ERROR;
+    dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
+    g_atm_priv_data.aal_desc_base = p;
+    p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
+    g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
+
+    //  allocate memory for RX (OAM) descriptors
+    p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
+    if ( p == NULL )
+        return IFX_ERROR;
+    dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
+    g_atm_priv_data.oam_desc_base = p;
+    p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
+    g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
+
+    //  allocate memory for RX (OAM) buffer
+    p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
+    if ( p == NULL )
+        return IFX_ERROR;
+    dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
+    g_atm_priv_data.oam_buf_base = p;
+    p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
+    g_atm_priv_data.oam_buf = p;
+
+    //  allocate memory for TX descriptors
+    p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
+    if ( p == NULL )
+        return IFX_ERROR;
+    dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
+    g_atm_priv_data.tx_desc_base = p;
+
+    //  allocate memory for TX skb pointers
+    p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
+    if ( p == NULL )
+        return IFX_ERROR;
+    dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
+    g_atm_priv_data.tx_skb_base = p;
+
+    //  setup RX (AAL) descriptors
+    rx_desc.own     = 1;
+    rx_desc.c       = 0;
+    rx_desc.sop     = 1;
+    rx_desc.eop     = 1;
+    rx_desc.byteoff = 0;
+    rx_desc.id      = 0;
+    rx_desc.err     = 0;
+    rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
+    for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
+        skb = alloc_skb_rx();
+        if ( skb == NULL )
+            return IFX_ERROR;
+        rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
+        g_atm_priv_data.aal_desc[i] = rx_desc;
+    }
+
+    //  setup RX (OAM) descriptors
+    p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
+    rx_desc.own     = 1;
+    rx_desc.c       = 0;
+    rx_desc.sop     = 1;
+    rx_desc.eop     = 1;
+    rx_desc.byteoff = 0;
+    rx_desc.id      = 0;
+    rx_desc.err     = 0;
+    rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
+    for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
+        rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
+        g_atm_priv_data.oam_desc[i] = rx_desc;
+        p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
+    }
+
+    //  setup TX descriptors and skb pointers
+    p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
+    ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
+    for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
+        g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
+        g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
+    }
+
+    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
+        g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
+
+    return IFX_SUCCESS;
+}
+
+static INLINE void clear_priv_data(void)
+{
+    int i, j;
+    struct sk_buff *skb;
+
+    for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
+        if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
+            for ( j = 0; j < dma_tx_descriptor_length; j++ )
+                if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
+                    dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
+        }
+    }
+
+    if ( g_atm_priv_data.tx_skb_base != NULL )
+        kfree(g_atm_priv_data.tx_skb_base);
+
+    if ( g_atm_priv_data.tx_desc_base != NULL )
+        kfree(g_atm_priv_data.tx_desc_base);
+
+    if ( g_atm_priv_data.oam_buf_base != NULL )
+        kfree(g_atm_priv_data.oam_buf_base);
+
+    if ( g_atm_priv_data.oam_desc_base != NULL )
+        kfree(g_atm_priv_data.oam_desc_base);
+
+    if ( g_atm_priv_data.aal_desc_base != NULL ) {
+        for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
+            if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
+                skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
+                dev_kfree_skb_any(skb);
+            }
+        }
+        kfree(g_atm_priv_data.aal_desc_base);
+    }
+}
+
+static INLINE void init_rx_tables(void)
+{
+    int i;
+    struct wrx_queue_config wrx_queue_config = {0};
+    struct wrx_dma_channel_config wrx_dma_channel_config = {0};
+    struct htu_entry htu_entry = {0};
+    struct htu_result htu_result = {0};
+    struct htu_mask htu_mask = {    set:        0x01,
+                                    clp:        0x01,
+                                    pid_mask:   0x00,
+                                    vpi_mask:   0x00,
+                                    vci_mask:   0x00,
+                                    pti_mask:   0x00,
+                                    clear:      0x00};
+
+    /*
+     *  General Registers
+     */
+    *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
+    *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
+    *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
+    *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
+    *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
+
+    /*
+     *  WRX Queue Configuration Table
+     */
+    wrx_queue_config.uumask    = 0;
+    wrx_queue_config.cpimask   = 0;
+    wrx_queue_config.uuexp     = 0;
+    wrx_queue_config.cpiexp    = 0;
+    wrx_queue_config.mfs       = aal5r_max_packet_size;
+    wrx_queue_config.oversize  = aal5r_max_packet_size;
+    wrx_queue_config.undersize = aal5r_min_packet_size;
+    wrx_queue_config.errdp     = aal5r_drop_error_packet;
+    wrx_queue_config.dmach     = RX_DMA_CH_AAL;
+    for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
+        *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
+    WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
+
+    /*
+     *  WRX DMA Channel Configuration Table
+     */
+    wrx_dma_channel_config.chrl   = 0;
+    wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
+    wrx_dma_channel_config.mode   = 0;
+    wrx_dma_channel_config.rlcfg  = 0;
+
+    wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
+    wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
+    *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
+
+    wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
+    wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
+    *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
+
+    /*
+     *  HTU Tables
+     */
+    for ( i = 0; i < MAX_PVC_NUMBER; i++ )
+    {
+        htu_result.qid = (unsigned int)i;
+
+        *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
+        *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
+        *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
+    }
+    /*  OAM HTU Entry   */
+    htu_entry.vci     = 0x03;
+    htu_mask.pid_mask = 0x03;
+    htu_mask.vpi_mask = 0xFF;
+    htu_mask.vci_mask = 0x0000;
+    htu_mask.pti_mask = 0x07;
+    htu_result.cellid = OAM_RX_QUEUE;
+    htu_result.type   = 1;
+    htu_result.ven    = 1;
+    htu_result.qid    = OAM_RX_QUEUE;
+    *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
+    *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
+    *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
+    htu_entry.vci     = 0x04;
+    htu_result.cellid = OAM_RX_QUEUE;
+    htu_result.type   = 1;
+    htu_result.ven    = 1;
+    htu_result.qid    = OAM_RX_QUEUE;
+    *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
+    *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
+    *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
+    htu_entry.vci     = 0x00;
+    htu_entry.pti     = 0x04;
+    htu_mask.vci_mask = 0xFFFF;
+    htu_mask.pti_mask = 0x01;
+    htu_result.cellid = OAM_RX_QUEUE;
+    htu_result.type   = 1;
+    htu_result.ven    = 1;
+    htu_result.qid    = OAM_RX_QUEUE;
+    *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
+    *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
+    *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
+#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+    htu_entry.pid     = 0x0;
+    htu_entry.vpi     = 0x01;
+    htu_entry.vci     = 0x0001;
+    htu_entry.pti     = 0x00;
+    htu_mask.pid_mask = 0x0;
+    htu_mask.vpi_mask = 0x00;
+    htu_mask.vci_mask = 0x0000;
+    htu_mask.pti_mask = 0x3;
+    htu_result.cellid = OAM_RX_QUEUE;
+    htu_result.type   = 1;
+    htu_result.ven    = 1;
+    htu_result.qid    = OAM_RX_QUEUE;
+    *HTU_RESULT(OAM_ARQ_HTU_ENTRY) = htu_result;
+    *HTU_MASK(OAM_ARQ_HTU_ENTRY)   = htu_mask;
+    *HTU_ENTRY(OAM_ARQ_HTU_ENTRY)  = htu_entry;
+#endif
+}
+
+static INLINE void init_tx_tables(void)
+{
+    int i;
+    struct wtx_queue_config wtx_queue_config = {0};
+    struct wtx_dma_channel_config wtx_dma_channel_config = {0};
+    struct wtx_port_config wtx_port_config = {  res1:   0,
+                                                qid:    0,
+                                                qsben:  1};
+
+    /*
+     *  General Registers
+     */
+    *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
+    *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
+    *CFG_WRDES_DELAY    = write_descriptor_delay;
+
+    /*
+     *  WTX Port Configuration Table
+     */
+    for ( i = 0; i < ATM_PORT_NUMBER; i++ )
+        *WTX_PORT_CONFIG(i) = wtx_port_config;
+
+    /*
+     *  WTX Queue Configuration Table
+     */
+    wtx_queue_config.type  = 0x0;
+    wtx_queue_config.qsben = 1;
+    wtx_queue_config.sbid  = 0;
+    for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
+        *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
+
+    /*
+     *  WTX DMA Channel Configuration Table
+     */
+    wtx_dma_channel_config.mode   = 0;
+    wtx_dma_channel_config.deslen = 0;
+    wtx_dma_channel_config.desba  = 0;
+    for ( i = 0; i < FIRST_QSB_QID; i++ )
+        *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
+    /*  normal connection   */
+    wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
+    for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
+        wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
+        *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
+    }
+}
+
+
+
+/*
+ * ####################################
+ *           Global Function
+ * ####################################
+ */
+
+static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
+{
+    int i, j;
+
+    ASSERT(port_cell != NULL, "port_cell is NULL");
+    ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
+
+    for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
+        if ( port_cell->tx_link_rate[j] > 0 )
+            break;
+    for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
+        g_atm_priv_data.port[i].tx_max_cell_rate = port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
+
+    qsb_global_set();
+
+    for ( i = 0; i < MAX_PVC_NUMBER; i++ )
+        if ( g_atm_priv_data.conn[i].vcc != NULL )
+            set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
+
+    //  TODO: ReTX set xdata_addr
+    g_xdata_addr = xdata_addr;
+
+    g_showtime = 1;
+
+#if defined(CONFIG_VR9)
+    IFX_REG_W32(0x0F, UTP_CFG);
+#endif
+
+    printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr);
+
+    return IFX_SUCCESS;
+}
+
+static int atm_showtime_exit(void)
+{
+#if defined(CONFIG_VR9)
+    IFX_REG_W32(0x00, UTP_CFG);
+#endif
+
+    g_showtime = 0;
+
+    //  TODO: ReTX clean state
+    g_xdata_addr = NULL;
+
+    printk("leave showtime\n");
+
+    return IFX_SUCCESS;
+}
+
+
+
+/*
+ * ####################################
+ *           Init/Cleanup API
+ * ####################################
+ */
+
+/*
+ *  Description:
+ *    Initialize global variables, PP32, comunication structures, register IRQ
+ *    and register device.
+ *  Input:
+ *    none
+ *  Output:
+ *    0    --- successful
+ *    else --- failure, usually it is negative value of error code
+ */
+static int __devinit ifx_atm_init(void)
+{
+    int ret;
+    int port_num;
+    struct port_cell_info port_cell = {0};
+    int i, j;
+    char ver_str[256];
+
+#ifdef MODULE
+    reset_ppe();
+#endif
+
+    check_parameters();
+
+    ret = init_priv_data();
+    if ( ret != IFX_SUCCESS ) {
+        err("INIT_PRIV_DATA_FAIL");
+        goto INIT_PRIV_DATA_FAIL;
+    }
+
+    ifx_atm_init_chip();
+    init_rx_tables();
+    init_tx_tables();
+
+    /*  create devices  */
+    for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
+        g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", &g_ifx_atm_ops, -1, NULL);
+        if ( !g_atm_priv_data.port[port_num].dev ) {
+            err("failed to register atm device %d!", port_num);
+            ret = -EIO;
+            goto ATM_DEV_REGISTER_FAIL;
+        }
+        else {
+            g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
+            g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
+            g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
+            g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
+        }
+    }
+
+    /*  register interrupt handler  */
+    ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
+    if ( ret ) {
+        if ( ret == -EBUSY ) {
+            err("IRQ may be occupied by other driver, please reconfig to disable it.");
+        }
+        else {
+            err("request_irq fail");
+        }
+        goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+    }
+    disable_irq(PPE_MAILBOX_IGU1_INT);
+
+    ret = ifx_pp32_start(0);
+    if ( ret ) {
+        err("ifx_pp32_start fail!");
+        goto PP32_START_FAIL;
+    }
+
+    port_cell.port_num = ATM_PORT_NUMBER;
+    ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
+    if ( g_showtime ) {
+        for ( i = 0; i < ATM_PORT_NUMBER; i++ )
+            if ( port_cell.tx_link_rate[i] != 0 )
+                break;
+        for ( j = 0; j < ATM_PORT_NUMBER; j++ )
+            g_atm_priv_data.port[j].tx_max_cell_rate = port_cell.tx_link_rate[j] != 0 ? port_cell.tx_link_rate[j] : port_cell.tx_link_rate[i];
+    }
+
+    qsb_global_set();
+    validate_oam_htu_entry();
+
+    /*  create proc file    */
+    proc_file_create();
+
+    ifx_mei_atm_showtime_enter = atm_showtime_enter;
+    ifx_mei_atm_showtime_exit  = atm_showtime_exit;
+
+    ifx_atm_version(ver_str);
+    printk(KERN_INFO "%s", ver_str);
+
+    printk("ifxmips_atm: ATM init succeed\n");
+
+    return IFX_SUCCESS;
+
+PP32_START_FAIL:
+    free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
+REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
+ATM_DEV_REGISTER_FAIL:
+    while ( port_num-- > 0 )
+        atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
+INIT_PRIV_DATA_FAIL:
+    clear_priv_data();
+    printk("ifxmips_atm: ATM init failed\n");
+    return ret;
+}
+
+/*
+ *  Description:
+ *    Release memory, free IRQ, and deregister device.
+ *  Input:
+ *    none
+ *  Output:
+ *   none
+ */
+static void __exit ifx_atm_exit(void)
+{
+    int port_num;
+
+    ifx_mei_atm_showtime_enter = NULL;
+    ifx_mei_atm_showtime_exit  = NULL;
+
+    proc_file_delete();
+
+    invalidate_oam_htu_entry();
+
+    ifx_pp32_stop(0);
+
+    free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
+
+    for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
+        atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
+
+    ifx_atm_uninit_chip();
+
+    clear_priv_data();
+}
+
+module_init(ifx_atm_init);
+module_exit(ifx_atm_exit);
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_core.h b/package/ifxmips-dsl-api/src/ifxmips_atm_core.h
new file mode 100644 (file)
index 0000000..f7774fb
--- /dev/null
@@ -0,0 +1,249 @@
+/******************************************************************************
+**
+** FILE NAME    : ifxmips_atm_core.h
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 7 Jul 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : ATM driver header file (core functions)
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 17 JUN 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+#ifndef IFXMIPS_ATM_CORE_H
+#define IFXMIPS_ATM_CORE_H
+
+
+
+#include <asm/ifx/ifx_atm.h>
+#include "ifxmips_atm_ppe_common.h"
+#include "ifxmips_atm_fw_regs_common.h"
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*
+ *  Compile Options
+ */
+
+#define ENABLE_DEBUG                    1
+
+#define ENABLE_ASSERT                   1
+
+#define INLINE
+
+#define DEBUG_DUMP_SKB                  1
+
+#define DEBUG_QOS                       1
+
+#define ENABLE_DBG_PROC                 1
+
+#define ENABLE_FW_PROC                  1
+
+#ifdef CONFIG_IFX_ATM_TASKLET
+  #define ENABLE_TASKLET                1
+#endif
+
+
+/*
+ *  Debug/Assert/Error Message
+ */
+
+#define DBG_ENABLE_MASK_ERR             (1 << 0)
+#define DBG_ENABLE_MASK_DEBUG_PRINT     (1 << 1)
+#define DBG_ENABLE_MASK_ASSERT          (1 << 2)
+#define DBG_ENABLE_MASK_DUMP_SKB_RX     (1 << 8)
+#define DBG_ENABLE_MASK_DUMP_SKB_TX     (1 << 9)
+#define DBG_ENABLE_MASK_DUMP_QOS        (1 << 10)
+#define DBG_ENABLE_MASK_DUMP_INIT       (1 << 11)
+#define DBG_ENABLE_MASK_ALL             (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
+
+#define err(format, arg...)             do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
+
+#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
+  #undef  dbg
+  #define dbg(format, arg...)           do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
+#else
+  #if !defined(dbg)
+    #define dbg(format, arg...)
+  #endif
+#endif
+
+#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
+  #define ASSERT(cond, format, arg...)  do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
+#else
+  #define ASSERT(cond, format, arg...)
+#endif
+
+
+/*
+ *  Constants
+ */
+#define DEFAULT_TX_LINK_RATE            3200    //  in cells
+
+/*
+ *  ATM Port, QSB Queue, DMA RX/TX Channel Parameters
+ */
+#define ATM_PORT_NUMBER                 2
+#define MAX_QUEUE_NUMBER                16
+#define OAM_RX_QUEUE                    15
+#define QSB_RESERVE_TX_QUEUE            0
+#define FIRST_QSB_QID                   1
+#define MAX_PVC_NUMBER                  (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
+#define MAX_RX_DMA_CHANNEL_NUMBER       8
+#define MAX_TX_DMA_CHANNEL_NUMBER       16
+#define DATA_BUFFER_ALIGNMENT           EMA_ALIGNMENT
+#define DESC_ALIGNMENT                  8
+#define DEFAULT_RX_HUNT_BITTH           4
+
+/*
+ *  RX DMA Channel Allocation
+ */
+#define RX_DMA_CH_OAM                   0
+#define RX_DMA_CH_AAL                   1
+#define RX_DMA_CH_TOTAL                 2
+#define RX_DMA_CH_OAM_DESC_LEN          32
+#define RX_DMA_CH_OAM_BUF_SIZE          (CELL_SIZE & ~15)
+#define RX_DMA_CH_AAL_BUF_SIZE          (2048 - 48)
+
+/*
+ *  OAM Constants
+ */
+#define OAM_HTU_ENTRY_NUMBER            3
+#define OAM_F4_SEG_HTU_ENTRY            0
+#define OAM_F4_TOT_HTU_ENTRY            1
+#define OAM_F5_HTU_ENTRY                2
+#define OAM_F4_CELL_ID                  0
+#define OAM_F5_CELL_ID                  15
+//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
+//  #undef  OAM_HTU_ENTRY_NUMBER
+//  #define OAM_HTU_ENTRY_NUMBER          4
+//  #define OAM_ARQ_HTU_ENTRY             3
+//#endif
+
+/*
+ *  RX Frame Definitions
+ */
+#define MAX_RX_PACKET_ALIGN_BYTES       3
+#define MAX_RX_PACKET_PADDING_BYTES     3
+#define RX_INBAND_TRAILER_LENGTH        8
+#define MAX_RX_FRAME_EXTRA_BYTES        (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
+
+/*
+ *  TX Frame Definitions
+ */
+#define MAX_TX_HEADER_ALIGN_BYTES       12
+#define MAX_TX_PACKET_ALIGN_BYTES       3
+#define MAX_TX_PACKET_PADDING_BYTES     3
+#define TX_INBAND_HEADER_LENGTH         8
+#define MAX_TX_FRAME_EXTRA_BYTES        (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
+
+/*
+ *  Cell Constant
+ */
+#define CELL_SIZE                       ATM_AAL0_SDU
+
+
+
+/*
+ * ####################################
+ *              Data Type
+ * ####################################
+ */
+
+typedef struct {
+    unsigned int            h;
+    unsigned int            l;
+} ppe_u64_t;
+
+struct port {
+    unsigned int            tx_max_cell_rate;
+    unsigned int            tx_current_cell_rate;
+
+    struct atm_dev         *dev;
+};
+
+struct connection {
+    struct atm_vcc         *vcc;
+
+    volatile struct tx_descriptor
+                           *tx_desc;
+    unsigned int            tx_desc_pos;
+    struct sk_buff        **tx_skb;
+
+    unsigned int            aal5_vcc_crc_err;       /*  number of packets with CRC error        */
+    unsigned int            aal5_vcc_oversize_sdu;  /*  number of packets with oversize error   */
+
+    unsigned int            port;
+};
+
+struct atm_priv_data {
+    unsigned long           conn_table;
+    struct connection       conn[MAX_PVC_NUMBER];
+
+    volatile struct rx_descriptor
+                           *aal_desc;
+    unsigned int            aal_desc_pos;
+
+    volatile struct rx_descriptor
+                           *oam_desc;
+    unsigned char          *oam_buf;
+    unsigned int            oam_desc_pos;
+
+    struct port             port[ATM_PORT_NUMBER];
+
+    unsigned int            wrx_pdu;        /*  successfully received AAL5 packet       */
+    unsigned int            wrx_drop_pdu;   /*  AAL5 packet dropped by driver on RX     */
+    unsigned int            wtx_pdu;        /*  successfully tranmitted AAL5 packet     */
+    unsigned int            wtx_err_pdu;    /*  error AAL5 packet                       */
+    unsigned int            wtx_drop_pdu;   /*  AAL5 packet dropped by driver on TX     */
+
+    ppe_u64_t               wrx_total_byte;
+    ppe_u64_t               wtx_total_byte;
+    unsigned int            prev_wrx_total_byte;
+    unsigned int            prev_wtx_total_byte;
+
+    void                   *aal_desc_base;
+    void                   *oam_desc_base;
+    void                   *oam_buf_base;
+    void                   *tx_desc_base;
+    void                   *tx_skb_base;
+};
+
+
+
+/*
+ * ####################################
+ *             Declaration
+ * ####################################
+ */
+
+extern unsigned int ifx_atm_dbg_enable;
+
+extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
+
+extern void ifx_atm_init_chip(void);
+extern void ifx_atm_uninit_chip(void);
+
+extern int ifx_pp32_start(int pp32);
+extern void ifx_pp32_stop(int pp32);
+
+
+
+#endif  //  IFXMIPS_ATM_CORE_H
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_danube.c b/package/ifxmips-dsl-api/src/ifxmips_atm_danube.c
new file mode 100644 (file)
index 0000000..5768678
--- /dev/null
@@ -0,0 +1,272 @@
+/******************************************************************************
+**
+** FILE NAME    : ifxmips_atm_danube.c
+** PROJECT      : UEIP
+** MODULES      : ATM
+**
+** DATE         : 7 Jul 2009
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : ATM driver common source file (core functions)
+** COPYRIGHT    :       Copyright (c) 2006
+**                      Infineon Technologies AG
+**                      Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+** 07 JUL 2009  Xu Liang        Init Version
+*******************************************************************************/
+
+
+
+/*
+ * ####################################
+ *              Head File
+ * ####################################
+ */
+
+/*
+ *  Common Head File
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <asm/delay.h>
+
+/*
+ *  Chip Specific Head File
+ */
+#include <asm/ifx/ifx_types.h>
+#include <asm/ifx/ifx_regs.h>
+#include <asm/ifx/common_routines.h>
+#include <asm/ifx/ifx_pmu.h>
+#include "ifxmips_atm_core.h"
+#include "ifxmips_atm_fw_danube.h"
+
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*
+ *  EMA Settings
+ */
+#define EMA_CMD_BUF_LEN      0x0040
+#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
+#define EMA_DATA_BUF_LEN     0x0100
+#define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
+#define EMA_WRITE_BURST      0x2
+#define EMA_READ_BURST       0x2
+
+
+
+/*
+ * ####################################
+ *             Declaration
+ * ####################################
+ */
+
+/*
+ *  Hardware Init/Uninit Functions
+ */
+static inline void init_pmu(void);
+static inline void uninit_pmu(void);
+static inline void init_ema(void);
+static inline void init_mailbox(void);
+static inline void init_atm_tc(void);
+static inline void clear_share_buffer(void);
+
+
+
+/*
+ * ####################################
+ *            Local Variable
+ * ####################################
+ */
+
+
+
+/*
+ * ####################################
+ *            Local Function
+ * ####################################
+ */
+
+static inline void init_pmu(void)
+{
+    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
+    PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
+    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
+    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
+    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
+    PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
+    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
+    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
+}
+
+static inline void uninit_pmu(void)
+{
+    PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
+    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
+    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
+    PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
+    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
+    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
+    PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
+}
+
+static inline void init_ema(void)
+{
+    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
+    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
+    IFX_REG_W32(0x000000FF, EMA_IER);
+    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
+}
+
+static inline void init_mailbox(void)
+{
+    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
+    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
+    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
+    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
+}
+
+static inline void init_atm_tc(void)
+{
+    //  for ReTX expansion in future
+    //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); //  pnum = 6
+    //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); //  pnum = 6
+}
+
+static inline void clear_share_buffer(void)
+{
+    volatile u32 *p = SB_RAM0_ADDR(0);
+    unsigned int i;
+
+    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
+        IFX_REG_W32(0, p++);
+}
+
+/*
+ *  Description:
+ *    Download PPE firmware binary code.
+ *  Input:
+ *    src       --- u32 *, binary code buffer
+ *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
+ *  Output:
+ *    int       --- IFX_SUCCESS:    Success
+ *                  else:           Error Code
+ */
+static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
+{
+    volatile u32 *dest;
+
+    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
+        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
+        return IFX_ERROR;
+
+    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
+        IFX_REG_W32(0x00, CDM_CFG);
+    else
+        IFX_REG_W32(0x02, CDM_CFG);
+
+    /*  copy code   */
+    dest = CDM_CODE_MEMORY(0, 0);
+    while ( code_dword_len-- > 0 )
+        IFX_REG_W32(*code_src++, dest++);
+
+    /*  copy data   */
+    dest = CDM_DATA_MEMORY(0, 0);
+    while ( data_dword_len-- > 0 )
+        IFX_REG_W32(*data_src++, dest++);
+
+    return IFX_SUCCESS;
+}
+
+
+
+/*
+ * ####################################
+ *           Global Function
+ * ####################################
+ */
+
+extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
+{
+    ASSERT(major != NULL, "pointer is NULL");
+    ASSERT(minor != NULL, "pointer is NULL");
+
+    *major = ATM_FW_VER_MAJOR;
+    *minor = ATM_FW_VER_MINOR;
+}
+
+void ifx_atm_init_chip(void)
+{
+    init_pmu();
+
+    init_ema();
+
+    init_mailbox();
+
+    init_atm_tc();
+
+    clear_share_buffer();
+}
+
+void ifx_atm_uninit_chip(void)
+{
+    uninit_pmu();
+}
+
+/*
+ *  Description:
+ *    Initialize and start up PP32.
+ *  Input:
+ *    none
+ *  Output:
+ *    int  --- IFX_SUCCESS: Success
+ *             else:        Error Code
+ */
+int ifx_pp32_start(int pp32)
+{
+    int ret;
+
+    /*  download firmware   */
+    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
+    if ( ret != IFX_SUCCESS )
+        return ret;
+
+    /*  run PP32    */
+    IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
+
+    /*  idle for a while to let PP32 init itself    */
+    udelay(10);
+
+    return IFX_SUCCESS;
+}
+
+/*
+ *  Description:
+ *    Halt PP32.
+ *  Input:
+ *    none
+ *  Output:
+ *    none
+ */
+void ifx_pp32_stop(int pp32)
+{
+    /*  halt PP32   */
+    IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
+}
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h b/package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h
new file mode 100644 (file)
index 0000000..c36c968
--- /dev/null
@@ -0,0 +1,429 @@
+#ifndef IFXMIPS_ATM_FW_DANUBE_H
+#define IFXMIPS_ATM_FW_DANUBE_H
+
+
+/******************************************************************************
+**
+** FILE NAME    : ifxmips_atm_fw_danube.h
+** PROJECT      : Danube
+** MODULES             : ATM (ADSL)
+**
+** DATE         : 1 AUG 2005
+** AUTHOR       : Xu Liang
+** DESCRIPTION  : ATM Driver (PP32 Firmware)
+** COPYRIGHT    :      Copyright (c) 2006
+**                     Infineon Technologies AG
+**                     Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+**    This program is free software; you can redistribute it and/or modify
+**    it under the terms of the GNU General Public License as published by
+**    the Free Software Foundation; either version 2 of the License, or
+**    (at your option) any later version.
+**
+** HISTORY
+** $Date        $Author         $Comment
+**  4 AUG 2005  Xu Liang        Initiate Version
+** 23 OCT 2006  Xu Liang        Add GPL header.
+*******************************************************************************/
+
+
+#define ATM_FW_VER_MAJOR        0
+#define ATM_FW_VER_MINOR        1
+
+
+static unsigned int firmware_binary_code[] = {
+    0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
+    0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,
+    0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,
+    0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,
+    0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,
+    0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,
+    0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,
+    0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,
+    0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,
+    0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,
+    0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,
+    0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,
+    0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,
+    0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,
+    0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,
+    0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000,
+    0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080,
+    0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020,
+    0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,
+    0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000,
+    0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000,
+    0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848,
+    0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C,
+    0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A,
+    0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000,
+    0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE,
+    0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000,
+    0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002,
+    0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002,
+    0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000,
+    0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002,
+    0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2,
+    0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000,
+    0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960,
+    0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600,
+    0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000,
+    0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030,
+    0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031,
+    0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000,
+    0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604,
+    0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960,
+    0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A,
+    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912,
+    0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE,
+    0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000,
+    0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966,
+    0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
+    0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080,
+    0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000,
+    0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000,
+    0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000,
+    0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000,
+    0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C,
+    0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA,
+    0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000,
+    0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010,
+    0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000,
+    0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000,
+    0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822,
+    0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008,
+    0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000,
+    0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000,
+    0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018,
+    0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A,
+    0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002,
+    0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,
+    0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000,
+    0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
+    0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932,
+    0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000,
+    0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000,
+    0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080,
+    0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930,
+    0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916,
+    0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022,
+    0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8,
+    0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A,
+    0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000,
+    0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040,
+    0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000,
+    0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8,
+    0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000,
+    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000,
+    0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,
+    0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C,
+    0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C,
+    0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000,
+    0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA,
+    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000,
+    0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932,
+    0xCA400000, 0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000,
+    0xC0004934, 0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002,
+    0x6E684000, 0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002,
+    0x6E642000, 0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0,
+    0xDBA80000, 0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080,
+    0x00000000, 0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002,
+    0x6E640000, 0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030,
+    0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80,
+    0xC2800000, 0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006,
+    0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000,
+    0xC000100A, 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930,
+    0xCA02E010, 0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990053B0, 0xDA980000, 0xC6140000,
+    0xC6580000, 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000,
+    0x80000300, 0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000,
+    0x40100000, 0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000,
+    0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940,
+    0xCE400040, 0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172,
+    0x5A6C0010, 0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000,
+    0xC0004940, 0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040,
+    0x46610000, 0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000,
+    0xC2000000, 0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080,
+    0x46E50000, 0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2,
+    0x00000000, 0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068,
+    0xC7700208, 0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028,
+    0xC7700908, 0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944,
+    0xCF000000, 0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E,
+    0xCB400000, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004,
+    0xCB000080, 0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078,
+    0x00000000, 0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000,
+    0xC6E00010, 0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000,
+    0x8800FFFA, 0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930,
+    0xCA42E010, 0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000,
+    0xC2000000, 0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0,
+    0xC0004862, 0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C,
+    0xCE400000, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A,
+    0xCFC00000, 0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8,
+    0xC1220002, 0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000,
+    0xC0004934, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000,
+    0x58380008, 0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002,
+    0x7235A000, 0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000,
+    0xC760E718, 0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990060A8,
+    0xC0004828, 0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112,
+    0xC0004940, 0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A,
+    0xCA400000, 0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400,
+    0x8800FFFA, 0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 0x5C000200, 0xCE800000,
+    0xC000493E, 0xCA000000, 0xC2400000, 0x5838000C, 0xCE400000, 0x990060A8, 0xC0004830, 0xC9400000,
+    0xC6180000, 0xC0004930, 0xC6100080, 0xCD000080, 0x80000090, 0xC2400002, 0x58380008, 0xCE400008,
+    0xC0004944, 0xCF400000, 0x80000260, 0xC000493C, 0xCA400000, 0xDFE80000, 0x5A300018, 0xC0007200,
+    0x40200000, 0xCA000000, 0x58380008, 0xC6501080, 0xCD001080, 0x5838000A, 0xCE800000, 0x58380026,
+    0xCE000000, 0xC0004944, 0xCF400000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x80000020,
+    0x00000000, 0x990060A8, 0xC0004826, 0xC9400000, 0xC1800002, 0x8000FDC0, 0xC2000000, 0xC2400200,
+    0xDF600040, 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000,
+    0xDA980001, 0x00000000, 0xC0004934, 0xCA000000, 0x00000000, 0xC2800000, 0xA6020140, 0xC2400004,
+    0xC2000200, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFC2, 0x00000000, 0xC000491A, 0xC9800000,
+    0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, 0xD9980001,
+    0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xC2400200, 0xDF600040,
+    0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000, 0xDA980001,
+    0x00000000, 0x58380008, 0xCA400000, 0xC2000000, 0xCE000020, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE001080,
+    0x5838000A, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0000838, 0xC2500002,
+    0xCE440808, 0xC0004848, 0xCB840000, 0xC2000000, 0xC000082C, 0xCA040030, 0x5FB80002, 0xC0004848,
+    0xCF840000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840000, 0x00000000,
+    0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000DEC0, 0xC2000000, 0xDF600040, 0x5E200080, 0x84000252,
+    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480C, 0xCA000000, 0xC0004910,
+    0xCA400000, 0xC000492C, 0xCA800000, 0xC0004968, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0x76610000, 0x76A10000, 0x762D6000, 0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE,
+    0x762D6000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000,
+    0x62014008, 0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968,
+    0xCA400000, 0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
+    0x5911FE14, 0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002,
+    0xC2000000, 0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000,
+    0x46B18000, 0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20,
+    0x99005930, 0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400028A,
+    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC000492A,
+    0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0x76318000, 0x76718000, 0x840001EA, 0xC201FFFE, 0x76318000, 0x5AEC0002, 0x6B2D0010,
+    0x5EA00000, 0x84000002, 0x6A2D0000, 0x8000FFF8, 0xC7200000, 0x62016008, 0xC0004956, 0xCEC00000,
+    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000,
+    0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6EF4A000,
+    0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834000E, 0xC2000000, 0xCA0000E0, 0x58340008,
+    0xC2400000, 0xCA420080, 0x5834000C, 0xC2800000, 0xCA832018, 0x6E644010, 0x42250000, 0x4229E000,
+    0xC39A8008, 0x58340008, 0xCB809020, 0x58340008, 0xC2800000, 0xCA810018, 0x6EE0A000, 0x6EE44000,
+    0x46610000, 0x46E10000, 0x5A200008, 0x5A200E28, 0x42290000, 0xC6380068, 0xC6F81C20, 0x99005930,
+    0xDB980000, 0xDBD80001, 0x00000000, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,
+    0xCC400000, 0xC0001A1C, 0xCA000000, 0xC2400008, 0x6A452000, 0x76610000, 0x8400D91A, 0xC0000A28,
+    0xC3800000, 0xCB840030, 0xC0000A14, 0xC3400000, 0xCB440030, 0xC0004880, 0xCB040000, 0xB7B4D8CA,
+    0x58041802, 0xCAC00000, 0xA7000018, 0x00000000, 0x00000000, 0xA6C8D898, 0xC2800000, 0xC6E80020,
+    0x80000030, 0xC2800000, 0xC7282020, 0xC000490E, 0xCA400000, 0x6BE9E000, 0x00000000, 0x77E52000,
+    0x8400D848, 0x6EA0A000, 0x6E944000, 0x45610000, 0x46A10000, 0x5A204E20, 0x5820000C, 0xCA000000,
+    0xC0004946, 0xCE800000, 0xA6220348, 0x00000000, 0xC2200060, 0xC0004948, 0xCE000010, 0xCE001040,
+    0xC240000A, 0xC000494A, 0xCE400000, 0xC2B60002, 0xC0004964, 0xCE801B08, 0x99005C00, 0xC00048A0,
+    0xC8840000, 0x00000000, 0xC0004946, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000,
+    0x4579C000, 0x47F9C000, 0x5BB84E20, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005708,
+    0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000, 0x00000000,
+    0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,
+    0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
+    0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874,
+    0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000,
+    0xC7400000, 0xCE000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
+    0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
+    0x990060A8, 0xC0004836, 0xC9400000, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8,
+    0x00000000, 0xC1220002, 0xD90C0000, 0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002,
+    0xCE440808, 0x58880002, 0xB608FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D498, 0xC0004946,
+    0xCBC00000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002,
+    0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000,
+    0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000,
+    0xC3400000, 0xC6340008, 0xC000494E, 0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020,
+    0x6F304000, 0x43298000, 0xC000493C, 0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000,
+    0xC2800000, 0xC66AE028, 0xC0004954, 0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000,
+    0x84000152, 0x462D2000, 0x8800011A, 0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A,
+    0x00000000, 0x800000A8, 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC3400002,
+    0xC000494E, 0xCF400000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
+    0xC2800002, 0x6ABD4000, 0x7E814000, 0x76A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0xC2200060, 0xC0004948, 0xCE001040, 0xC2000000, 0xC000494C, 0xCE000000, 0x80000068,
+    0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001,
+    0xC7800000, 0xC2200058, 0xC0004948, 0xCE001040, 0xC2000002, 0xC000494C, 0xCE000000, 0xC2000006,
+    0xC0001006, 0xCE000000, 0x5838000A, 0xCA400000, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE000000,
+    0xC000100A, 0xCE400000, 0xC0004954, 0xCA800000, 0xC200000C, 0xC000494A, 0xCE000000, 0xC0004948,
+    0xCE800010, 0xC2B60000, 0xC0004964, 0xCE800000, 0x99005C00, 0xC00048A0, 0xC8840000, 0x00000000,
+    0xC0004946, 0xCBC00000, 0xC000494C, 0xCA000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,
+    0x5BB84E20, 0x5E200000, 0x840000E2, 0x00000000, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000,
+    0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000,
+    0x00000000, 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
+    0x00000000, 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14,
+    0x15000000, 0xC000493C, 0xCA800000, 0xC000494E, 0xCAC00000, 0xC3000018, 0xC3400006, 0x5E200000,
+    0x84000012, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1080, 0xC72C0420, 0xC76C0818,
+    0x58380010, 0xCA800000, 0x58380008, 0xCEC00000, 0xC6280108, 0xC0004874, 0xC8040000, 0x6C908000,
+    0x44908000, 0x44908000, 0x40100000, 0xCB000000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE800000,
+    0xC0004952, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0xC000494C,
+    0xCA000000, 0xC0004950, 0xCAC00000, 0x5E200000, 0x84000052, 0xDFE80000, 0x7E814000, 0x5834001A,
+    0xCE800000, 0x990060A8, 0xC0004834, 0xC9400000, 0xC1800002, 0x990060A8, 0xC0004838, 0xC9400000,
+    0xC6D80000, 0xC1220002, 0xD90C0000, 0x5E200000, 0x84000028, 0x5838002C, 0xCB000000, 0xDFE80000,
+    0x00000000, 0x58380014, 0xCF000000, 0x80000000, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE800000,
+    0xC3000000, 0xC0000A14, 0xCB040030, 0xC2D00002, 0xC0000A28, 0xCEC40808, 0xC000494E, 0xCA800000,
+    0x58880002, 0xB4B0FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x5EA80000, 0x8400013A, 0x5E200000,
+    0x84000128, 0xC000493C, 0xCA800000, 0x00000000, 0x00000000, 0x5AA80060, 0xCE800000, 0x99005D40,
+    0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC0004952,
+    0xCAC00000, 0x58380000, 0xCA800000, 0xC30C0002, 0xC7F00020, 0xA6800078, 0x00000000, 0x00000000,
+    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0001800, 0xCA000000, 0x00000000, 0x00000000,
+    0xA60CFFCA, 0xC6F00508, 0xC6B0C408, 0xCF000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
+    0x8000CB48, 0xDCBC0001, 0x5FFC0000, 0x8400003A, 0xC3800002, 0xDB880001, 0x5FFC0004, 0x8400C4B2,
+    0xC3800000, 0xDB880001, 0xC3CE0002, 0xC0000800, 0xCFC00708, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14,
+    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
+    0x40080000, 0xCBC00000, 0xC4380000, 0x00000000, 0xC000480E, 0xCA000000, 0xC0004858, 0xCB440000,
+    0x00000000, 0x00000000, 0x46350000, 0x88000098, 0x00000000, 0xA7C00028, 0xC0004854, 0xC1000002,
+    0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x800000C0, 0x00000000, 0xA7D20118, 0x00000000,
+    0xC7E14048, 0xC2400000, 0xC6246030, 0xC200006A, 0x46610000, 0xC6240038, 0xC0000810, 0xCE440038,
+    0x8000FF58, 0xC2000000, 0xC0000808, 0xCA040018, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x5A200002,
+    0x5E600010, 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002,
+    0xC0000818, 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005348, 0xC0004848, 0xC9440000,
+    0xC1800000, 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005C8, 0x5B740002, 0xC0004858, 0xCF440000,
+    0xC7800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030,
+    0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980540, 0x00000000, 0xC0800000, 0x80000530,
+    0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000,
+    0xA7C00110, 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C,
+    0xCE040000, 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000,
+    0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980430, 0x00000000,
+    0xC0800000, 0x80000420, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000,
+    0xC2000000, 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000,
+    0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000,
+    0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C,
+    0xCE040000, 0x80000320, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
+    0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA780022A, 0x00000000, 0x00000000, 0xA7C001EA,
+    0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, 0x00000000, 0xC0004850, 0xCA040000,
+    0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, 0xCE040000, 0xB624008A, 0x00000000,
+    0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, 0xCE040008, 0xC0004848, 0xC9440000,
+    0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8,
+    0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C,
+    0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000,
+    0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000,
+    0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70,
+    0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008,
+    0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002,
+    0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0,
+    0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838,
+    0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000,
+    0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8,
+    0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712,
+    0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000,
+    0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000,
+    0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004,
+    0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914,
+    0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8,
+    0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000,
+    0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900,
+    0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000,
+    0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000,
+    0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80,
+    0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080,
+    0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000,
+    0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080,
+    0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8,
+    0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000,
+    0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000,
+    0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002,
+    0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020,
+    0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,
+    0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000,
+    0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080,
+    0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8,
+    0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080,
+    0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000,
+    0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000,
+    0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000,
+    0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C,
+    0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000,
+    0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028,
+    0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100,
+    0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000,
+    0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
+    0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000,
+    0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508,
+    0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002,
+    0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004,
+    0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E,
+    0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000,
+    0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002,
+    0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912,
+    0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A,
+    0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020,
+    0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000,
+    0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000,
+    0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000,
+    0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
+    0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18,
+    0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200,
+    0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000,
+    0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200,
+    0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010,
+    0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000,
+    0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80,
+    0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000,
+    0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000,
+    0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080,
+    0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028,
+    0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A,
+    0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000,
+    0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C,
+    0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000,
+    0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000,
+    0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA,
+    0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08,
+    0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20,
+    0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002,
+    0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080,
+    0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000,
+    0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000,
+    0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000,
+    0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000,
+    0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8,
+    0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808,
+    0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C,
+    0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000,
+    0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002,
+    0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0,
+    0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001,
+    0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001,
+    0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002,
+    0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000,
+    0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
+    0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E,
+    0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000,
+    0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000,
+    0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948,
+    0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000,
+    0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080,
+    0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000,
+    0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002,
+    0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000,
+    0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001,
+    0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008,
+    0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,
+    0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
+    0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028,
+    0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0,
+    0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1,
+    0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000,
+    0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA,
+    0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000,
+    0x00000000,
+};
+
+static unsigned int firmware_binary_data[] = {
+};
+
+
+#endif  //  IFXMIPS_ATM_FW_DANUBE_H
diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h b/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h
new file mode 100644 (file)
index 0000000..a5f59b8
--- /dev/null
@@ -0,0 +1,364 @@
+#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
+#define IFXMIPS_ATM_FW_REGS_COMMON_H
+
+
+
+#if defined(CONFIG_DANUBE)
+  #include "ifxmips_atm_fw_regs_danube.h"
+#elif defined(CONFIG_AMAZON_SE)
+  #include "ifxmips_atm_fw_regs_amazon_se.h"
+#elif defined(CONFIG_AR9)
+  #include "ifxmips_atm_fw_regs_ar9.h"
+#elif defined(CONFIG_VR9)
+  #include "ifxmips_atm_fw_regs_vr9.h"
+#else
+  #error Platform is not specified!
+#endif
+
+
+
+/*
+ *  PPE ATM Cell Header
+ */
+#if defined(__BIG_ENDIAN)
+    struct uni_cell_header {
+        unsigned int        gfc     :4;
+        unsigned int        vpi     :8;
+        unsigned int        vci     :16;
+        unsigned int        pti     :3;
+        unsigned int        clp     :1;
+    };
+#else
+    struct uni_cell_header {
+        unsigned int        clp     :1;
+        unsigned int        pti     :3;
+        unsigned int        vci     :16;
+        unsigned int        vpi     :8;
+        unsigned int        gfc     :4;
+    };
+#endif  //  defined(__BIG_ENDIAN)
+
+/*
+ *  Inband Header and Trailer
+ */
+#if defined(__BIG_ENDIAN)
+    struct rx_inband_trailer {
+        /*  0 - 3h  */
+        unsigned int        uu      :8;
+        unsigned int        cpi     :8;
+        unsigned int        stw_res1:4;
+        unsigned int        stw_clp :1;
+        unsigned int        stw_ec  :1;
+        unsigned int        stw_uu  :1;
+        unsigned int        stw_cpi :1;
+        unsigned int        stw_ovz :1;
+        unsigned int        stw_mfl :1;
+        unsigned int        stw_usz :1;
+        unsigned int        stw_crc :1;
+        unsigned int        stw_il  :1;
+        unsigned int        stw_ra  :1;
+        unsigned int        stw_res2:2;
+        /*  4 - 7h  */
+        unsigned int        gfc     :4;
+        unsigned int        vpi     :8;
+        unsigned int        vci     :16;
+        unsigned int        pti     :3;
+        unsigned int        clp     :1;
+    };
+
+    struct tx_inband_header {
+        /*  0 - 3h  */
+        unsigned int        gfc     :4;
+        unsigned int        vpi     :8;
+        unsigned int        vci     :16;
+        unsigned int        pti     :3;
+        unsigned int        clp     :1;
+        /*  4 - 7h  */
+        unsigned int        uu      :8;
+        unsigned int        cpi     :8;
+        unsigned int        pad     :8;
+        unsigned int        res1    :8;
+    };
+#else
+    struct rx_inband_trailer {
+        /*  0 - 3h  */
+        unsigned int        stw_res2:2;
+        unsigned int        stw_ra  :1;
+        unsigned int        stw_il  :1;
+        unsigned int        stw_crc :1;
+        unsigned int        stw_usz :1;
+        unsigned int        stw_mfl :1;
+        unsigned int        stw_ovz :1;
+        unsigned int        stw_cpi :1;
+        unsigned int        stw_uu  :1;
+        unsigned int        stw_ec  :1;
+        unsigned int        stw_clp :1;
+        unsigned int        stw_res1:4;
+        unsigned int        cpi     :8;
+        unsigned int        uu      :8;
+        /*  4 - 7h  */
+        unsigned int        clp     :1;
+        unsigned int        pti     :3;
+        unsigned int        vci     :16;
+        unsigned int        vpi     :8;
+        unsigned int        gfc     :4;
+    };
+
+    struct tx_inband_header {
+        /*  0 - 3h  */
+        unsigned int        clp     :1;
+        unsigned int        pti     :3;
+        unsigned int        vci     :16;
+        unsigned int        vpi     :8;
+        unsigned int        gfc     :4;
+        /*  4 - 7h  */
+        unsigned int        res1    :8;
+        unsigned int        pad     :8;
+        unsigned int        cpi     :8;
+        unsigned int        uu      :8;
+    };
+#endif  //  defined(__BIG_ENDIAN)
+
+/*
+ *  MIB Table Maintained by Firmware
+ */
+struct wan_mib_table {
+    u32                     res1;
+    u32                     wrx_drophtu_cell;
+    u32                     wrx_dropdes_pdu;
+    u32                     wrx_correct_pdu;
+    u32                     wrx_err_pdu;
+    u32                     wrx_dropdes_cell;
+    u32                     wrx_correct_cell;
+    u32                     wrx_err_cell;
+    u32                     wrx_total_byte;
+    u32                     res2;
+    u32                     wtx_total_pdu;
+    u32                     wtx_total_cell;
+    u32                     wtx_total_byte;
+};
+
+/*
+ *  Host-PPE Communication Data Structure
+ */
+
+#if defined(__BIG_ENDIAN)
+    struct wrx_queue_config {
+        /*  0h  */
+        unsigned int    res2        :27;
+        unsigned int    dmach       :4;
+        unsigned int    errdp       :1;
+        /*  1h  */
+        unsigned int    oversize    :16;
+        unsigned int    undersize   :16;
+        /*  2h  */
+        unsigned int    res1        :16;
+        unsigned int    mfs         :16;
+        /*  3h  */
+        unsigned int    uumask      :8;
+        unsigned int    cpimask     :8;
+        unsigned int    uuexp       :8;
+        unsigned int    cpiexp      :8;
+    };
+
+    struct wtx_port_config {
+        unsigned int    res1        :27;
+        unsigned int    qid         :4;
+        unsigned int    qsben       :1;
+    };
+
+    struct wtx_queue_config {
+        unsigned int    res1        :25;
+        unsigned int    sbid        :1;
+        unsigned int    res2        :3;
+        unsigned int    type        :2;
+        unsigned int    qsben       :1;
+    };
+
+    struct wrx_dma_channel_config {
+        /*  0h  */
+        unsigned int    res1        :1;
+        unsigned int    mode        :2;
+        unsigned int    rlcfg       :1;
+        unsigned int    desba       :28;
+        /*  1h  */
+        unsigned int    chrl        :16;
+        unsigned int    clp1th      :16;
+        /*  2h  */
+        unsigned int    deslen      :16;
+        unsigned int    vlddes      :16;
+    };
<