[ar71xx] fix the PCI byte lane enable generation code, based on a patch by Chris...
authorGabor Juhos <juhosg@openwrt.org>
Wed, 17 Sep 2008 13:29:47 +0000 (13:29 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Wed, 17 Sep 2008 13:29:47 +0000 (13:29 +0000)
SVN-Revision: 12617

target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c

index e3e80a9..f27c171 100644 (file)
@@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
 
 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
-       {0xf, 0xe, 0xd, 0xc},
-       {0xc, 0x9, 0x3, 0x1},
-       {0x0, 0x0, 0x0, 0x0},
-       {0x0, 0x0, 0x0, 0x0},
+       {0x0, 0xf, 0xf, 0xf},
+       {0xe, 0xd, 0xb, 0x7},
+       {0xc, 0xf, 0x3, 0xf},
+       {0xf, 0xf, 0xf, 0xf},
 };
 
 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
 {
        u32 t;
 
-       t = ble_table[size][where & 3];
+       t = ble_table[size & 3][where & 3];
+       BUG_ON(t == 0xf);
        t <<= (local) ? 20 : 4;
        return t;
 }