[brcm63xx] add support for bcm6345 SoC, needs testing
authorFlorian Fainelli <florian@openwrt.org>
Fri, 20 Mar 2009 15:08:02 +0000 (15:08 +0000)
committerFlorian Fainelli <florian@openwrt.org>
Fri, 20 Mar 2009 15:08:02 +0000 (15:08 +0000)
SVN-Revision: 14953

target/linux/brcm63xx/config-2.6.27
target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

index f2c312e..bcf9fd2 100644 (file)
@@ -14,6 +14,7 @@ CONFIG_BASE_SMALL=0
 # CONFIG_BCM47XX is not set
 CONFIG_BCM63XX=y
 CONFIG_BCM63XX_CPU_6338=y
+CONFIG_BCM63XX_CPU_6345=y
 CONFIG_BCM63XX_CPU_6348=y
 CONFIG_BCM63XX_CPU_6358=y
 CONFIG_BCM63XX_ENET=y
index b21c03e..a3ac72a 100644 (file)
@@ -8,6 +8,11 @@ config BCM63XX_CPU_6338
        select USB_OHCI_BIG_ENDIAN_DESC
        select USB_OHCI_BIG_ENDIAN_MMIO
 
+config BCM63XX_CPU_6345
+       bool "support 6345 CPU"
+       select USB_OHCI_BIG_ENDIAN_DESC
+       select USB_OHCI_BIG_ENDIAN_MMIO
+
 config BCM63XX_CPU_6348
        bool "support 6348 CPU"
        select HW_HAS_PCI
index f9b6eeb..bc7ed50 100644 (file)
@@ -71,6 +71,26 @@ static const unsigned long bcm96338_regs_spi[] = {
        [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
 };
 
+/*
+ * 6345 register sets and irqs
+ */
+
+static const unsigned long bcm96345_regs_base[] = {
+       [RSET_PERF]             = BCM_6345_PERF_BASE,
+       [RSET_TIMER]            = BCM_6345_TIMER_BASE,
+       [RSET_WDT]              = BCM_6345_WDT_BASE,
+       [RSET_UART0]            = BCM_6345_UART0_BASE,
+       [RSET_GPIO]             = BCM_6345_GPIO_BASE,
+};
+
+static const int bcm96345_irqs[] = {
+       [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
+       [IRQ_UART0]             = BCM_6345_UART0_IRQ,
+       [IRQ_DSL]               = BCM_6345_DSL_IRQ,
+       [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
+       [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
+};
+
 /*
  * 6348 register sets and irqs
  */
@@ -217,9 +237,11 @@ static unsigned int detect_cpu_clock(void)
 {
        unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 
-       if (BCMCPU_IS_6338()) {
+       if (BCMCPU_IS_6338())
                return 240000000;
-       }
+
+       if (BCMCPU_IS_6345())
+               return 140000000;
 
        /*
         * frequency depends on PLL configuration:
@@ -294,6 +316,11 @@ void __init bcm63xx_cpu_init(void)
                bcm63xx_irqs = bcm96338_irqs;
                bcm63xx_regs_spi = bcm96338_regs_spi;
                break;
+       case CPU_BCM6345:
+               expected_cpu_id = BCM6345_CPU_ID;
+               bcm63xx_regs_base = bcm96345_regs_base;
+               bcm63xx_irqs = bcm96345_irqs;
+               break;
        case CPU_BCM6348:
                expected_cpu_id = BCM6348_CPU_ID;
                bcm63xx_regs_base = bcm96348_regs_base;
index 74e553f..2ad2c9d 100644 (file)
@@ -12,6 +12,7 @@
  * arm mach-types)
  */
 #define BCM6338_CPU_ID         0x6338
+#define BCM6345_CPU_ID         0x6345
 #define BCM6348_CPU_ID         0x6348
 #define BCM6358_CPU_ID         0x6358
 
@@ -33,6 +34,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6338()      (0)
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6345
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id() BCM6345_CPU_ID
+# endif
+# define BCMCPU_IS_6345()      (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+#else
+# define BCMCPU_IS_6345()      (0)
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6348
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -122,6 +136,15 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UDC0_BASE             (0xfffe3000) /* USB_CTL_BASE */
 #define BCM_6338_MEMC_BASE             (0xfffe3100)
 
+/*
+ * 6345 register sets base address
+ */
+#define BCM_6345_PERF_BASE             (0xfffe0000)
+#define BCM_6345_TIMER_BASE            (0xfffe0200)
+#define BCM_6345_WDT_BASE              (0xfffe021c)
+#define BCM_6345_UART0_BASE            (0xfffe0300)
+#define BCM_6345_GPIO_BASE             (0xfffe0400)
+
 /*
  * 6348 register sets base address
  */
@@ -204,6 +227,20 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
                return BCM_6338_MEMC_BASE;
        }
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+       switch (set) {
+       case RSET_PERF:
+               return BCM_6345_PERF_BASE;
+       case RSET_TIMER:
+               return BCM_6345_TIMER_BASE;
+       case RSET_WDT:
+               return BCM_6345_WDT_BASE;
+       case RSET_UART0:
+               return BCM_6345_UART0_BASE;
+       case RSET_GPIO:
+               return BCM_6345_GPIO_BASE;
+       }
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6348
        switch (set) {
        case RSET_DSL_LMEM:
@@ -461,6 +498,17 @@ enum bcm63xx_irq {
 #define BCM_6338_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
 #define BCM_6338_SDIO_IRQ              (IRQ_INTERNAL_BASE + 17)
 
+/*
+ * 6345 irqs
+ */
+#define BCM_6345_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_DSL_IRQ               (IRQ_INTERNAL_BASE + 3)
+#define BCM_6345_ATM_IRQ               (IRQ_INTERNAL_BASE + 4)
+#define BCM_6345_USB_IRQ               (IRQ_INTERNAL_BASE + 5)
+#define BCM_6345_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 12)
+
 /*
  * 6348 irqs
  */