ramips/rt305x: add initial support for Rt5350 SoC
authorGabor Juhos <juhosg@openwrt.org>
Wed, 12 Sep 2012 19:03:12 +0000 (19:03 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Wed, 12 Sep 2012 19:03:12 +0000 (19:03 +0000)
Somehow detecting the RAM size in common/setup.c doesn't
work here, it always detects 64M and then crashes on devices
with less RAM.
Probably using MEMC_REG_SDRAM_CFG1 to know the RAM size is how
it could be, for now I use the mem=32M kernel parameter to get
stuff working.

Signed-off-by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 33381

target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c
target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

index 0afbb2f..c59135c 100644 (file)
@@ -22,6 +22,7 @@ enum rt305x_soc_type {
        RT305X_SOC_RT3052,
        RT305X_SOC_RT3350,
        RT305X_SOC_RT3352,
+       RT305X_SOC_RT5350,
 };
 
 extern enum rt305x_soc_type rt305x_soc;
@@ -51,6 +52,11 @@ static inline int soc_is_rt3352(void)
        return rt305x_soc == RT305X_SOC_RT3352;
 }
 
+static inline int soc_is_rt5350(void)
+{
+       return rt305x_soc == RT305X_SOC_RT5350;
+}
+
 #define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
 #define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
 
index db037a5..930b333 100644 (file)
@@ -76,6 +76,9 @@
 #define RT3352_CHIP_NAME0      0x33335452
 #define RT3352_CHIP_NAME1      0x20203235
 
+#define RT5350_CHIP_NAME0      0x33355452
+#define RT5350_CHIP_NAME1      0x20203035
+
 #define CHIP_ID_ID_MASK                0xff
 #define CHIP_ID_ID_SHIFT       8
 #define CHIP_ID_REV_MASK       0xff
 #define RT3352_SYSCFG0_CPUCLK_LOW      0x0
 #define RT3352_SYSCFG0_CPUCLK_HIGH     0x1
 
+#define RT5350_SYSCFG0_CPUCLK_SHIFT    8
+#define RT5350_SYSCFG0_CPUCLK_MASK     0x3
+#define RT5350_SYSCFG0_CPUCLK_360      0x0
+#define RT5350_SYSCFG0_CPUCLK_320      0x2
+#define RT5350_SYSCFG0_CPUCLK_300      0x3
+
 #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
 
 #define RT3352_CLKCFG1_UPHY0_CLK_EN    BIT(18)
index 9585476..c46a174 100644 (file)
@@ -62,6 +62,27 @@ void __init rt305x_clocks_init(void)
                rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
                rt305x_uart_clk.rate = 40000000;
                rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
+       } else if (soc_is_rt5350()) {
+               t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
+                    RT5350_SYSCFG0_CPUCLK_MASK;
+               switch (t) {
+               case RT5350_SYSCFG0_CPUCLK_360:
+                       rt305x_cpu_clk.rate = 360000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
+                       break;
+               case RT5350_SYSCFG0_CPUCLK_320:
+                       rt305x_cpu_clk.rate = 320000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4;
+                       break;
+               case RT5350_SYSCFG0_CPUCLK_300:
+                       rt305x_cpu_clk.rate = 300000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
+                       break;
+               default:
+                       BUG();
+               }
+               rt305x_uart_clk.rate = 40000000;
+               rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
        } else {
                BUG();
        }
index 07e950a..92ae56d 100644 (file)
@@ -404,7 +404,7 @@ void __init rt305x_register_usb(void)
 {
        if (soc_is_rt305x() || soc_is_rt3350()) {
                platform_device_register(&rt305x_dwc_otg_device);
-       } else if (soc_is_rt3352()) {
+       } else if (soc_is_rt3352() || soc_is_rt5350()) {
                platform_device_register(&rt3352_ehci_device);
                platform_device_register(&rt3352_ohci_device);
        } else {
index 179f9b7..856d869 100644 (file)
@@ -54,6 +54,9 @@ void __init ramips_soc_prom_init(void)
        } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
                rt305x_soc = RT305X_SOC_RT3352;
                name = "RT3352";
+       } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
+               rt305x_soc = RT305X_SOC_RT5350;
+               name = "RT5350";
        } else {
                panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
        }
@@ -68,7 +71,7 @@ void __init ramips_soc_prom_init(void)
 
        ramips_mem_base = RT305X_SDRAM_BASE;
 
-       if (soc_is_rt305x() || soc_is_rt3350()) {
+       if (soc_is_rt305x() || soc_is_rt3350() || soc_is_rt5350()) {
                ramips_mem_size_min = RT305X_MEM_SIZE_MIN;
                ramips_mem_size_max = RT305X_MEM_SIZE_MAX;
        } else if (soc_is_rt3352()) {